PPt on PD-SOI

PRAMOD KUMAR AGARWAL Roll Number-211EE1323 Under The Guidance of Prof. P. K. Sahu

Department of Electrical Engineering National Institute of Technology Rourkela, Pin-769008. NOV-2012

Presentation Outlines

INTRODUCTION What is Technology node ? What is scaling ? MOS-TRANSISTOR BASICS LITERATURE SURVEY OBJECTIVE PROBLEM STATEMENT MODEL & SIMULATION RESULT ANALYSIS CONCLUSION FUTURE WORK PUBLICATION REFERRENCES

National Institute of Technology, Rourkela.

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Technology Node

Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistorTransistor Scaling

Investment

Better Performance/Cost

Market Growth

Technology Node - It is the minimum metal line width/ size of the elements on the chip .YEAR: Technology node: 200490nm

200665nm

200845nm

201032nm

201122nm

201414nm3


Introduction

Scaling

In a new node all features of the circuit reduces by 70% of previous

node. This practice of periodic size reduction is called scaling.For Ex.

50% reduction in area i.e., 0.7 x 0.7 = 0.49

Nearly twice as many circuits can be fabricated on each wafer with new technology node. Moores LawChenming Hu, Modern Semiconductor Devices for Integrated Circuits, chapter-7,2009.National Institute of Technology, Rourkela. 4

Scaling

The number of transistors on an integrated circuit will double every 18 months.

Advantages Technology shrinks by 0.7/generation With every generation can integrate 2x more functions per chip; chip cost does not increase significantly. Cost of function by 2x.

Applications Communications Consumer Electronics Computers Military Industrial


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Introduction Scaling is desirable : To improve the performance and efficiency To integrate more transistors into the same chip

Scaling

Scaling aims towards is as shownTransistor size reduces Interconnections decreases Capacitance between the interconnectsC = (*A) / d

Hence suitable for RF Transmission applications

Switching speed increases at each node Circuit delay reduces = C*V/ I

Chenming Hu, Modern Semiconductor Devices for Integrated Circuits, chapter-7,2009.


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MOS-TRANSISTOR BASICSGateDrain/Sourc e

Channel Gate Drain/Source Substrate

Channel

Drain/Sourc e

Substrate

Basic Elements of Traditional Mosfet

S.M. Sze, Kwok K Ng, Physics of Semiconductor Devices , Jhon Willy and Sons, Third edition, 2009.


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MOS-TRANSISTOR BASICS

A Traditional MOSFET

Partially Depleted Silicon-On-Insulator (PD-SOI) MOSFET Advantages ShortcomingsKink Effect

Uses a highly doped n-type poly silicon gate electrode, a highly doped n-type source/drain, a p-type substrate, and a SiO2 gate dielectric .

Excellent Isolation Reduced leakage currents Improved switching speeds Nonlinear effect & etc..National Institute of Technology, Rourkela.

Eric Vogel, Technology and Metrology of New Electronic Material and Devices, Nature Nanotechnology, 2, 25 - 32 (2007)

highly undesirable8

Literature SurveyYear Author Name Title & Publication 1988 J. P. Colinge Reduction of kink effect in thin-film SOI MOSFETs 2001 M. Youssef Hammad and Dieter K. Schroder Analytical Modeling of the Partially-Depleted SOI MOSFET

RemarkNumerical simulation is used to show that the potential and electric field distribution within thin, fully depleted (FD) SO1 devices is quite different from that observed within thicker, partially depleted (PD An analytical model above threshold is developed. Floating-body effects appear at a slightly higher current in the linear region and early in saturation, a kink later in saturation, and eventually premature breakdown. The lateral BJT on SOI possess low parasitic capacitances, promises low power consumption and allows tuning of the SOI layer to optimize the overall device performance. The use of partial buried oxide reduces the parasitic capacitances and increases the switching speed of the devices.9

A High Performance Lateral Bipolar Junction Transistor on Selective Buried Oxide

2009

Sajad A. Loan, S. Qureshi and S. S. K. Iyer


Literature SurveyYear Author Name Title & Publication Remark

M.Narayanan, H.AlNashash, Baquer Mazhari, Dipankar Pal and Mahesh Chandra Analysis of Kink Reduction in SOI MOSFET Using Selective Back Oxide Structure

2012

Presents a complete analysis of kink effect in SOI MOSFETs. Provides a method for minimization of the kink phenomenon by introducing back oxide at selected regions below the source and drain. A device model that explains the kink behavior of the structure for varying gap lengths is also developed.


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ObjectiveInvestigation and minimization of kink phenomenon in the drain voltage-current characteristics of PD-SOI MOSFET by using various parameters variations in the

proposed structure such as : Variation of back oxide gap length (g) keeping gap oxide width (w) constant. Variation of back oxide gap width (w) keeping gap oxide length (g) constant. Variation in gate oxide thickness (to x) Using Dual Insulator (DI) as gate oxide in the ratio 1:1


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Problem StatementDesign of 1. Selective back oxide (Selbox) PD-SOI MOSFET with single gate material 2. PD-SOI MOSFET with dual insulator (DI) as gate material

Study the behaviour of the parameters like 1. Id Vs V ds for both BULK and PD-SOI MOSFET 2. Id Vs V ds with variation in Selbox gap length (g)

3. Id Vs V ds with variation in Selbox gap width (w)4. Id Vs V ds with variation in gate oxide thickness (t ox) 5. Id Vs V ds with dual insulator in the ratio (1:1) as gate material

M . Narayanan , H. Al-Nashash , Banquer Mazhari, Dipankar Pal, Mahesh Chandra, Analysis of kink Reduction in SOI MOSFET Using Selective Back Oxide, Hindawi Publishing Corporation Active and Passive Electronic components, vol. 2012


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Model & SimulationAttributes Value 2 um 0.01 um

1.The schematic structures of PD-SOI, SELBOX structure and PD-SOI with double insulator (DI)

Channel length (L1) Gate Oxide Thickness (tox)

MOSFETs are shown in Fig.1, Fig.2 and Fig.3respectively . 2. Device dimensions and doping concentrations taken for simulation are given in the table shown aside.

Thickness of the BOX (tbox)Thickness of silicon body (tsi) Channel Doping (NA) Source Doping (ND) Drain Doping (ND) Total device length including source and drain length Source/Drain length (LS/LD) Models taken for simulation

0.4 um0.49 um 2x1017cm-3 1x1019cm-3 1x1019cm-3

3.5 um

0.75 um each SRH , FLD, IMPACT SELB13

Fig1.Device structure of PD-SOI


Model & Simulation

r=

3.9

r=

20

Fig 2. Device Structure of SELBOX

Fig 3. Device structure of PD-SOI using Dual Insulator

1. The oxide thickness is maintained at t ox=10nm for the structures in Fig.2 and Fig.3 and a plot of electrical output characteristics between drain current vs. voltage is analyzed for varying gate oxide thickness (t ox) for Fig.1. 2.The work function for the gate material is assumed as M1=4.8ev .In Fig.3 the device structure with dual insulator (DI) having permittivity of 3.9 and 20 is considered respectively.


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Result Analysis

Fig4. Simulation of Drain Current (ID) as a function of Drain Voltage (VDS) for PD-SOI MOSFET

Fig 5. Simulation of ID as a function of VDS for both BULK & PD-SOI MOSFET


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Result Analysis1. In Fig 4., the onset of kink takes place at a kink voltage of 1V for gate source voltage (V gs) of 2.2V

2. The simulated output characteristics of bulk MOSFET with identical device dimension and doping concentration along with PD-SOI characteristics is illustrated and compared in Fig.5 3. In Fig.5 presence of kink is clearly visible in PD-SOI device while the same is not present in bulk MOSFETs

4. In order to minimize the kink in the output characteristics of PD-SOI device selbox structure is

designed as shown in Fig.2 previously.


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Result Analysis

Fig 6. Simulation of ID as a function of VDS for SelBox structure with varying gap length (g)

Fig 7. Simulation of ID as a function of VDS for SelBox structure with varying gap width (w)


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Result Analysis1. Fig.6 gives the output characteristics of the selbox device with varying gap length. In this figure, the oxide thickness has been maintained at 0.4um.The gap length (g) is increased from 0.004um to 0.010um.

2. The increase in gap length results in an increase in the kink voltage and hence for larger values for gap length the kink will completely disappear. 3. The kink voltage have a significant dependence with respect to the thickness of the buried oxide. The kink can also be effectively reduced with a small gap in the buried oxide. 4. Fig.7 gives the variation of kink voltage with buried oxide for a fixed gap length of 0.009um.In this figure, the back oxide thickness is varied from 0.25um to 0.45um for a fixed gap length of 0.009um. 5. A selbox device with thinner back oxide thickness is more likely to behave as bulk MOSFET and is less susceptible to the kink effect.


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Result Analysis

Fig 8.Simulation of ID as a function of VDS for PD-SOI MOSFET with Dual Insulator (DI)

Fig 9. Simulation of ID as a function of VDS for PD-SOI MOSFET with varying gate oxide

thickness (tox)National Institute of Technology, Rourkela. 19

Result Analysis1. In this work, it has been presented that the kink effect can be minimized up to a certain extent using a dual insulator below the gate electrode while preserving the necessary advantages of the SOI device at the same time.

2. In Fig.8, a comparison has been made between the output characteristics of PD-SOI device using singleand dual insulator.

3. From the figure it can be seen that in simple PD-SOI the onset of kink takes place at a kink voltage of

around 1V for a gate to source voltage of 2.2V while in PD-SOI using dual insulator (DI) the kinkoccurs at a higher value of drain voltage for the same value of V g s 4. From Fig.9 it can be analyzed that at shorter gate oxide thickness, the drain saturation current increases strongly and hence is less susceptible to kink phenomenon.


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Conclusion We have investigated the DC performance for PD-SOI MOSFETs as a function of variations in different structures parameters. PD-SOI MOSFET devices exhibit nonlinearities due to the presence of kink in the output current voltage characteristics. The design and simulation on electrical characteristics of PD-SOI and Selbox structures has been successfully done using commercially available device simulation software ATLASTM.

Variations in the parameters of these structures have been carried out to study their effect on thedevice DC performance.

From all above simulation results the kink i.e. One of the severe limitations of PD-SOI MOSFET can be suppressed using proper parameter variations along with variation in gate oxide thickness and using dual insulator as gate material.


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Future Work1. Modelling & Simulation of new devices like Junction less (J-less) MOSFETs with characterization of its DC and AC performance .

2.Optimization of Device parameters and its possible fabrication.

Publications1. Pramod Kumar Agarwal, Kumar Prasannajit Pradhan, Sushanta Kumar Mohapatra, Prasanna Kumar Sahu, Insulating layer parameters are still in reduction of kink, Nirma University International Conference on Engineering (NUiCONE-2012)", Ahmedabad, 6 to 8 Dec 2012.

(Accepted)


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References[1] K. Konrad Young, Short-Channel Effect in Fully Depleted SOI,IEEE Transactions on Electron Devices, vol 36. no2. February 1989. [2] Ran-Hong Yan, Abbas Ourmazd, and Kwing F. Lee, Scaling the Si MOSFET: From Bulk to SOI to Bulk, IEEE Transactions on Electron Devices, vol. 39. no. 7, July 1992. [3] Jean-Pierre Colinge, Multiple-gate SOI MOSFETs , Solid-State Electronics, vol. 48, pp. 897-905, 2004. [4] J. P. Colinge Reduction of kink effect in thin-film SOI MOSFETs, IEEE Electron Device Letters, Vol. 9, Issue: 2, pp: 97 99, Feb, 1988. [5]. AnuragChaudhry and M. Jagadesh Kumar, Senior Member, IEEE, Controlling Short-Channel Effects in Deep-Submicron SOI MOSFETs for Improved Reliability: A Review, IEEE Transactions on Device and Materials Reliability, vol. 4, No. 1, March 2004. [6]. Sajad A. Loan, S. Qureshi and S. S. K. Iyer, A High Performance Lateral Bipolar Junction Transistor on Selective Buried Oxide, International Semiconductor Device Research Symposium (ISDRS), pp: 1 2, Dec, 2009.

[7]. Sajad A. Loan, S. Qureshi, and S. Sundar Kumar Iyer, A Novel Partial-Ground-Plane-Based MOSFET on Selective BuriedOxide: 2-D Simulation Study, IEEE Transactions on Electron Devices, Vol. 57, No. 3, pp: 671-680, Mar, 2010.


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References[8]. S.Qureshi, Sajad A. Loan, and S. S. K. Iyer, A High Performance MOSFET on Selective Buried Oxide with Improved Short Channel Effects, International Semiconductor Device Research Symposium (ISDRS), pp: 1 2, Dec, 2009. [9]. Koichi Kato, Tetsunciiu Wada, and Kenji Taniguchi Analysis of Kink Characteristics in Silicon-on-lnsula.tor MOSFETs Using Two-CarnsnierModeling, IEEE Transactions on Electron Devices, Vol.-32, No.2, pp: 458-462, Feb, 1985 . [10]. M. Youssef Hammad and Dieter K. Schroder, Analytical Modeling of the Partially-Depleted SOI MOSFET, IEEE Transactions on Electron Devices, Vol. 48, No. 2, pp: 252-258, Feb, 2001. [11]. Marina Valdinoci, Luigi Colalongo, Giorgio Baccarani, GuglielmoFortunato, A. Pecora, and I. Policicchio, Floating Body Effects in Polysilicon Thin-Film Transistors, IEEE Transactions on Electron Devices, Vol. 44, No. 12, pp: 2234-2241, Dec 1997. [12]. ATLAS manual: SILVACO Int. Santa Clara, 2008. [13]. The International Technology Roadmap for Semiconductors www.itrs.net


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References[1]. Randall L. Geiger, Phillip E. Allen, Noel R. Strader, VLSI Design Technology for Analog & Digital Circuits, McGraw-Hill Publishing Company, 1990. [2]. Amara Amara ,OlivierRozeau, Planar Double-Gate Transistor From Technology to Circuit, Springer Science + Business Media, 2009. [3]. Ban P. Wong, Anurag Mittal, Yu Cao, Greg Starr, Nano-CMOS Circuit and Physical Design, A John Wiley & Sons, Interscience Publication, 2005. [4]. ColmDurkan, Current at the Nano scale An Introduction to Nano electronics, Imperical College Press, 2007. [5]. Harry Veendrick, Nanometer CMOS ICs from basics to ASICs, Springer, my business media, 2008. [6]. S.M. Sze, Kwok K Ng, Physics of Semiconductor Devices, Jhon Willy and Sons, Third edition, 2009.


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References[7]. R.S.Muller, I.T.Kamins, Device Electronics for Integrated Circuits , John Wiely & Sons., 1986. [8]. Y.Tsividis, Operation & Modeling of The MOS Transistor, Mc Graw Hill, 1999.

[9]. J.M.Rabaey, A.Chandrakasan, B.Nikolic Digital Integrated Circuits:A Design Perspective, 2nd edition, Pearson, 2003.[10]. Sung-Mu Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysi & Design, 3rd edition, Tata Mc Graw Hill , 2003.


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References[1]. www.ieee.org/ [2]. www.elsevier.com/

[3]. nptel.iitm.ac.in/[4]. www.stanford.edu/ [5]. http://berkeley.edu/ [6]. www.iisc.ernet.in/ [7]. www.tandf.co.uk /journals/ [8]. http://www.nitrkl.ac.in/ [9]. http://nptel.iitm.ac.in/ [10]. www.itrs.net/


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PPt on PD-SOI