SEMINAR ON LOGIC SEMINAR ON LOGIC OPTIMIZATIONOPTIMIZATION::

PRESENTED BYPRESENTED BY

1.MONIRA AKHTAR 1.MONIRA AKHTAR BANUBANU

2.RAJAT SUBHRA 2.RAJAT SUBHRA KARMAKARKARMAKAR

3.MANOSHI ROY3.MANOSHI ROY

Logic Optimization

• Logic optimization, a part of logic synthesis, is the process of finding an equivalent representation of the specified logic circuit under one or more specified constraints.

• The goals of logic optimization are: Minimization of delay times Minimization of the required area

Today, logic optimization is divided into various categories based on two criteria:

Based on circuit representation Two-level logic optimization Multi-level logic optimization Based on circuit characteristics Sequential logic optimization Combinational logic optimization

Binary Decision Diagrams (BDD)

• Based on recursive Shannon expansion

f = x fx + x’ fx’

• Compact data structure for Boolean logic– can represents sets of objects (states)

encoded as Boolean functions• Canonical representation

– reduced ordered BDDs (ROBDD) are canonical

– essential for verification

BDD Reduction Rules -1

Eliminate redundant nodes (with both edges pointing to same node)

f = a’ g(b) + a g(b) = g(b)(fa + fa’ = 1)b

g

a

b

f

g

BDD Reduction Rules -2

Merge duplicate nodes (isomorphic subgraphs)• Nodes must be unique

f1 = a’ g(b) + a h(c) = f2 f = f1 = f2

a a

b c

hg

f1 f2

a

b c

g h

f

BDD Construction

• Reduced Ordered BDD

1 edge

0 edgea b c f

0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 01 0 1 11 1 0 01 1 1 1

Truth table

f = ac + bc

Decision tree

10 0 0 1 0 10

a

b

c

b

c c c

f

BDD Construction – cont’d

10

a

b

c

b

c c c

f f

10

a

b

c

b

c

10

a

b

c

f = (a+b)c

2. Merge duplicate nodes

1. Merge terminal nodes 3. Remove redundant nodes

What’s Good about BDDs

• Powerful Operations– Creating, manipulating, testing– Maintain “closure” property

• Each operation produces form suitable for further operations

• Generally Stay Small Enough– Especially for digital circuit applications– Given good choice of variable ordering

• Weak Competition– No other method comes close in overall strength– Especially with quantification operations

Finite State Machines

• Any Circuit with Memory Is a Finite State Machine– Even computers can be viewed as huge FSMs

• Design of FSMs Involves– Defining states– Defining transitions between states– Optimization / minimization

• Above Approach Is Practical for Small FSMs Only

State Machines: Definition of Terms• State Diagram

•Illustrates the form and function of a state machine. Usually drawn as a bubble-and-arrow diagram.

• State•A uniquely identifiable set of values measured at various points in a digital system.

• Branch•A change from present state to next state.

• Next State•The state to which the state machine makes the next transition, determined by the inputs present when the device is clocked.

Finite State Machine

•Mealy Machine•A state machine that determines its outputs from the present state and from the inputs.

•Moore Machine•A state machine that determines its outputs from the present state only.

Mealy Machine

Mealy machine is a finite-state machine whose output values are determined both by its current state and by the values of its inputs.

named after George H. Mealy

Moore Machine

Moore machine is a finite-state machine whose output values are determined solely by its current state.

Named after Edward F. Moore

1. Current outputs are effected by the current states and current inputs.

2. Outputs are unstable until current inputs achieve steady state.

3. Difficult to engineers because of the unstable outputs.

4. Require less hardware.

5. Inputs can effect outputs in current clock period.

1. Current Outputs are effected by the current state only

2. Current outputs are always stable.

3. Easy to engineers since current outputs are stable.

4. Require more hardware.

5. Inputs can affect outputs in next clock period only

Mealy Machine Moore Machine

References

Digital fundamentals – Thomas L. Floyd en.wikipedia.org/wiki/Logic_optimization

www.dms.umontreal.ca/~sms/RAUTENBACH_logic_no_overlays.pdf

en.wikipedia.org/wiki/Binary_decision_diagram

en.wikipedia.org/wiki/Finite-state_machine

THANK YOU