PowerBench Programmable Power Supply Final presentation – part B March 22 th, 2009 Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi HS DSL

PowerBenchProgrammable Power Supply

Final presentation – part BMarch 22th, 2009

Gregory KaplanDmitry Babin

Supervisor: Boaz Mizrahi

HS DSLHS DSL

Topics

• Overview– Basic reminder– Targets and expectations– Top-level survey of the implementation

• Implementation– Schematics– CAD simulations

• Layout– Design guidelines and overview– Features of interest

• Mechanics– Thermal– UI

• Future developments

Active load

Power supply

Control unit

User interface for standalone operation

LCD KeysLEDs

User interface

DUT

Measurement unit

OverviewA brief reminder

OverviewA brief reminder

Power supply unit capabilities– Variable source/sink

operation

– Four independent outputs

– Configurable current limits

– Fast load transient simulation

– DRAM-like power consumption simulation

– Two-way communication with a PC

OverviewDesign targets vs projected capabilities I

OverviewDesign targets vs projected capabilities I

• Source operation– Output voltage: 0.9 to 12.6 V– Output current: 0 to 3.5 A– Programming resolution:

< 5 mV– Ripple and noise: < 20 mV

peak-to-peak– Settling time: < 1 ms

• Load operation– Input current: 0 to 3.5 A– Programming resolution:

< 1 mA– Fast (< 100 ns) transient

load simulation

OverviewDesign targets vs projected capabilities II

OverviewDesign targets vs projected capabilities II

DC-DC

Converter

Post

regulator

ADC

ADC

Voltage Sense

DAC

Current Sense

Output

FPGA

Controller

Block

Output

setting

Input

voltage

sense

feed-

forward

Tempe-rature

Current

limit

PWM

Microprocessor

OverviewControl Scheme

ADC

AuxiliaryVoltage Sense

OverviewControl Scheme

OverviewSource/Sink/Measurement Module 1 (Outputs 1, 2)

OUTPUT 1

RETURN 1

MIC4102YM

TO

/FR

OM

FP

GA

OUTPUT 2

RETURN 2

MIC4102YM

MOSFET Driver

MOSFET Driver

VDD

LT2296-CUP

LT2296-CUP

A/D Converter

2 PWM

2 PWM

1 SOURCE/SINC

VDD2 ADC CONTROL

4 SPI14 ADC DATA

14 ADC DATA

2 ADC CONTROL

1 CLR

1 SOURCE/SINC

4 SPIAD7914

4-Ch 10-bit ADC AD5415YRUZD/A Converter

OverviewSource/Sink/Measurement Module 1 (Outputs 1, 2


OUTPUT 3

RETURN 3

MIC4102YM

TO

/FR

OM

FP

GA

OUTPUT 4

RETURN 4

FAN3227TMX

MOSFET Driver

MOSFET Driver

VDD

VDD

LT2296-CUP

LT2296-CUP

A/D Converter

2 PWM

2 PWM

1 SOURCE/SINC

1 SOURCE/SINC

AD5415YRUZ

VDD

D/A Converter

2 ADC CONTROL

4 SPI14 ADC DATA

14 ADC DATA

2 ADC CONTROL

1 CLR

AD79144-Ch 10-bit ADC4 SPI


USBPort

16 DATA

USB CONTROL2

2Mbit SPI Flash

SPI DATA IN, OUT, CLK

3 SPI CS,WP,HOLD

2 PROG_B*,DONE*

ADC Output

ADC Control

PWM

SPI

* Dedicated conf pins

16

DATA

USBHigh-Speed

USB

5 USB

CONTROL

USB Control

CY7C68013A-100AXC

M25P20-VMN6

XilinxSPARTAN 3-EXC3S250E-4-PQ208

MicrochipPIC18F87J50

-I/CT

OverviewControl Module

TO

/FR

OM

SS

M M

OD

UL

E

DAC

21

Real Time Clock

Temperature monitor

(2 devices)

LM75CIM-5

RTC-8564JE

I2C

4

Keypad

Graphic LCD Module

Optrex F-51553GNBJ

-LW-AEN

PB1-PB4

845

1

PB0

OverviewControl Module

OverviewPower flow – Control Module

OverviewPower flow – Control Module

Universal Input

Up to 100W

ECM10015.8V

LM3668SD

LTC4090

FAN4855MTC

Li-ion

3.7-4.2V

(optional)

3.3V

5V

AC/DC Converter

DC/DC Converter + Battery Charger

3.3V Buck-Boost

DC/DC Booster

VDD

MicrochipPIC18F87J50

Graphic LCD Module

Optrex F-51553GNBJ

-LW-AEN

CY7C68013AM25P20 RTC-8564JE XilinxSPARTAN 3-E

2.5V

1.2V

VDD

VDD

Vaux

Vcore

VDD

VDD

VDD

Up to 85mA

Up to 15mA

Up to 0.8mA

Up to 222mA More than

100mA

Up to 42mA

BR1255Small Li battery

(optional)

5V, VBAT+0.3V or VBAT

TPS73001

TPS62003

2.5V LDO

1.2VBuck

5V, VBAT+0.3V or VBAT

OverviewPower flow - Source/Sink/Measurement Module

Universal Input

Up to 100W

ECM100

AC/DC Converter

15.8V (Direct from AC)

OUTPUT 1

RETURN 1

MOSFET Driver

14 bit ADCDAC

10 bit ADCDAC

DACDAC

14 bit ADC14 bit ADC

14 bit ADC

3.3V

×4

OverviewPower flow - Source/Sink/Measurement Module

5V

, V

BA

T+

0.3

V o

r V

BA

T

ADP1611

Boost

LT3580

Inverter

15.8V (From AC or battery)

-15.8V (From AC or battery)

Topics






Implementation

• 3 separate boards from the start:– “Digital” – control board– “Analog” – sink/source/measurement (SSM)– “Panel” – user interface (UI)

• The design process:– Component selection– Schematics– Simulation– Layout

Implementation – Schematics Introduction

• Environment: – OrCAD Capture 16.0– Custom library for all the parts– Hierarchical design– Use of “instances” where applicable

• Component selection– Priority to Zoran stock when possible– Minimum different components – All ICs in “accessible” packages (no DFN or BGA except when unavoidable)– Price

• Design guidelines– Clear schematics with maximum relevant information– Maximum flexibility in the post-layout stage– Scalability and “overheads”

Implementation – Schematics Control Module : Clock

R 1 9 2 3 3 R m c u _ p ic _ c lk _ rR 1 9 3 3 3 R m c u _ u s b _ c lk _ rR 1 9 4 3 3 R m c u _ f p g a _ c lk _ rR 1 9 5 3 3 R m c u _ d e b u g _ c lk _ r

R1

90

4.7

k

o s c _ e n

V C C 3 p 3

X1

C P P F X7 L T-A 7 B C -XX. XXXN P

TR I S TA TE1

G N D

2

O U TP U T3

V C C

4

C 8 7 1 0 0 n F

m c u _ u s b _ c lkC 9 1 1 0 0 n F

I C S 8 3 0 4 -A M L FU 1 2

VD

DO

1V

DD

2

C L K3

GN

D4

N Q 05

N Q 16

N Q 27

N Q 38

m c u _ f p g a _ c lkm c u _ d e b u g _ c lk

m c u _ p ic _ c lk

V C C 3 p 3

m c u _ x 1 _ c lk o u t

C 9 2 1 0 0 n F

R1

91

33

R

mc

u_

u1

2_

clk

in

• Clock buffer and oscillator running at 24MHz

• Alternate clock sources (crystals) can be used for the MCU and USB chips

Implementation – Schematics Control Module : Power distribution I

R 4 0

==>

C 5 64 7 0 n F

re g _ b o o s t

re g _ h v e nC 5 51 u F 2 5 V

V C C _ R E G

L TC 4 0 9 0 E D J C

U 9

S Y N C1

P G2

R T3

V C4

N TC5

V N TC6

H V P R7

C H R G8

P R O G9

G A TE1 0

B A T1 1

H V E N2 2

H V I N2 1

BO

OS

T1

9

S W2 0

H V O U T1 8

TI M E R1 7

S U S P1 6

H P W R1 5

C L P R O G1 4

O U T1 3

I N1 2

EP

23

Q 3S i2 3 3 3 D S

p o we r_ m c u _ c h rg -

V B U S

Q 2S i2 3 3 3 D S

L 3 6 . 8 u H 4 . 3 A

B 8 2 4 6 4 Z 4 6 8 2 M 0 0 0

R 4 3 3 4 k 1 %re g _ p ro g

R 4 5 2 9 . 4 k 1 %re g _ rt

re g _ v c 2 re g _ v c

R 4 2 2 . 2 1 k 1 %re g _ c lp ro g

C 6 12 2 0 n F

Timer = 2.24HUSB_I_lim = 452.5mAI_charge = 1.47APWM_freq. = 1MHz

For 1000 mA*h battery use R43=100kTimer = 6.6 hours (charging will auto-stop when Vbat=4.2V and Ichrg_actual<0.1*Ichrg_prog)I_charge = 0.4 A

+ C 5 74 7 u F 2 5 V

re g _ v n t c

re g _ n t c

R 4 61 0 k 1 %

R 4 1 4 7 k

V B A T

m c u _ p o we r_ h p wr

re g _ s w

m c u _ p o we r_ t im e r

m c u _ p o we r_ s u s p

C 6 02 2 0 p F

R2

26

4.7

k

V C C 1 5 p 0

C 5 81 0 u F 2 5 V

R2

27

4.7

k

re g _ h v o u t

re g _ g a t e _ r

re g _ h v p r-

R 3 4 7 k

TP 4 7

R 4 0 2 . 2 kC 5 92 2 0 p FN C

re g _ g a t e

t° R T1N TC L E 1 0 0 E 3 1 0 3 J B 01 0 k N TC

C 6 21 0 u F 2 5 V

D 2S S C 5 3 L -E 3

re g _ p o we rg o o d

• A dedicated power manager IC select from either high-voltage DC line, battery or USB power sources, converting them to a voltage around the battery voltage or 5V

• It also charges the battery when possible (and permission is granted by the MCU)

Implementation – Schematics Control Module : Power distribution II

D 31 N 4 1 4 8

May be low-

voltage (6.3V)

p wrb t n _ n o rm o p n

C 4 71 0 0 n F

V C C 3 p 3

C 1 0 11 0 0 n F

D 1 71 N 4 1 4 8

R 4 44 7 0 k

3 P 3 _ B U C K _ B O O S T

3 P 3 _ B U C K _ B O O S T

V C C 3 p 3V C C _ R E G

b b 3 p 3 _ e n

b b 3 p 3 _ rd

C 1 0 21 0 0 n F

R 3 84 7 0 k


R5

47

k

2 P 5 _ L D O

2 P 5 _ L D O

ld o 2 p 5 _ e n

V C C _ R E G V C C 2 p 5

V C C _ R E G

V C C _ R E G

1 P 2 _ B U C K

1 P 2 _ B U C K


b u c k 1 p 2 _ e n

5 P 0 _ B O O S T

5 P 0 _ B O O S T

V G G _ R E G

b o o s t 5 p 0 _ e n b o o s t 5 p 0 _ lb o -

V C C 5 p 0

V C C _ R E G

m c u _ p o we r_ f p g a p w_ e n

Off-boardpower on/off button

Q 4S I 2 3 1 2 B D S

Com

mon

Nor

mO

pnN

orm

Cls

J 1 7C O N N R C P T 3

123V C C 3 p 3

m c u _ p o we r_ lc d p w_ e n

m c u _ io _ p o we r_ a llo f f -

V C C 3 p 3

R 6 4 7 k

pw

rbtn

_c

om

m

V C C 2 p 5

V C C _ R E G

R 3 74 7 0 k

V C C 1 p 2

V C C 3 p 3

D 1 6 1 N 4 1 4 8

C 91 u F 2 5 V

• The 3.3V converter masters other secondary converters (the 5V, 2.5V and 1.2V ones):

– while 3.3V rail is low, all secondary converters are turned off (including the 3.3V converter itself!)

– while 3.3V rail is high, secondary converters may be turned on/off by the MCU (if 3.3V is turned off, the system may be turned on only by a button)

Implementation – Schematics Control Module : Connectors

• Connection to the other boards– 120-pin 0.1” connector to the SSM module– 40-pin 0.1” connector to the UI module

• End-user interface– USB-B connector

• Debug and programming– JTAG– ICSP– 12-pin and 14-pin debug ports on the USB chip– 2 x 38-pin MICTOR connectors– 2 SMA-type connector footprints

Implementation – Schematics Control Module : Connectors

f p g a _ a n a lo g _ d a c _ c lk 1 _ r

J 3

H E A D E R 3 0 X2

2468

1 01 21 41 61 82 02 22 42 62 83 03 23 43 63 84 04 24 44 64 85 05 25 45 65 86 0

135791 11 31 51 71 92 12 32 52 72 93 13 33 53 73 94 14 34 54 74 95 15 35 55 75 9

f p g a _ a n a lo g _ f p g a 1 2 6 _ r

f p g a _ a n a lo g _ c h 1 _ re la y _ r

J 4

H E A D E R 3 0 X2

2468

1 01 21 41 61 82 02 22 42 62 83 03 23 43 63 84 04 24 44 64 85 05 25 45 65 86 0

135791 11 31 51 71 92 12 32 52 72 93 13 33 53 73 94 14 34 54 74 95 15 35 55 75 9

a n a lo g _ f p g a _ a d c 1 _ d a t a 7 _ r

a n a lo g _ f p g a _ a d c 4 _ d a t a 8 _ ra n a lo g _ f p g a _ a d c 4 _ d a t a 6 _ r

f p g a _ a n a lo g _ a d c 4 _ s h d n _ r

a n a lo g _ f p g a _ a d c 3 _ d a t a 1 0 _ r

a n a lo g _ f p g a _ a d c 4 _ d a t a 1 2 _ ra n a lo g _ f p g a _ a d c 4 _ d a t a 1 0 _ r




a n a lo g _ f p g a _ a d c 1 _ o f _ r





m c u _ d e b u g _ c lk _ a n a lo g _ r


f p g a _ a n a lo g _ f p g a 8 3 _ r


f p g a _ a n a lo g _ d a c _ c lr-_ r

m c u _ re s e t _ o u t _ a n a lo g _ r

f p g a _ a n a lo g _ d a c _ s y n c 1 _ r



f p g a _ a n a lo g _ d a c _ ld a c 1 _ r


V C C _ R E G




f p g a _ a n a lo g _ c h 1 _ s y n c _ r


f p g a _ a n a lo g _ a d c 3 _ c lk _ r

m c u _ s c l_ a n a lo g _ r



f p g a _ a n a lo g _ d a c _ d o u t 1 _ r



V C C 3 p 3



f p g a _ a n a lo g _ a d c 5 _ c s -_ r

f p g a _ a n a lo g _ a d c 5 _ d o u t _ rf p g a _ a n a lo g _ a d c 2 _ c lk _ r

f p g a _ a n a lo g _ c h 4 _ s w2 _ r


V C C 3 p 3

f p g a _ a n a lo g _ d a c _ c lk 2 _ r







f p g a _ a n a lo g _ c h 2 _ p wm _ ra n a lo g _ f p g a _ a d c 3 _ d a t a 2 _ r




a n a lo g _ f p g a _ a d c 2 _ d a t a 9 _ rf p g a _ a n a lo g _ d a c _ ld a c 2 _ r

f p g a _ a n a lo g _ c h 4 _ re la y _ r a n a lo g _ f p g a _ a d c 2 _ d a t a 6 _ r

a n a lo g _ f p g a _ a d c 3 _ d a t a 1 3 _ r f p g a _ a n a lo g _ c h 1 _ p wm _ r


a n a lo g _ f p g a _ a d c 1 _ d a t a 1 _ ra n a lo g _ f p g a _ a d c 1 _ d a t a 3 _ ra n a lo g _ f p g a _ a d c 1 _ d a t a 5 _ r



f p g a _ a n a lo g _ d a c _ s y n c 2 _ r





f p g a _ a n a lo g _ c h 3 _ p wm _ r


m c u _ s d a _ a n a lo g _ ra n a lo g _ f p g a _ a d c 5 _ d in _ r











m c u _ p o we r_ f p g a _ s h d n _ r




f p g a _ a n a lo g _ d a c _ d o u t 2 _ r

f p g a _ a n a lo g _ c h 4 _ s w1 _ r

a n a lo g _ f p g a _ a d c 3 _ d a t a 1 _ ra n a lo g _ f p g a _ a d c 1 _ d a t a 1 3 _ r


• The SSM module connector– Signal speed of up to 100MHz– Adequate grounding around clock lines– No crossing between signals (will be shown later in the layout stage)– “Fast” lines spread between “slow” lines

Implementation – Schematics SSM Module : DC-DC Buck Converter

F B 8 B L M 2 1 P G 2 2 1 S N 1

F B 2 2 B L M 2 1 P G 2 2 1 S N 1

b u c k _ s wn o d e

Q 4 4I R L 3 7 1 4 P B F

Q 4 5I R L 3 7 1 4 P B F

C 1 0 3 1 u F

C1

02

4.7

uF

50

V

C2

66

10

0n

F 5

0V

U 1 1

M I C 4 1 0 2 Y M

VD

D1

HB

2

H O3

H S4

P W M5

L S6

VS

S7

L O8

L 8 1 0 u H 4 . 3 A

P 0 8 4 5

V C C 1 5 p 8 _ wa ll

b u c k _ lg a t e

b u c k _ h g a t e

b u c k _ o u t

bu

ck

_b

str

ap

C2

54

4.7

uF

50

V

C 1 0 54 7 0 u F 2 5 V

D5

SS

C5

3L

-E3

c o n n _ b u c k _ p wm

c o n n _ b u c k _ s y n c

c o n v _ ld o _ a d c 4 c h _ v o u t

• A buck DC-DC converter– Input: 15.8V– Output: 0..X V– Maximum operating frequency: Y KHz– Estimated efficiency: Z%– Can work both in continuous and discontinuous conduction modes– High-frequency spikes are rejected by the output ferrites

Implementation – Schematics SSM Module : Positive LDO

• A low-dropout post-regulator– Input: X ..Y V– Output: 0..X V– Loop bandwidth: X MHz– Actively controlled by the DAC output– Proposed mode of operation: constant power dissipation– Smoothes the buck converter’s output ripple

R1

19

10

0k

NC

ld o _ p _ g a t eld o _ p _ v re f

R 2 2 7 1 0 R

C2

00

10

0n

F 5

0V

To mode switch(source/sink)

R1

21

33

0R

1W

D6

01

N4

14

8

ld o _ m o d e s w_ v o u t

C2

01

27

0u

F 1

6V

NC

D6

5B

ZV

55

-C1

5

ld o _ p _ f e e d b a c k

Q 1 1 F Q P 2 7 P 0 6

-

++

-

U 3 6 A

L T1 2 1 5 C S 8

12

3

48

C2

05

10

0n

F 5

0V

V S S m 1 5 p 8 _ wa ll

C2

02

27

0u

F 1

6V

NC

Vref : [0 ... 2.5V]

C2

78

47

0u

F 1

6V

C2

76

47

0u

F 1

6V

a m u x _ ld o _ v re f

C2

03

27

0u

F 1

6V

NC

c o n v _ ld o _ a d c 4 c h _ v o u t

R1

23

10

k 1

%

G N D _ S E N S E

R1

20

43

.2k

1%

C2

04

10

0n

F

R1

22

10

0k C

27

74

70

uF

16

V

ldo

_d

iod

es

C2

58

4.7

uF

50

V

V S S _ m 1 5 p 8

Input offset voltage trimming

R 2 2 4 1 0 R

C 2 6 2 1 0 n F 2 5 V

C 2 2 4 1 0 0 n F 5 0 V

loa

d_

p_

in+

R1

47

11

8k

1%

+

-

+

-

OVC

Vostrim

U 4 0

L T1 1 2 2 D S 8

3

2

74

65

1

8

R1

48

31

.6k

1%

Q 1 5I R L 3 7 1 4 P B F

lo a d _ p _ rc 2

R 1 5 11 5 0 m O h m 1 %

loa

d_

p_

fb

lo a d _ p _ g a t e

R 1 4 91 0 0 kN C

D 5 0R B 4 1 1 D

lo a d _ p _ o s 5

lo a d _ p _ o s 1

a m u x _ lo a d _ p _ v re f

lo a d _ p _ in

R1

50

10

Rlo

ad

_p

_rc

C2

28

10

nF

25

V

Implementation – Schematics SSM Module : Active load

• A varying load– Resistance varies from X Ohm to Y Ohm– Loop bandwidth X MHz– Desired current is set by the output of the DAC– Too much output inductance can interfere with operation

Implementation – Schematics SSM Module : Mode switching

'0' to close the pass MOSFET (SOURCE mode)'1' to open it (SINK mode)

mod

esw

_p_

in_

znr_

anod

mod

esw

_p_

gate

s

Q 2 8P M B S 3 9 0 6

c o n n _ c h _ m o d e

0[V] .. 3.3[V] to+15.x[V] .. -15.x[V] level shifter

Level shifter supply ORing (used to close the pass MOSFETwhen +-15.8V supplies are powered off, but DUT is powered on;about 0.2mA is consumed from DUT)

mod

esw

_p_

out_

znr_

anod

mod

esw

_p_

c2

R17

147

k

m o d e s w_ p _ b 1 Q 2 92 N 3 9 0 4

R 1 7 5 4 7 0 k

mod

esw

_p_

c1

R17

747

k

R17

347

0k

V C C _ 1 5 p 8

mod

esw

_p_

b2

V S S _ m 1 5 p 8

D 4 0

R B 4 1 1 D

D 4 1

R B 4 1 1 D

Q 3 02 N 3 9 0 4

R17

447

0km

odes

w_p

_b3

ld o _ m o d e s w_ v o u t

m o d e s w_ p _ b u lk s

R17

247

km

odes

w_p

_c3

mod

esw

_p_

OR

ed15

V

R 1 7 6 1 0 k

Q 2 7 BS i4 9 4 3 B D Y3

4

56

Q 2 7 A

S i4 9 4 3 B D Y

12

78

D44

1N41

48

D45

1N41

48

D43

BZ

V55

-C15

D42

BZ

V55

-C15

NC

• A low-resistance circuit used to switch between the source and sink modes

– Resistance X mOhm

– Switching time Y msec

Implementation – Schematics SSM Module : Current sensing

A fully differential instrumentation amplifier reads the voltage across a 30mOhm resistor in the power path, amplifying it by X times before feeding a differential pair to the ADC. Amplifier bandwidth is 1 MHz.

-

++

-

U 2 4 A

L T1 1 2 6 C S 8

78

1

26

-

++

- U 2 4 B

L T1 1 2 6 C S 8

54

3

26

Fully diff. instrumentation amplifier(1st stage - one pole, 2nd stage - 2 poles)

PD# hasinternalpull-up

V C C _ 1 5 p 8

Positive !!!

-

++

-

PD

#

U 2 5

TH S 4 1 3 0 C D G N

12

3

4

5

67

8

EP

R 7 92 . 8 k 1 %

R 8 22 . 8 k 1 %

vd

iff+

_fb

dif

f+

m o d e s w_ c u rrs e n s e _ v o u tc u rrs e n s e _ d u t _ v o u t

p re +

p re -

V C C _ 1 5 p 8

rga

in+

R 8 72 . 8 k 1 %

R 8 01 5 k 0 . 1 %

vd

iff-

_fb

a d c c _ c u rrs e n s e _ v o c m

c u rrs e n s e _ a d c c _ o u t -

cu

rrs

en

se

_in

-

c u rrs e n s e _ a d c c _ o u t +

rga

in-

C 1 4 74 7 p F 1 %

R 8 62 . 8 k 1 %

R S 4 A 3 0 m O h m L V K 1 2 R 0 3 0 F E R

12

34

V S S _ m 1 5 p 8

R 8 41 5 k 0 . 1 %

R 8 51 . 4 7 k 1 %

V C C _ 1 5 p 8

C 1 4 9 1 0 p F 1 %

R8

37

.87

k 1

%

C 1 4 4 1 0 p F 1 %

C 1 4 8 1 0 p F 1 %

dif

f-

R 8 11 . 4 7 k 1 %

Sourced current ==>

C 1 4 3 1 0 p F 1 %

<== Sunk current

V S S _ m 1 5 p 8

cu

rrs

en

se

_in

+

Implementation – Schematics SSM Module : Power distribution example

F B 1 9B K 2 1 2 5 H S 1 0 1

N C

F B 1 3B K 2 1 2 5 H S 1 0 1

D 4 6 R B 4 1 1 D

V S S m 1 5 p 8 _ b a t

V S S m 1 5 p 8 _ wa ll

V S S m 1 5 p 8 _ b a t

V S S m 1 5 p 8 _ b a t

V S S m 1 5 p 8 _ wa ll

V S S m 1 5 p 8 _ wa ll

V S S m 1 5 p 8 _ b a t

V C C _ R E G

F B 1 4B K 2 1 2 5 H S 1 0 1

R1

94

47

k

1 5 p 8 in v _ p in

V C C 3 p 3

Q 3 82 N 3 9 0 4

F B 1 6B K 2 1 2 5 H S 1 0 1

F B 1 8B K 2 1 2 5 H S 1 0 1

15

p8

inv

_g

ate

Q 3 9I R L 3 7 1 4 P B F

F B 1 2B K 2 1 2 5 H S 1 0 1

N C

-15.8V inverter / ORing

V S S m 1 5 p 8 _ wa ll

Q 3 6P M B S 3 9 0 6

Q 3 5F Q P 2 7 P 0 6

V S S m 1 5 p 8 _ wa ll

V S S m 1 5 p 8 _ c h 4V S S m 1 5 p 8 _ b a t

-15.8V distrib. to channels ==>

R2

19

47

0k

inv

_s

w_

c1

V S S m 1 5 p 8 _ c h 3

15

p8

inv

_e

n

V S S m 1 5 p 8 _ c h 2

inv

_s

w_

b2

V S S m 1 5 p 8 _ c h 1

F B 1 5B K 2 1 2 5 H S 1 0 1

N C

1 5 P 8 I N V 1

1 5 P 8 I N V

1 5 p 8 in v _ in

1 5 p 8 in v _ o u t

1 5 p 8 _ e n

V C C 1 5 p 8 _ wa ll

R2

02

47

k

R1

91

47

k

R1

90

47

0k

inv

_s

w_

b1

V C C 1 5 p 8 _ wa ll

Q 3 72 N 3 9 0 4

R1

95

47

k

F B 1 7B K 2 1 2 5 H S 1 0 1

N C

Negative rail

Generation of the -15.8V supply rail from battery or the +15.8 DC input and its distribution to the different channels

Implementation – Schematics SSM Module : DC-DC Cuk Converter

A converter that inverts the +15.8V power input to generate a 0..-12.6V output:

A

B

U 1 7

F A N 3 2 2 7 TM X

E N A1

I N A2

O U TA7

I N B4

E N B8

O U TB5

VD

D6

GN

D3

C 1 1 3 1 5 0 u F 2 0 V

c o n n _ c u k _ s w1

c o n n _ c u k _ s w2

Q 4 6I R L 3 7 1 4 P B F

C 1 1 2 1 5 0 u F 2 0 V

Q 4 7I R L 3 7 1 4 P B F

F B 9 B L M 2 1 P G 2 2 1 S N 1

c u k _ c c

TX2

C M S 1 -2 -R

1

2 3

4 c u k _ o u tc o n v _ ld o _ a d c 4 c h _ v o u t

c u k _ s w2 _ g a t e

c u k _ s w1 _ g a t e

cu

k_

sw

no

de

_in

F B 2 3 B L M 2 1 P G 2 2 1 S N 1

V C C 1 5 p 8 _ wa ll

Negative output

C1

07

4.7

uF

50

V

C1

08

10

0n

F 5

0V

C1

10

22

uF

35

V

C1

11

22

uF

35

V

cu

k_

sw

no

de

_o

ut

Implementation – Schematics SSM Module : 4-Ch 10-bit ADC

Measuring the outputs of the DC-DC converters before the post-regulator in each of the 4 channels

R2

35

31

.6k

1%

R2

33

10

k 1

%

R2

34

10

k 1

%

+

-+

-

Vostrim

NC U 4 8

L M 7 4 1 C M

1

2

3

4

6

7

58

c o n v 3 _ ld o 3 _ a d c 4 c h _ v o u t _ lc o n v 4 _ ld o 4 _ a d c 4 c h _ v o u t _ l

L 2 1 . 8 u H 0 . 9 5 O h m

R 2 3 6 5 . 6 2 k 1 %

L 3 1 . 8 u H 0 . 9 5 O h mL 4 1 . 8 u H 0 . 9 5 O h mL 5 1 . 8 u H 0 . 9 5 O h m

V C C 1 5 p 8 _ wa ll

V S S m 1 5 p 8 _ wa ll

10-bit ADC

U 8

A D 7 9 1 4 B R U Z

VD

RIV

E1

5

V I N 39 V I N 2

1 0 V I N 11 1

D O U T1 4

S C L K1

V I N 01 2

R E F I N7

AG

ND

16

AG

ND

8A

VD

D6

AV

DD

5

AG

ND

13

AG

ND

4

C S #3

D I N2

v c c 3 p 3 _ a d c 4 c h

V C C 3 p 3

c o n v 1 _ ld o 1 _ a d c 4 c h _ v o u t _ l

c o n n _ a d c 4 c h _ c s -

c o n n _ a d c 4 c h _ s c lkc o n n _ a d c 4 c h _ d in

c o n v 1 _ ld o 1 _ a d c 4 c h _ v o u t

a d c 4 c h _ c o n n _ d o u t

a d c 4 c h _ d iv 3a d c 4 c h _ d iv 4

ad

c4

ch

_4

_v

-

R 2 2 9 4 7 kR 2 3 0 4 7 kR 2 3 1 4 7 k

C8

91

00

nF C

86

10

0n

F

C8

71

00

nF

C8

81

00

nF

v re f _ 2 p 5

Inverts the Cuk converter's output

a d c 4 c h _ d iv 1

LC input filters:

Division ratio Rup/(Rup+Rdn): .... 47k/(47k+10k) = 14.25V/2.5VInput divider:

-3dB freq.: ...................... 100 kHzAttenuation at Fs/2=500kHz: ...... 31.7 dB (38.5 times)

F B 5

B K 2 1 2 5 H S 1 0 1

C9

02

.2u

F

c o n v 2 _ ld o 2 _ a d c 4 c h _ v o u ta d c 4 c h _ d iv 2

C 2 8 3 1 0 0 n F 5 0 VC

91

2.2

uF

R2

32

10

k 1

%

C9

22

.2u

F

C9

32

.2u

F

c o n v 2 _ ld o 2 _ a d c 4 c h _ v o u t _ l


C 2 8 4 1 0 0 n F 5 0 V


Implementation – Simulations Introduction

• Environment:– PSPICE– LTSPICE– Texas Instruments simulator

• Simulation goals:– Switching times– Stability (open + closed loop)– Voltage levels– Reliability

• Key simulations:– Power ORing circuits– All amplifier circuits (LDO, active load, active filters)– All analog switches

• Major obstacles– Highly non-linear circuits– Unknown external load parameters

Implementation – Simulation Active load – open loop response

• Below is shown a PSPICE simulation of the open loop response of the active load circuit:– Load current: 200mA– DUT voltage: 12.6V– 0-dB point – 4Mhz– Phase margin: 71.4deg– Gain margin : 25.5dB

Green: Open loop gain (dB)Red: Open loop phase (deg)

Implementation – Simulation Active load – transient behavior

• Below is shown a PSPICE simulation of the transient behavior of the active load circuit:– Load current step: 1A with a rise/fall time of 500ns (2MHz)– DUT voltage: 12.6V– Overshoot: 95mA– Settling time: 300ns to within 5%– Assumed lead inductance of 0.5uH and contact resistance of 150mOhm

Green: Control input voltageRed: DUT current

Implementation – SimulationInstrumentation amplifier – frequency response

• Below is shown a PSPICE simulation of the frequency response of the instrumentation amplifier used as the active filter in the current sense circuit:

– Bandwidth: 1MHz– Maximum ripple within bandwidth: 0.4dB– DC gain: 19.5dB

Green: Control input voltageRed: DUT current

Implementation – SimulationMode switch circuit - transient

• Below is shown a PSPICE simulation of the frequency response of the switching circuit used to select between the source and sink functions

– Switching time:– Maximum resistance:

Implementation – Debug

• Control module:– ICSP port– JTAG port– 2 MICTOR connectors in parallel to most major data and control lines– 2 free Cypress ports available for debugging (test points)– 4 DIP switches and 4 LEDs on dedicated debug IOs of FPGA– Ground test points spread across the board

• SSM module– Ground test points spread across the board– Most components in packages with leads to enable easy connection

Topics






Layout Introduction

• Environment– OrCAD 16.0 netlists– Mentor PCB Layout tools

• Design Guidelines– Signal reliability (minimize crosstalk and parasitics)– EM compatibility (low emissions and susceptibility)– Thermal considerations– Mechanical considerations

Layout Control Module - Overview

• 167x168 mm• 6 layers• 1 oz copper • Stackup:

1.Component side: signal

2.Ground

3.Signal + low power

4.Signal + low power

5.Power

6.Print side: signal

• Components on both sides

Connection to SSM module

PowerC

on

nectio

n to

UI m

od

ule an

d d

ebu

g in

terfaces

Deb

ug

Control hardware

Layout SSM Module - Overview

Layout SSM Module – Signal path

Layout SSM Module – Power path

Layout SSM Module – Power planes

Layout UI Module

Layout SSM Module – Overview

• 157x168 mm• 8 layers• 1 oz copper• Stackup

– Component side: signal– Layer 2: power– Layer 3: signal (horizontal)– Layer 4: signal (vertical)– Layer 5: GND– Layer 6: differential striplines– Layer 7: GND– Print side: signal


Layout UI – Overview

• 110x230 mm• 2 layers• 1 oz copper• Stackup

– Component side: signal + power– Print side: signal + power


Topics






Mechanical Design Introduction

• 3 boards – one system case– Hard plastic (ABS) case: 260x180x105 mm– Battery and power supply included– Cutouts: user interface and connectors (power, USB)

• Environment– Google SketchUp 6.0

Mechanical Design User Interface

• Graphic 128x64 LCD (up to 8x16 text characters)• 4x4 Keypad + ‘Enter’ key• 4 ‘soft’ keys under the LCD• 4 LED indicators• Power on / battery on indicator• Buzzer

Mechanical Design Thermal characteristics

• Characteristics:– When sinking current, each channel can generate up to 25W of heat

– When sourcing current, losses of up to 3W per channel are expected

– Self-power circuits exhibit efficiencies of around 90%, meaning thermal losses on the order of up to several watts overall

• Solutions:– Ventilation holes throughout the case

– All heat-generating components chosen so that they can withstand the temperature rise

– Big custom-made heatsink attached to the transistors of the source/sink stages

– External fans will be added to the case

– Constant temperature monitoring by the MCU enable shutdown in case of overheating

Statistics

1 project

2 partners

3 boards

10 months

~60 breakfasts at Zoran

129 different electronic components

~1700 man-hours

996 nets

1221 total electronic components

4017 solder pads

609 710 399 bytes in project folder

From now on:

Looking for code monkeys

Documents

PowerBench Programmable Power Supply Final presentation – part B March 22 th, 2009 Gregory Kaplan Dmitry Babin Supervisor: Boaz Mizrahi HS DSL