310 Philips Tech. Rev. 44, No. 8/9/10, 310-320, May 1989

Power integrated circuits

M. Amato, G. Bruning, S. Mukherjee and 1. T. Wacyk

Microelectronics has made a great impact on the development of electronic systems, especiallyin signal processing and computing. This has been mainly due to the reduction in transistorsizes and the advanced fabrication techniques now available for very-large-scale integrated(VLSI) circuits. One of the factors common to these integrated circuits, however, is that theyoperate at low currents and low voltages (e.g. 5 V); they cannot conduct high currents or di-rectly withstand high voltages. This means that VLSI circuitry cannot interface directly withpower equipment or fuljill other common requirements for power handling. However, recentadvances in power devices, analogous to the developments in VLSI circuits, have led to verymuch smaller dimensions for integratable power devices and to new gate-controlled devicestructures requiring very little drive power. These developments make an integrated circuittechnology combining power devices and low-voltage control circuitry economically viable.The components made in this technology are known as Power Integrated Circuits or PICs.A special category of PICs, known as High- Voltage Integrated Circuits (HVICs), provideshigh-voltage interfacing at relatively low currents, generally between logic circuits and very-high-power discrete devices.

Introduetion

Power IC technology is attractive for many rea-sons. Enhanced performance, increased reliability,and reduced cost are among the benefits that resultwhen a number of discrete components are replacedby a PlC. Entirely new system approaches also be-come feasible, such as multiplexed power distributionfor automobiles.

On the performance side PICs offer a numberof de-sirable features. The noise level in power electroniccircuits is usually very high as a result of fast high-voltage and current switching, e.g. 500V in 20 ns at a2-Jls repetition interval. In discrete circuits wiring in-ductances and stray capacitances tend to be sensitiveto this noise and require very special care in layoutand design. In a PlC, interconnecting leads are soshort that the inductive pick-up is significantly re-

M. Amato, G. Bruning, Dr S. Mukherjee and Dr J. T. Wacyk arewith Philips Laboratories, North American Philips Corporation,Briarc/ijf, New York, U.S.A.

duced. Capacitive coupling is also reduced since theparasitic capacitances are lower.

On-chip proteetion such as thermal shutdown canbe directly linked to the power device instead of at-taching a temperature sensor to a heat sink on which adiscrete power device is mounted. This is very impor-tant as this possibility demonstrates both a functionaladvantage and a saving in discrete components. Con-trol circuits for over-current and over-voltage protee-tion may now be added where economic aspects for-merly prohibited this and called for overdesign.The incorporation of intelligence into power circuitscan have such distinct effects that it is sometimesreferred to as 'smart power' [11.

For all these reasons PICs are likely to enhance per-formance and have an impact on manufacturing costby component reduction. Although the advantagesare manifold there are challenges to meet as well.Owing to the increased process complexity, the cost of

Philips Tech. Rev. 44, No. 8/9/10

manufacturing PICs per unit area of silicon is higherthan for discrete power devices. The' cost advantageof a PlC over a discrete implementation depends onthe overall system economics, where the benefit isderived from a lower package count, smaller printed-circuit board, less weight, etc. Furthermore, since theapplications in power electronics are very diverse, ahigh degree of flexibility in power devices is required.Both difficulties are addressed by offering more con-trol capability, smaller power device structures, in-creased reliability, and a fast turn-around design cycleresulting from advanced design methods.

Power electronics can be found today in any ma-chine or device which requires a form of electricityother than that supplied by the primary source (e.g.from the utility company) and where a high degree ofregulation of output voltage, output current or out-put power is desired. Fig. 1 illustrates the diversity of

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DFig. I.Typical applications for Power Integrated Circuits (PICs) asa function of operating voltage Vop and load current 11, To empha-size the differences from other IC technologies, dashed lines in-dicate the practical working ranges for common digital IC tech-nology and linear bipolar IC technology. HVICs are special typesof PICs which can function as interfaces between ICs fabricated indifferent technologies.

applications and operating requirements for PICs.Some typical examples are:• switched-mode power supplies or switching regula-tors, which efficiently convert a.c. power into d.c.power and are found in almost all computers, televi-sion sets and electronic equipment;• motor controls, which provide precise speed andtorque control in applications including washing ma-

POWER ICs 311

chines, compressor motors, disk drives and shavers;• electronic ballasts for discharge lamps, which givelower energy consumption for a given amount oflight;• automotive switches, which replace mechanicalrelays and expensive heavy wiring harnesses.The interface between large discrete power devices

and the common low-current, low-voltage ICs can bemade by High-Voltage Integrated Circuits (HVICs),which operate at relatively low currents and high volt-ages. These are also indicated in fig.l.PlC technology is the result of a number of recent

advances in microelectronics. These include integrat-able power devices such as the Lateral Double-dif-fused MOS (LDMOS) transistor and the Lateral In-sulated-Gate Bipolar Transistor (LIGBT), and thedevelopment of a fabrication process which combinesboth low-voltage CMOS control and these power de-vices on the same chip. The problem of making fulluse of these advances has also been addressed at thesame time. The construction of a structured designmethod permits the non-expert designer of ICs andpower devices to design application-specific PICsbased on a standard-cell approach and a highly auto-mated layout technique. Examples of power inte-grated circuits [21 are depicted in jig.2. The figureshows two versions of a PlC designed for a televisionswitched-mode power supply. These circuits combinea 500-V/5-A switch with all the control and proteetionfunctions, including on-chip over-temperature protec-tion, which are required by the television powersupply. In fig. 20 an LDMOS transistor, which is thedominant structure on the chip, has been used for thepower switch, whereas in fig. 2b an LIGBT is shown.The LIGBT is a relatively recent development and,because it can handle a higher current density than theLDMOS device, it clearly results in a smaller andcheaper chip for a given function. The control circuitis located under the power devices and is the same inboth cases.In the following sections we shall first give a detailed

description of the devices and the technology whichcan be used in the fabrication of economically attrac-tive PICs. We shall make a distinction here betweenhigh-voltage circuits and high-current circuits, whichrequire different approaches. Then we shall explainour design methodology, since the ease of design is adecisive factor in the economic viability of PICs, andeven more so for Application-Specific PICs (ASPICs).

[1] D. Paxman, Smart power, Phys. World, No. 2 (January),26-28, 1989.

[2] S. Mukherjee, M. Amato, I. Wacyk and V. Rummennik,LDMOS and LIGT's in CMOS technology for power in-tegrated circuits, Int. Electron Devices Meeting, WashingtonD.C., 1987, Tech. Digest, pp. 778-781.

312 M. AMA TO et al. Philips Tech. Rev. 44, No. 8/9/10

a

Fig.2. Two examples of a PlC for application in a televisionswitched-mode power supply. The large structures are the powertransistors. The intricate, finely detailed structures are the signal-processing circuitry for control and proteetion and are the same forboth ICs. a) The power transistor here is of the Lateral Double-diffused MOS (LDMOS) type; the area is 22 mm". b) When aLaterallnsulated-Gate Bipolar Transistor (LlGBT) is used, the totalarea can be reduced to 11 mm",

Devices and technology

Research on semiconductor power devices that canbe used in PIes is concentrated on two main devicegroups:• high-voltage devices (breakdown voltage> 250 V),and• high-current devices (on-current> 5 A).

In both, reducing the size of the power device for thesame function is a main objective of the research. Inmany applications power devices occupy more thanhalf the area of the PlC chip. This means that reduc-tion of power-device size is a key to increased perfor-mance per unit cost.

High voltage

The high-voltage PlC technology developed at thePhilips Research Laboratories in Briarcliff (NewYork, U.S. A.) combines low-voltage CMOS controlcircuits with high-voltage transistors on a single siliconchip. High-voltage devices can be made as vertical orlateral structures in PlC technology. Integration ofvertical high-voltage transistors and low-voltage con-trol circuitry requires the use of thick or multiple epi-taxial layers, or complicated and expensive dielectricinsulation. Lateral power-device integration, on theother hand, requires only a thin epitaxial layer(5-10 urn), which is more compatible with standardlow-voltage process technology.

Normally the high-voltage transistors are operatedas switches. For low power dissipation, the high-voltage transistors must be capable of blocking highvoltages with small leakage currents when 'off' andhave a low forward-voltage drop when the switch is'on'. Two types of lateral high-voltage output tran-sistors are used: the LDMOS and the LlGBT. Thesetransistors are capable of operating over a wide rangeof voltages (up to more than 1000 V), frequencies (upto several megahertz) and currents (up to several am-peres).

The integrated LDMOS transistor is a MOS-baseddevice with a lateral buffer zone (drift region) betweenthe active channel and the output (drain) of the tran-sistor. When the transistor is 'off' the drift regiondepletes, so that the voltage decreases laterally acrossthe transistor. A cross-section of an LDMOS tran-sistor is shown in fig. 3, indicating the high-voltagedrift region associated with the device. The depletionof the drift region is a two-dimensional effect, whichis called RESURF (for REduced SURFace electricfields [3J [4J. This effect is controlled during the manu-facture of the IC by ion implantation and diffusion ofthe moderately doped drift region. LDMOS powertransistors, unlike bipolar transistors, are majority-carrier devices and are capable of operating at veryhigh frequencies. However, the drift region acts as ahigh resistance when the device is 'on', and higher-voltage devices require longer drift regions. The driftgeometry, drift doping, buried layer, and substratedoping levels must be optimized to give the highestbreakdown voltage with the lowest resistance for agiven silicon area.

Philips Tech. Rev. 44, No. 8/9/10

LDMOS

______ L~d ,~

poly drifl region

Fig.3. Cross-sectional view of a Lateral Double-diffused MOS(LDMOS) device. S source, G gate, D drain. The drift region has alength Ld' The significanee of the other designations is:Psub p- -type substratePb p-type buried layerPc p-type diffusion for channelPiso p+-type isolation diffusionnepi n-type epitaxial layernw n-type welln+ n" -type diffusion for source and drainAI aluminium metallizationPoly polysilicon layerSi02(l) silicon 'field' oxide from LOCOS processingSi02(2) silicon isolation oxide(Between the conducting polysilicon layer and the semicond uctingchannel diffusion there is always a very thin insulating Si02 layer ofsome tens of nanometers; this is not shown explicitly here or in thefollowing figures.)

5

3

2'-------'------'-----'----------'100 200 300 500 1000V

Fig.4. Specific on-resistance Ron A plotted against breakdown volt-age Vbf for a typical LDMOS transistor (simulated results); Ronrepresents the resistance in Q and A the silicon area of the transistorin mm",

[3] J. A. Appels and H. M. J. Vaes, High voltage thin layer de-vices (RESURF devices), Int. Electron Devices Meeting, Was-hington D.C., 1979, Tech. Digest, pp. 238-241.

[4] S. Co lak, Effects of drift region parameters on the static prop-erties of power LDMOST, IEEE Trans. ED-28, 1455-1466,1981.

[5] M. Darwish and K. Board, Lateral resurfed COMFET, Elec-tron. Lett. 20, 519-520, 1984.

POWER les 313

The specific on-resistance of a transistor is definedas the resistance at a specific breakdown voltage forunit area of silicon. A lower specific on-resistance (in-dicated by Ron'A and with the dimension Q'mm2)

means a more efficient design which translates into asmaller chip size for specified power dissipation and alower silicon cost. The relationship between specificon-resistance and breakdown voltage for a typical in-tegrated LDMOS transistor is shown in fig. 4. When ahigh current and a low power dissipation are required,the LDMOS transistors are laid out with the sourceand drain regions interdigitated, increasing the chan-nel width and reducing the total on-resistance. Thiscan be seen in the diagrams of the switched-modepower supply chip in fig. 2. The LDMOS transistor isbest suited for high-frequency applications where ther.m.s. load current is less than 1A.Although the LDMOS has been one of the pioneer-

ing MOS power devices in PIes for high-voltage ap-plications, the major limitation of this device is arelatively high specific on-resistance due to the ma-jority-carrier conduction. For high voltages (> 250V)the major contributor to the on-resistance is the driftregion shown in fig. 3. Since the drift region is de-signed to sustain the drain voltage in the off-statewithout reaching the critical breakdown field in sil-icon, the doping of this region is limited by theRESURF conditions. In order to overcome this lim-itation the LIGBT was developed [51. In the LIGBT, aminority-carrier injector is provided at the drain endas shown in fig. 5a. The injection of minority carriersinto the drift region in the on-state modulates the con-ductivity of the drift region and thereby reduces theeffective on-resistance of the transistor. Therefore,for a similar device size, the LIGBT exhibits a loweron-resistance than the LDMOS by a factor of 5 ormore depending upon the breakdown voltage and cur-rent level. This device can also be viewed as a MOS-gated bipolar transistor. Tn the LIGBT, the minority-carrier injection, or the bipolar transistor turn-on,occurs above a certain drain voltage (0.6 V) requiredfor forward bias of the injector junction. Below thisvoltage the device does not turn on, producing an ad-ditional nonlinearity in the current/voltage charac-teristics as compared with the LDMOS shown infig. 6.However, in switching applications this nonlinearitydoes not pose a limitation except for setting a lowerlimit to the voltage drop across the device in theon-state.The injection of minority carriers in the LIGBT

device results in increased turn-off delay (1-3 IlS) forthe structure shown in fig. 5a as compared with theLDMOS (10 ns), because of storage-time effects. Animprovement in the turn-off time of the LIGBT is

314 M. AMATO el al. Philips Tech. Rev. 44, No. 8/9/10

standard L1GBT

~ ~L~d ~

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G

b

Fig.5. a) Cross-sectional view of a Lateral Insulated-Gate BipolarTransistor. The device looks very much like an LDMOS (see fig. 3),but the drain diffusion is now of the p+-type and is made in a regioncalled nbuf which is intended to prevent punch-through from thedrain to the substrate. The combination of drain and drift regionfunctions as an injector junction. Conduction in the on-state is there-fore due to both majority carriers and minority carriers, which re-duces the on-resistance by a factor of 5 or more. b) Introducing anadditional shorting nt-diffusion at the drain gives a 'shorted-anodeLlGBT' or 'clamped-anode LIGBT'. This device combines the ad-vantages of the LDMOS transistor and the LIGBT.

10A .-------------

shorted-anode LIGBT

-vosFig. 6. Typical characteristics showing drain current ID plotted againstdrain/source voltage Vos for an LDMOS transistor, an LlGBT andtwo shorted-anode LIGBTs.

achieved by incorporating a shorting n+-diffusion atthe drain as shown in fig. Sb [61 [71. The addition ofthis shorting diffusion results in more efficient removalof electrons thereby decreasing the turn-off time toless than 330 ns. Additionally, the shorting n" -diffu-sion enables conduction of this 'shorted-anodeLIGBT' prior to the turn-on of the injector junctionin a manner similar to the LDMOS, thereby reducingthe voltage drop across the device and the power lossduring switching. The d.c. current/voltage charac-teristics of the shorted-anode LIGBT are shown infig.6 for two cases, together with those of the conven-tional LIGBT and LDMOS. From this figure it is clearthat at high forward voltages the current level of theshorted-anode LIGBT is similar to that of the con-ventional structure because of the dominance of theconductivity modulation and bipolar conduction.

The high-voltage 'Briarcliff' IC process is based ona junction-isolated technology utilizing a relativelythin (6-7 urn), high-resistivity, n-type epitaxiallayer.The process architecture is based on a dual-well low-voltage CMOS process with self-aligned n-wells andp-wells, as shown in the cross-section of fig. 7. Thep- -substrate ensures good high-voltage operation inthe lateral LDMOS and LIGBT devices, while theburied n"-layer provides latch-up suppression in theCMOS control portions of the chip. The n-well is usedfor the channel in the low-voltage PMOS transistorsand for the drift region in the LDMOS and LIGBTdevices. The buried p-layer provides extra field shap-ing in the LDMOS and LIGBT high-voltage devices.A heavily doped p+-diffusion in source areas of thehigh-voltage transistors provides latch-up suppressionin the LIGBT, better proteetion from inductive surgesand insulation from the low-voltage circuitry. Howev-er, it is not necessary to provide this insulation in thecontrol-circuit sections of the chip. The technologyfeatures self-aligned-to-polysilicon NMOS, PMOSand LDMOS/LIGBT channels on 600 Á (60 nm) ofgate oxide. It also features standard LOCOS proces-sing, 3-Jlm design rules, and two polysilicon ('poly')layers for high-quality poly/poly capacitors and in-sulated poly resistors.

Several issues need to be considered in combiningLIGBTs with CMOS devices. The interaction of mi-nority carriers generated by the LIGBT with theCMOS low-voltage sections is one of the most impor-tant considerations. In this respect the shorted-anodeLIGBT described earlier, turns out to offer a partien-larly promising approach. The anode short, com-bined with the buried layer and the deep isolationdiffusions, helps to confine the minority carriers closeto the power device and extract them efficiently. This,combined with n-type and p-type buried layers in the

Philips Tech. Rev. 44, No. 8/9/ JO

low-voltage CMOS

poly(2)poly(l)

capoeitor Y PMOS

Fig. 7. Cross-section of low-voltage CM OS devices that can easily becombined with the high-voltage devices of fig. 3 and fig. 5. This figureshows an NMOS transistor, a PMOS transistor and an integratedcapacitor. The significanee of the designations not given earlier is:p; p-type wellPf p-type 'field' diffusionnb n" -type buried layerThe field diffusion is also called a 'channel-stop' diffusion because itshould prevent the formation of parasitic channels.

low-voltage sections, has been found to be adequatein eliminating the interaction problems with low-voltage CMOS circuits.

High current

In high-current applications the Vertical DMOS(VDMOS) is the most commonly used MOS gate-con-trolled power device. In this type of device the drain issituated under the source (jig. 8a), hence the term'vertical'. The major contributors to the on-resistancein this device are the channel resistance and the pinchresistance. The reduction of these two components istherefore a primary goal and is most convenientlyachieved by reducing the cell size by advanced lithog-raphy and minimizing the spacing between the ad-jacent channel regions also known as the pinch orJFET region (JFET = Junction Field Effect Tran-sistor). Reducing the size of the pinch region helps toreduce the size of the cell but also tends to increase thepinch resistance. Therefore an optimization is calledfor.

With the advent of silicon trench-etching tech-niques using reactive ion etching (RIE) an alternate ap-proach becomes feasible. Instead of fabricating the

[6] R. Jayaraman, V. Rumennik, B. Singer and E. H. Stupp,Comparison of high voltage devices for power integrated cir-cuits, Int. Electron Devices Meeting, San Francisco, Cal.,1984, Tech. Digest, pp. 258-261.

[7] P. A. Gough, M. R. Simpson and V. Rumennik, Fast switchinglateral insulated gate transistor, Int. Electron Devices Meeting,Los Angeles, Cal., 1986, Tech. Digest, pp. 218-221.

[8] S. Mukherjee, M. Kim, L. Tsou and M. Simpson, TDMOS-an ultra-low on-resistance power transistor, IEEE Trans.ED-35, 2459, 1988.

POWER ICs 315

channels on the silicon surface, thereby using up sil-icon area, the silicon trench provides the possibility ofconstructing the MOS transistor channel along thetrench side wall yielding a Trench Double-diffusedMOS (TDMOS) transistor (fig.Sb) [8]. This in ef-fect provides a pseudo-three-dimensional integration,thereby increasing the silicon area efficiency (morechannel width for the same silicon area). Additionally,by providing an even more pronouncedly vertical cur-rent path the pinch resistance is dramatically reducedas compared with conventional VDMOS transistors.The combination of these factors results in a substan-tial reduction in specific on-resistance.The above approach has been used in a five-mask

process for fabricating TDMOS transistors with rectan-

VDMOS

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Fig. 8. a) Cross-section of a Vertical Double-diffused MOS (VDMOS)device. A part of a periodic (e.g. interdigitated) structure is shownhere, so that multiple sources can be identified. The basic unit iscalled a cell and the cell pitch is indicated by Leen. The drain is situ-ated beneath the sources and the electron flow in the conducting stateis represented by dashed arrows. A number of resistances affect themagnitude of the electron flow: the channel resistance Rc, the accu-mulation resistance Race, the pinch resistance Rpineh, the epitaxial-layer resistance Repi and the resistance Rsub of the n" -type substratensub' b) An increased channel density per unit area of silicon and con-siderable reduction of the pinch resistance can be obtained by usingtrench-etching techniques. Here a cross-section of the resultingTrench Double-diffused MOS (TDMOS) transistor is shown. Thechannel is no longer situated on the surface of the silicon crystal, butvertically, next to the gates.

316 M. AMA TO et al. Philips Tech. Rev. 44, No. 8/9/10

gular cell geometry. A Scanning Electron Microscopie(SEM) cross-section of one of the transistors is shownin fig.9a. Fig.9b shows the current/voltage charac-teristics of this transistor. The specific on-resistancefor the device is 50 mO'mm2 with a breakdown volt-age of more than 60 V. For comparison, the specificon-resistance that can be achieved with conventionalVDMOS for the same voltage range is several timeshigher than this.

a

b

Fig.9. a) Cross-section of a TDMOS transistor made by scanningelectron microscopy (SEM); 1 scale division = I urn. b) Measuredcharacteristics showing drain current plotted against drain/sourcevoltage for this device; I vertical scale division = 10 mA; 1 hor-izontal scale division = 50 m V; the gate/source voltage varies insteps of 2 V.

In seeking further improvement of TDMOS de-vices, several factors have to be borne in mind.First, the current conduction along the trench sidewall results in carrier (electron) mobility degradationand consequent increase in channel resistance. Thisdegradation is strongly dependent upon the siliconcrystal lattice orientation, trench-etching technologyand the pre-gate oxidation cleaning processes. Among

the other parameters of importance, one of the mostsignificant parameters is the fixed oxide charge on thetrench side wall. This is also a function of the pre-oxidation cleaning process as well as the oxidationconditions.

The drain/ source breakdown voltage of theTDMOS transistor is determined by a combination ofn-epi and p-body doping concentration together withthe trench-etching profile. Two breakdown mech-anisms can be identified: planar junction breakdownand avalanche breakdown under the gate. In specificsituations as in the devices described above, the break-down voltage is determined by a combination of theabove mechanisms, resulting in 'field crowding' at thetrench corners. It is expected that rounded trench cor-ners will improve the breakdown voltage in suchcases. Other ways of improving the breakdown volt-age involve modification of the n-epi concentrationand thickness and p-body doping profile. Simulationsshow that by proper choice of these parameters break-down voltage can be increased with minimal changeof on-resistance.

With the maturity of the RIE trench-etching tech-nology used in VLSI memory products, the combina-tion of TDMOS devices with standard CMOS controlappears to be a practical approach for production.The technology is also compatible with standardVDMOS devices.

Design methodology

A major challenge to the widespread application ofPICs is the difficulty of translating a discrete power-system design into a functionally equivalent IC. Apower system usually interfaces to a complex elec-trical load and is required to deal with real-worldanalog voltages and currents. Because it is not easy tomodel and simulate complex systems of this type, thesystem engineer traditionally addresses the problemby building a breadboard prototype, and arrives at asolution by a process of testing and redesign. How-ever, the resulting design may not be well suited forintegration, and may require a considerable develop-ment effort to achieve an effective IC implementation.In addition, while logic ICs are designed for standard-ized electrical operating parameters, the operatingvoltages and currents for a PlC depend on the specificapplication and can range over several hundred voltsand from a fraction of an ampere to tens of amperes.So although there will be a number of standard-prod-uct PICs developed for large-volume applications, agreat number of the requirements will be specific to aparticular application requiring a customized IC im-plementation.

Philips Tech. Rev. 44, No. 8/9/10

To address the requirements of designing PICs, amethodology has been evolved in which advancedCAD techniques are used in the design of the Applica-tion-Specific Power IC (ASPIC) [91. The objective isto make PlC design available to the engineer who isnot necessarily an expert IC designer, so that powersystems are developed and optimized for integrationright from the start of the design process. A secondobjective is to make PICs economical for the largenumber of applications that only require a moderatevolume of products. This is made possible by employ-ing advanced CAD techniques to reduce the time andengineering effort required to produce customized sil-icon chips. The design methodology comprises threemajor facets:• structured design techniques;• a knowledge base of PlC design;• customized software tools for computer-aided de-sign and computer-aided engineering (CAD/CAE).First, the overall methodology is based on a frame-

work of structured design techniques that are similarto those successfully employed in digital VLSI. Thesetechniques have been extended to address the mixedanalog/digital/power environment for circuits used inPlC designs. As in any complex system, the key tosuccessfully managing the complexity is to partitionthe system into smaller modules or building blocks, sothat the design can take place at a high level of ab-straction. The specific low-level details of device andcircuit implementation are treated by experts in theseareas. In addition, the building blocks have beendeveloped in accordance with a set of rules that gov-ern their interface properties and lead to predictablebehaviour when the modules are combined into largernetworks. These rules, together with the computerprograms that execute them, form the basis of thestructured design. Several levels of abstraction areused in the PlC design process illustrated in fig. 10. Atthe top of the hierarchy is the system diagram whichconsists of the PlC represented as a functional block,circuit models for the external sources and loads, andother external components. The PlC itself can be par-titioned into various levels of increasing detail untilthe transistor-level circuit is finally reached. The rulesof the structured design are carried down to the levelof the primitive building blocks, or standard cells,which embody both analog and digital operations,and are described by simple functional relationships.An application is customized by structuring theknown functions to solve the system problem. A bene-fit of designing a system at a level of abstraction re-

[9] 1. Wacyk, M. Amato and V. Rumennick, A power IC withCMOS analog control, IEEE Int. Solid-State Circuits Conf.,Anaheim, Cal., 1986, Digest of Tech. Papers, pp. 16-17.

POWER ICs 317

moved from the detailed circuit and device structureis that when the cells are upgraded as a result of tech-nology scaling, the system can easily be 'recast' in thenew process, e.g. for improved economy or perfor-mance.

systemdiagram

///

block level •

/'/'

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Fig.IO. PlC structured design hierarchy. Severallevels of abstrac-tion are shown, with varying degrees of detail. The design at eachlevel can be carried out independently, as long as certain explicit de-sign rules are obeyed. The highest level is the diagram of the systemin which the PlC is to be applied. Then we have the block diagramof the PlC. One step lower we have the standard cells from whichthe blocks of the PlC are built up and the lowest level consists ofthe electrical circuits of the standard cells.

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Fig.11. Examples of several high-voltage transistor layouts, ob-tained ('compiled') from different sets of input parameters with thedesign program PROCEDURAL HIGH-VOLTAGE DEVICE LAYOUT GEN-

ERATOR. This program produces a complete sequence of layoutmask files for each transistor in a few minutes. The main inputparameters for the four cases are shown in the table.

Secondly, a knowledge base of PlC design in termsof power devices and power-related circuit functionsis captured in computer programs and in the compu-ter database. These form a catalog of building blocksthat contain detailed device layout structure and spe-cific circuit implementations of analog and digitalfunctions in the target technology. One example ofsuch a program is the PROCEDURAL HIGH-VOLTAGE

DEVICE LAYOUT GENERATOR [lOl. Given a set of inputparameters that may include the desired breakdownvoltage, on-resistance, physical aspect ratio, etc., thecomplete mask-ready layout is generated ('compiled')in a matter of minutes. Fig. 11 shows several com-pleted devices.The circuit functions that make up the standard-cell

library are another form of stored knowledge, andrange in complexity from simple comparators andamplifiers to high-performance pulse-width modula-tors. They include many specialized functions forpower control and proteetion as well as standardanalog and digital types. These cells are represented inseveral forms in the computer database for use indifferent stages of the design process, as shown infig. 12. The symbol designates the cell's functional be-haviour, the circuit diagram its structural form, andthe layout corresponds to its representation in thephysical domain. The cells have been specifically em-

bios~t>o",bios out+

Fig. 12. The standard cells of the structured design are representedin the computer knowledge base in several forms, as shown here fora cascode operational amplifier: a) symbol, b) circuit diagram,c) layout.

simulator automatic parameter(analog s place sdigital) route extractor

~ ~~

design using analysis GOS 1Isystem - standard I- & I-- layout mask data silicon

specification cells verification geometry foundry

~

~

packagedcelldatabase chips

Fig.13. Overview of the overall PlC design procedure. Most terms used in this diagram are self-explanatory. ODSII is a defacto standard within the IC industry for the format of layout data onmagnetic tape; it refers to the format developed for and used by CALMA layout systems.

Philips Tech. Rev. 44, No. 8/9/10

bodied in CMOS technology to conform to the struc-tured design, and to achieve low-power operation andhigh packing density.

Finally, specific CAD/CAB tools have been devel-oped and customized to automate the tedious anderror-prone aspects of the design process.Fig.13 shows the major steps in the overall design

procedure. An advanced design workstation serves as

a platform for the highly integrated set of softwareprograms. The system design is carried out using thesymbolic representation of the functional blocks. Afundamental requirement for the ASPIC design meth-odology is the ability to verify the system operationbefore silicon is fabricated. A circuit-simulation pro-gram of the type known as SPICE [ll] is used to evaluatesmall portions of the design in detail. A second ap-proach using the Continuous Logic (CLOGIC) simula-tor [12] allows a complete system-level simulation tobe carried out several orders of magnitude faster thana SPICE simulation. CLOGIC is a functional-level sim-ulator that was developed at Philips Research Labora-tories at Briarcliff specifically to address the need forverifying large-scale analog/digital circuits. In bothsimulators the appropriate netlists, which represent acomplete survey of the interconnections of all thecomponents, are generated automatically from thehigh-level system description, using the circuit rep-resentations of the standard cells. After a successfulverification, the design is reduced to a physical chiplayout in several steps. An automatic placement and

POWER ICs 319

routing program is used to create a control block di-rectly from the circuit netlist. This and the otherblocks at the top of the design hierarchy are as-sembled and interconnected into a finished chipdesign with a program developed at Briarcliff calledASPICGEN • Coded in a procedural layout language,ASPICGEN invokes layout generators for various mod-ules and automatically places and routes the high-

voltage devices, blocks of control circuitry, devicedrivers, and I/O pads according to a specified chipfloorplan.Two examples of a PlC design carried out with the

methods described above have already been shown infig.2. In both cases the power device layouts werecreated by the compilation program described earlier,the control section was implemented using standardcells, and the final chip was assembled automatically.Intended for high-frequency switching control appli-cations, the PlC contains a high-speed pulse-widthmodulator for duty-cycle control, a high-gain erroramplifier for gain and compensation, voltage and

[ID] N. J. Elias, A case-study in silicon compilation software en-gineering, HVDEV high voltage device layout generator, Proc.24th ACM/IEEE Design Automation Conf., Miami Beach,Fla., 1987, pp. 82-88.

[11] L. W. Nagel, SPICE2: a computer program to simulate semi-conductor circuits, Electronics Research Laboratory, Mem-orandum No. ERL-M520, College of Engineering, Univ. ofCalifornia, Berkeley, CaL, May 9, 1975.

[12] D. Oiannopoulos, J. C. Lin, I.T. Wacyk and J. 1.Woo, Cir-cuit simulation of power ICs, IEEE Int. Solid-State CircuitsConf., San Francisco, Cal., 1988, Digest of Tech. Papers,pp. 262-263.

320 POWER ICs

bias-current reference sources, and a proteetion andstart-up sequence controller. In a switched-modepower supply operating at a switching frequency of0.5 MHz, this chip delivered a regulated power levelof nearly 100 W. The LDMOS version has been op-erated at a switching rate of up to 3 MHz. or morewhile the LIGBT version provides comparable powercontrol in a substantially reduced chip size for fre-quencies of up to 100 kHz or more. Implementationof the analog and digital functions in CMOS resultedin a total operating current requirement for the con-trol and high-voltage device gate of less than 2.5 mAfor a switching frequency of 100 kHz.

Concluding remarks

The new technology of power integrated circuits ismaking progress similar to that in VLSI circuitry interms of size reduction and fabrication technology.The combination of control circuitry and power de-vices on the same silicon wafer provides significantopportunities for cost reduction and improved perfor-mance in power control applications. Applications

Philips Tech. Rev. 44, No. 8/9/10

such as power supplies, electronic ballasts, domesticappliances, automotive switches, and others are ex-pected to benefit as the new technology becomes as-similated into power systems design.

The valuable contributions to the development ofPI Cs by the many members of the device, process, IC& systems design, CAD, and clean-room groups aregratefully acknowledged.

Summary. Power integrated circuits (PICs) are becoming an im-portant branch of microelectronics. These circuits can be applied inmotor control, power supplies, lighting and automotive areas. Onespecific category of PlC is known as the High-Voltage IC (HVIC).The key to the economically successful design of PICs is the abilityto produce devices which can handle high voltages (several hundredvolts) or high currents (up to tens of amperes) with a small siliconarea. New device techniques which achieve this are discussed. Sincemany PI Cs have to be designed for specific applications (ASPICs),special design tools have been evolved which allow the rapid design('silicon compilation') and simulation of the entire power system.Examples of the application of these tools to a switched-modepower supply are presented.

Philips Tech; Rev. 44, No. 8/9/10, 321-324, May 1989

These publications are contributed by staff from the laboratories and other establishments that formpart of or are associated with the Philips group of companies. Many of the articles originate fromthe research laboratories named below. The publications are listed alphabetically by journal title.

Philips GmbH Forschungslaboratorium Aachen, AWeiBhausstraJ3e, 5100 Aachen, Germany

Philips Research Laboratory, Brussels, B2 avenue Van Becelaere, 1170 Brussels, Belgium

Philips Natuurkundig Laboratorium, EPostbus 80000, 5600 JA Eindhoven, The Netherlands

Philips GmbH Forschungslaboratorium Hamburg, HVogt-Kölln-StraBe 30, 2000 Hamburg 54, Germany

Laboratoires d'Electronique et de Physique Appliquée, L3 avenue Descartes, 94450 Limeil-Brévannes, France

Philips Laboratories, N.A.P.C., N345 Scarborough Road, Briarcliff Manor, N.Y. 10510, U.S.A.

Philips Research Laboratories, RCross Oak Lane, RedhilI, Surrey RHI 5HA, England

Philips Research Laboratories, Sunnyvale, SP.O. Box 9052, Sunnyvale, CA 94086, U.S.A.

A. G. Dirks& J. J. van den Broek E

G. N. A. van Veen, T. S. Bailer &J. Dieleman E

P. Bellen", J. P. Chevalier>, G. P.Martin" (·C.E.C.M.-C.N.R.S.,Vitry), E. Dupont-Nivet, C. Thiebaut& J. P. André L

P. J. A. Thijs, E. A. Montie, H. W.van Kesteren & G. W. 't Hooft E

E. A. Montie, P. J. A. Thijs & G. W.'tHooft E

A. E. T. Kuiper, M. F. C. Willemsen,J. M.G. Bax&F. H.P. H. Habraken(Univ. Utrecht) E

A. Valster, J. P. André, E. Dupont-Nivet & G. M. Martin E,L

C. W. J. Beenakker, H. van Houten& B. J. van Wees (Univ. of Technol.,Delft) E

K. A. Schouhamer Immink

F. W. A. Dime &M. Brouha

P. Philippe, W. EI-Kamali &V.Pauker L

F. E. J. KrusemanAretz

Scientific publications

321

O-AbCu formation at room temperature in meta- Acta MetalI. 37stable AI-Cu alloy films

9-15 1989

A time-of-flight study on the nanosecond laser AppI. Phys. A 47induced etching of Cu with Cla at 308 nm

183-192 1988

Chemicalordering in GaxInl_xP semiconductor Appl, Phys, Lett. 52alloy grown by metalorganic vapor phase epitaxy

Atomic abruptness in InGaAsP/InP quantum wellhetero-interfaces grown by low-pressure organo-metallic vapor phase epitaxy

Photoluminescence excitation spectroscopy ofGaxInl_xAsyPl_y/InP

Oxidation behaviour of LPCVD silicon oxynitridefilms

High-power AIGaInP three-ridge type laser diodearray

Mode interference effect in coherent electronfocusing

E Coding techniques for partial-response channels

E Soft-magnetic properties of microcrystallineCO-Fe-Si-f alloys prepared by sputtering

Physical equivalent circuit model for planar Schottkyvaractor diode

E On a recursive ascent parser

N. Willerns" , R. Collier" & J. 't'Hart" A synthesis scheme for British English intonation(. Inst. for Perception Res., Eind-hoven)

E. W. Meijer, S. Nijhuis &F. C. B. M. van Vroonhoven E

G. N. A. van Veen, T. Baller" &A. E. de Vries" (·FOM, Amster-dam) E

Poly-l,2-azepines by the photopolymerization ofphenyl azides. Precursors for conducting polymerfilms

A time-of-flight study of the neutral species pro-duced by nanosecond laser etching of CuCI at 308 nm

567-569 1988

AppI. Phys. Lett. 53 971-973 1988

ibid. 1611-1613 1988

AppI. Surf. Sci. 33-34 757-764 1988

Electron. Lett. 24 326-327 1988

Europhys. Lett. 7 359-364 1988

IEEE Trans. COM-36 1163-1165 1988

IEEE Trans. MAG-24 1862-1864 1988

IEEE Trans. MTT-36 250-255 1988

Inf. Process. Lett. 29 201-206 1988

J. Acoust. Soc. Am. 1250-1261 198884

J. Am. Chem. Soc. n09-7210 1988110

J. AppI. Phys. 60 3746-3749 1986

322

P. Boher, M. Renaud, L. J. vanIJzendoorn, J. Barrier &Y. Hily E,L

G. J. van Gurp, D. L. A. Tjaden,G. M. Fontijn & P. R. Boudewijn E

A. H. van Ommen, A. H. Reader &J. W. C. de Vries E

P. C. P. Bouten &G. de With

A. J. M. Kaizer &A. Leeuwestein E

M. de Keijser, C. van Op dorp &C. Weber E

H. F. J. van 't Blik & H. J. M.Boerrigter-Lammers E

P. J. A. Thijs, T. van Dongen, P. I.Kuindersma, J. J. M. Binsma,L. F. Tiemeyer, J. M. Lagemaat,D. Moroni &W. Nijman E,L

M. Erman, P. Jarry, R. Gamonal,J.-L. Gentner, P. Stephan &C. Guedon L

U. Dressel", U.Dormann" (*Univ.K. H. J. Buschow

Meister+ , E.Bayreuth)' &

E

Y. L. Raikher (Inst. of ContinuousMedia Mechanics, Perm) & P. C.Scholten E

SCIENTIFIC PUBLICATIONS

Structural and electrical properties of silicon nitridefilms prepared by multipolar plasma-enhanced de-position

Zinc diffusion in InGaAsP

Influence of microstructure on the resistivity ofMoSi2 thin films

E Crack nucleation at the surface of stressed fibers

Calculation of the sound radiation of a nonrigidloudspeaker diaphragm using the finite-elementmethod

Peculiar asymmetrie flow pattern in a vertical axi-symmetric VPE reactor

On the MOVPE growth ofself-aligned laser struc-tures

High quality InGaAsP-InP for multiple quantumweil laser diodes grown by low-pressure OMVPE

Monolithic integration of a GaInAs p-i-n photo-diode and an optical waveguide: modeling andrealization using chloride vapor phase epitaxy

Nuclear quadrupole interaction of gadolinium andeuropium in cubic, ferromagnetically ordered inter-metallic compounds

Magnetic colloid in an ac magnetic field; constantbirefringence effect

Philips Tech. Rev. 44, No. 8/9/10

J. Appl. Phys. 63 1464-1472 1988

J. Appl. Phys. 64 3468-3471 1988

ibid. 3574-3580 1988

ibid. 3890-3900 1988

J. Audio Eng. Soc. 36 539-551 1988

J. Cryst, Growth 92 33-36 1988

ibid. 165-170 1988

J. Cryst, Growth 93 863-869 1988

J. Lightwave Technol. 399-412 1988LT-6

J. Magn. & Magn. 91-100 1988Mater.74

ibid. 275-280 1988

F. J. C. M. Tooienaar E Silica-induced exaggerated grain growth in MnZn J. Mater. Sci. 23 3144-3150 1988ferrite

S. M. Wolfrum E Dry pressing of surface-modified powders J. Mater. Sci. Lett. 7 1130-1132 1988

A. H. Boonstra & C. A. M. Mulder Effect of hydrolyticpolycondensation oftetraethoxy- J. Non-Cryst, Solids 201-206 1988E silane on specific surface area of Si02 gels 105

H. T. Hintzen &H. M. van Noort E Investigation of luminescent Eu-doped sesquioxides J. Phys. Chem. Solids 873-881 1988Ln203 (Ln = In, Sc, Y, La, Gd, Lu) and some 49mixed oxides by 161EuMössbauer spectroscopy

H. Verweij &W. H. M. Bruggink E

R. Eppenga, M. F. H. Schuurmans&H. W. A. M. Rompa E

A.H.EI-Sayed*, G.J. Nieuwenhuys*,J. A. Mydosh" (*Univ. Leiden) &K. H. J. Buschow E

M. Erman, C. Alibert*, J. A.Cavaillès, P. Frijlink & C. Bouche"(* Univ. des Sciences et Techniquesdu Languedoc, Montpeflier) L

D. Moroni, J. N. Patillon, E. P.Menu, P. Gentric&J. P. André L

J. Haisma

A. J. Walker & P. H. Woerlee

M. G. Pitt & P. A. van der Plas

P. T. J. Biermans, T. Poorter &H. J. H. Merks-Eppingbroek E

Precision determination of the stoichiometry para-meter x of YBa2CUgOx

Ab-initio determinations of semiconductor spin-orbit splittings from ASW

Electron spin resonance in ternary intermetalliccompounds with MgAgAs structure

Assessment of a multiple quantum well and a super-lattice structure by spectroscopie ellipsometry , elec-troreflectance and photoreflectance modulationspectroscopy

Optical investigation of InGaAs-InP quantum wells

E SOl technologies: their past, present and future

E A mobility model for MOSFET device simulation ibid.

E Limitations on n+/p+ spacing due to shadowing ibid.effects in a 0.71lm retrograde well CMOS process

The impact of different hot-carrier-degradationcomponents on the optimization of submicronn-channel LDD transistors

ibid. 1063-1069 1988

ibid. 1119-1124 1988

J. Phys. F 18 2265-2281 1988

J. Physique 48(Colloque C5)

C5/139- 1987C5/142

ibid. C5/143- 1987C5/146

C4/3- 1988C4/12

C4/265- 1988C4/268

C4/553- 1988C4/556

C4/787- 1988C4/790

J. Physique 49(Colloque C4)

ibid.

G. L. J. A. Rikken*, J. A. M. M. vanHaaren", W. van der Wel (Univ. ofTechnoI., Delft), A. P. van Gelder+,H. van Kempen+ (+ Univ. Nijmegen),P. Wyder* (* Max-Planck-Inst. fürFestkörperforschung, Grenoble &Univ. Nijmegen), J. P. André,K. Ploog (Max-Planck-Inst. für Fest-kërperforschung, Stuttgart) & G.Weimann (Forschungsinst. der Deut-schen Bundespost, Darmstadt) L

R. Eppenga & M. F. H. Schuurmans Effect of bulk inversion asymmetry on [001], [110], ibid.E and [111] GaAs/AIAs quantum wells

C. W. J. Beenakker & H. van Houten Boundary scattering and weak localization of elec- Phys. Rev. B 38E trons in a magnetic field

Philips Tech. Rev. 44, No. 8/9/10

M. L. Verheijke & R. M. W. JansenE

M. L. Verheijke & R. M. W. JansenE

T. S. Bailer, G. N. A. van Veen &J. Dieleman E

A. Heerschap, J. J. van Vaals, A. H.Bergman, J. H. den Boef, P. H. J.van Gerwen & E. J. 's-Gravenmade(Univ. Groningen) E

A. H. van Ommen

J. Haisma, C. Langereis, J. M. M.Pasmans & J. E. J. Schmitz E

A. Djemel*, J. Castaing* (* Lab. dePhysique des Matériaux, CNRS,Meudon) & M. Duseaux L

R. Piotrzkowski*, J. L. Robert"(*Univ. des Sciences et Techniquesdu Languedoc, Montpellier), E.Litwin-Staszewska (Polish Academyof Sciences, Warsaw)&J.P.André L

F. P. Widdershoven

J. Aarts, A.-J. Hoeven & P. K.Larsen E

G. E. W. Bauer & T. Ando (Univ.Tokyo) E

L. W. Molenkamp, G. E. W. Bauer,R. Eppenga & C. T. Foxon E,R

P. Kuiper", G. Kruizinga*, J.Ghijsen", M. Grioni*, P. J. W.Weijs*, F. M. F. de Groot*, G. A.Sawatzky* (*Univ. Groningen),H. Verweij, L. F. Feiner & H.Petersen (Berliner Elektronen-speicherring-Geselischaft für Syn-chrotronstrahlung, Berlin) E

P. Astié*, J. J. Couderc*, P.Chomel*, D. Quelard" (* Lab. dePhysique des Solides, Toulouse) &JYI. Duseaux L

M. G. J. Heijman

H. M. J. Boots & N. A. Dotson(Univ. of Minnesota, Minneapolis,MN) E

SCIENTIFIC PUBLICATIONS

The single-comparator method in thermal neutronactivation analysis extended for some (n,p) reactions

Determination of characteristic neutron flux para-meters of nuclear reactors for thermal neutronactivation analysis

The role of chlorinated surface films in excimer laseretching of Cu at low CI2 pressures

In vivo alp NMR studies of rat salivary glands at6.3 Tesla

E Low dislocation SOl by oxygen implantation

Laser recrystallization of polysilicon on mono-crystalline insulating substrates

Interaction between dislocations and In in In-dopedGaAs single crystals under high-temperature plasticdeformation

Pressure study of metastability in Ga1_xAlxAs/GaAs:Si heterojunctions

Two-terminal resistance of quantum Hall devices

E Ionized-impurity scattering due to clusters of cor- ibid.related impurities

Core-level study of the phase transition on theGe(III)-c (2x8)surface

Exciton mixing in quantum wells

Exciton binding energy in (AI,Ga)As quantum wells:effects of crystal orientation and envelope-functionsymmetry

X-ray absorption study of the 0 2p hole concentra-tion dependence on 0 stoichiometry in YBa2CuaOx

Thermal activation of plastic deformation ofundoped GaAs between 528 and 813 K

E Reactive sputter etching of magnetic materials in anHCI plasma

The simulation of free-radical cross-linking polym-erization: the effect of diffusion

323

J. Radional. & Nucl. 103-111 1988Chem.125

ibid. 113-125 1988

J. Vac. Sci. & Tech- 1409-1413 1988nol. A6

Magn. Resonance in 129-141 1988Med.8

Mater. Res. Soc. 43-52 1988Symp, Proc. 107

Microelectron. Eng. 8 105-120 1988

Philos. Mag. A 57 671-676 1988

Phys. Rev. B 37 1031-1034 1988

ibid. 6181-6186 1988

ibid.

10923- 198810926

3232-3240 1988

3391-3394 1988

3925-3930 1988

6015-6030 1988

6147-6150 1988

ibid.

ibid.

ibid. 6483-6489 1988

Phys, Stat. Sol. a 96 225-242 1986

Plasma Chem, & 383-397 1988Plasma Processing 8

Polym. Commun. 29.' 346-349 1988

324 SCIENTIFIC PUBLICATIONS Philips Tech. Rev. 44, No. 8/9/10

L.Minnema&J. M. van der Zande E Pattern generation of polyimide coatings and its Polyrn. Eng. & Sci. 28 815-822 1988application in an electrophoretic image display

L. M. G. Feijs E A formalisation of design structures

E. Delhaye, C. Rocher, M. Fichelson A 3.0 ns, 330 mW 8x8 GaAs Booth's multiplier&1. Lecuru L

L. J. M. Esser, H. C. G. van Kuijk, A smearfree accordion CCD imagerJ. G. C. Bakker, C. H. L. Weijtens&A. J. P. Theuwissen E

P. J. Severin &W. BardoeI

P. Pesqué & C. Blanc

L. J. M. Kuijpers

M. Jimenez-Melendo", A. Djemel",J. P. Riviëre", J. Castaing"(. Lab. de Physique de Matériaux,CNRS, Meudon), C. Thomas & M.Duseaux L

S. Makram-Ebeid &P. Boher

P. F. Fontein", J. M. Lagemaat, J.Wolter+ (·Univ. of Technol., Eind-hoven) & J. P. André E,L

R. H. Coursant, J. M. Tellier, L.Eyraud", P. Eyraud" (. INSA, Lab.de Génie Electrique et Ferroélectri-cité, Villeurbanne) &M. Fink (Univ.de Paris VII, Paris) L

C. Mequio, R. H. Coursant & J. M.Tellier L

M. Klee, G. M. Stollman, S. Stotz &J. W. C. de Vries E,A

A. H. van Ommen

P. W. J. M. Boumans, J. J. A. M.Vrakking & A. H. M. Heijms E

P. America & J. de Bakker (Centrefor Mathematics and ComputerScience, Amsterdam) E

J. J. P. Bruines

J. J. M. Ruigrok

P. Boher, J. Schneider, M. Renaud&J.-P. Landesman L

R. Mabon, J. P. Landesman, B. J.Schäfer & J. Bonnet (Univ. de ParisSud, Orsay) L

E Evanescent-mode coupling in a bicore fibre: experi-ments and applications

L Increasing of the grating lobe effect in multiscattersmedium

E Impact of the decrease in CFC emissions on refri-geration: target of the IlR initiative

Influence of indium on the dissociation of disloca-tions in GaAs of high temperature

L Defect pairs and clusters related to the EL2 centre in ibid.GaAs

Magnetic field modulation - a method for measur-ing the Hall conductance with a Corbino disc

Characterization of modified lead titanate piezo-ceramics. Application to the design of array trans-ducers

Characterization of piezoplastics

Preparation and transport properties of supercon-ducting layers in the Ca-Sr-Bi-Cu-O system

E Diffusion of ion-implanted group III and V im-purities in Si02

Mutual spectral interferences of rare earth elementsin inductively coupled plasma atomic emission spec-trometry - Il. Approach to the compilation and useof pseudo physically resolved spectral data

Designing equivalent semantic models for processcreation

L Time-resolved study of solidification phenomena onpulsed-laser annealing of amorphous silicon

E Theoretical and experimental investigations onshort-wavelength recording

Passivation des semiconducteurs Ill-V: utilisation deplasmas multipolaires en ambiance ultravide

Spectrometrie de photoelectrons X et UV pour lesuivi in-situ de I'exposition de GaAs (100) et (110) ades plasmas multipolaires

Proc. COMP EURO 214-229 198888 - System Design:Concepts, Methodsand Tools, Brussels1988

Proc. IEEE Gallium 249-252 1987Arsenide IntegratedCircuit Symp., Port-land, OR, 1~87

Proc. ICCE Int. 10-11 1988Conf. on Consumerelectronics, Rose-mont, IL, 1988

Proc. SPIE 949 220-228 1988

Proc. Ultrasonics 849-852 1987Syrnp., Vol. 2, I?en-ver, CO, 1987

Rev. Int. Froid 11 371-384 1988

Rev. Phys, Appl. 23 251-255 1988

847-862 1988

Semicond. Sci. Tech- 915-918 1988nol. 3

Sensors & Actuators 351-363 198813

Sensors & Actuators 1-8 198814

Solid State Commun. 613-617 198867

Solid State Phe- 133-152 1988nomen a 1&2

Spectrochim. Acta 1365-1404 198843B

Theor. Comput. Sci. 109-176 198860

Thesis, Eindhoven 1-175 1988

Thesis, Enschede 1-554 1988

Vide/Couches Minces 207-213 198843

ibid. 251-252 1988

Volume 44, No. 8/9/10 Published 20th May 1989pages 237-324

PHILIPS

PHILIPS REVI EW.----------Volume 44,No.11/12,November1989----------

Contents

A farewell message 325K. Bulthuis

The Compact Disc Interactive system 326B. A. G. van Luyt and L. E. Zegers

Information combined as pictures, sound and text can be locatedand retrieved in a user/system dialogue

Then and Now (1939-1989) 334

Phosphor screens in cathode-ray tubesfor projection television 335

R. Raue, A. T. Vink and T. WelkerPhosphor screens for projection television are very different

from screens for direct-view television

Electron guns for projection television . 348T. G. Spanjer, A. A. van Gorkum and W. M. van Alphen

A new electron-optical design gives the bright and sharp picturesrequired for high-definition projection television

A diagnostic X-ray tube with spiral-groove bearings 357E. A. Muijderman, C. D. Roelandse, A. Vetter and P. Schreiber

.Spiral-groove bearings with liquid metal as a lubricantconduct heat away and pass electric current

Scientific publications 364

Subject index, Volumes 36-44 365

Author index, Volumes 36-44 374

P. Geittner and H. Lydtin, Manufacturing optical fibres by thePCVD process,

Philips Tech. Rev. 44, No. 8/9/10, 241-249, May 1989'.Optical fibres for telecommunications are either multimode fibres (step- orgraded-index) or single-mode fibres. Single-mode fibres have either a steppedprofile with a small core diameter or a complex layered refractive-index profile.The last type of fibres are called DFSM (Dispersion-Flattened Single-Mode)fibres. In fibres of this type pulse broadening due to mode dispersion does notoccur and material dispersion and waveguide dispersion almost completelycompensate one another. The Philips PCVD (Plasma-activated ChemicalVapour Deposition) process can be used for the manufacture of fibres withcomplicated index profiles. Closely controlled amounts of dopants such asGe02 can be introduced into the basic Si02 material at very low concentra-tions. The concentration of OH- ions, which can introduce an intolerably highattenuation, has been greatly reduced by adding C2Fs to the reactive gas miJl-ture. This reduced the attenuation due to OH- ions to a minimum value ofO.ldB/km.

D. J. Gravesteijn, C. J. van der Poel, P. M. L. O. Scholte andC. M. J. van Uijen, Phase-change optical recording,

Philips Tech. Rev. 44, No. 8/9/10, 250-258, May 1989.In phase-change optical recording the recording layer of a disc is heated locallybya focused laser beam. Heating crystalline material to just above the meltingpoint and then cooling it rapidly causes it to change from the crystalline phaseto the amorphous phase; while heating amorphous material below the meltingpoint has just the opposite effect. The read-out of written effects depends onthe difference in optical properties between the two phases. The choice of mat-erials for the recording layer is determined not only by the optical properties,but also by the crystallization behaviour. The stability of amorphous areas andthe crystallization rate at higher temperatures are particulary important here,A material with a very high crystallization rate, GaSb, is found to be suitablefor non-erasable recording in an amorphous recording layer. For erasable re-cording in a crystalline recording layer all the requirements can be met with anInSbTe alloy. The first results of recording experiments with these materialslook very promising. I

O. Dössel, M. H. Kuhn and H. Weiss, Magnetic fields in med-ical diagnostics: MR and SQUID,

Philips Tech. Rev. 44, No. 8/9/10, 259-267, May 1989.A magnetic-resonance (MR) system with a two-tesla superconducting magnetwas installed at the Philips laboratories in Hamburg in 1983. Good images ofcross-sections of the human body were produced at this high field, but therewere difficulties due to the chemical-shift effect. This effect gave a blurred im-age because the images due to water and fat did not coincide. The difficulty wasresolved by suppressing one of these images. This was a first step in the devel-opment of MR spectrometry, an analytical method that gives informationabout the chemical processes in a small region of the human body. As the mamfield increases the resolution of MR speetrometry improves. An MR system.with the high flux density of four teslas was therefore developed and broughtinto operation. Another development from the Hamburg laboratories is 'aSQUID magnetometer (SQUID stands for Superconducting QUantum In-terference Device), which will be used for detecting the extremely weakmagnetic field generated by the currents in the neurons ofthe brain. A SQUIDconsists of a superconducting ring with two Josephson junctions. The SQUJpwill be used in reconstructing an image of neuronal activity from measure-ments of the field around the brain. I

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P. Blood, C. T. Foxon and E. D. Fletcher, The application ofsemiconductor superlattices to short-wavelength lasers,

Philips Tech. Rev. 44, No. 8/9/10, 268-273, May 1989.This research shows that short-period superlattice structures can be used to ad-vantage in a variety of short-wavelength semiconductor lasers. Molecularbeam epitaxy has been used to grow laser structures in which the AlxGal_xAsalloy regions have been replaced by all-binary short-period (AlAs).(GaAs)msuperlattices embodying binary layers as thin as three monolayers. Quanturn-well lasers with superlattice barriers and GaAs wells have a lower thresholdcurrent than equivalent structures using alloys. An analysis of the performanceof devices with different cavity lengths shows that the optical-scattering lossesin these structures are indeed very low. There is evidence for a leakage currentassociated with recombination in the barrier regions though it should be pos-sible to reduce this by modifying the design ofthe superlattice barrier. Double-heterostructure lasers have been made with an all-binary superlattice active re-gion which operates at 786 nm and with encouraging values of thresholdcurrent.

M. F. H. Schuurmans, R. Coehoorn, R. Eppenga and P. J .. Kelly, Predicting the properties of materials: dream or reality?,

Philips Tech. Rev. 44, No. 8/9/10, 276-286, May 1989.Before new materials are used in commercial products their properties must beknown. This information can be acquired from experiments, of course. Prop-erties can also be calculated even before the materials exist. One of the the-ories that can be used in these calculations is the density functional theory. Thepresent developments in this field are discussed with the aid of results obtainedfrom the theory. These results relate to materials in the ground state: thedifferent crystal structures of silicon at increasing pressure, the rearrangementof atoms at the surface of silicon, the consequences for the crystallattice whenoxygen is incorporated and the magnetic behaviour of iron-yttrium com-pounds. The theory can also be used, with some modification, for predictingthe emission of light from GaAslAlAs superlattices.

A. Bruffaerts, E. Henin and A. Pirotte, A sound basis for the. generation of explanations in Expert Systems,

Philips Tech. Rev. 44, No. 8/9/10,287-295, May 1989.In this article we have argued that a wide spectrum of explanations can be use-ful in an expert system. We have looked briefly at attempts to generate some ofthese explanations. A general architecture has been proposed for expertsystems, clearly distinguishing between the functions of two cooperatingagents, a dialogue manager and a problem-solver. We have argued that a log-ical framework is most convenient for a precise declarative version of theknowledge base and of its relationships to query answers from the problem-solver. Our own work is aimed at the development of a powerful problem-solver component along those lines. Formalisms and tools have been developedfor generating a form of proof tree that offers a sound basis for the conven-tional trace-based how-, why-, why-not-explanations. A logic-based object-oriented knowledge-representation formalism is being designed to support auniform encoding of knowledge and meta-knowledge for the generation ofmore conceptual explanations.

G. Conner and R. H. Lane, HS3: an advanced bipolar-le tech-nology,

Philips Tech. Rev. 44, No. 8/9/10, 296-301, May 1989.HS3 has been shown to be a versatile, high-performance IC-manufacturingprocess. The process consists of a single core process and a number of modularadditions. Each addition requires an extra masking step and corresponds to anoptional product family, such as analog circuits, ECL gate arrays, memoryand logic circuits, and operational amplifiers for automotive applications.High production numbers in the core process facilitate statistical process con-trol. The excellent properties of npn transistors with 1 by 3 urn emitter are de-monstrated by a Gummei plot and a plot of cut-off frequency iT against collec-tor current.

M. Rocchi, Research on monolithic GaAs MESFET circuits at ,LEP,

Philips Tech. Rev. 44, No. 8/9/10, 302-309,May 1989.In GaAs MESFETs (MEtal-Semiconductor Field-Effect Transistors), the gatemetal is directly applied to the GaAs surface to form a Schottky-barrier diode.The transit time of electrons beneath the gate electrode can be very short (downto a few ps) so that these transistors have very good high-frequency (> 1GHz)characteristics. During the last fifteen years monolithic circuits based on GaAsMESFETs have been extensively investigated at LEP. Significant progress indevice technology has greatly widened the field for both digital and analog ap-plications. High-speed low-power digital GaAs ICs can be used in instrumenta-tion and telecommunication systems, in supercomputers and in systems forfast signal processing. Analog GaAs ICs can be used in various r.f. and micro-wave devices, not only for professional applications at frequencies up to30GHz, but also for consumer applications such as the 12-GHz front-ends fordirect satellite television reception. The future of GaAs MESFET ICs will de-pend closelyon the evolution of special semiconductor heterostructures forhigh-frequency devices and also on the economic effects ofthe submicron min-iaturization of GaAs devices and their silicon counterparts.

M. Amato, G. Bruning, S. Mukherjee and I.T. Wacyk, Powerintegrated circuits,

Philips Tech. Rev. 44, No. 8/9/10, 310-320, May 1989.Power integrated circuits (PI Cs) are becoming an important branch of micro-electronics. These circuits can be applied in motor control, power supplies,lighting and automotive areas. One specific category of PlC is known as theHigh-Voltage IC (HVIC). The key to the economically successful design ofPICs is the ability to produce devices which can handle high voltages (severalhundred volts) or high currents (up to tens of amperes) with a small siliconarea. New device techniques which achieve this are discussed. Since many PICshave to be designed for specific applications (ASPICs), special design toolshave been evolved which allow the rapid design ('silicon compilation') and sim-ulation of the entire power system. Examples of the application of these toolsto a switched-mode power supply are presented.