ENHANCED POWER GATING SCHEMES FOR LOW LEAKAGE LOW GROUND BOUNCE NOISE IN DEEP SUBMICRON CIRCUITS

ABSTRACT: The development of digital integrated circuits is

challenged by higher power consumption. The combination of higher clock speeds, greater

functional integration, and smaller process geometries has contributed to significant growth in power density.

Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance.

But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages.

In this paper we are going to design such an efficient technique related to ground bounce noise reduction using power gating circuits

EXISTING SYSTEMS:

Existing system is using Power gating circuits which will most probably reduce the complexity of the circuit.

As complexity reduced power consumption can be further more reduced.

The Existing system is very much immune to the ground bounce noise.But it need more components (Inductor,Transmission gates)

Increase circuit complexity

EXISTING CIRCUIT:

PROPOSED SYSTEM:

In Proposed system we provide novel circuit structure named “Dual stack” as a new remedy for designers in terms of static power and dynamic powers.

Novel technique there are two sleep transistors is forcedly stacked in both pull-up and pull-down networks

It maintaining the exact logic state, two extra transistors are used with the pull-up and pull-down networks.

PROPOSED POWER GATING CIRCUIT:

Novel stacked sleep approach

CONCEPT OF GROUND BOUNCE

System InputThat is Affected

Inductance of lead frame, bound wired,

package pin, etc.

LoadCapacitance

Current flow (red) during a high to low transition causing “bounce.” This can change the input thresholds to the device as well as result in output pulses being transmitted to a receiver.

Quiet DeviceOutput ThatIs Affected

GROUND BOUNCE - DEFINITION

Noise on a ‘quiet’ output. Voltage with respect to ground.

SwitchingOutputs

Low QuietOutput

High QuietOutput

VOLP

VOLV

VOHP

VOHV

VDD BOUNCE

GROUND BOUNCE - DEFINITIONXILINX TERMINOLOGY

GROUND BOUNCE - MEASURING

Measured on pin with greatest noise. Worst-case pin usually furthest from ground. VOLP and VOLV are measured on a quiet line that is

a ‘0’; switching outputs transition from high to low for ground bounce.

VOHP and VOHV are measured on a quiet line that is a ‘1’; switching outputs transition from low to high for supply droop.

GROUND BOUNCE - MEASURING

• • •

GROUND BOUNCE - MEASURING

• • •

GROUND BOUNCE - MEASURINGWORST-CASE VS. BEST-CASE PIN

Worst-case Best-case

GROUND BOUNCE - MEASURING

Design system and test equipment to support measurement of ground bounce Control of patterns

When using reprogrammable devices Special patterns can be loaded to exercise the I/O

buffers and measure ground bounce.

REDUCING GROUND BOUNCE

Use low slew outputs unless needed Don’t group SSO’s together; break them up.

Xilinx: two for each side of a ground pin Control number of SSOs through sequencing

Example: Do address and data busses need to switch at the same time?

For some families [fill in], programming “unused” outputs will improve grounding or supply for output stages.

REDUCING GROUND BOUNCE

Use buffers, particularly for large memory arrays or long lines Everything does not have to be inside of the FPGA or

ASIC Avoid sockets For spare pad locations, pre-wire power, ground,

and bypass capacitor connections “haywired” power and ground connections will have

unneeded inductance.

TOOLS USED

DSCH Microwind

APPLICATIONS:

In future mobile Systems for low leakage & enhanced battery efficiency.

Future Integrated circuits for low power and high speed applications using power gated cicuits.

APPLICATIONS

In future mobile Systems for low leakage & enhanced battery efficiency.

Future Integrated circuits for low power and high speed applications using power gated cicuits.

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Suhwan Kim, Chang Jun Choi, Deog- Kyoon Jeong, Kosonocky, Sung Bac Park, " Reducing ground bounce noise and stabilizing he data- retention voltage of power- gating structures" IEEE transactions on Electron Devices, vol. 55, pp. 197-205, June 2008.

Shilpi Birla, Neeraj K. Shukla, Manisha Pattanaik and R. K Singh "Analysis of the data stability and leakage reduction in the various SRAM cells topologies", International Journal of engineering science & technology computer (HEST), Singapore, vol. 2(7), 2010, pp. 2936-2944, ISSN: 0975- 5462.

M. Tie, H. Dong, T. Wong, Xu Cheng, " Dual- Vth leakage reduction with fast clock skew scheduling enhancement", IEEE conference on Design Automation & Test in Europe, 2010, pp. 520-525.