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Power Factor Correction by Overtone Removal. Robert S. Wrathall January 15, 2013. Essence of the Invention. Works in the frequency domain rather than time domain. Power Factor Correction by Closed Loop removal of harmonic frequency overtones - PowerPoint PPT Presentation
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Power Factor Correction by Overtone Removal
Robert S. Wrathall
January 15, 2013
2
Essence of the Invention
Works in the frequency domain rather than time domain.
Power Factor Correction by Closed Loop removal of harmonic frequency overtones
Sensing the harmonic content of the current wave form and removing it by closed loop feedback methods
Near perfect PFC over all conditions
04/19/2023 Robert S. Wrathall
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Advantages
Works at constant frequency in PWM mode
Works at same max current as CCM mode Higher switching frequency Inductor size reduced by approximately
20x in value. Inductor size limited by DCM requirement
at switching frequency, voltages and load current.
04/19/2023 Robert S. Wrathall
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Advantages The inductor is one of the more costly
elements Higher frequency operation minimizes
inductance This technique is particularly adapted to
digital power control Does not require high speed current sense Can be adaptable to buck-boost
configuration
04/19/2023 Robert S. Wrathall
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Basic Circuit
The basic circuit is a boost converter operating on the rectified AC voltage
The boost converter is operated in the discontinuous mode, the current in the inductor goes to zero each
cycle
04/19/2023 Robert S. Wrathall
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Simplified Typical Block diagram of basic AC to DC circuit
C1
REF
AC source
Vin
Voltage to PWM
Current sense
Idiode
Iswitch
ground
Vout Iload
Outer loop Voltage control
Low speed
feedback
L1
D1
Rcs
AMPLIFIER
04/19/2023 Robert S. Wrathall
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Basic operation
The input diode bridge converts the AC supply to a rectified DC supply.
The amplifier operates to control the pulse width of the boost converter to control the output voltage with a constant pulse width
The “outer loop” with the amplifier is a generally slow loop
04/19/2023 Robert S. Wrathall
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Basic operation
The PWM circuit shown has some minimal power factor correction features
If a second loop, the PFC loop, is added, this allows the PWM circuit to do power factor correction
PFC is a lower order correction to the main “outer” loop as shown in the simplified PFC circuit
04/19/2023 Robert S. Wrathall
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Simplified Typical Block diagram of basic PFC circuit
C1
REF
AC source
Vin
Voltage to PWM
difference
PFC correction circuits
Current sense
timing
Idiode
Iswitch
ground
Vout Iload
Outer loop Voltage control
Low speed
feedback
CS out
Inner loop. Power Factor Control
L1
D1
Rcs
AMPLIFIER
Correction
04/19/2023 Robert S. Wrathall
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Demonstration
A numerical simulation shows the operation of the power factor correction circuit.
A condition is chosen which accentuates the ability of this technique for power factor correction.
The condition is the input voltage is close to the output voltage and the inductor is as large as possible with no PFC
Duty factor is ratio Ton / Ttotal
04/19/2023 Robert S. Wrathall
No correctionDiscontinuous to continuous transition
Vin 240v rmsVout 400vIload 5 ampPower 2kwL1 20uHD 0.115PwrFctr .662
This plot shows the operation of the uncorrected basic circuit. Under these conditions there is a transition to continuous mode.
04/19/2023 Robert S. Wrathall
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Observations
These conditions were chosen to be extreme.
This condition forces the inductor into the continuous conduction mode (CCM)
The Power Factor is low, near 60%.
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Removal of 2nd Harmonic
The correction circuit operates by the detection of discrete harmonics of the fundamental
The amplitude of the harmonic is amplified and multiplied by its respective sine wave and subtracted from the PWM duty factor to make a new, corrected current wave form.
04/19/2023 Robert S. Wrathall
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Optimization by removal of only the 2nd Harmonic
Vin 240v rmsVout 400vIload 5 ampPower 2kwL1 20uHDnom 0.202PwrFctr .987
04/19/2023 Robert S. Wrathall
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2nd Harmonic Correction
Correcting for just the lowest harmonic produces a power factor of 98%
The harmonic content can be seen in the duty factor wave form
The continuous current mode operation has been removed by shifting current to the lower voltage portions of the input wave.
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7 Harmonic correction The simulation has capability of removing
up to 7 harmonics. This would not normally be necessary in a real appliction.
There is a small coupling between the several harmonics through the operation of the outer loop
For full removal, the operation needs to be iterated several times
This slide show the result of 3 iterations
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Three times through the algorithm optimizing 7 harmonics each time
Vin 240v rmsVout 400vIload 5 ampPower 2kwL1 20uHPwrFctr 0.999
04/19/2023 Robert S. Wrathall
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Discussion 1 harmonic removal seems good, 7 is
excellent, maybe overkill The number of harmonics removed
determines the bandwidth of the current sense and the speed of the analog to digital conversion
Typically the BW will be less than 3 kHz and the current sense sample frequency 6 kHz
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Basic PFC Correction Circuit
Fourier Transform
Fundamental rejection
Overtone selection
CS
Soft start
gain
Inverse Transform
Resampling
ADC
timing
DAC output
Lowpass filter
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harmonic removal
The algorithm is based on the idea that the uncorrected circuit does a modest job at power factor correction.
It also depends on the idea that the removal of a harmonic using the uncorrected circuit is nearly independent of all other harmonics.
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Algorithm
First block is a low pass filter to filter out the switching noise
Second block is an ADC Third is a Fourier transform Fourth rejects the fundamental and selects
either individual or all the harmonics of the fundamental
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Algorithm Fifth is a gain block with a soft start. This
gain block can be located anywhere on the chain
Sixth is the inverse transform Seventh is a resampling block. The
original transform may only require a 6kHz sampling but the switching frequency might be 200kHz. The resampling matches these.
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Algorithm
Finally there is an DAC to convert to an analog signal.
If the outer loop is a digital loop this signal may remain in digital form to modify the outer loop response.
The outer loop must be slow
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Software requirements Fourier transform occurs once each
8.333ms Transform only requires 30 data points for
7 odd overtones conversion every 8.33ms Resampling requires 833 points for a
100kHz switching frequency. 8 time points result from the inverse
transform. These must be padded by 104 points each.
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Sample rate
Sample rate 0.277 ms Fourier transform is simplified
Only real sine terms are needed Only odd terms, N=3,5…, are needed Of 32 points of sampled data only 8 points are
required from the FFT in the frequency domain
Likewise in the inverse only 8 or less terms are used.
04/19/2023 Robert S. Wrathall
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Light Load Operation The duty factor must be kept above a
minimum on-time of the PWM circuit for smooth operation.
As the duty factor drops, cycle skipping may be implemented to keep the duty factor reasonable.
As some point too many cycles will be skipped and the inner loop will no longer be adaptive. The last measured values may be used as shown in other patents
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Summation This technique eliminates fast current
sense This technique does a nearly perfect
power factor correction over all operating conditions
Requires a minimal amount of computation overhead
Fixed frequency operation for noise considerations
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Summation
Not dependent on component or switching frequency considerations
In particular, allows for a much smaller inductor
Works as well as or better than critical conduction mode techniques
04/19/2023 Robert S. Wrathall