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High Efficiency CMOS Class E Power Amplifier

Using 0.13 m Technology

S.A.Z Murad, M.F Ahamd, M. Mohamad Shahimin,

R.C Ismail and K.L Cheng

School of Microelectronic Engineering,

Universiti Malaysia Perlis,

Kampus Pauh Putra, 02600 Arau, Perlis, [email protected]

R.Sapawi

Department of Electronics, Faculty of Engineering,

Universiti Malaysia Sarawak,

94300 Kota Samarahan, Sarawak, Malaysia

[email protected]

AbstractThis paper presents the design of a 2.4-GHz CMOS

Class E power amplifier (PA) for wireless applications in Silterra

0.13-m CMOS technology. The Class E PA proposed in this

paper is a single-stage PA in a cascode topology in order to

minimize the device stress problem. All transistors are arranged

in parallel to decrease on-resistance for high efficiency with on-

chip input and output impedance matching. The simulation

results indicate that the PA delivers 11.9 dBm output power and

53% power added efficiency (PAE) with 1.3-V power supply into

a 50- load. The chip layout is 0.27 mm.

Keywords-component; Class E; power amplifier; Silterra;

output power; power added efficiency

I. INTRODUCTIONRecently, wireless systems demand a low cost, compact,

power efficient, high integration and reliable consumersdevices. In addition, more and more signal processing is donein CMOS and high levels of integration are desired forreducing a cost and achieving compact systems. Hence, thewireless transceivers need to merge as many components as

possible in a single chip using low cost technology. Therefore,there is a demand in utilizing CMOS PAs in a single chiptransceiver called system on chip (SoC). However, as thedown-scaling of MOS devices continues, the CMOS PA is notthe optimum technology of choice due to the problem such aslow oxide breakdown voltage, low current drive capability,substrate coupling, low quality and high tolerances of on-chip

passives [1][2]. Although a lot of researches have beenconducted recently to realize fully integration of PAs into SoC,unfortunately it is still a major challenge [3], particularly when

designing in GHz frequencies range.In CMOS, Class E PA is the most favored candidates

among all classes of switching mode power amplifiers (Class D& Class F) due to their circuit simplicity and excellent PAE[4]. High PAE is important because PAs typically dominate the

power consumption in a wireless transmitters system.However, the linearity is very poor due to the switching nature,thus the systems with the constant envelope modulationscheme such as FSK (or FM) are most suitable for switched-mode amplifiers. Furthermore, signal swing in a Class E PAcan be two or three times the supply voltage that seriously

stresses MOS devices. Safe device operating conditions can beguaranteed by decreasing supply voltage is usually less thanthe maximum available, at the price of efficiency degradation

[1,5]. Cascode configurations have been used to overcome thedevice stress problem in MOS devices [1].

Most CMOS PAs that are published choose differentialtopology to obtain high linearity watt range [6]. Since thecomponents driven by the PA and the antenna input are stillsingle-ended, such a topology still requires off-chip baluns forconverting signals from single-ended to differential and viceversa [7]. Therefore, fully integrated CMOS chip is difficult torealize. However, on-chip baluns can be integrated indifferential topology for converting signals, but the design

becomes complicated and increased the chip size [1],[8].

This paper describes a 2.4 GHz Class E single-stage PAdesigned using Silterra 0.13-m CMOS process. The proposed

design employed cascode topology to increase breakdownvoltage and the power stage transistors are arranged in parallelto decrease the switch on-resistance. This method helps toreduce the losses thus increase efficiency.

II. CIRCUIT DESIGNThe complete schematic of the proposed Class E PA single-

stage cascode topology is shown in Fig. 1. Cin and Lin are partof the on-chip input matching. Rb is a bias resistance for M1.

Figure 1. Complete schematic of the proposed single-stage Class E PA.

2012 IEEE Symposium on Wireless Technology and Applications (ISWTA), September 23-26, 2012, Bandung, Indonesia

978-1-4673-2210-2/12/$31.00 2012 IEEE 85


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The power stage is implemented byconsists of common-source (CS) amplifier,gate (CG) amplifier, M2. A cascode structuimproving the breakdown voltage. The

between the drain and source of M1 and Mdrains of M2 to ground can sustain about 2.significantly improves the breakdown volshunt capacitor calculated using the equatio

the calculated value does not include the paM1 and M2, the optimization is neededefficiency and high output power. The switc

be minimized by increasing the size of aThus, to optimize the performance ofaltogether, thirteen transistors in paralleltransistors in parallel for CG were selected.maximum width of 10 m and minimum lThe gate of M1 is biased at 0.5 V, M2resistor R, and the Vdd for M2 is 1.3 V.

The design load network for the outputthe selected Vdd, frequency, and the wantedvalues of Cshunt, Ls, and Cs were calculate

[9]. Ls and Cs is a series resonant network isthe equation of 1 at frequency 2DC inductance Ldc is 6 nH connecting the Csupply connection.

The last part of the proposed design iusing L-matching network. This network cLo and capacitor Co is employed due to itsThe impedance matching is important in r

power loss and delivering as much as possload [12]. This matching network is careensure that the optimization resistance [4] isstandard load at RF output terminal. Thelements can be derived using equations in [1

III. SIMULATION RESULThe circuit design of the Class E si

simulated using Mentor Graphics simulatorm CMOS process. Fig. 2 shows the simuland current waveform of the power stage.wherein the voltage and current are not oveother can be observed. On the other handcurrent are not maximum level at the same

power dissipation or the product of drain care minimized. Therefore, high efficiency caminimum voltage is non-zero because of tresistance.

Fig. 3 shows the simulation result for(Pout) and PAE versus input power (Pin). Ithe maximum output power is 11.9 dBm witinput power of 0 dBm. The output power is iinput power, however the PAE is decrease

power beyond 0 dBm. The degradation ofparasitics effects.

cascode topologyM1 and common-e is employed foraximum voltage

2 is 1.3 V, so theV. This topology

age. Cshunt is ain [9]. However,

asitic capacitor ofto achieve highon-resistance canswitch transistor.the power stagefor CS and nine

ll devices have angth of 0.13 m.is biased through

stage is based onoutput power. Theusing equation in

designed based on.4 GHz. The finiteG drain to the DC

output matchingnsists of inductorcircuit simplicity.

educing reflectionible power to theully optimized toconverted to 50

output matching2].

S

ngle-stage PA issing Silterra 0.13-ated drain voltageClass E operationlapping with each, the voltage andtime, that is; therrent and voltagebe obtained. Thee transistors on-

the output powert can be seen that

53% PAE for anncreasing with thed when the inputAE is due to the

Figure 2. Transient response for d

Figure 3. Output power a

The output power and Pshown in Fig. 4, the output

proportional to Vdd, from 9 dvoltage is swept from 1.0 V tooutput power can be controllFinally, Fig. 5 shows the simuthe PA as a function of frequdBm. The output power achanging between the frequenTherefore, this PA obtains 100

Figure 4. Output power an

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Freque

Pou

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-20 -15 -10

Pout

PAE

Pi

Pout(dBm)

Pout(dBm)

CurrentVoltag

rain current and drain voltage of M2.

nd PAE versus input power.

E versus supply voltage arepower changes approximately

Bm to 14 dBm when the supply1.6 V. It can be noted that the

ed through the supply voltage.lated output power and PAE ofncy when the input power is 0d PAE are not significantlycies' ranges of 2.352.45 GHz.MHz bandwidth.

d PAE versus supply voltage.

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Pout

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0.0010.00

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PAE(%)

cy (GHz)

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(dBm)

PAE(%)

dd (V)

PAE(%)

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Figure 5. Output power and PAE as a function of frequency.

Table 1 shows the comparison of performances of thepreviously reported Class E PA and this work. The proposeddesign obtains good efficiency with the smaller chip size whencompare with the previous work. The layout of the proposedClass E PA is presented in Fig. 6. The chip area, including the

pads is 0.84 mm 0.42 mm; this layout is going to tape out forfabrication.

Figure 6. Layout of the proposed Class E PA on 0.13-m CMOStehcnology.

IV. CONCLUSIONIn this paper, a 2.4 GHz single stage Class E PA with

parallel transistors for wireless applications in the Silterra 0.13-m CMOS process is presented. The proposed topology

employed cascode structure to overcome the device stressproblem of submicron CMOS transistors and both the input,and the output matching network have been designed on-chip.The use of parallel transistors helps to decrease the on-resistance switching thus the high efficiency can be obtained.The simulation results show that the proposed PA can deliver11.9 dBm output power with the maximum PAE of 53%.Besides, it has very low supply voltage. The proposed PA can

be used for wireless communication systems such asBluetooth's mobile phone and integratable with other RFtransceivers.

TABLE I. PERFORMANCE SUMMARY OF CMOSPOWERAMPLIFIER

Reference [10] [11] [12] [13]* [14]This

work

Technology

(m)

0.13CMOS

0.09CMOS

0.18CMOS

0.13CMOS

0.18SiGe

0.13CMOS

Frequency

(GHz)2.4 2.55 2.4 1.4-1.8 2.4 2.4

Vdd (V) 3.3 2.5 1.8 2.5 2.0 1.3

Pout

(dBm)19.2 20.1 21.09 19.5 22.4 11.9

PAE (%) 27.8 43.6 57 43 33.4 53.0

Chip size

(mm)0.37 N/A N/A 3 2.6** 0.35

Cost (USD)

/100 dies1.85 - - 15 26 1.45

*Post-layout simulation results

** Estimation from the layout.

ACKNOWLEDGMENT

The authors wish to express their appreciation to thesupport and contributions from those who assist in this researchespecially Universiti Malaysia Perlis (UniMAP) for providingthe incentive short term research grant (9009-00002) andFRGS grant (9003-00301) that enabled the production of thisarticle.

REFERENCES

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[2] Tirdad Sowlati & Domine M.W. Leenaerts,A 2.4 GHz 0.18um CMOSself-biased cascode PA, IEEE Journal of Solid State Circuit, vol.38, no.

8, pp. 1318-1324, August 2003.[3] Hafez Found, Abdel-Hali Zekry and Khalid Fawzy, Self-Biased 0.13-

m CMOS 2.4-GHz Class E Cascode Power Amplifier, 26 th NationalRadio Science Conference (NRSC 2009), 17-19 March, 2009.

[4] Sohiful Anuar Zainol Murad, Ramesh K. Pokharel, Haruichi Kanaya,Keiji Yoshida and Oleg Nizhnik, A 2.4-GHz 0.18-m CMOS Class Esingle-ended switching power amplifier with a self-biased cascode, Int.J. Electronic. Commun. (AEU), vol. 64, pp. 813-818, 2010.

[5] K.L.R. Mertens and M.S.J. Steyaert, A 700 MHz 1-W Fully differentialCMOS Class E Power Amplifier, IEEE Journal of Solid State Circuitsvol. 37, pp. 137-141, 2003.

[6] Riccardo Brama, Luca Larcher, Andrea Mazzanti & Francesco Svelto,A 30.5 dBm 40% PAE CMOS class E PA with integrated balun for RFapplications, IEEE Journal of Solid-State Circuits, vol. 43, no. 8,August 2008.

[7]

Tang Tat Hung & Mourad N.El-Gamal, Class E PA for RFapplications, Proc. of the 2003 Int. Symposium on Circuits andSystems, ISCAS '03, vol.1, pp. I-449 - I-452, 25-28 May 2003.

[8] P. Reynaert and M.S.J Steyaert,A 2.45-GHz 0.13-m CMOS PA withparallel amplification, IEEE Journal Of Solid-State Circuits, vol. 42,no. 3, pp. 551-562, March 2007.

[9] Phairoj Leungvongsakorn and Apinunt Thanachayanont. A 0.1-WCMOS Class-E Power Amplifier for Bluetooth Applications. TENCONIEEE Conference on Convergent Technology for Asia-Pacific Region2003. p. 1348-51.

[10] S.A.Z Murad, R.K Pokharel, H. Kanaya and K. Yoshida, A 2.4 GHz0.18-m CMOS Class E single-ended power amplifier without sipralinductors, IEEE 2010 10th Topical Meeting on Silicon Monolithic

0

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PoutPAE

P

out(dBm)

PAE(%)

Frequency (GHz)


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Integrated Circuits in RF Systems (SIRF 2010), pp. 25-28, 11-13 Jan,2010.

[11] Danish Kalim, Denis Erguvan and Renato Negra, Study on CMOSClass-E power amplifiers for LTE applications, German MicrowaveConference, pp. 186-189, 15-17 March 2010.

[12] Reza Meshkin, Alireza Saberkari, Mohammad Niaboli-Guilani, ANovel 2.4 GHz CMOS Class-EPower Amplifier with Efficient PowerControl for Wireless Communcations, 17th IEEE InternationalConference on Electronics, Circuits, and Systems (ICECS), pp. 599-602,

12-15 Dec. 2010.

[13] H. R. Khan, A. Raheem Qureshi, Q. Wahab, A Fully Integrated Class-EPower Amplifier in 0.13um CMOS Technology, IEEE 9th InternationalNew Circuits and Systems Conference (NEWCAS), pp. 410-413, 26-29June 2011.

[14] Su Jie, et al, A 2.4 GHz High Efficient Monolithic Class E PowerAmplifier, Asia Pacific Conference on Postgraduate Research inMicroelectronics and Electronics (PrimeAsia), pp. 271 - 274, 22-24Sept. 2010.


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