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Computer Organization and Architecture Lab List of Experiments 1. Performance Analysis: Run a benchmark test suite, and analyzing the performance of the underlying hardware of computer. 2. Hardwired Design of Combinational Circuits: Structural modeling of circuits for Decoder, Comparators, and Parity Checker. 3. Hardwired Design of Sequential Circuits: Behavioral modeling of circuits for Flip Flop, Counter, and Synchronizer logic.. 4. Hardwired Design of Data Bus: Data flow modeling of Tri State Buffer and 4:1 multiplexer. 5. Design of Computing Components: 4 bit ALU design, NXM size of RAM and ROM, frequency divider (divided by3) using finite state diagram, and design of bus Circuit. 6. Design of Hard Wired Logic for Traffic Controller: Design a traffic light controller for an intersection with a main street, a side street, and a pedestrian crossing. 7. Assembly Programming: 8085 and 8086 assembly programming for understanding of syntax and commands with their applications.

Poster COA Lab

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Page 1: Poster COA Lab

Computer Organization and Architecture Lab

List of Experiments

1. Performance Analysis: Run a benchmark test suite, and analyzing the performance of the

underlying hardware of computer.

2. Hardwired Design of Combinational Circuits: Structural modeling of circuits for

Decoder, Comparators, and Parity Checker.

3. Hardwired Design of Sequential Circuits: Behavioral modeling of circuits for Flip Flop,

Counter, and Synchronizer logic..

4. Hardwired Design of Data Bus: Data flow modeling of Tri State Buffer and 4:1

multiplexer.

5. Design of Computing Components: 4 bit ALU design, NXM size of RAM and ROM,

frequency divider (divided by3) using finite state diagram, and design of bus Circuit.

6. Design of Hard Wired Logic for Traffic Controller: Design a traffic light controller for

an intersection with a main street, a side street, and a pedestrian crossing.

7. Assembly Programming: 8085 and 8086 assembly programming for understanding of

syntax and commands with their applications.