52
AN13219 PN7160 antenna design and matching guide Rev. 1.2 — 13 September 2021 Application note COMPANY PUBLIC Document information Information Content Keywords NFC, PN7160, antenna design, antenna matching/tuning Abstract This application note is intended to provide some guidelines regarding the way to design an NFC antenna for the PN7160 chip. It also provides guidelines on how to properly match this antenna to PN7160. Standalone antenna performances evaluation and final RF system validation (PN7160 + tuning/matching network + NFC antenna within its final environment) are also covered by this document.

PN7160 antenna design and matching guide

  • Upload
    others

  • View
    22

  • Download
    0

Embed Size (px)

Citation preview

Page 1: PN7160 antenna design and matching guide

AN13219PN7160 antenna design and matching guideRev. 1.2 — 13 September 2021 Application note

COMPANY PUBLIC

Document informationInformation Content

Keywords NFC, PN7160, antenna design, antenna matching/tuning

Abstract This application note is intended to provide some guidelines regardingthe way to design an NFC antenna for the PN7160 chip. It also providesguidelines on how to properly match this antenna to PN7160. Standaloneantenna performances evaluation and final RF system validation (PN7160 +tuning/matching network + NFC antenna within its final environment) are alsocovered by this document.

Page 2: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Rev Date Description

1.2 20210913 Security status changed into "Company restricted", no content change

1.1. 20210820 Security status changed into "Company restricted"

1.0 20210412 Initial version

Revision history

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 2 / 52

Page 3: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

1 Introduction

PN7160 is a highly integrated NFC transceiver IC for contactless communication at13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulationconcept completely integrated for different kinds of contactless communication methodsand protocols at 13.56 MHz.

It is able to operate both in reader/poller mode and in card/listener mode.

PN7160 is intended to be connected to an external coil antenna through a specificmatching/tuning network.

The purpose of this document is first to provide some guidelines regarding the designof an NFC antenna intended to be connected to PN7160 (recommended antennacharacteristics).

It then depicts a measurement method to evaluate the performances of the antennabefore it is connected to NXP NFC chips.

The next chapter explains how to determine the tuning/matching network to be placedbetween a given antenna and PN7160 (based on the antenna electrical equivalentcircuit).

RF performance validation procedure is finally proposed.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 3 / 52

Page 4: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

2 Recommended NFC antenna characteristics

PN7160 can be connected to a standard coil antenna commonly used on the markettoday.

Those antennas are typically made of spiral loop (single loop antenna). The outlinedimensions, the number of turns, the copper track thickness, width and spacing definethe antenna characteristics.

Figure 1. Standard coil antenna example

2.1 Standard coil antenna designPN7160 was tested and validated with the below described single loop antenna.

2.1.1 40 mm x 40 mm

Figure 2. 40 mm x 40 mm antenna drawing

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 4 / 52

Page 5: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Physical outlines of the antenna board are shown here

Description Value Unit

size 40 x 40 mm

# turns 4

Copper width 0.4 mm

Spacing 0.3 mm

Copper height 35 μm

Table 1. 40 mm x 40 mm antenna outlines

2.1.2 Recommended characteristics

In case one wants to design their own single loop antenna for PN7160, it isrecommended to fulfill the characteristics described below:

Description Min Max

Size 800 mm² 5000 mm²

# turns 2 8

Copper width 0.2 mm 2 mm

Spacing 0.2 mm 2 mm

Copper thickness 20 µm

Antenna inductance tolerance (*) +/-3%

Table 2. Recommended standard coil antenna physical characteristics

(*) It is important that antenna characteristics (inductance and parasitic) are kept withina certain tolerance in production as they impact the system characteristics (i.e. esp.impedance matching) and thus performances.

Please note that those characteristics can still be changed.

2.1.3 Antenna size

NFC antenna dimensions must allow a good coupling with all the readers used in thefield such as in subways all around the world (e.g. China transit, Inter-Operability Test).

If the NFC antenna is too small, there will be communication issues with readers havinga large antenna. The H field coming from the reader is radiated within a limited volumearound the reader antenna and, for large antenna, the field strength at the center isvery weak, therefore, placing a small card antenna at the very center of a large readerantenna will result in bad communication due to small coupling factor.

2.2 Single loop antennaPN7160 was designed for Active Load Modulation (ALM) concept, opposed to PassiveLoad Modulation (PLM) where the NFC chip modulates directly the H field coming fromthe reader. ALM provides high performances and significant margins to NFC standardcriteria. It also allows the usage of smaller antenna.

In card mode, PN7160 provides 3 different modes to generate LMA which we call mode1 (SINGLE), mode 2 (DUAL) and mode 3. These 3 modes can be programmed bysoftware.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 5 / 52

Page 6: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

The LMA is doubled by passing from mode 1 to mode 2, and again from mode 2 to mode3.

• ALM Mode 1:

Figure 3. ALM mode 1 concept

On the left graph, the red curve shows the 13.56 MHz voltage at the NFC chip antennawhich is induced by the reader field, the blue curve shows the modulation pattern. Thismodulation pattern is generated by actively driving 13.56 MHz with TX1 or TX2 whilethe other TX pin (TX2 or TX1) is kept silent. On the right, we can see the modulatedreader field.

• ALM Mode 2:

Figure 4. ALM mode 2 concept

In this mode, the modulation pattern is generated by actively driving 13.56 MHz withTX1 and TX2. The modulation depth observed is twice the modulation depth of mode 1.

In card mode, the Single Loop Antenna is simultaneously used to receive the signal fromthe reader, synchronize to it (clock recovery), and generate the Load modulation backto the reader. To prevent from potential phase shift due to the superposition at the Rxpin of the incoming signal and the transmitted one, the clock recovery is done before thedata exchange (i.e. before the modulated signal is transmitted) and is frozen during thetransmission.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 6 / 52

Page 7: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 5. Single Loop Antenna concept (mode 1 illustration)

Figure 6. Load modulation illustration

The phase shift error can be defined as follows:

1. The Static phase shift error is the one that can be observed after having defined theoptimized HW tuning and phase clock register setting. This error is almost stable vs.the field strength of the reader, when coupling factor with reader can change it. Thisphase clock error is observed on sub modulated carrier.

2. The Dynamic phase shift error is coming from ALM signal generation by addition onboth signals. This error is maximum for low field strength (high distance), when ALMlevel is comparable to reader field strength. This error is affecting the 13.56 MHzcarrier.

On the figure below LMA result examples are shown for Upper Side Band and LowerSide Band in the 3 modes available for PN7160 (respectively mode 1, mode 2, mode 3).

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 7 / 52

Page 8: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 7. Example Side Bands ISO results for modes 1, 2, 3

To minimize the phase error, it is necessary to limit the level of the load modulationamplitude (LMA) and to adjust the balance of the Side Bands when the field strength islow.

This can be done by optimizing the phase setting in the following conditions:

• Use reader with low coupling factor (ISO test bench or Pegoda reader as example). Inthis condition, the best setting is the one(s) that is providing:– The minimum field strength response for ISO test bench (<1 A/m - 0.5 A/m typical)– The maximum communication distance with Pegoda reader (>5 cm)

• Use EMVCo test bench where Load Modulation Amplitude is tested at differentdistances and positions:– This test should confirm the best setting, taking into account coupling factor impact:

– Optimized setting should provide full passed EMVCo test.– In this condition, and depending on the HW tuning, it can happen that min

field strength (and then communication distance) is not the optimum, but finalperformance should be still under the limit (<1 A/m)

In these conditions, interoperability with various readers should be optimum.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 8 / 52

Page 9: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

3 Shielding and environment impact

3.1 Why is shielding importantThe PN7160 and the associated NFC antenna are intended to be integrated into any kindof device.

Those devices could be composed of metallic parts such as batteries, the PCBs,electronic components and even sometimes a chassis.

If metal is placed close to the NFC antenna the alternating magnetic field generatessome eddy currents in the metal. These eddy currents create a magnetic field in oppositedirection; it absorbs power, and leads to detuning of the antenna due to a decreasedinductance and quality factor. Therefore, it is necessary to shield the antenna with ferritefor proper operation in close metallic environment.

Adding a ferrite sheet allows to shield the antenna against the influence of metal.

The following figures are intended to highlight this phenomenon based on antennafield distribution simulation results. In order to simplify the simulation, results below arebased on a circular antenna with a radius of 7.5 cm with 1 turn and a copper wire of1 mm thickness. The right part shows the field distribution and the left part shows themagnitude of the field strength H over the distance d. The minimal field strength of HMIN =1.5 A/m defined by ISO 14443 is marked with doted vertical line.

The first figure shows the field distribution in an ideal environment without any metal nearthe antenna.

Figure 8. Field distribution of a circular antenna with open air environment

The second picture shows the field distribution of the same antenna but with a metalplane near to it. The magnitude of the field strength has significantly decreasedcompared to the open-air case which leads to a decreased operating distance.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 9 / 52

Page 10: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

026 4

5 cm

Minimum field strength

Hmin=1.5 A/m

Field strengthcolor map

metal plane

d

|H| [A/m]

Figure 9. Field distribution of a circular antenna with a metal plane

The last figure shows the effect of adding a ferrite plane (µR=40) between the metal planeand the antenna coil itself. The field distribution is still modified but the operating distancerecovers its original open-air level.

026 4

d

7.5 cm

Minimum field strength

Hmin=1.5 A/m

Field strengthcolor map

metal planeferrite plane

Figure 10. Field distribution of a circular antenna with a metal plane and a ferrite sheet

The simulation shows that the use of a ferrite reduces the generated eddy currents in ametal plane. The ferrite sheet changes the antenna environment characteristics, whichresult in a fixed detuning of the antenna itself.

This shielding will significantly impact the antenna electrical equivalent model so it iskey that when doing PN7160 tuning/matching network calculation, the antenna model ismeasured with the ferrite already in place (when applicable).

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 10 / 52

Page 11: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

3.2 Ferrite shielding recommendationIn order to reach a proper shielding, the ferrite sheet must at least cover the entiresurface of the antenna.

It is highly recommended to have an overlay but not too high because otherwise it willtend to reduce the stray field strength.

This trade-off is illustrated by the picture below:

Figure 11. Ferrite sheet overlay recommendation

The Ferrite quality is also a key parameter which needs to be considered to assess theeffectiveness of the shielding.

A high relative permeability is recommended because it allows to achieve a goodshielding with a lower thickness.

The material must be specified for a high magnetic permeability in the frequency rangethat is involved in NFC operation, i.e. 13.56 MHz.

The relative magnetic permeability of a material is made of two parts: µr’ is the real partof relative permeability and µr’’ is the imaginary part. µr’’ is reflecting the magnetic lossesin the material.

Recommended values are:

µr’ between 40 and 150 at 13.56 MHz and µr’’ as low as possible: < 3 at 13.56 MHz.

Please note that the level of shielding not only depends on the material used but also onthe thickness of the ferrite sheet. For a given permeability, the thickest sheet provides thestrongest shielding.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 11 / 52

Page 12: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

4 Antenna tuning and matching to the PN7160

4.1 Default configurationThe figure below shows the default configuration for the antenna connection.

Figure 12. PN7160 antenna matching/tuning circuit

4.2 Antenna tuning/matching procedure overviewAn overview of the antenna tuning/matching procedure is depicted on the followingfigure:

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 12 / 52

Page 13: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 13. Antenna tuning/matching procedure overview

4.3 Step 1: Antenna model measurement

4.3.1 Electrical parameters overview

Based on the antenna physical characteristics, its electrical equivalent model can bemeasured and computed.

For this, the antenna must be connected to a Vector Network Analyzer (VNA) to measurethe series and parallel components.

Please note that the antenna equivalent circuit must be determined under thefinal environmental conditions especially when the antenna will be operated in metalenvironment or when a ferrite sheet is used for shielding.

The target of this modeling step is to get the L, R, C equivalent of the antenna.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 13 / 52

Page 14: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Antenna

Ra

La

Ca

Figure 14. Series equivalent circuit

Recommended values:

La = 0.3...3µH => a minimum inductance value may be required to achieve expected

NFC performances of the system

Ca = 3...30pF => should be kept low to achieve a self-resonance frequency > 25 MHz

Ra = 0.1...2Ω => the lower the Ra, the lower the losses

fra (self-resonance frequency of the antenna) = 25 MHz or above (direct link with Ca)

If Ca is too large, the antenna may not be tunable for 13.56 MHz

In order to get these antenna electrical equivalent parameters, 2 methods are proposedbelow depending on the available equipment:

4.3.2 Measurement method with high end vector network analyzer:

Some VNA like Agilent 4294A or 4395A can determine directly the series or parallelequivalent circuit by measuring the magnitude and the phase of the impedance of theconnected antenna.

The antenna must be position in its final housing to consider all parasitic effects likemetal influence on quality factor, inductance and additional capacitance.

The antenna needs to be connected to the VNA by using an appropriate test fixture thatdoes not influence any antenna parameters.

The analyzer must be calibrated (open, short and load compensation at the calibrationplane) and the test fixture (e.g. additional wire length) needs to be compensated (open,short compensation at the connection points) before each measurement.

Settings: |Z|, Θ

Start frequency: 1 MHz

Stop frequency: above self-resonance frequency of the antenna (point where antennaimpedance is real: pure resistance)

Advantages:

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 14 / 52

Page 15: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

• Fast and simple method

Disadvantages:

• High-end equipment required• Low accuracy of the measurement which especially results from the loss resistance for

high quality factor coils (Q > 60).

4.3.3 Measurement method with any network analyzer

Alternatively, a network analyzer without any equivalent circuit functionality can be usedin combination with some calculation to determine the antenna electrical equivalent.

The antenna needs to be connected to the analyzer by using an appropriate test fixturethat does not influence the antenna parameters.

The analyzer must be calibrated (open, short and load compensation at the calibrationplane) and the test fixture (e.g. additional wire length) needs to be compensated (open,short compensation at the connection points) before each measurement.

Measured parameter: S11

Chart: impedance Smith chart

Start frequency: 1 MHz

Stop frequency: above self-resonance frequency of the antenna

4 parameters must be extracted from the above measurement to get the serial equivalentcircuit of the antenna:

Rs Equivalent resistance at f = 1 MHz

La Equivalent inductance at f = 1 MHz

Rp Equivalent resistance at the self-resonance frequency

fra Self-resonance frequency of the antenna

All 4 parameters depend on the antenna geometry:

• Rs is mainly defined by the thickness of the copper wire• Rp is mainly defined by the skin effect and changes with thickness and distance

between the turns• La of the antenna is a geometrical value. Basically, increasing the number of turns

increases the Q factor but decreases the effective antenna area and reduces its fieldstrength.

First, the antenna capacitance Ca can be calculated with:

(1)

The following figure illustrates a typical antenna impedance Smith chart measured from 1MHz to 50 MHz.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 15 / 52

Page 16: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Rs = 0.82 Ohms, La = 2.99 µH Rp = 18 kOhms, fra = 29.14 MHz

Figure 15. Example of results for antenna characteristic circuit

Based on the Smith chart trace, the series equivalent resistance Ra of the antenna at theoperating frequency fop = 13.56 MHz can be calculated.

Ra

La

Ca

Rs

La

Ca Rp

Figure 16. Series equivalent resistance calculation

(2)

(3)

The parallel resistance Rp(fra) obtained by measurements must be calculated to theparallel equivalent value at 13.56 MHz. This is accomplished in equation (2).

Ra in equation (3) is then calculated by using Rp(13.56 MHz).

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 16 / 52

Page 17: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Please note that this equivalent resistor value is then only valid at 13.56 MHz.

4.3.4 Optional: Quality factor adjustment

The antenna quality factor should not exceed 35. A typical antenna Quality factor valueis between 15 and 20. If the antenna Q is too large, it can lead to signal shaping andsystem frequency bandwidth issues. In case the measured antenna quality factor is toolarge, RQ resistors in series can be used to damp it.

The following calculation method can be used to determine the damping resistor value.

The quality factor of the antenna is calculated with

(4)

RQ value, resistances in series at each side of the antenna, needed to reach a desiredantenna Q factor (Qtarget) can be calculated by:

(5)

Practical consideration:

In a mobile environment where ferrite shielding is required, a large quality factor is veryunlikely. In this case, damping resistors are not needed.

It is anyhow advised to try to keep antenna Q at least above 15 in order to achieve goodperformance.

If Q<15 it will have an impact to overall performances, as the current into the antenna willbe lower with same Tx driver output power.

4.3.5 Determination of the parallel equivalent circuit:

The parallel equivalent circuit of the antenna including the optional damping resistors RQcan be calculated as follow:

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 17 / 52

Page 18: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Antenna

RQ

RQ

Rpa LpaCpa

Figure 17. Parallel equivalent circuit

(6)

4.4 Step 2: EMC filter design (L0 and C0 definition)The EMC filter circuit for the PN7160 fulfills two functions: the filtering of the signalharmonic frequencies and impedance transformation block.

The main properties of the impedance transformation are:

• Decreasing risetime after a modulation phase (reader mode)• Increasing the receiving bandwidth

L0 and C0 value definition:

L0 = 160 nH – 560 nH

Filter resonance frequency fr0 = 15 MHz ...17 MHz, => C0

(7)

The EMC filter resonance frequency fr0 must be higher than the upper sidebandfrequency determined by the highest data rate (848 kHz sub carrier) in the system (i.e.14.4 MHz)

Example:

A recommended value of 160 nH for L0 is chosen to calculate the capacitance C0.

L0 = 160 nH

fr0 = 15.5 MHz

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 18 / 52

Page 19: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

C0 = 659 pF → chosen: 560 pF

The EMC filter and the matching network must transform the antenna impedanceZmatch(f) to the required TX matching resistance Rmatch at the operating frequency of f=13.56 MHz.

Figure 18. Impedance transformation

The measured Zmatch(f) can be modeled in an equivalent circuit loading each TX pin withRmatch/2 at 13.56 MHz.

By cutting the circuitry after the EMC filter and by using the precondition Rmatch/2, theremaining components C1 and C2 can be calculated.

Please note that Rmatch/2 does not correspond to the driver output impedance

Figure 19. Definition of transformation impedance Ztr

(8)

(9)

(10)

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 19 / 52

Page 20: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

(11)

4.5 Step 3: Reader mode matching (C1 and C2 definition)C1 and C2 are used in combination with the EMC filter to tune the antenna to 13.56 MHzand at the impedance value Rmatch.

The resulting Smith card (S11 measured between TX1/TX2 pins) could look as on thefigure below for a 20 Ω symmetrical tuning.

Figure 20. Smith diagram for symmetrical antenna tuning

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 20 / 52

Page 21: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

The reason for the higher cut-off frequency of the EMC filter is a higher stability with closecoupling devices in reader mode: less impact of detuning effect on power consumptionincrease.

The following formulas are then used to calculate the series (C1) and parallel (C2)matching capacitances:

(12)

(13)

Where Lpa, Cpa and Rpa come from the measured antenna parallel electrical equivalent(see step 1) and Rtr and Xtr are coming from the EMC filter components value definition(see step 2).

The matching circuit elements C1 and C2 must be chosen to get the required matchingresistance Rmatch at 13.56 MHz at the PN7160 TX pins.

Based on the values calculated with the above formula, the matching impedance Zmatch =Rmatch + jXmatch must be measured with an impedance or network analyzer. TX1 and TX2pins of PN7160 (unpowered) are the probing points for the network/impedance analyzerto measure Zmatch.

Figure 21. Measurement of the matching impedance

All tuning and measurement of the NFC antenna must be performed at the final mountingposition to consider all parasitic effects like metal which influences the quality factor, theinductance and parasitic capacitance.

Those theoretical values for C1 and C2 calculated from formulas (12) and (13) needto be applied on a real circuit and the resulting Smith chart must be measured. The

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 21 / 52

Page 22: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

components values can then be adjusted to fine-tune the system. (Theoretical valuescontain some model uncertainty and antenna measurement uncertainty as well).

4.6 Step 4: Rx path tuning (Rrx and Crx definition)

4.6.1 Receiver block functionality

The Rx block consists of an AGC which regulates the voltage at Rx pins to reach theoptimum receiver input voltage. To achieve this, the AGC can attenuate the Rx signalcoming from the antenna thanks to a voltage divider. The series resistance is external tothe chip, the shunt resistance is in the Rx block, switchable within a certain range.

Figure 22. Rx path

On the graph below the AGC role is shown.

Figure 23. Rx path

The oscilloscope snapshot gives the typical 13.56 MHz sine wave expected on the Rx pin(on a 0.9 V DC bias, called Vmid).

The orange curve shows the Rx peak voltage (probed on the Rx pin with a lowcapacitance oscilloscope probe) when the device is placed on an ISO bench generatingthe expected H field. We can see that above 1 A/m the Rx voltage is regulated toapproximately 1.55 V (target is 1.6 Vpk). Below 1 A/m the signal received at the antennais not enough to be regulated up to this optimal value.

The gray curve gives the Rx Vpeak value when the AGC is not regulating but fixed toits minimum attenuation (code=0x000). It is not recommended to have a signal above2Vpeak.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 22 / 52

Page 23: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

The blue curve gives the Rx Vpeak value when the AGC is not regulating but fixed to itsmaximum attenuation (code=0x3FF). Here the signal is too much attenuated and stays ina 1 Vpk range.

4.6.2 Rx connection

As shown at the beginning of this chapter, two configurations are possible for the Rx pathcomponents.

1. The first one consists of connecting an R, C serial network between the Rx pins andthe EMC filters termination point. We generally say that Rx tap point is at EMC filter.

2. The second connection path is a direct connection of the RX circuit at the antennapads, we generally say that Rx tap point is at the antenna. In this case, the Crx ACcoupling capacitor can be removed but we advise to keep it connected to avoiddecreasing too much the Q factor of the antenna

The purpose of Crx capacitors is to provide an AC coupling of the Rx signal. A value of 1nF can generally be used.

Rrx resistor provides a voltage attenuator bridge (made of external Rrx series + internalRagc shunt) to adjust the Rx voltage swing (or peal voltage).

• The first step of the Rx path tuning process is to define which Rx path connection is thebest.Direct Rx connection at the antenna allows to reach a better sensitivity in card modebut it tends to reduce the quality factor of the antenna which affects the reader modeperformances (due to larger transmission losses) and the transmission strength in cardmode. This is particularly the case when the value of the RX resistor is low.To determine where to connect the Rx path, the Rx circuitry must be disconnected andthe voltage amplitude must be measured at the 2 possible connection points in readermode and under an external RF field of 1.5 A/m in card mode:1. If the voltage at the EMC filter in card mode is large enough (@1.5 A/m ~ 1 V or

more), use the EMC filter as starting point for the RX path tuning2. If the voltage is not large enough the RX path has to be connected to the antenna

For small antennas, it is strongly advised to connect the Rx Path directly to theantenna since due to low antenna coupling the signal amplitude at the EMC filter islikely to be smaller than 1 V.

• Once the RX connection point has been defined, Rrx value must be carefully adjustedto be close to the edge of the allowed input range under worst case conditions.Otherwise, the reception capabilities of the device could be reduced (if Rrx is too high,Hmin field detection in card mode will be reduced).For RX path tuning process, both reader mode and card mode must be considered andRrx value must be defined according to the highest voltage measured.1. In card mode, the worst-case conditions are met when an external RF field of 7.5

A/m is applied on the device. These conditions can be easily obtained with an ISO10373-6 [1] assembly PCD test bench.

2. In reader mode, the worst-case conditions are antenna-dependent and they arelinked to the tag load applied. Therefore, it is recommended to switch on thePN7160 RF field and to try different tag load to determine the maximum amplitudethat can be reached on the RX connection point.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 23 / 52

Page 24: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Pros cons

Rx connected to EMCfilter

- Rx path connection does notdecrease the Q factor-Recommended connection for largeantenna

Amplitude signal might be notenough to guarantee goodperformances especially withsmall antenna and ALM

Rx connected toAntenna

Maximize the signal captured by theRx path=> useful for clock recoveryaccuracy for ALM

The Rx resistor value impactsthe Q factor

Table 3. Rx connection pros and cons

NXP recommendation is to use antenna Rx tap point for small antennas (typicallysmaller than 800 mm2) and EMC filter tap point connection for large antenna(typically larger than 800 mm2).

4.7 Components characteristics

Component Maximumtolerance

Type Maximum rating

L0 5% Murata LQW18 (wire wound)TDK MLJ1608

(Multilayer Ferrite)

400 mA at least at 13.56 MHz

C0 2% NP0 - COG 16 V at least

C1 2% NP0 - COG 50 V or 25 V(*)

C2 2% NP0 - COG 50 V or 25 V(*)

Rq 5% N/A N/A

RRX 5% N/A N/A

CRX 5% X7R 50 V or 25 V(*)

CVMID 10% X7R 4 V at least

Antennainductance

3%

Table 4. Components characteristics

(*) the choice of 50 V or 25 V voltage depends on antenna characteristics and operatingconditions: the voltage at antenna terminals should be measured in the worst caseconditions e.g measurement in card mode by using the ISO10373-6 [1] assembly PCDtest bench to generate a field strength of 12 A/m.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 24 / 52

Page 25: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

5 Matching/Tuning verification

The antenna has first to be matched to PN7160 as described in the previous chapter.

Then the steps described below can be followed to verify the antenna matching/tuning.

During the antenna matching process, PN7160 IC is not powered.

5.1 Matching impedance tuning

Figure 24. Measurement of the matching impedance

The value of C1 changes the magnitude of the matching impedance. After changing C1,the imaginary part of Zmatch must be compensated by adjusting C2 as well.

C2 changes mainly the imaginary part of Zmatch.

C0 value shifts the EMC filter resonance frequency.

Here are some typical behaviors that can be observed on the network analyzer whileplaying on C1, C2 and C0:

Figure 25. Impact of C1

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 25 / 52

Page 26: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 26. Impact of C2

Figure 27. Impact of C0

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 26 / 52

Page 27: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

5.2 Matching components toleranceIt is highly recommended to use 2% tolerance components for the matching. The impactof the matching component tolerance was simulated and the impedance shift is given inthe table below.

C1/C2 deviation -5% -2% 0% +2% +5%

Impedance @13.56 MHz 20 Ω 21 Ω 20 Ω 19 Ω 17 Ω

Table 5. Impact of C0, C1 and C2 component errors on matching impedance

Figure 28. Impact of C0, C1 and C2 component tolerance (error) on a 20 Ω impedancematching

Adding the tolerances of the antenna itself, the NFC performances can be significantlyimpacted.

5.3 Matching impedance targetThe available TVDD voltage settings for TX drivers are the followings:

min max

TXLDOvoltages(Volts)

2.7 3 3.3 3.6 3.9 4.2 4.5 4.7 4.75 5 5.25

Table 6. TVDD voltage settings

To use the chip at its best, typical matching impedances of the antenna versus TVDD aregiven in the table below.

TVDD ≤ 3.3 V TVDD ≥ 3.6 V

Target impedance (typical) 15 Ω 20 Ω

Table 7. Target impedance

Vup is the input voltage of the TXLDO which generates TVDD voltage used by TX drivers.The current specification of TVDD is given in the table below.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 27 / 52

Page 28: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 29. Maximum current ratings for TVDD for different antenna loading conditions

Figure 30. Example of Vup Current measured for different TVDD for a 15 Ohms matching(50x30mm antenna)

5.4 Impedance matching for TVDD=3.3 VFor CONFIG 1 setup where the TXLDO is programmed at 3.3 V or below (generatinga TVDD between 3.15 V down to 2.3 V according to TVDD drop setting), a symmetricimpedance curve with Zmatch=15 Ω at 13.56 MHz shall be seen on the network analyzeras on the figure below.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 28 / 52

Page 29: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 31. Typical Smith chart of the symmetric Reader/Writer tuning

5.5 Impedance matching for TVDD=5.25 VWhen the chip is used in CONFIG 2 (using a DC-DC) and TXLDO set to 5.25 V generallyusing a TVDD at 4.7 V or 5 V target matching is Zmatch=20 Ω at 13.56 MHz (with DPCenabled) symmetric tuning. It shall be seen on the network analyzer as on the figurebelow.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 29 / 52

Page 30: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 32. Smith chart of the TVDD=5.2 V Reader/Writer tuning

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 30 / 52

Page 31: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

6 Dynamic Load Modulation Amplitude (DLMA)

For Card mode, the NFCC includes a specific feature called “dynamic LMA control” whichmakes it possible to adapt the Load Modulation Amplitude to the received field strength.

With this capability, the device can generate an optimized signal in Card modeand provide better performances (better interoperability with readers and largercommunication distances).

The NFCC in Card mode receives the RF signal from the reader on its Rx path. On thereceive path, the internal AGC and ADC generate a code according to the RF signalstrength received.

A mapping of these codes as a function of the reader field strength can be built. Thismapping depends on the sensitivity of the receive path which includes the antennaperformances and overall Rx path losses.

Having this mapping, a lookup table can be built to adjust the LMA according to the AGCvalues. Basically, for large field strength, small LMA gain can be used and for small fieldstrength larger LMA gain can be applied.

For more details, please refer to the dedicated Application Note [6].

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 31 / 52

Page 32: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

7 Dynamic Power Control (DPC)

In reader mode, the NFCC can adapt the current injected into the antenna according tothe antenna detuning. This feature called Dynamic Power Control (DPC) monitors thecurrent generated on the TX drivers and in case of antenna detuning, it limits this current(preventing it from clamping) by adjusting the TX signal amplitude.

Thanks to DPC, the NFC antenna can be matched in order to always deliver themaximum power, with no risk of having the TX current going beyond its specification.

Without DPC enabled, the matching must target higher impedance in order to have guardbands against high antenna detuning.

For more details, please refer to the dedicated Application Note [7].

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 32 / 52

Page 33: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

8 Performance verification and fine tuning

8.1 Field strength measurementWhen PN7160 is configured in reader mode, the strength of the emitted RF field can bemeasured by using a Reference PICC that is placed at a short distance from PN7160antenna. The reference PICC is calibrated on the relevant test bench: its output voltagecorresponds to a well-defined field strength. The output voltage of the Reference PICCcan be measured with an oscilloscope or directly measured with a voltmeter if thePN7160 is configured to emit a continuous RF field.

Based on the targeted standard compliance, the reference PICC to be used can bedifferent.

The Reference PICC to be used to check compliance with the ISO/IEC14443 standard(see [2]) is described in the ISO/IEC10373-6 standard (see [1]). Here is the specificationof the field strength required by the ISO/IEC14443 standard:

• No operating volume is required, a minimum field strength of 1.5 A/m must be achieved• Requirement is to be within 1.5 A/m to 7.5 A/m

This requirement is usually met at short distance (<2 cm).

The NFC Forum standard (see [3]) defines 3 different reference PICC so-called referencelisteners. The required operating volume is much smaller than EMVCo: the distance is upto 0.5 cm only. This specification can more easily be met with all 3 Reference PICC.

8.2 Carrier envelop shape verificationThe following pulse shape checks are a quick way for investigating the shaping of thegenerated RF field when the PN7160 is configured in reader mode.

The Reference PICC of the relevant standard has to be used for checkingcompliance of the waveform timings instead of the simple probe loop that isdescribed below.

This measurement is also an indirect verification of the Q-factor provided that it has adirect influence on the edges of the modulation shape.

An oscilloscope with a bandwidth of at least 50 MHz has to be used to carry out theshaping measurements (see Fig31).

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 33 / 52

Page 34: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 33. Setup to check the Q-factor

CH1: Use a loop with the ground line shortcut at the probe to enable inductive signalcoupling. Hold the probe loop closely above the antenna. When the shaping complianceto a given standard is verified, the corresponding reference PICC must be connected toCH1.

CH2: Used as trigger if possible

The absolute measured voltage in CH1 depends on the coupling (= distance) betweenthe probe loop and the reader antenna. The influence of the coupling on the shape canbe neglected. The complete antenna tuning and Q checking should be done without anycard (or metal environment) at proximity of the PN7160 antenna.

8.2.1 Pulse shape according to the ISO/IEC 18092 standard

It is recommended to check the pulse shape according to the values given in Figure 34and Figure 35.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 34 / 52

Page 35: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 34. Pulse shape according to ISO/IEC18092 standard @106 kbps

The time t1-t2 describes the time span, in which the signal falls from 90% down below5% of the signal amplitude. As the pulse length of the PN7160 is accurate enough, onlythe time t2 has to be checked: the signal has to remain below 5% for the time t2.

The most critical time concerning rising carrier envelope is t4. It must be checked that thecarrier envelope at the end of the pause reaches 60% of the continuous wave amplitudewithin 0.4µs.

t2 [µs]Pulse length(Condition)

t1 [µs]

(t1 ≤ 2,5) (t1 > 2,5)

t3 [µs] t4 [µs]

Maximum 3.0 t1 1.5 0.4

Minimum 2.0 0.7 0.5 0.0 0.0

Table 8. Pulse shape definitions according to ISO/IEC18092 standard @106 kbps

Please note that standard can evolve so the value mentioned in this tabled areonly shown for quick reference. Final value must be retrieved from the latest officialpublication of the corresponding standard.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 35 / 52

Page 36: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 35. Pulse shape according to ISO/IEC18092 standard @212 and 424 kbps

212 kbps 424 kbps

tf 2.0 µs max 1.0 µs max

tr 2.0 µs max 1.0 µs max

y 0.1 (a-b) 0.1 (a-b)

hf, hr 0.1 (a-b) max 0.1 (a-b) max

Table 9. Pulse shape definitions according to ISO/IEC18092 standard @212 and 424kbps

Please note that standard can evolve so the value mentioned in this tabled areonly shown for quick reference. Final value must be retrieved from the latest officialpublication of the corresponding standard.

8.2.2 Pulse shape according to the ISO/IEC14443 standard

The shaping measurement can be done in a similar way for ISO/IEC14443 standard (see [2]). The relevant Reference PICC has to be used.

The ISO/IEC14443 standard type B modulation index has also to be measured: it shouldbe in the range from 8% up to 14%. It is the main parameter to verify for ISO/IEC14443standard type B compliance.

Modulation index calculation is depicted in the next figure.

It must be noted that the PN7160 integrates an automatic adjustment of the modulationindex to keep it constant whatever the antenna environment.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 36 / 52

Page 37: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 36. Modulation Index (m) calculation in Reader/Writer mode

8.3 Load modulation amplitude measurementWhen the PN7160 is configured in card mode, it can transmit data to the external reader/writer (or NFC passive initiator) by modulating the amplitude of the external RF field. Anexample is shown in the below figure:

Figure 37. Card Emulation: EMVCo test bench measurement

The different standards define the amplitude of the load modulation in card mode. Itvaries with the field strength of the reader/writer or the distance from its antenna.

The load modulation amplitude or sideband level amplitude has to be measured by usinga specific test bench which is different for each standard (ISO, EMVCo, NFC Forum).

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 37 / 52

Page 38: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

8.4 Fine tuning through registersIn addition to the matching/tuning methodology, the RF performance can be fine-tuned bythe means of registers which are accessible from the PN7160 host interface.

Please refer to PN7160 User manual (see [4]) and the PN7160 RF settings guide (see[5]) to get more insight on the definition of the registers, as well as their use to optimizethe performance in card and reader modes.

8.4.1 Card mode

First, the load modulation mode (Card mode) has to be selected via the followingregister:

CLIF_TX_CONTROL_REG (transition RF_CLIF_CFG_TARGET)

The corresponding values are the following:

MODE Register Value

Mode 1 0x28

Mode 2 0x08

Mode 3 0x48

Table 10. Load Modulation generation modes register values

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 38 / 52

Page 39: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 38. Generating LMA mode 1, 2 and 3

The two following registers can be adjusted to fine tune the load modulation amplitudeare CLOCK_CONFIG_DLL_ALM and CLIF_ANA_TX_AMPLITUDE_REG

CLOCK_CONFIG_DLL_ALM is the first register to use, to adjust the phase offset betweenthe received signal and the transmitted signal (by 45° steps).

Based on this offset, the signal emitted is more or less in phase with the emitted fieldfrom the reader. Thus, its impact on the amplitude of the reader field is different, and candrastically impact the corresponding load modulation.

The phase offset correspondence is given by the bits 2:0 as follows:

0x00 0x00 => 0° phase offset.

0x2D 0x00 => 45° phase offsetAN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 39 / 52

Page 40: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

0x5A 0x00 => 90° phase offset

0x87 0x00 => 135° phase offset

0XB4 0x00 => 180° phase offset

0XE1 0x00 => 225° phase offset

0x0E 0x01 => 270° phase offset

0x3B 0x01 => 315° phase offset

Practical consideration:

A safe way to adjust the clock phase is to place the setup on the EMVCO test bench, at2cm distance and check the load modulation test. By visualizing the signal captured bythe EMVCO test bench one can adjust the register to get optimal LMA.

On the picture below are shown the signals captured on the EMVCO test bench for asetup placed at 2cm distance:

The top picture shows the resulted load modulation signal for a setup with a well-adjustedclock.

The picture at the bottom shows the resulted load modulation of the same setup but witha clock phase not adjusted.

Figure 39. ALM – Phase offset adjustment

CLIF_ANA_TX_AMPLITUDE_REG is the second register to use to adjust the N-MOStransistor conductance value which is applied during the modulated and non-modulatedphases. This is required when the load modulation shape requires some adjustment tocomply with the targeted standards.

Only the following bits are dedicated to the transmission in card mode for ALM :

• the TX_GSN_CW_CM parameter which is the impedance of the N-MOS transistorapplied during the continuous wave period in card mode.

• the TX_GSN_MOD_CM parameter which is the impedance of the N-MOS transistorapplied during the modulation period in card mode.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 40 / 52

Page 41: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

It is also possible to adjust the load modulation amplitude by choosing the amplitudeof the output signal generated at PN7160 TX pin. Mainly, the amplitude range is 0V toTVDD but a TVDD drop can be applied to reduce the amplitude.

This is done by modifying the TX_CW_AMPLITUDE_ALM_CM bits of theCLIF_ANA_TX_AMPLITUDE_REG register.

The available drops are:

• Maximum amplitude – typically 150mV• Maximum amplitude – typically 250mV• Maximum amplitude – typically 500mV• Maximum amplitude – typically 1000mV

8.4.2 Reader mode

For reader mode, some registers can be used to optimize the communication distanceswith tags (ex: MIFARE Ultralight, MIFARE DESFire, topaz…).

The first check to be done is to compare the communication distance and the powerdistance for reference cards. The power distance corresponds to the maximumdistance at which the tag starts to wake up, but fails to exchange the data properly.The communication distance corresponds to the maximum distance at which the tagexchanges the data correctly with the reader. When the setup is correctly programmed,both distances are nearly equal (only a couple of mm differences).

The method to evaluate the POWER distance and READING distance is usually thefollowing:

0. Set the chip in normal polling mode (not Low-Power detector polling)

1. Put a scope probe loop #1 on top of the antenna (on a corner of the antenna in ordernot to disturb the field too much). You can make 2 loops with the gnd wire to capturemore field power.

2. Set the trigger for Probe #1 (typically trigger on a low pulse detection min=450 ns /max=6 µs for type A request)

3. Put a 2nd probe loop on a type A card and check the max distance (using plasticspacers) at which the card is powered but where the device does not necessarily see thecard

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 41 / 52

Page 42: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 40. Reader Mode: POWER distance and READING distance check

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 42 / 52

Page 43: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 41. Type A card response captured with the oscilloscope

Figure 42. Oscilloscope capture with the 2 probes

When the difference between POWER distance and READING distance is too high (5mm or more), it means that the Rx path can be optimized thanks to the following register:

CLIF_ANA_RX_REG: to set the AGC gain

CLIF_SIGPRO_RM_CONFIG1_REG: to set the level detection threshold (MIN LEVEL)

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 43 / 52

Page 44: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

8.5 Functional performances

8.5.1 Basics

The performance verification of the setup using PN7160 can be finalized by somefunctional checks to evaluate the user experience.

Reader mode:

For instance, the communication distance in reader mode with some cards can beverified:

• MIFARE Ultralight• MIFARE DESFire• Topaz 512• FeliCa card• ISO/IEC14443-B card• Phone in P2P mode

Card mode:

The communication distance in card mode with some readers can be verified:

• Pegoda• Omnikey 5321• Vivopay 5000• ACR122• …

In case unsatisfying results are met during the performance verification step, thetuning/matching circuit must be adjusted (fine-tuned) to improve.

8.5.2 Performances based on a PN7160 demo board 50 mm x 30 mm antenna

Here are typical results obtained on the demo board PN7160 at 3.3 V TVDD, using a50x30mm antenna on metal plate + ferrite.

The matching impedance is 15 Ohms.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 44 / 52

Page 45: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Figure 43. Card mode LMA on EMVCo bench

As observed on Figure 43, without DLMA (green curve) it would not be possible to usemode 2 and mode 3 as at 0 cm these two modes exhibit too large LMA (over EMVCospecification 80 mVpp). Using DLMA green curve, we can have an LMA optimized at alldistances, i.e. below max limit at short distances, and largest LMAs at high distances.

Figure 44. Reader mode distances for typical cards

Figure 21 shows the POWER versus READING distances obtained with the setupdescribed above for different Type A cards.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 45 / 52

Page 46: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

9 References

[1] ISO/IEC10373-6 standard – Identification cards – Test methods – Part 6: Proximitycards – 2001 release

[2] ISO/IEC14443 standard – Identification cards - Contactless integrated circuit(s)cards – Proximity cards – 2001 release

[3] NFC Forum – NFC Analog Specification[4] UM11495 - PN7160 User manual[5] AN13218 - PN7160 RF settings guide[6] AN13223 - PN7160 Dynamic load modulation amplitude guide[7] AN13224 - PN7160 Dynamic power control guide

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 46 / 52

Page 47: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

10 Abbreviations

Abbreviation Meaning

A/m Ampere per meter (magnetic field strength measurement unit)

AGC Automated Gain Control

AN Application Note

CH1 / CH2 Channel 1 / Channel 2

EMC ElectroMagnetic Compatibility

Hmin / Hmax Minimal and Maximum magnetic field strength

H-field Magnetic field

IC Integrated Circuit

ISO/IEC International Standard Organization / International Electrotechnical Community

mA milli Ampere

MHz Mega Hertz

NFC Near Field Communication

NFCC NFC Controller (i.e. PN7160)

PCB Printed-circuit board

PCD Proximity Coupling Device (Contactless reader)

PICC Proximity Integrated Circuit Card (Contactless card)

Q / Q-factor Quality Factor

RF Radiofrequency

TBD To Be Defined

V Voltage

Vpp Peak to peak voltage

Table 11. Abbreviations

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 47 / 52

Page 48: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

11 Legal information

11.1 DefinitionsDraft — A draft status on a document indicates that the content is stillunder internal review and subject to formal approval, which may resultin modifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included in a draft version of a document and shall have noliability for the consequences of use of such information.

11.2 DisclaimersLimited warranty and liability — Information in this document is believedto be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to theaccuracy or completeness of such information and shall have no liabilityfor the consequences of use of such information. NXP Semiconductorstakes no responsibility for the content in this document if provided by aninformation source outside of NXP Semiconductors. In no event shall NXPSemiconductors be liable for any indirect, incidental, punitive, special orconsequential damages (including - without limitation - lost profits, lostsavings, business interruption, costs related to the removal or replacementof any products or rework charges) whether or not such damages are basedon tort (including negligence), warranty, breach of contract or any otherlegal theory. Notwithstanding any damages that customer might incur forany reason whatsoever, NXP Semiconductors’ aggregate and cumulativeliability towards customer for the products described herein shall be limitedin accordance with the Terms and conditions of commercial sale of NXPSemiconductors.

Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer’s ownrisk.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makesno representation or warranty that such applications will be suitablefor the specified use without further testing or modification. Customersare responsible for the design and operation of their applications andproducts using NXP Semiconductors products, and NXP Semiconductorsaccepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXPSemiconductors product is suitable and fit for the customer’s applicationsand products planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriatedesign and operating safeguards to minimize the risks associated withtheir applications and products. NXP Semiconductors does not accept anyliability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orthe application or use by customer’s third party customer(s). Customer isresponsible for doing all necessary testing for the customer’s applicationsand products using NXP Semiconductors products in order to avoid adefault of the applications and the products or of the application or use bycustomer’s third party customer(s). NXP does not accept any liability in thisrespect.

Export control — This document as well as the item(s) described hereinmay be subject to export control regulations. Export might require a priorauthorization from competent authorities.

Evaluation products — This product is provided on an “as is” and “with allfaults” basis for evaluation purposes only. NXP Semiconductors, its affiliatesand their suppliers expressly disclaim all warranties, whether express,implied or statutory, including but not limited to the implied warranties ofnon-infringement, merchantability and fitness for a particular purpose. Theentire risk as to the quality, or arising out of the use or performance, of thisproduct remains with customer. In no event shall NXP Semiconductors, itsaffiliates or their suppliers be liable to customer for any special, indirect,consequential, punitive or incidental damages (including without limitationdamages for loss of business, business interruption, loss of use, loss ofdata or information, and the like) arising out the use of or inability to usethe product, whether or not based on tort (including negligence), strictliability, breach of contract, breach of warranty or any other theory, even ifadvised of the possibility of such damages. Notwithstanding any damagesthat customer might incur for any reason whatsoever (including withoutlimitation, all damages referenced above and all direct or general damages),the entire liability of NXP Semiconductors, its affiliates and their suppliersand customer’s exclusive remedy for all of the foregoing shall be limited toactual damages incurred by customer based on reasonable reliance up tothe greater of the amount actually paid by customer for the product or fivedollars (US$5.00). The foregoing limitations, exclusions and disclaimers shallapply to the maximum extent permitted by applicable law, even if any remedyfails of its essential purpose.

Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancybetween the translated and English versions.

Security — Customer understands that all NXP products may be subjectto unidentified or documented vulnerabilities. Customer is responsiblefor the design and operation of its applications and products throughouttheir lifecycles to reduce the effect of these vulnerabilities on customer’sapplications and products. Customer’s responsibility also extends to otheropen and/or proprietary technologies supported by NXP products for usein customer’s applications. NXP accepts no liability for any vulnerability.Customer should regularly check security updates from NXP and follow upappropriately. Customer shall select products with security features that bestmeet rules, regulations, and standards of the intended application and makethe ultimate design decisions regarding its products and is solely responsiblefor compliance with all legal, regulatory, and security related requirementsconcerning its products, regardless of any information or support that maybe provided by NXP. NXP has a Product Security Incident Response Team(PSIRT) (reachable at [email protected]) that manages the investigation,reporting, and solution release to security vulnerabilities of NXP products.

11.3 Licenses

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of theNear Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent rightinfringed by implementation of any of those standards. Purchase of NXPSemiconductors IC does not include a license to any NXP patent (or otherIP right) covering combinations of those products with other products,whether hardware or software.

11.4 TrademarksNotice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

MIFARE — is a trademark of NXP B.V.DESFire — is a trademark of NXP B.V.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 48 / 52

Page 49: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

MIFARE Ultralight — is a trademark of NXP B.V.NXP — wordmark and logo are trademarks of NXP B.V.

FeliCa — is a trademark of Sony Corporation.

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 49 / 52

Page 50: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

TablesTab. 1. 40 mm x 40 mm antenna outlines .....................5Tab. 2. Recommended standard coil antenna

physical characteristics ..................................... 5Tab. 3. Rx connection pros and cons ..........................24Tab. 4. Components characteristics ............................ 24Tab. 5. Impact of C0, C1 and C2 component errors

on matching impedance .................................. 27Tab. 6. TVDD voltage settings .................................... 27

Tab. 7. Target impedance ............................................27Tab. 8. Pulse shape definitions according to ISO/

IEC18092 standard @106 kbps ...................... 35Tab. 9. Pulse shape definitions according to ISO/

IEC18092 standard @212 and 424 kbps ........ 36Tab. 10. Load Modulation generation modes register

values .............................................................. 38Tab. 11. Abbreviations ...................................................47

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 50 / 52

Page 51: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

FiguresFig. 1. Standard coil antenna example .........................4Fig. 2. 40 mm x 40 mm antenna drawing .....................4Fig. 3. ALM mode 1 concept ........................................6Fig. 4. ALM mode 2 concept ........................................6Fig. 5. Single Loop Antenna concept (mode 1

illustration) ......................................................... 7Fig. 6. Load modulation illustration .............................. 7Fig. 7. Example Side Bands ISO results for modes

1, 2, 3 ................................................................8Fig. 8. Field distribution of a circular antenna with

open air environment ........................................ 9Fig. 9. Field distribution of a circular antenna with

a metal plane .................................................. 10Fig. 10. Field distribution of a circular antenna with

a metal plane and a ferrite sheet .................... 10Fig. 11. Ferrite sheet overlay recommendation ............ 11Fig. 12. PN7160 antenna matching/tuning circuit .........12Fig. 13. Antenna tuning/matching procedure

overview .......................................................... 13Fig. 14. Series equivalent circuit .................................. 14Fig. 15. Example of results for antenna

characteristic circuit .........................................16Fig. 16. Series equivalent resistance calculation ..........16Fig. 17. Parallel equivalent circuit ................................ 18Fig. 18. Impedance transformation ...............................19Fig. 19. Definition of transformation impedance Ztr ......19Fig. 20. Smith diagram for symmetrical antenna

tuning ...............................................................20Fig. 21. Measurement of the matching impedance .......21Fig. 22. Rx path ............................................................22Fig. 23. Rx path ............................................................22Fig. 24. Measurement of the matching impedance .......25Fig. 25. Impact of C1 ................................................... 25

Fig. 26. Impact of C2 ................................................... 26Fig. 27. Impact of C0 ................................................... 26Fig. 28. Impact of C0, C1 and C2 component

tolerance (error) on a 20 Ω impedancematching ..........................................................27

Fig. 29. Maximum current ratings for TVDD fordifferent antenna loading conditions ................28

Fig. 30. Example of Vup Current measured fordifferent TVDD for a 15 Ohms matching(50x30mm antenna) ........................................ 28

Fig. 31. Typical Smith chart of the symmetricReader/Writer tuning ....................................... 29

Fig. 32. Smith chart of the TVDD=5.2 V Reader/Writer tuning ....................................................30

Fig. 33. Setup to check the Q-factor ............................ 34Fig. 34. Pulse shape according to ISO/IEC18092

standard @106 kbps .......................................35Fig. 35. Pulse shape according to ISO/IEC18092

standard @212 and 424 kbps .........................36Fig. 36. Modulation Index (m) calculation in Reader/

Writer mode .....................................................37Fig. 37. Card Emulation: EMVCo test bench

measurement ...................................................37Fig. 38. Generating LMA mode 1, 2 and 3 ...................39Fig. 39. ALM – Phase offset adjustment ...................... 40Fig. 40. Reader Mode: POWER distance and

READING distance check ............................... 42Fig. 41. Type A card response captured with the

oscilloscope .....................................................43Fig. 42. Oscilloscope capture with the 2 probes ...........43Fig. 43. Card mode LMA on EMVCo bench .................45Fig. 44. Reader mode distances for typical cards ........ 45

AN13219 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.

Application note Rev. 1.2 — 13 September 2021COMPANY PUBLIC 51 / 52

Page 52: PN7160 antenna design and matching guide

NXP Semiconductors AN13219PN7160 antenna design and matching guide

Contents1 Introduction ......................................................... 32 Recommended NFC antenna

characteristics ..................................................... 42.1 Standard coil antenna design ............................42.1.1 40 mm x 40 mm ................................................42.1.2 Recommended characteristics ...........................52.1.3 Antenna size ......................................................52.2 Single loop antenna ...........................................53 Shielding and environment impact ................... 93.1 Why is shielding important ................................ 93.2 Ferrite shielding recommendation ................... 114 Antenna tuning and matching to the

PN7160 ............................................................... 124.1 Default configuration ........................................124.2 Antenna tuning/matching procedure

overview ...........................................................124.3 Step 1: Antenna model measurement ............. 134.3.1 Electrical parameters overview ........................134.3.2 Measurement method with high end vector

network analyzer: .............................................144.3.3 Measurement method with any network

analyzer ........................................................... 154.3.4 Optional: Quality factor adjustment ..................174.3.5 Determination of the parallel equivalent

circuit: ...............................................................174.4 Step 2: EMC filter design (L0 and C0

definition) ......................................................... 184.5 Step 3: Reader mode matching (C1 and C2

definition) ......................................................... 204.6 Step 4: Rx path tuning (Rrx and Crx

definition) ......................................................... 224.6.1 Receiver block functionality ............................. 224.6.2 Rx connection ..................................................234.7 Components characteristics .............................245 Matching/Tuning verification ............................255.1 Matching impedance tuning .............................255.2 Matching components tolerance ......................275.3 Matching impedance target ............................. 275.4 Impedance matching for TVDD=3.3 V ............. 285.5 Impedance matching for TVDD=5.25 V ........... 296 Dynamic Load Modulation Amplitude

(DLMA) ................................................................317 Dynamic Power Control (DPC) .........................328 Performance verification and fine tuning ........338.1 Field strength measurement ............................338.2 Carrier envelop shape verification ................... 338.2.1 Pulse shape according to the ISO/IEC

18092 standard ................................................348.2.2 Pulse shape according to the ISO/

IEC14443 standard ..........................................368.3 Load modulation amplitude measurement .......378.4 Fine tuning through registers ...........................388.4.1 Card mode .......................................................38

8.4.2 Reader mode ...................................................418.5 Functional performances ................................. 448.5.1 Basics .............................................................. 448.5.2 Performances based on a PN7160 demo

board 50 mm x 30 mm antenna ...................... 449 References ......................................................... 4610 Abbreviations .................................................... 4711 Legal information ..............................................48

Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© NXP B.V. 2021. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 13 September 2021Document identifier: AN13219