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D21 MLB - DVT (OK2FAB)
Sub Designs
1 OF 81
04/14/2017
LAST_MODIFICATION=Tue Jun 6 18:57:04 2017
SCH,MLB,D21
04/14/2017
04/14/201704/14/2017
WiFiANTFeeds
27
SYSTEM POWER: PMU (4/4)
SYSTEM POWER: B2B Battery
SYSTEM POWER: B2B Cyclone
AUDIO: Speaker Amp BottomAUDIO: CODEC (2/2)
sync
4
04/14/2017
04/14/201704/14/201704/14/201704/14/201704/14/201704/14/2017
66
16
LOWER ANTENNAUPPER ANTENNA
SIM, DEBUG CONN
5
sync
SYSTEM POWER: PMU LDOs (3/4)sync
6817
11/28/2016
BB: CONTROL & HS PERIPHERALS [6]
62 I/O: USB PDI/O: HydraI/O: B2B DOCK
07/18/2016
10
15
SOC: Power (1/3)SOC: Power (2/3)
SYSTEM POWER: PMU Bucks (1/4)SYSTEM POWER: PMU Bucks (2/4)
syncsync
04/14/2017
sync
sync
04/14/2017
75
04/14/2017
SOC: MIPI + ISP
sync
04/14/2017
04/14/201704/14/201704/14/2017
04/14/201704/14/2017
18
TEST POINTSFRONT PAGEMETROCIRC31 40
sync
12
SYSTEM: BOM TABLES (2/2)
syncsyncsync
04/14/2017
sync
7
sync
sync
2937
3231
1314
23
SOC: AOP
AUDIO: CODEC (1/2)
46
03/17/201704/14/2017
sync
152
BB: POWER
SYSTEM POWER: Boost
4559
CG: PMUs
42
48
sync
51
22
SYSTEM POWER: Iktara
11
4344
54
04/14/2017 50
sync
9
10
sync 04/14/2017
11
sync
XCVR
4
HIERARCHY
NFC
34
UAT MATCH AND TUNER
LB PAD
41
02/24/2017sync
RADIOS65
sync
35
38
36
XCVR
HB PADUHB PAD
HB DSM
SymbolPortsGuinness
4
6
15161718
25262728
30
3940
42
47
545556575859
61
63
65
7071727374
798081
3
121314
16
28
30
3334
36
39
4347
505155565758
61
63646580
75
23
56789
1213
15
1920212212
41
sync
sync
syncsync
sync
sync
sync
syncsyncsyncD21_MLB_DOE
PROBE POINTS
WIFI
06/19/2016
09/19/2016
04/14/201704/14/201710/10/201604/14/201707/18/2016
11/28/2016
sync
2G PA14
sync
69
3849
76
04/14/2017
BB: GPIOS & QLINK
SYSTEM: I2C MAP
26
CG: Niki
sync
1
49
60
35
37
test_mlb32
48
sync
GNSS
RFFE TO GPO TRANSLATOR
PMIC: BUCKS & LDOS
page1
377
sync
67
COUPLER2
LB DSM
64
syncPMIC: CLOCKS & CONTROL
SYSTEM POWER: Charger
29
04/14/2017
04/14/201704/14/201704/14/201704/14/2017
NAND
212019
191817
SOC: PCIE
SYSTEM:MECH COMPONENTSSYSTEM: TestpointsBOOTSTRAPPINGSOC: JTAG,USB,XTAL
8 11
SOC: LPDPSOC: SERIAL + SMCSOC: GPIO + UART
SOC: Power (3/3)
12
syncsyncsyncsync
sync
41
FRONT PAGE15304/14/2017
ARC: Driver
TABLE OF CONTENTS
04/14/2017
04/14/2017
QPOET MODULE106204/14/201704/14/2017
04/14/201704/14/2017
78
04/14/2017
3332
syncsync
CAMERA: B2B Strobe + ButtonsCAMERA: FCAM + FOREHEADCAMERA: Strobe DriversCAMERA: B2B Tele (TN)CAMERA: B2B Wide (KY)CAMERA: PMU (2/2)
SENSORS
24
SYSTEM: BOM TABLES (1/2)
CAMERA: PMU (1/2)
04/14/201704/14/2017
sync
CG: B2B ORB + MESACG: B2B DISPLAY + TOUCH
AUDIO: Speaker Amp Topsync
04/14/2017sync
I/O: Accessory BuckI/O: Overvoltage Cut-Off Circuit
051-02159
2017-06-06000892701210 ENGINEERING RELEASED
1 OF 80
10.0.00.122.0D21 2017_06_06_17:14:31RADIO_MLB S
0.50.0 SNFC_MLBD20 2017_05_26_07:54:42
WIFI_MLB SD21 0.20.0 2017_05_16_02:56:32
0.35.0RADIO_MLB_FFD21 S 2017_06_02_14:56:02
SYNC_DATE=06/19/2016SYNC_MASTER=sync
1 PCBPCBF,MLB,D21 ?820-00846
SCH,MLB,D211051-02159 SCH ?
CR-1 : @MLB_LIB.MLB(SCH_1):PAGE1
TABLE OF CONTENTS
DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_HIERARCHY_CONFIG_ITEM
TABLE_HIERARCHY_CONFIG_ITEM
TABLE_HIERARCHY_CONFIG_HEAD
SOURCE PROJECT SUB-DESIGN NAME VERSION SOFTHARD/ SYNC_DATE/TIME
TABLE_HIERARCHY_CONFIG_ITEM
TABLE_HIERARCHY_CONFIG_ITEM
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
D21x Specific
To enable alt in SUBBOM
D21x Specific
SENSORS
D21x Specific
D21x Specific
Default is typical
SOFT-TERM CAP SUB BOMS
AGNES INPUT
D21x Specific
D21x Specific
RCAM B2Bs
STROBE B2Bs
AUDIO
DISPLAY B2Bs
MOJAVE
ORB/MESA B2Bs
MAMBA LDO
ACC BUCK OUTPUT
CHESTNUT LDO
RCAM (TELE)
ANSEL INPUT
D21x Specific
T2
EEEE Codes
IKTARA DIODES SUB BOMS
#31526972: Update Iktara Diodes APNs
Footprint is ONSEMI
Primary is DIODES
AGNES OUTPUT
SOC
FOREHEAD B2Bs
D21x Specific
SIPs
2 OF 81
10.0.0
2 OF 80
051-02159
BOM_TABLE_ALTS HUNT, STATS SIP339M00012 M4100339M00013
BOM_TABLE_ALTS339M00011 339M00010 M5500 NIKI, STATS SIP
SoC,S,3GB 18nm DDR,B1U1000BOM_TABLE_ALTS339S00432 339S00416
U1000339S00431 339S00416 BOM_TABLE_ALTS SoC,S,3GB 20nm DDR,B1
CRITICALSoC,H,3GB 21nm DDR,B1339S00416 1 COMMONU1000
U1000BOM_TABLE_ALTS339S00415 339S00416 SoC,M,3GB 20nm DDR,B1
BOM_TABLE_ALTS U1000339S00416 SoC,S,3GB 1xnm DDR,B1339S00418
BOM_TABLE_ALTS U1000339S00416 SoC,S,3GB 20nm DDR,B1339S00417
U1000BOM_TABLE_ALTS339S00429 339S00416 SoC,H,3GB 20nm DDR,B1
U1000BOM_TABLE_ALTS339S00416339S00430 SoC,M,3GB 20nm DDR,B1
EEEE FOR (MLB,639-03380,ROW,EXTREME) CRITICAL EEEE_EXTREME_ROWEEEE_HNVF1825-7691
EEEE FOR (MLB,639-04442,ROW,ULTRA) EEEE_J08X825-7691 1 CRITICAL EEEE_ULTIMATE_ROW
EEEE FOR (MLB,639-03377,JP,EXTREME)1 EEEE_HNV8 CRITICAL825-7691 EEEE_EXTREME
EEEE FOR (MLB,639-04441,JP,ULTRA) EEEE_J08R CRITICAL1825-7691 EEEE_ULTIMATE
C6320,C6321,C6322,C6323,C6324CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA138S00159 SOFT_CAP5
SUBBOM,MLB,SCHOTTKY DIODES,ONSEMI,D21SUBBOM_DSBOM_TABLE_ALTS685-00172 685-00171
SUBBOM,MLB,SCHOTTKY DIODES,DIODES,D21 SUBBOM_DS1685-00171
DIODES_DSD3400,D3401,D3402,D3403DIODES,SHOTTKY DIODE,30V,2A,06034371S00133
4 ONSEMI_DSD3400,D3401,D3402,D3403ONSEMI,SHOTTKY DIODE,30V,2A,0603371S00132
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 2 TYPICAL_CAPC4025,C4026
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA138S00159 2 C4025,C4026 SOFT_CAP
C3909,C3925,C3926CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA138S00159 3 SOFT_CAP
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA10 SOFT_CAPC2870-C2872,C2874-C2876,C2970,C2971,C2980,C2981138S00159
138S0831 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA TYPICAL_CAP10 C2870-C2872,C2874-C2876,C2970,C2971,C2980,C2981
138S00159 2 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA SOFT_CAPC3351,C3352
C3909,C3925,C3926138S0831 3 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA TYPICAL_CAP
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4303138S0831 1 TYPICAL_CAP
C4805,C4809,C4914,C4926,C4929CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 5 TYPICAL_CAP
C6320,C6321,C6322,C6323,C6324CAP,TYPICAL,2.2UF,6.3V,0201,MURATA5138S0831 TYPICAL_CAP
C5802-C5804,C5811,C5880CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA138S00159 5 SOFT_CAP
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA SOFT_CAPC4303138S00159 1
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4250,C4261 TYPICAL_CAP2138S0831
C4250,C4261 SOFT_CAP138S00159 2 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA
BOM_TABLE_ALTS SUBBOM_CAP SUBBOM,MLB,CAP,SOFT,D21685-00151685-00152
138S0831 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA2 C3351,C3352 TYPICAL_CAP
138S00159 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA3 SOFT_CAPC3602,C3611,C3622
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 3 TYPICAL_CAPC3602,C3611,C3622
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA SOFT_CAP5138S00159 C3791,C3795-C3798
C3791,C3795-C3798CAP,TYPICAL,2.2UF,6.3V,0201,MURATA TYPICAL_CAP138S0831 5
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C4805,C4809,C4914,C4926,C4929 SOFT_CAP138S00159 5
C5016,C5018,C5134,C5029,C5136138S00159 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA5 SOFT_CAP
C5016,C5018,C5134,C5029,C5136CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 5 TYPICAL_CAP
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C5611138S00159 SOFT_CAP1
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C5611138S0831 TYPICAL_CAP1
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C5700,C5705,C5716,C5721138S00159 4 SOFT_CAP
C5700,C5705,C5716,C5721CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 4 TYPICAL_CAP
C5802-C5804,C5811,C5880CAP,TYPICAL,2.2UF,6.3V,0201,MURATA5138S0831 TYPICAL_CAP
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA138S00159 C58901 SOFT_CAP
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA138S0831 TYPICAL_CAP1 C5890
138S00160 CAP,SOFT-TERM,10UF,10V,0402,MURATA C4907,C4903,C4904,C49314 SOFT_CAP
C4907,C4903,C4904,C4931CAP,TYPICAL,10UF,10V,0402,MUR/KYO TYPICAL_CAP138S0979 4
C5600,C5602,C5603,C5702,C5703CAP,SOFT-TERM,10UF,10V,0402,MURATA SOFT_CAP138S00160 5
CAP,TYPICAL,10UF,10V,0402,MUR/KYO5138S0979 C5600,C5602,C5603,C5702,C5703 TYPICAL_CAP
TYPICAL_CAP CAP,0201,2.2UF,6.3V,KYOCERA138S0831138S00049 ALL
1 SUBBOM_CAP685-00151 SUBBOM,MLB,SOFT-TERM,D21
138S00159 9 SOFT_CAPC2900,C2901,C2903,C2906,C2907,C2910-C2913CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA
138S0831 TYPICAL_CAPCAP,TYPICAL,2.2UF,6.3V,0201,MURATA9 C2900,C2901,C2903,C2906,C2907,C2910-C2913
138S00159 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA SOFT_CAP15 C2851-C2852,C2854-C2860,C2862-C2866,C2868
138S0831 C2851-C2852,C2854-C2860,C2862-C2866,C2868 TYPICAL_CAP15 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA
SYNC_MASTER=sync SYNC_DATE=02/24/2017
SYSTEM: BOM TABLES (1/2)
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_ALT_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
Multi-Vendor Criticals
Mamba LDO
Load Switch
Isolator Switch
NAND BOM Options
Global Ferrites Alternates
Ansel L
BUCK1 Slave
BUCK5/7
BUCK8/9/10
BUCK1 Master
Boost Alt
BUCK1 Slave
BUCK0 Slave
BUCK0/2/4/11 Master
Crystal Alts
PMID1 Zener Diode
ZRB Caps
Global R/C Alternates
3 OF 81
10.0.0
3 OF 80
051-02159
138S00186 MUR,CAP,ZRB,4.7UF,25V,0603
MUR,CAP,ZRB,2.2UF,25V,0402138S00185
CRITICALNAND,H,ULTRA,TLC ULTIMATEU26001335S00287
138S00144 ALLBOM_TABLE_ALTS CAP,0402,26UF,4V,MURATA138S00143
138S00151 ALL138S00150 CAP,0402,15UF,4V,TAIYOBOM_TABLE_ALTS
0402,16uF@1V138S00144
132S0296 CAP,CER,X5R,1000PF,10%,6.3V,01005
U26001335S00240 EXTREMENAND,H,EXTREME,TLC CRITICAL
371S00121 BOM_TABLE_ALTS371S00030 DZ3300 DIODE,ZENER,20V
152S00617 ALLBOM_TABLE_ALTS IND,0.1UH,29MOHM,6.1A,1608,H=.65152S00710
152S00621 ALL152S00713 IND,0.47UH,35MOHM,3.5A,2012,H=.65BOM_TABLE_ALTS
152S00714 ALL152S00622 BOM_TABLE_ALTS IND,1UH,100MOHM,2.1A,2012,H=.65 152S00631 IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012
CAP,CER,X5R,0.1UF,20%,6.3V,01005132S0316
CAP,CER,X5R,0.22UF,20%,6.3V,0201132S0304
BOM_TABLE_ALTS353S00932 353S00576 U5890 STMICRO LDO
BOM_TABLE_ALTS TI,LOAD SW,TPS22915C353S01039353S00999 U6100
BOM_TABLE_ALTS353S01007 U6100 ONSEMI,LOAD SW,NCP333353S01039
BOM_TABLE_ALTS Y1000197S00120 197S00118 EPSON,XTAL,24MHz,1.6x1.2
138S00142 ALL CAP,0201,3UF,6.3V,SAMSUNG138S00141 BOM_TABLE_ALTS
138S00141 CAP,0201,4UF,6.3V,MURATAALLBOM_TABLE_ALTS138S00140
152S00711 ALLBOM_TABLE_ALTS IND,0.1UH,21MOHM,7.2A,2012,H=.65152S00619
ALLBOM_TABLE_ALTS152S00652152S00654 IND,MLD,1.2UH,20%,3A,72MO,H=0.8MM,2016,CYN
ALL152S00656 BOM_TABLE_ALTS IND,MLD,1.0UH,20%,3A,80MO,H=0.65,2016,TY152S00655
ALL152S00651 BOM_TABLE_ALTS IND,MLD,1.2UH,2.8A,100MO152S00653
FLTR, 65 OHMS, 0605155S00012 ALLBOM_TABLE_ALTS155S00168
152S00716 152S00626 BOM_TABLE_ALTS IND,1UH,78MOHM,2.5A,2012,H=.80ALL
152S00717 ALL152S00631 BOM_TABLE_ALTS IND,1UH,60MOHM,3.2A,2016,H=.80
152S00718 152S00632 IND,1UH,52MOHM,3.2A,2016,H=.80ALLBOM_TABLE_ALTS
152S00719 ALL IND,0.47UH,55MOHM,3.8A,2012,H=.65152S00639 BOM_TABLE_ALTS
152S00720 ALL152S00640 BOM_TABLE_ALTS IND,0.47UH,55MOHM,3.8A,2012,H=.65
ALL152S00641152S00721 BOM_TABLE_ALTS IND,1UH,60MOHM,3.6A,2016,H=.80
IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012152S00640
BOM_TABLE_ALTS155S0581 155S00067 ALL FERR, 240OHM, 0.38OHM DCR, 0201
155S0610 FERR BD, 150OHM, TDKALL155S00194 BOM_TABLE_ALTS
155S00200 ALLBOM_TABLE_ALTS FERR BD, 150OHM, TY155S0610
ALLBOM_TABLE_ALTS IND,0.47UH,20%,2.5A,80MO,1608,TY152S00558 152S00557
FERR BD,10OHM,1.1A,50MOHM DCR,01005ALL155S0876155S00340 BOM_TABLE_ALTS
ALL155S0660155S00339 FERR BD,22OHM,1.8A,40MOHM DCR,0201BOM_TABLE_ALTS
155S00338 155S0661 FERR BD,33OHM,1.5A,55MOHM DCR,0201ALLBOM_TABLE_ALTS
152S00651 IND,1.2UH, 3A, 2016, 0.65Z
152S00650 IND,0.47UH,6.6A,3225,0.8Z
152S00623 IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016
IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016152S00632
IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012152S00641
IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012152S00626
152S00622 IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012
IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012152S00621
IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012152S00620
IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608152S00617
155S0610 FERR BD, 150OHM, 01005
CAP,0201,4UF,4V,TYBOM_TABLE_ALTS ALL138S00164 138S00138
CAP,0402,20UF,6.3V,TY138S00146138S00165 BOM_TABLE_ALTS ALL
CAP,0402,22UF,4V,TYALLBOM_TABLE_ALTS138S00143138S00163
138S00049 CAP,0201,2.2UF,6.3V,KYOCERAALL138S0831 BOM_TABLE_ALTS
ALL CAP,0201,3UF,6.3V,SAMSUNG138S00142 138S00140 BOM_TABLE_ALTS
197S00118 XTAL, 24M, 1612, TDK
CAP,0201,4UF,6.3V,TYBOM_TABLE_ALTS138S00140 ALL138S00166
ALL138S00140 CAP,0201,4UF,6.3V,KYOBOM_TABLE_ALTS138S00141
ALL138S00048 138S00003 CAP,X5R,15UF,6.3V,0.65MM,0402,KYOBOM_TABLE_ALTS
BOM_TABLE_ALTS132S00088132S0639 CAP,X5R,0.47UF,25V,0.39MM,0201,MURALL
138S00145 ALL CAP,0402,20UF,6.3V,KYOCERABOM_TABLE_ALTS138S00146
138S00138 BOM_TABLE_ALTS ALL CAP,0201,4.7UF,4V,KYOCERA138S00139
BOM_TABLE_ALTS138S00143 ALL CAP,0402,22UF,4V,KYOCERA138S00144
ALL CAP,0402,14UF,4V,MURATA138S00149 BOM_TABLE_ALTS138S00150
CAP,CER,X5R,0.22UF,20%,6.3V,01005ALLBOM_TABLE_ALTS132S0436 132S0400
CAP,CER,1UF,20%,10V,X5R,0201,MURATAALLBOM_TABLE_ALTS138S0706 138S0739
T,1z,ULTIMATEBOM_TABLE_ALTS335S00284 U2600335S00287
U2600BOM_TABLE_ALTS335S00285 335S00287 T,BiCS3,ULTIMATE
BOM_TABLE_ALTS335S00287 S,BiCS3,ULTIMATEU2600335S00288
BOM_TABLE_ALTS335S00276 335S00240 U2600 SS,3Dv4,EXTREME
U2600BOM_TABLE_ALTS S,BiCS3,EXTREME335S00247 335S00240
BOM_TABLE_ALTS T,BiCS3,EXTREMEU2600335S00228 335S00240
BOM_TABLE_ALTS U2600 SS,3Dv4,ULTIMATE335S00287335S00286
BOM_TABLE_ALTS ALL311S00114 SPDT,TI311S00126
BOM_TABLE_ALTS Y1000 NDK,XTAL,24MHz,1.6x1.2197S00118197S0612
0402,5.1uF@3V138S00146
CAP,CER,X5R,1000PF,10%,10V,01005132S0396
CAP,CER,X5R,0.22UF,20%,6.3V,01005132S0436
CAP,CER,X5R,0.1UF,10%,25V,0201132S0534
CAP,CER,X5R,1UF,10%,25V,0402132S0663
CAP,CER,0.047UF,10%,25V,X5R,0201132S0664
CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM138S00014
CAP,X5R,4.7UF,20%,25V,0402138S00070
CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402138S0652
CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM138S0979
155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605
155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005
118S0717 RES, 3.92K, 0.1%, 0201
CAP,X5R,4.7UF,6.3V,0.65MM,0402138S0652
CAP,CER,X5R,1UF,20%,6.3V,0201138S0706
132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005
138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201
138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDKALL138S00024 BOM_TABLE_ALTS
ALL CAP,0402,15UF,4V,KYOCERA138S00148 BOM_TABLE_ALTS138S00150
BOM_TABLE_ALTS CAP,0201,4UF,4V,MURATAALL138S00139 138S00138
197S00120 XTAL, 24M, 1612, EPSON
CAP,CER,NP0/C0G,27PF,5%,16V,01005131S0223
CAP,CER,NP0/C0G,12PF,5%,16V,01005131S0220
CAP,CER,NP0/C0G,47PF,5%,16V,01005131S0216
131S00053 CAP,CER,C0G,220PF,5%,10V,01005
RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201118S00068
RES,MF,1/20W,2M OHM,5,0201,SMD117S0055
107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005
CAP,CER,X5R,0.1UF,10%,16V,0201132S0288
CAP,CER,X5R,470PF,10%,10V,01005132S0275
CAP,X5R,0.022UF,20%,6.3V,01005132S00093
CAP,CER,X5R,0.01UF,10%,6.3V,01005132S0245
132S0249 CAP,CER,X7R,220PF,10%,10V,01005
132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005
CAP,CER,NP0/C0G,220PF,2%,50V,0201131S0883
132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402
131S0804 CAP,CER,27PF,5%,C0G,25V,0201
CAP,CER,NP0/C0G,100PF,5%,16V,01005131S0307
CAP,CER,NP0/C0G,15PF,5%,16V,01005131S0225
SUPPR,TRANS,VARISTOR,12V,33PF,01005377S0106
197S0446 XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612
CAP,CER,X5R,1UF,20%,6.3V,0201138S0692
CAP,CER,X5R,1UF,10%,25V,0402138S0683
138S00128 CAP,CER,X5R,0.47UF,20%,6.3V,01005
138S00149 0402-3T,10.5uF@1V
0201,3uF@1V138S00139
138S00141 0201,1.1uF@3V
197S0612 XTAL, 24M, 1612, NDK
ALLBOM_TABLE_ALTS138S00133 CAP,CER,X5R,0.47UF,20%,6.3V,01005138S00128
BOM_TABLE_ALTS CAP,CER,X5R,0.22UF,20%,6.3V,20%ALL138S0739 138S0706
BOM_TABLE_ALTS CAP,CER,1UF,20%,10V,X5R,0201,KYOCERAALL138S0945 138S0739
CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO138S0648 ALLBOM_TABLE_ALTS138S0652
RES, 3.92K, 0.1%, 0201ALLBOM_TABLE_ALTS118S0764 118S0717
1uF,25V,0402,X5R,10%138S0683 1 CRITICAL COMMONC3301
SYSTEM: BOM TABLES (2/2)SYNC_DATE=03/17/2017SYNC_MASTER=test_mlb
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
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C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
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D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEMTABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
TABLE_5_ITEM
TABLE_CRITICAL_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
CRITICAL PART# COMMENTTABLE_CRITICAL_HEAD
TABLE_CRITICAL_ITEM
TABLE_CRITICAL_ITEM
Front Shields
radio_mlb_ff: SUAT1_KF
OO
radio_mlb_ff: SUAT2_RF
#25046211
FIDUCIALS
Oradio_mlb_ff: AGND_RF
Current as of D21 MCO 056-03352 REV 42
O
Changed to 860-00746 in P2
TOP SIDE
Back Shields
4 OF 81
10.0.0
4 OF 80
051-02159
ZT04082.50R1.70-NSP
STDOFF-2.57OD1.43ID-0.899H-SM
STDOFF-2.57OD1.43ID-0.899H-SM
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSPFID
01005
16VNP0-C0G
5%100PF
NP0-C0G
100PF5%16V
01005
16V
01005NP0-C0G
5%100PF
SHIELD-LOWER-FRONT-D21
SM
SM
SHIELD-FRONT-UPPER-D21
SM
SHIELD-SOFT-UPPER-BACK-D21
SM
SHIELD-SOFT-LOWER-BACK-D21
0P5SM1P0SQ-NSP
ROOM=ASSEMBLY
FID
FID
ROOM=ASSEMBLY
0P5SM1P0SQ-NSP
STDOFF-2.6OD1.6ID-0.96H-TH
STDOFF-2.9OD0.81H-SM1
10VC0G-CERM
5%220PF
01005
5%
01005
10VC0G-CERM
220PF5%10V
220PF
C0G-CERM01005
56PF25V5%
01005NP0-C0G-CERM
25V5%
NP0-C0G-CERM
56PF
01005
56PF25V5%
01005
01005
16VCERM
2%18PF
01005
16VCERM
2%18PF
4PF+/-0.1PF16VNP0-C0G01005
16V
01005NP0-C0G
+/-0.1PF4PF
2%16VCERM01005
18PF
01005
16VNP0-C0G
+/-0.1PF4PF
220PF10V
01005
5%
C0G-CERM NP0-C0G-CERM
56PF25V5%
01005
C0G-CERM
5%
01005
10V
220PF
CERM
2%18PF
01005
16VNP0-C0G01005
16V+/-0.1PF4PF
10VC0G-CERM
5%220PF
01005
STDOFF-2.56OD1.4ID0.99H-SM
C0G-CERM10V
01005
5%220PF
FID0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSPFID
FID
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSP
ROOM=ASSEMBLY
FID0P5SQ-SMP3SQ-NSP
0P5SQ-SMP3SQ-NSPFID
ROOM=ASSEMBLY
ROOM=ASSEMBLY
0P5SQ-SMP3SQ-NSPFID
FID0P5SM1P0SQ-NSP
ROOM=ASSEMBLY
ROOM=ASSEMBLY
FID0P5SM1P0SQ-NSP
ROOM=ASSEMBLY
0P5SM1P0SQ-NSPFID
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SYSTEM:MECH COMPONENTS
CHASSIS_GND_BS403
CHASSIS_GND_BS401
CHASSIS_GND_BS401 CHASSIS_GND_BS402
CHASSIS_GND_BS402
NORTH_SCREW_EXPOSED
CHASSIS_GND_BS403
C04171
2
C04071
2
C04181
2
C04081
2
C04011
2
C04021
2
C04201
2
C04101
2
C04041
2
C04211
2
C04111
2
C04221
2
C04121
2
C04051
2
C04061
2
C04131
2
C04141
2
C04151
2
C04161
2
1
BS04041
1
BS04021
FD0409
1
FD0408
1
FD0407
1
FD0406
1
FD0405
1
FD0404
1
FD04021
FD04011
FD0410
1
FD0412
1
1
2
C04091
2
C04191
2
SH04031
SH04011
SH04001
SH04021
FD04031
FD0411
1
BS04071
BS04011
BS04031
STDOFF-2.6OD1.6ID-0.96H-TH
C0403
NP0-C0G-CERM
BS0405
1
BS0406STDOFF-2.6OD0.869H-TH
4
4 34
4 34 4
4
4
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
Probe Points
SOC Debug
MOJAVE
RF Debug
PMU Debug
LCM BACKLIGHT SOURCE (3/4)
SENSE TP
LCM BACKLIGHT SINK1
LCM BACKLIGHT SINK2
ANALOG MUX B OUTPUTNote: Fiducial used as test point
LCM
AMUX
LVCC GROUND
VDD_MAIN
LVCC TP
POWER GROUND
VBATT
VBUS1
VBUS2
CALLISTO
Test Points
ANALOG MUX A OUTPUT
IN THE FACTORY FIXTURE. TP IS TO HELP WITH USB SI
FOR DIAGS
FORCE DFU
DFU
E75
Per #27963227: BUCK1 is GPU
SOC DDRPOWER
NAND Debug
BB UAT DebugLCM BACKLIGHT SOURCE
LCM BACKLIGHT SINK3
LCM BACKLIGHT SINK4
Change to BUCK1_FB to save 1 via in layout
HYDRA
ACCESSORY ID AND POWER
#29098531:GPU THROTTLE
PCIE Refclk
Sensor SPI
GPU GROUND SENSE
#29282469:SOCHOT
#29162687:CODEC BCLK
#29794618:CCG2
SOC CPU/GPU
BACKLIGHT Debug
5 OF 81
BUCK1_FB
10.0.0
5 OF 80
051-02159
1
PP0525
1TP0541
1
PP0524
1
PP0523
1
PP0522
1
PP0545
1
PP0544
1
PP0543
2 1XW0520
1
PP0562
1
PP0595
1
PP0596
1
PP0510
1
PP0509
1
PP0508
1TP0528
1TP0529
1TP0527
1TP0526
2 1
XW05401TP0540
1
PP05911
PP0590
1
PP0564
1
PP0563
2 1XW0510
1TP0510
1TP05112 1XW0511
1TP0530
1TP0531
1TP0532
1TP0533
1TP0534
1TP0535
1TP0524
1TP0523
1
PP0521
1
PP0561
1
PP0560
1
PP0514
1
PP0515
1
PP0516
1
PP0580
1
PP0581
1
PP0582
1
PP0583
1
PP0500
1
PP0501
1
PP0503
1
PP0512
1
PP0513
1
PP0520
1
PP0530
1
PP0531
1
PP0540
1
PP0541
1
PP0542
1
PP0550
1
PP0504
1TP0513
1
FD0501
1TP0500
1TP0501
1TP0520
1TP0521
1TP0515
1TP0522
1TP0525
1
FD0500
1TP0514
1TP0502
1TP0503
1TP0504
1TP0505
1TP0506
1TP0507
1TP0516
1TP0508
NAND_ANI0_VREF
AP_VDD_GPU_SENSE
PMU_AMUX_AY
WLAN_TO_AP_TIME_SYNC
PP_CPU_PCORE
AP_CPU_PCORE_SENSE
TP_SOC_SENSE
TP_VSS_CPU_SENSE
TP_VSS_SENSE
DWI_PMGR_TO_BACKLIGHT_CLK
DWI_PMGR_TO_BACKLIGHT_DATA
UAT_TUNER_RFFE_DATA
AP_TO_NFC_FW_DWLD_REQ
SPI_AOP_TO_IMU_SCLK
TP_VDD_DCS_SENSE
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
90_PCIE_AP_TO_NAND_REFCLK_P
HYDRA_TO_TIGRIS_VBUS1_VALID_L
90_PCIE_AP_TO_NAND_REFCLK_N
SPMI_PMU_BI_PMGR_SDATA
UAT_TUNER_RFFE_CLK
PP1V8_S2
SWD_AOP_TO_MANY_SWCLK
NAND_ANI1_VREFPP_CPU_PCORE_LVCC
AP_GPU_GND_SENSE
PP_DISPLAY_BL34_ANODE_CONN
PP_DISPLAY_BL34_CAT2_CONN
PP_DISPLAY_BL12_CAT2_CONN
PP_DISPLAY_BL12_CAT1_CONN
PP_DISPLAY_BL34_CAT1_CONN
PP_DISPLAY_BL12_ANODE_CONN
PP16V0_MESA_CONN
PMU_AMUX_BY
MESA_TO_BOOST_EN_CONN
HYDRA_CON_DETECT_CONN_L
PP_HYDRA_ACC2_CONN
PP_HYDRA_ACC1_CONN
90_HYDRA_DP2_CONN_N
90_HYDRA_DP2_CONN_P
90_HYDRA_DP1_CONN_N
90_HYDRA_DP1_CONN_P
PMU_HYDRA_TO_AP_FORCE_DFU
DFU_STATUS
PP_VDD_MAIN
IKTARA_COIL2_CONN
IKTARA_COIL1_CONN
PP_BATT_VCC
LVCC_CPU_GND
PP_VBUS1_E75
PP_VBUS2_IKTARA
PP_GPU_LVCC
AP_TO_PMU_TEST_CLKOUT
TP_VDDQL_SENSE
TP_DDR_VSS_SENSE
SWD_AP_BI_NAND_SWDIO
SPI_AOP_TO_IMU_MOSI
SPI_IMU_TO_AOP_MISO
SPI_AOP_TO_COMPASS_CS_L
COMPASS_TO_AOP_INT
PHOSPHORUS_TO_AOP_INT
MAKE_BASE=TRUE
BUCK1_FB
AP_TO_PMU_SOCHOT_L
PMU_TO_AP_THROTTLE_GPU1_L
CCG2_TO_SMC_INT_L
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
BOARD_ID0
AP_DEBUG3
PP3V0_S2
AOP_TO_DDR_SLEEP1_READY
SYSTEM: TestpointsSYNC_DATE=04/14/2017SYNC_MASTER=sync
P2MM-NSMSM
ROOM=TEST
46 11
ROOM=TESTTP-P55
SMP2MM-NSM
ROOM=TEST
38 36 13
21 7 SM
P2MM-NSM
ROOM=TEST
21 7
P2MM-NSMSM
ROOM=TEST
27 13
27 13
27 13
SMP2MM-NSM
ROOM=TEST
ROOM=TEST
SMP2MM-NSM
SM
ROOM=TEST
P2MM-NSM
OMIT
SHORT-20L-0.05MM-SMROOM=SOC
P2MM-NSM
ROOM=TESTSM
17 11 6
ROOM=TESTSM
P2MM-NSM
P2MM-NSM
ROOM=TESTSM
50 12
50 12
15
16
15
P2MM-NSMSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
P2MM-NSM
ROOM=TEST
SM
TP-P55ROOM=TEST
TP-P55ROOM=TEST
TP-P55ROOM=TEST
41 11
41 11
18 14
18 14
ROOM=TESTTP-P55
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
TP-P55ROOM=TEST
SMROOM=TEST
P2MM-NSM
SMP2MM-NSM
ROOM=TEST
17
17
P2MM-NSM
ROOM=TESTSM
SMP2MM-NSM
ROOM=TEST
OMIT
ROOM=SOCSHORT-20L-0.05MM-SM
TP-P55
ROOM=TEST
ROOM=TEST
TP-P55SHORT-20L-0.05MM-SM
OMIT
ROOM=SOC
TP-P55ROOM=TEST
TP-P55ROOM=TEST
ROOM=TESTTP-P55
ROOM=TESTTP-P55
TP-P55ROOM=TEST
ROOM=TESTTP-P55
TP-P55ROOM=TEST
ROOM=TESTTP-P55
21 11 SM
P2MM-NSM
ROOM=TEST
50 17 13
17 13
SMROOM=TEST
P2MM-NSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
SMP2MM-NSM
ROOM=TESTSM
P2MM-NSM
SMROOM=TEST
P2MM-NSM
14
16
16
ROOM=TEST
P2MM-NSMSM
P2MM-NSM
ROOM=TESTSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
SMP2MM-NSM
50 48 47 46 44 33 20
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11
50
50
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
P2MM-NSMSM
P2MM-NSMSM
ROOM=TEST
21 7
9
12 6
ROOM=TESTSM
P2MM-NSM
SMROOM=TEST
P2MM-NSM
SMP2MM-NSM
ROOM=TEST
SMP2MM-NSM
ROOM=TEST
P2MM-NSMSM
ROOM=TEST
SM
ROOM=TEST
P2MM-NSM
SM
ROOM=TEST
P2MM-NSM
ROOM=TEST
P2MM-NSMSM
P2MM-NSM
ROOM=TEST
SM
21 14
21 14
15 13
17 8
17 8
27 13
27 13
27 13
47 24
P2MM-NSMSM
TP-P55ROOM=TEST
ROOM=TEST
0P5SM1P0SQ-NSPFID
ROOM=TESTTP-P55
TP-P55ROOM=TEST
TP-P55ROOM=TEST
ROOM=TESTTP-P55
TP-P55ROOM=TEST
TP-P55ROOM=TEST
ROOM=TESTTP-P55
FID0P5SM1P0SQ-NSP
ROOM=TEST
ROOM=TESTTP-P55
TP-P55ROOM=TEST
ROOM=TESTTP-P55
TP-P55ROOM=TEST
TP-P55ROOM=TEST
TP-P55ROOM=TEST
TP-P55ROOM=TEST
TP-P55ROOM=TEST
ROOM=TESTTP-P55
21
42
42
42
42
42
42
43
21
43
48
48
48
48 47
48 47
48 47
48 47
47 21 12
12
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19
26 25
26 25
24 23
48 24
25 24
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
PPIN
A
PPIN
IN PP
IN PP
IN
IN
IN
PP
PP
PP
PPIN
PP
PP
IN
IN
IN
IN
IN
PP
PP
PP
A
A
A
IN
IN
IN
IN
A
A
PP
PP
IN
IN
PP
PP
A
A
A
A
A
A
A
A
A
A
IN PP
IN
IN
PP
PP
PP
PP
PP
IN
IN
IN
PP
PP
PP
PP
IN
IN
IN
IN
PP
PP
PP
IN
IN
IN
PP
PP
PP
PP
PP
PP
PP
PP
PP
IN
IN
IN
IN
IN
IN
IN
IN
IN
PP
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0100 CARRIER
0010 DVT Note: Future board revs TBD
1000 EVT
xxxx SPARE
xxxx SPARES
00100 D21 MLB
01010 D201 MLB
0=EUREKA, 1=KAROO
1011 PROTO2 (HALOGEN DOE)
001 SPI0 TEST MODE
FLOAT=LOW, PULLUP=HIGH
BOOT_CONFIG[2:0]
SELECTED -->
111 FAST SPI0 TEST
No connect
No connect
FLOAT=LOW, PULLUP=HIGH
110 SLOW SPI0 TEST
1001 PROTO2v5
BOARD_REV[3:0]
xxxx SPARE
0000 PVT
01101 D211 DEV
0=MLB, 1=DEV
01=D20x, 10=D21x
00011 D20 DEV
No connect
101 n/a
100 n/a
011 SPI0 NAND TEST
010 SPI0 NAND
01100 D211 MLB
000 SPI0
#30903807:Nostuff R0600 to move to PoR BOOT_CONFIG
BOOTSTRAPPING:BOARD REVBOARD IDBOOT CONFIG
00010 D20 MLB
FLOAT=LOW, PULLUP=HIGH
BOARD_ID[4:0]
SELECTED -->
xxxx SPARES
SELECTED -->
1100 PROTO2
1101 SPARE
1110 PROTO1
1111 Pre-Proto (Placeholder)
00101 D21 DEV
01011 D201 DEV
6 OF 81
10.0.0
6 OF 80
051-02159
21
R0612
21
R0610
21
R0611
21
R0623
21
R0622
21
R0621
21
R0601
21
R0600
21
R0620
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
BOARD_ID0
BOARD_ID1
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
BOARD_REV0
BOARD_ID3
BOARD_REV3
BOARD_REV1
BOARD_ID2
BOARD_ID4
BOARD_REV2
PP1V8_IO
BOOTSTRAPPINGSYNC_DATE=09/19/2016SYNC_MASTER=sync
1/32W
1.00KMF
5% 01005ROOM=SOC
NOSTUFF
ROOM=SOC
1.00K
NOSTUFF
010055%1/32W MF
NOSTUFF
MF1/32W5% 01005
ROOM=SOC
1.00K
5%
1.00K
ROOM=SOC
1/32W MF01005
1/32W MF
1.00K
5%
NOSTUFF
01005ROOM=SOC
ROOM=SOC01005MF
5%1/32W
1.00K
NOSTUFF
ROOM=SOC
MF5%
1/32W01005
1.00K
01005MF
1/32W1%
4.7K
ROOM=SOC
4.7K
01005MF
1/32W
NOSTUFF
ROOM=SOC
1%17 11
17 11
12 5
12
17 11 5
12
11
12
12
12
12
12
42 40 33 31 30 29 28 18 17 15 11 9 8 7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
3.14-3.46V @ 12mA MAX
0.765V - 0.84V @ 5mA MAX
SOC - USB, JTAG, XTALVDD18_USB: 1.62-1.98V @ 20mA MAXVDD18_XTAL:1.62-1.98V @ 2mA MAX
USB Reference
#31656746: Update 24MHz XTAL APNs
10 OF 80
7 OF 81
051-02159
10.0.0
GND
GND
GND
4
31
2
Y1000
21
R1020
BA27BA28
AW5
AN15
AN14
AU28
AP14
AT7
AV7
AU8
AW6
AY6BA6
AY4BA4
V2
W4
AF34
AG38A30
AV6
AT10
AT9AT12
AT13
AT8
W5
AD3AD2
B31
AW21AT22
AU7
AV5AT34
AT27
U1000
21
FL1092
2
1 C10932
1 C1092
2
1R1000
2
1 C1010
2
1R1010
21
R1011
2
1 C1011
2
1 C1095
2
1 C1090
MAKE_BASE=TRUE
SOC_24M_O
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_SOCHOT_L
AP_USB_REXT
PP1V8_XTAL
AP_TO_NAND_FW_STRAP
PMU_TO_SYSTEM_COLD_RESET_R_L
SWD_DOCK_BI_AP_SWDIOSWD_DOCK_TO_AP_SWCLK
PMU_TO_AP_HYDRA_ACTIVE_READYPMU_TO_SYSTEM_COLD_RESET_L
AP_TO_PMU_TEST_CLKOUT
AP_TO_NAND_RESET_L
AP_TO_PMU_AMUX_OUT
90_USB_AP_DATA_P90_USB_AP_DATA_N
USB_VBUS_DETECT
PMU_TO_AP_THROTTLE_PCORE_LPMU_TO_AP_THROTTLE_ECORE_L
PMU_TO_AP_THROTTLE_GPU0_LPMU_TO_AP_THROTTLE_GPU1_L
AP_TO_PMU_WDOG_RESET
PP0V8_SOC_FIXED_S1
PP3V3_USB
PP1V8_IO
XTAL_AP_24M_OUTXTAL_AP_24M_IN
MAKE_BASE=TRUE
SOC: JTAG,USB,XTALSYNC_DATE=04/14/2017SYNC_MASTER=sync
24MHZ-30PPM-9.5PF-60OHM1.60X1.20MM-SM
ROOM=SOCCRITICAL
5%1/32W
10K
ROOM=SOC
MF01005
47 41 21
21
21 5
21
17
21 12
21
21 5
21
21
24
47
47
21
17
21 5
47
47
CRITICAL
ROOM=SOC
OMIT_TABLE
WLCSPTMIT78B1-C5
240OHM-25%-0.2A-0.9OHM
01005ROOM=SOC
6.3V
0201
2.2UF20%
X5R-CERM
ROOM=SOC
0.1UF
ROOM=SOC01005
6.3VX5R-CERM
20%
ROOM=SOC
2001/32W
01005
1%
MF
ROOM=SOC
CERM16V5%
01005
12PF
NOSTUFF
511K1%1/32W
01005ROOM=SOC
MF
1/32W
1.00K
5%
MF
ROOM=SOC01005 12PF
01005
16V5%
ROOM=SOC
CERM
01005
6.3VX5R-CERM
20%0.1UF
ROOM=SOC
ROOM=SOC01005
6.3VX5R-CERM
20%0.1UF
18 15 14 10 9 8
20
42 40 33 31 30 29 28 18 17 15 11 9 8 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC GND
IN
IN
IN
IN
NCNCNC
NCNC
OUT
IN
IN
OUT
IN
OUT
IN
BI
BI
OUT
OUT
OUT
IN
BI
SYM 1 OF 16
VDD1
2_UH
1_HS
IC0
VDD1
8_XT
AL
VDD1
8_US
B
VDD3
3_US
B
VDD_
FIXE
D_US
B
XO0XI0
CPU_TRIGGER0
USB_REXT
DROOP
SOCHOT1
WDOG
CPU_TRIGGER1
GPU_TRIGGER0GPU_TRIGGER1
USB_ID
USB_VBUS
USB_DPUSB_DM
ANALOGMUX_OUT
SSD_BFH
TESTMODE
HOLD_RESET
COLD_RESET*
JTAG_TMSJTAG_TCK
JTAG_TDI
SSD_RESET*
CFSB_AON
TST_CLKOUT
CFSB
UH1_HSIC0_STBUH1_HSIC0_DATA
JTAG_SEL
JTAG_TDOJTAG_TRST*
NC
VDD_FIXED_PCIE_xxx:0.765V - 0.84V @ 140mA MAX
PCIE
LIN
K 0 PC
IE L
INK
3PC
IE L
INK
2
PCIe Clock Request Pull-Ups
PCIe Reset Pull-Downs
VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX
VDD18_PCIE:1.62V - 1.98V @ 81mA MAX
SOC - PCIE INTERFACES
8 OF 81
VOLTAGE=0.9V
VOLTAGE=1.2V
10.0.0
11 OF 80
051-02159
2
1R1150
21C1133
21C1132
21C1131
21C1130
21C1103
21C1102
21C1101
21C1100
2
1 C11912
1 C11922
1 C119321
R1194
2
1 C1194
AP27
AM27
AP31
AP29
AN30
AM31
AM29
AP26
AN26
AV35AW35
AV33AW33
AY32BA32
AY30BA30
BA36AY36
BA34AY34
AV31AW31
AV29AW29
AU32
AY24BA24
AV25AW25
AW26AY26
AW27AV27
AH36
AJ38AK38
AJ37
AU30AT30
AJ36
AK37AL37
AL38
U1000
21C1120
21C1121
21C1122
21C1123
2
1 C119821
R1198
2
1C1199
2
1R1131
2
1R1130
2
1R1100
2
1R1121
2
1R1101
90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_WLAN_TO_AP_RXD_N
90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_TXD_C_P90_PCIE_AP_TO_WLAN_TXD_C_N
PCIE_AP_TO_WLAN_RESET_L
90_PCIE_AP_TO_BB_TXD_C_P
PCIE_BB_BI_AP_CLKREQ_L
90_PCIE_AP_TO_BB_REFCLK_P90_PCIE_AP_TO_BB_REFCLK_N
PCIE_AP_TO_BB_RESET_L
90_PCIE_AP_TO_BB_TXD_C_N
90_PCIE_AP_TO_WLAN_REFCLK_N
PCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_WLAN_TO_AP_RXD_C_P
PP0V8_SOC_FIXED_PCIE_REFBUF
PCIE_AP_TO_WLAN_RESET_LPCIE_AP_TO_BB_RESET_L
90_PCIE_WLAN_TO_AP_RXD_C_N
PCIE_NAND_BI_AP_CLKREQ_L
AP_PCIE_RCAL
PP1V8_IO
PCIE_WLAN_BI_AP_CLKREQ_L
90_PCIE_AP_TO_WLAN_TXD_N
90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_BB_TO_AP_RXD_P
90_PCIE_AP_TO_BB_TXD_N
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_BB_TO_AP_RXD_C_N90_PCIE_BB_TO_AP_RXD_C_P
PCIE_AP_TO_NAND_RESET_L
90_PCIE_AP_TO_NAND_REFCLK_P
PCIE_NAND_BI_AP_CLKREQ_L
90_PCIE_AP_TO_NAND_REFCLK_N
PP1V2_SOC PP1V8_IOPP1V2_SOC_PCIE_REFBUF
PP0V8_SOC_FIXED_S1
PCIE_AP_TO_NAND_RESET_L
90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_AP_TO_NAND_TXD_C_N90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_NAND_TO_AP_RXD_N90_PCIE_NAND_TO_AP_RXD_C_P90_PCIE_NAND_TO_AP_RXD_C_N
90_PCIE_AP_TO_NAND_TXD_N90_PCIE_AP_TO_NAND_TXD_P
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SOC: PCIE
ROOM=SOC
1/32W1%200
MF01005
X5R-CERMROOM=SOC
0.1UFGND_VOID=TRUE 6.3V
0100520%
X5R-CERMROOM=SOC
0.1UFGND_VOID=TRUE 6.3V
0100520%
X5R-CERMROOM=SOC
0.1UFGND_VOID=TRUE 6.3V
0100520%
X5R-CERMROOM=SOC
GND_VOID=TRUE
0.1UF6.3V01005
20%
GND_VOID=TRUE
ROOM=SOC
6.3VX5R 01005-1
0.22UF20%
GND_VOID=TRUE
ROOM=SOC
6.3VX5R 01005-1
0.22UF20%
GND_VOID=TRUE
ROOM=NAND
6.3VX5R 01005-1
0.22UF20%
GND_VOID=TRUE
ROOM=NAND
6.3VX5R 01005-1
0.22UF20%
50
50
50
50
50
50
50
50
X5R-CERM0201
2.2UF
ROOM=SOC
6.3V20%
1.0UF
0201-1ROOM=SOC
6.3VX5R
20%
X5R-CERM
0.1UF
ROOM=SOC
6.3V
01005
20%
0%
MF1/32W
ROOM=SOC
0.00
01005
ROOM=SOC
0.1UF
X5R-CERM6.3V
01005
20%
TMIT78B1-C5WLCSP
ROOM=SOC
ROOM=SOCX5R-CERM
0.1UFGND_VOID=TRUE 6.3V
0100520%
ROOM=SOC
0.1UFGND_VOID=TRUE
X5R-CERM6.3V01005
20%
50 8
50
50
50 8
50
17
50
50
0.1UF
X5R-CERMROOM=SOC
GND_VOID=TRUE 6.3V01005
20%
ROOM=SOCX5R-CERM
0.1UFGND_VOID=TRUE 6.3V
0100520%50 8
17
X5R-CERM
ROOM=SOC
0.1UF6.3V
01005
20%
0%
ROOM=SOC
MF
0.00
1/32W
01005 2.2UF
X5R-CERM0201
ROOM=SOC
6.3V20%
17
5%
MF
ROOM=SOC
1/32W
100K
01005
100K1/32W
5%
MF
ROOM=SOC01005
MF1/32W
5%100K
ROOM=SOC01005
ROOM=SOC
100K1/32W
5%
MF01005
ROOM=SOC
1/32W5%
MF
100K
01005
17 8
17 5
17 5
17 8
17
50 8
50 8
17 8
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
50 8
20 15 14 10 42 40 33 31
30 29 28 18 17 15 11 9 8 7 6
18 15 14 10 9 7
17 8
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
NCNC
IN
IN
OUT
OUT
IN
IN
OUT
OUT
SYM 2 OF 16
LINK1 LINK2
LINK3LINK0
PCIE_CLKREQ3*
PCIE_REF_CLK3_NPCIE_REF_CLK3_P
PCIE_CLKREQ2*
PCIE_RX3_N
PCIE_REF_CLK2_PPCIE_REF_CLK2_N
PCIE_PERST3*
PCIE_TX3_PPCIE_TX3_N
PCIE_RX3_P
PCIE_TX2_NPCIE_TX2_P
PCIE_PERST2*
PCIE_RX2_NPCIE_RX2_P
PCIE_REXT
PCIE_CLKREQ0*
PCIE_REF_CLK0_PPCIE_REF_CLK0_N
PCIE_TX0_NPCIE_TX0_P
PCIE_RX0_NPCIE_RX0_P
PCIE_REF_CLK1_P
PCIE_CLKREQ1*
PCIE_PERST0*
PCIE_REF_CLK1_N
PCIE_RX1_NPCIE_RX1_P
PCIE_EXT_REF_CLK_PPCIE_EXT_REF_CLK_N
PCIE_PERST1*
PCIE_TX1_PPCIE_TX1_N
VDD_
FIXE
D_PC
IE_R
EFBU
FVD
D_FI
XED_
PCIE
_REF
BUF
VDD_
FIXE
D_PC
IE_A
NAVD
D_FI
XED_
PCIE
_ANA
VDD_
FIXE
D_PC
IE_A
NA
VDD1
8_PC
IEVD
D18_
PCIE
VDD1
2_PC
IE_R
EFBU
FVD
D12_
PCIE
_REF
BUF
BI
OUT
OUT
OUT
BI
IN
OUT
OUT
OUT
NC
NCNC
IN
NC
OUT
BI
OUT
OUT
OUT
OUT
#29684166: Freq change to 400K, change PU to 2.2K
ISP I2C1
#29684166: Freq change to 400K, change PU to 4.3K
ISP I2C2
VDD_FIXED_MIPI:0.765V - 0.84V @ 40mA MAX
SOC - MIPI & ISP INTERFACES
VDD18_MIPI:1.62V - 1.98V @ 10mA MAX
SOC D3 -> DISPLAY D1 (N & P SWAP)
FCAM
MIP
I
ISP I2C3
ISP I2C0
Disp
lay
MIPI
SOC D1 -> DISPLAY D3DISPLAY MIPI LANE SWAPS
Pin assignment optimized for D21/D211 MLB
#30699217: Change camera shutdown pins
9 OF 81
10.0.0
12 OF 80
051-02159
21
R1241
2
1R1212
2
1R1211
2
1R1232
2
1R1231
2
1R1222
2
1R1221
2
1R1252
2
1R1250
2
1R1201
2
1R1202
G14
G12
F13
F11
AB36
AA35AC37AB34
R37
T37
U35
U36
R38
U37
V34
V36
U38
D11
A6
A7
B9
A10
A8
B6
B7
A9
B10
B8
D13
B15
B17
A16
A15
A17
B16
D12
B14
B12
A13
A14
A12
B13
AB38AA37
Y38Y34
Y36W36
V38W35
AB6
AB4AA3
Y4
AA5AA4
U1000
21
R1242
21
R1240
2
1 C12962
1 C12902
1 C12952
1 C1291
I2C2_ISP_SCLI2C2_ISP_SDA
PP1V8_IO
PP1V8_IO
PP1V8_IO
90_MIPI_FCAM_TO_AP_CLK_N90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_FCAM_TO_AP_DATA1_N
90_MIPI_FCAM_TO_AP_DATA0_N90_MIPI_FCAM_TO_AP_DATA0_P
90_MIPI_AP_TO_DISPLAY_DATA0_P90_MIPI_AP_TO_DISPLAY_DATA0_N
90_MIPI_AP_TO_DISPLAY_DATA3_P90_MIPI_AP_TO_DISPLAY_DATA3_N
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_DATA1_N
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_CLK_N90_MIPI_AP_TO_DISPLAY_CLK_P
MIPID_REXT
MIPI0C_REXT
PP1V8_IOPP0V8_SOC_FIXED_S1
I2C3_ISP_SDAI2C3_ISP_SCL
I2C0_ISP_SCL
I2C1_ISP_SDA
I2C0_ISP_SDA
I2C1_ISP_SCLI2C1_ISP_SDA
PP1V8_IO
I2C0_ISP_SCLI2C0_ISP_SDA
I2C1_ISP_SCL
I2C2_ISP_SCLI2C2_ISP_SDA
AP_TO_WIDE_CLK
AP_TO_TELE_CLK
AP_TO_FCAM_CLK
AP_TO_FCAM_CLK_R
AP_TO_MUON_BL_STROBE_EN
ISP_TO_FCAM_SHUTDOWN_L
AP_DEBUG3
ISP_TO_WIDE_SHUTDOWN_LISP_TO_TELE_SHUTDOWN_L
AP_TO_TELE_CLK_RAP_TO_WIDE_CLK_R
I2C3_ISP_SCLI2C3_ISP_SDA
90_MIPI_FCAM_TO_AP_DATA1_P
SOC: MIPI + ISPSYNC_DATE=04/14/2017SYNC_MASTER=sync
31
31
01005ROOM=SOC
1%
MF1/32W
33.2
ROOM=SOC
1.00K5%1/32WMF01005
1.00K5%
MF1/32W
01005ROOM=SOC
31 9
31 9
30
MF01005
1/32W
ROOM=SOC
4.3K1%
1/32WMF01005ROOM=SOC
1%4.3K
1/32W5%
MF
ROOM=SOC01005
2.2K
ROOM=SOC
MF1/32W5%
01005
2.2K
MF
2001%1/32W
01005ROOM=SOC
01005MF
ROOM=SOC
2001%1/32W
42
42
42
42
41
5
33
33
30
29 9
32 29 9
33 9
33 9
30 9
30 9
42
42
42
42
42
42
33
33
33
33
33
33
01005ROOM=SOC
MF1/32W5%1.00K
ROOM=SOC
1.00K5%1/32WMF01005
WLCSPTMIT78B1-C5
33.2
1/32W
01005MF
ROOM=SOC
1%
33.2
01005ROOM=SOC
1%1/32WMF
ROOM=SOC
X5R-CERM
0.1UF6.3V20%
01005
0.1UF
ROOM=SOC
6.3V20%
X5R-CERM01005
2.2UF20%6.3V
0201ROOM=SOC
X5R-CERM6.3VX5R-CERM
ROOM=SOC
2.2UF
0201
20%
33 9
33 9
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6 18 15 14 10 8 7
29 9
32 29 9
31 9
31 9
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
30 9
30 9
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
NC
NCOUT
OUT
OUT
OUT
OUT
BI
OUT
BI
OUT
BI
NCNC
NC
OUT
NC
NC
OUT
OUT
OUT
OUT
BI
BI
IN
IN
IN
IN
BI
BI
SYM 3 OF 16
ISP_I2C3_SCL
ISP_I2C1_SDA
ISP_I2C2_SDAISP_I2C2_SCL
ISP_I2C0_SDA
ISP_I2C1_SCL
ISP_I2C0_SCL
ISP_I2C3_SDA
SENSOR_INT
SENSOR0_CLKSENSOR1_CLKSENSOR2_CLK
SENSOR0_RSTSENSOR1_RSTSENSOR2_RSTSENSOR3_RSTSENSOR4_RST
SENSOR0_XSHUTDOWNSENSOR1_XSHUTDOWN
SENSOR1_ISTRBSENSOR0_ISTRB
MIPI0C_DNCLK
MIPI0C_REXT
MIPI0C_DPCLK
MIPI0C_DNDATA1MIPI0C_DPDATA1
MIPI0C_DNDATA0MIPI0C_DPDATA0
MIPI1C_REXT
MIPI1C_DNDATA0
MIPI1C_DNDATA1MIPI1C_DPDATA1
MIPI1C_DNCLKMIPI1C_DPCLK
MIPI1C_DPDATA0
MIPID_DPDATA0MIPID_DNDATA0
MIPID_DPDATA1MIPID_DNDATA1
MIPID_DPDATA2
MIPID_DPDATA3
MIPID_DNDATA2
MIPID_DNDATA3
DISP_TOUCH_BSYNC0DISP_TOUCH_BSYNC1
DISP_TOUCH_EB
MIPID_DNCLK
MIPID_REXT
MIPID_DPCLK
DISP_I2C_SDA
DISP_POL
DISP_I2C_SCL
VDD1
8_M
IPI
VDD_
FIXE
D_M
IPI
NC
NCNC
NC
SOC - LPDP INTERFACES
D21
OnlyLPDP TELE LANE SWAPS
SOC D3 -> TELE D2
VDD_FIXED_LPDP_RX:0.765V - 0.84V @ 47mA MAX
Desense for Wifi frequencies
VDD12_LPDP_RX:1.14V - 1.26V @ 66mA MAX
SOC D5 -> TELE D1SOC D4 -> TELE D0
10 OF 81
GNDGND
10.0.0
13 OF 80
051-02159
2
1C1301
2
1 C13962
1 C13902
1 C1395
R9 P9 G18
G16
T9M9
F16
F17
F15
A19B19
A20B20
A21B21
A24B24
A25B25
A26B26
B23
A23
D18
A22B22
D15D16D17D19D20D21
J4J5
K3K4
L4L5
M3M4
H6H3
G4G5
Y6Y2
U1000
2
1R1300
2
1 C13942
1 C13932
1 C13912
1 C1392PP0V8_SOC_FIXED_S1PP1V2_SOC
90_LPDP_WIDE_TO_AP_D0_P
90_LPDP_WIDE_TO_AP_D2_N90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_WIDE_TO_AP_D1_P90_LPDP_WIDE_TO_AP_D1_N
LPDP_TELE_BI_AP_AUX
AP_LPDPRX_RCAL_NEG
PP0V8_SOC_FIXED_S1
90_LPDP_TELE_TO_AP_D0_P
90_LPDP_TELE_TO_AP_D2_N
90_LPDP_TELE_TO_AP_D1_N
LPDP_WIDE_BI_AP_AUX
90_LPDP_TELE_TO_AP_D1_P
90_LPDP_WIDE_TO_AP_D0_N
MAKE_BASE=TRUE
SOC: LPDPSYNC_DATE=04/14/2017SYNC_MASTER=sync
WLCSPTMIT78B1-C5
300
01005-1ROOM=SOC
1/32WMF
1%
15PF
ROOM=SOC01005NP0-C0G-CERM
5%16V
0201
2.2UF6.3V20%
X5R-CERM
ROOM=SOC
6.3V
0.01UF
01005
ROOM=SOC
10%
X5R01005X5R-CERM6.3V20%
ROOM=SOC
0.1UF
ROOM=SOC01005
16V5%
100PF
NP0-C0G
31
31
31
31
31
31
31
20%
0201
2.2UF6.3V
ROOM=SOC
X5R-CERM0201
20%
ROOM=SOC
6.3VX5R-CERM
2.2UF
0201ROOM=SOC
2.2UF6.3VX5R-CERM20%
30
30
30
30
30
30
30
18 15 14 10 9 8 7 20 15 14 8
18 15 14 10 9 8 7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
NCNC
NC
NCNC
NCNC
NCNC
NCNC
SYM 4 OF 16
VDD_
FIXE
D_LP
DP_R
X
VDD_
FIXE
D_LP
DP_T
X
LPDP_TX0NLPDP_TX0P
LPDP_TX1PLPDP_TX1N
LPDP_TX2PLPDP_TX2N
LPDP_TX3PLPDP_TX3N
LPDP_CAL_DRV_OUT
LPDP_AUX_PLPDP_AUX_N
LPDP_CAL_VSS_EXT
EDP_HPDDP_WAKEUP
LPDPRX_RX_D0_P
LPDPRX_RX_D1_NLPDPRX_RX_D1_P
LPDPRX_RX_D0_N
LPDPRX_RX_D2_N
LPDPRX_RX_D3_NLPDPRX_RX_D3_P
LPDPRX_RX_D2_P
LPDPRX_RX_D4_P
LPDPRX_RX_D5_NLPDPRX_RX_D5_P
LPDPRX_RX_D4_N
LPDPRX_AUX_D0_P
LPDPRX_BYP_CLK_PLPDPRX_BYP_CLK_N
LPDPRX_AUX_D2_PLPDPRX_AUX_D1_P
LPDPRX_AUX_D4_PLPDPRX_AUX_D3_P
LPDPRX_AUX_D5_P
LPDPRX_RCAL_P
LPDPRX_RCAL_N
LPDPRX_EXT_C
VDD_
FIXE
D_PL
L_LP
DP
VDD1
2_PL
L_LP
DP
VDD1
2_LP
DP_R
X
VDD1
2_LP
DP_T
X
NC
NC
IN
IN
IN
IN
IN
IN
BI
NCNC
NCNC
IN
IN
IN
IN
IN
IN
BI
#29545367:100kHz uses 2.2kohm
AP I2C2
AP I2C1
AP I2C0
.
SOC - SERIAL INTERFACES
#29673218: Change R1440, R1441 to 2.2K
AP I2C3
SMC I2C0
SMC I2C1
#30765511:Add back R1461
SPI: Route as Daisy-Chain (No T's Allowed)
NC (Was BB_TO_AP_RESET_ACT_L)
11 OF 81
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
14 OF 80
051-02159
21
R1461
2
1R1440
2
1R1441
2
1R1410
2
1R1411
2
1R1430
2
1R1431
2
1R1421
2
1R1420
21
R1470
21
R1465
21
R1464
2
1R1450
2
1R1451
21
R1462
21
R1460
21
R1463
2
1R1401
2
1R1400
AW20AV21
AE37AF38AE35AE38
AE6AD5AE2AE4
AT23AW22AY22AU23
AU22BA22BA21AV22
AW15AW19
AU20AT20
AW16AY16
AL6
AM4AM5
AM3AL2
BA20
AG4
AH2
AH4AH6
AG5
AT35
AR36
AR35AR34
AT36
AH34
AG35
AG37AH38
AG36
AV23
AT24
AT26AT25
AW23
AC38AC36
B34A34
AD36AD38
AG2AG3
AF36AE36
AV19
U1000
21
R1480
I2C1_AP_SCLI2C1_AP_SDA
I2C2_AP_SDA
I2C3_AP_SCLI2C3_AP_SDA
I2C0_SMC_SCL
I2C2_AP_SCL
I2C0_SMC_SDA
I2C3_AP_SDAI2C3_AP_SCL
PP1V8_S2
I2C0_SMC_SCL
PP1V8_S2
I2C1_SMC_SCLI2C1_SMC_SDA
I2C0_SMC_SDA
I2C4_AP_SCLI2C4_AP_SDA
I2C1_SMC_SDA
IKTARA_TO_SMC_INTCCG2_TO_SMC_INT_L
I2C1_SMC_SCL
PP1V8_IO
SPI_TOUCH_TO_AP_MISO
SPI_AP_TO_MESA_SCLK_R
SPMI_PMGR_TO_PMU_SCLK
I2C1_AP_SCLI2C1_AP_SDA
PP1V8_IO
I2C0_AP_SDAI2C0_AP_SCL
PP1V8_IO
SPMI_PMU_BI_PMGR_SDATA
I2C2_AP_SCLI2C2_AP_SDA
I2S_AP_TO_CODEC_MCLK1
PP1V8_IO
AP_TO_NAND_SYS_CLK_R AP_TO_NAND_SYS_CLK
I2C0_AP_SDAI2C0_AP_SCL
AP_TO_TOUCH_CLK32K_RESET_L
DWI_PMGR_TO_BACKLIGHT_DATA
SPMI_PMGR_TO_PMU_SCLK_R
DWI_PMGR_TO_BACKLIGHT_CLK
SPI_AP_TO_TOUCH_SCLK_R
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R
I2S_AP_TO_SPKRAMP_TOP_MCLK
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SPI_AP_TO_TOUCH_SCLK
SPI_AP_TO_CODEC_SCLK
SPI_AP_TO_MESA_SCLKMESA_TO_AP_INT
SPI_AP_TO_CODEC_SCLK_R
SPI_MESA_TO_AP_MISO
SPI_CODEC_TO_AP_MISO
BOARD_ID3
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
I2S_CODEC_ASP3_TO_AP_DIN
AP_TO_CCG2_SWCLKCODEC_TO_AP_INT_L
I2S_BB_TO_AP_BCLK
I2S_BB_TO_AP_DIN
I2S_AP_TO_CODEC_ASP3_LRCLKI2S_AP_TO_CODEC_ASP3_BCLK
I2S_AP_TO_CODEC_ASP3_DOUT
I2S_AP_TO_CODEC_MCLK1_R
I2S_BB_TO_AP_LRCLK
I2S_AP_TO_BB_DOUT
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
SPI_AP_TO_TOUCH_MOSI
SPI_AP_TO_TOUCH_CS_L
SPI_AP_TO_CODEC_CS_L
SPI_AP_TO_CODEC_MOSI
SPI_AP_TO_MESA_MOSI
I2S_AP_TO_SPKRAMP_TOP_MCLK_R
AP_BI_CCG2_SWDIO
SOC: SERIAL + SMCSYNC_DATE=04/14/2017SYNC_MASTER=sync
MF
0.00
ROOM=SOC01005
0%1/32W
42
2.2K5%
ROOM=SOC
1/32WMF
01005
2.2K
01005
5%
MF1/32W
ROOM=SOC
2.2K
MF
5%1/32W
ROOM=SOC01005
5%
MF
ROOM=SOC01005
2.2K1/32W
MF
1.43K
01005
1/32W1%
ROOM=SOC
MF01005
1%1/32W
1.43K
ROOM=SOC
50
50
5%1/32W
MF
1.00K
01005ROOM=SOC
MF
ROOM=SOC
1.00K5%
1/32W
01005
40
40
0%
MF1/32W
01005
0.00
ROOM=SOC
21
0.00
ROOM=SOC01005
0%1/32WMF
17 6
42
38
MF1/32W1%
33.2
ROOM=SOC01005
46 5
01005
1/32W5%
ROOM=SOC
MF
4.7K
ROOM=SOC
4.7K5%
1/32W
01005MF
47 11
36
46
46
47 11
36
MF01005
0.00
1/32W
ROOM=SOC
0%
36
36
36
42
42
42
17
21 5
41 5
41 5
25
45 41 21 11
45 41 21 11
48 34 11
48 34 11
38 33 11
38 33 11
48 42 41 11
48 42 41 11
46 25 24 23 22 11
46 25 24 23 22 11
AG4
36
36
36
36
01005
1/32W
ROOM=SOC
1%
MF
33.236
50
50
17 6 5
17 6
6
43
43
43
ROOM=SOC
0%1/32WMF
0.00
01005
43
ROOM=SOC
MF1/32W
4.3K1%
01005MF
1/32W
01005
4.3K1%
ROOM=SOC
WLCSPTMIT78B1-C5
01005ROOM=SOC
0.00
MF
0%1/32W
46 25 24 23 22 11
48 42 41 11
48 42 41 11
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
46 25 24 23 22 11
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
47 11
47 11
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
48 34 11
48 34 11
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
45 41 21 11
45 41 21 11
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
38 33 11
38 33 11
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
NCIN
IN
NC
BI
OUT
OUT
IN
OUT
OUT
IN
BI
IN
BI
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
BI
OUT
OUT
IN
BI
OUT
OUT
BI
OUT
BI
BI
OUT
OUT
BI
NCNC
NCNC
NC
NC
OUT
OUT
IN
OUT
OUT
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
NCNC
SYM 6 OF 16
SPMI_SDATASPMI_SCLK
I2C0_SDAI2C0_SCL
I2C1_SCLI2C1_SDA
I2C2_SDA
I2C3_SCLI2C3_SDA
SMC_I2CM0_SCL
SEP_SPI0_MISO
SMC_I2CM1_SDA
SMC_UART0_TXD
SEP_SPI0_SCLK
SEP_SPI0_MOSI
SEP_I2C_SCLSEP_I2C_SDA
I2C2_SCL
SMC_UART0_RXD
SMC_I2CM0_SDA
SMC_I2CM1_SCL
DWI_CLK
NAND_SYS_CLK
DWI_DO
CLK24M_OUT
I2S0_BCLKI2S0_LRCK
I2S0_DOUT
I2S1_LRCKI2S1_BCLKI2S1_MCK
I2S0_DIN
I2S0_MCK
I2S2_MCKI2S2_BCLK
I2S2_DIN
I2S1_DINI2S1_DOUT
I2S2_LRCK
I2S2_DOUT
SPI0_MISO
I2S3_MCK
I2S3_DOUTI2S3_DIN
I2S3_BCLKI2S3_LRCK
SPI0_SSIN
SPI1_SCLKSPI1_SSIN
SPI1_MOSISPI1_MISO
SPI0_MOSISPI0_SCLK
SPI3_MISOSPI3_MOSISPI3_SCLK
SPI2_SSINSPI2_SCLKSPI2_MOSISPI2_MISO
SPI3_SSIN
#29471964: Remove PWM AP Timebase Calibration Connection for Prox
WEST
SOUT
HWES
TNO
RTHE
AST
EAST
SOC - GPIO INTERFACES
12 OF 81
10.0.0
15 OF 80
051-02159
P2R5
AF4AF5
N35N36M35K36
D31C32B32D30
B30C28B29B28
M37P36L36P34
AF2AF3
A28C30D28
AC4AB2
AK5AK4AK3AJ6AJ5AJ4AJ3V3V4V5U2U4U6T2T3T4T5R2R3R4P4P6
A32B33D29D32C34D33L35K34K38L37N37R35P38R36T35AL4
U1000
BOARD_ID0
BOARD_REV1
PMU_TO_AP_BUTTON_POWER_KEY_LPMU_TO_AP_BUTTON_VOL_DOWN_L
BOARD_REV0
BOARD_REV2
UART_ACCESSORY_TO_AP_RXD
SPKRAMP_TOP_TO_AP_INT_L
AP_TO_TOUCH_MAMBA_RESET_L
CAMPMU_TO_AP_IRQ_LAP_TO_BBPMU_RADIO_ON_L
UART_AP_TO_ACCESSORY_TXD
BOARD_REV3TOUCH_TO_AP_INT_L
AP_TO_WLAN_DEVICE_WAKE
BOARD_ID1PMU_HYDRA_TO_AP_FORCE_DFUDFU_STATUSBOARD_ID2BOARD_ID4AP_TO_PMU_AMUX_SYNC
BB_TO_AP_RESET_DETECT_LAP_TO_BB_TIME_MARK
UART_AP_DEBUG_TXD
AP_TO_DISPLAY_RESET_L
UART_AP_DEBUG_RXD
AP_TO_BB_MESA_ON
UART_BT_TO_AP_CTS_LUART_AP_TO_BT_RTS_LUART_BT_TO_AP_RXD
AP_TO_BB_RESET_LAP_TO_BB_COREDUMPAP_TO_NFC_DEV_WAKEAP_TO_CAMPMU_RESET_L
UART_AP_TO_WLAN_TXD
UART_AP_TO_BT_TXD
UART_WLAN_TO_AP_RXDUART_AP_TO_WLAN_RTS_LUART_WLAN_TO_AP_CTS_L
UART_AP_TO_NFC_TXDUART_NFC_TO_AP_RXD
UART_AP_TO_NFC_RTS_LUART_NFC_TO_AP_CTS_L
UART_GNSS_TO_AP_RXDUART_AP_TO_GNSS_RTS_L
UART_AP_TO_GNSS_TXD
UART_GNSS_TO_AP_CTS_L
AP_TO_BB_IPC_GPIO1
AP_TO_NFC_FW_DWLD_REQ
AP_TO_SPKRAMP_TOP_RESET_LAP_TO_BT_WAKE
AP_TO_GNSS_WAKE
PMU_TO_AP_PRE_UVLO_L
WLAN_TO_AP_TIME_SYNC
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SOC: GPIO + UART
21
21 7
50
50
50
50
42
50
50
50 5
50 5
42
5
47
47
50
50
50
50
50
50
50
50
50
50
50
50
47
47
21
21
6
6
6
6
42
6
6
6
47 21 5
50
6 5
38
29
38
50
50
50
29
WLCSPTMIT78B1-C5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
OUT
OUT
IN
OUT
NC
NC
NC
IN
NC
OUT
OUT
IN
NC
NC
OUT
NC
OUT
OUT
OUT
OUT
IN
NC
OUT
OUT
NC
NCNC
IN
OUT
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
SYM 5 OF 16
UART7_RXDUART7_TXD
UART4_TXD
UART4_CTS*
UART3_CTS*
UART2_RTS*
UART1_RTS*UART1_CTS*
UART0_TXDUART0_RXD
UART1_TXD
UART2_CTS*
UART1_RXD
TMR32_PWM0TMR32_PWM1TMR32_PWM2
UART2_RXDUART2_TXD
UART3_RXDUART3_TXD
UART4_RTS*UART4_RXD
UART3_RTS*
UART6_RXDUART6_TXD
GPIO_0GPIO_1GPIO_2GPIO_3GPIO_4GPIO_5GPIO_6GPIO_7GPIO_8GPIO_9GPIO_10
GPIO_14
GPIO_12GPIO_13
GPIO_11
GPIO_15
GPIO_20GPIO_19
GPIO_16GPIO_17GPIO_18
GPIO_23GPIO_24GPIO_25
GPIO_22GPIO_21
GPIO_26GPIO_27GPIO_28GPIO_29GPIO_30GPIO_31GPIO_32GPIO_33GPIO_34GPIO_35
GPIO_37GPIO_36
REQUEST_DFU2REQUEST_DFU1
#30638490: Route U1000/U5000 ASP1 BCLK, LRCLK with _R
VDDIO18_AOP:1.8V @ 15mA MAX
SOC - AOP
13 OF 81
10.0.0
16 OF 80
051-02159
2
1R1623
2
1R1622
2
1R1621
2
1R1620
21R1601
21R1602
2
1 C16902
1 C1691
AP19
AP17
AP15
AP13
AC2AC5
BA18
AY19
BA17
AT15AU11
AW8BA8
AY8AT14
AT21AY17
AV20
AV8AU10AW7
AW17AW18BA16
AU19BA15
BA13
AT19BA14
AW9AV10
AV9BA9
AY14BA12AV18AW14AT18BA10AV17BA11AY13AV15AU17AW13AV14AW12AV13AT17AV16AU16AY11AV12AY10AV11AT16
AW11AW10AU13AU14
AT11U1000
ALS_TO_AOP_INT_LAOP_TO_CODEC_RESET_L
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
SPI_AOP_TO_IMU_SCLK_R
SPI_IMU_TO_AOP_MISO
AOP_TO_MESA_BLANKING_EN
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
SPI_AOP_TO_IMU_SCLKSPI_AOP_TO_IMU_MOSI
UART_BB_TO_AOP_RXD
AOP_TO_WLAN_CONTEXT_AAOP_TO_WLAN_CONTEXT_B
I2S_AOP_TO_CODEC_MCLK2_RI2S_AOP_TO_CODEC_ASP2_LRCLK
I2S_CODEC_ASP2_TO_AOP_DIN
TOUCH_TO_AOP_GPO
I2S_AOP_TO_CODEC_ASP2_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
ACCEL_GYRO_TO_AOP_DATARDYSPI_AOP_TO_ACCEL_GYRO_CS_LACCEL_GYRO_TO_AOP_INT
PHOSPHORUS_TO_AOP_INT
DISPLAY_TO_MANY_BSYNC
AOP_TO_CODEC_CLP_EN
PROX_BI_AOP_INT_L_PWM
AOP_TO_SPKRAMP_BOT_ARC_RESET_L
SPI_AOP_TO_PHOSPHORUS_CS_L
AOP_TO_MESA_I2C_ISO_EN
COMPASS_TO_AOP_INT
I2C1_AOP_SCL
SWD_AOP_TO_MANY_SWCLK
I2C0_AOP_SCLI2C0_AOP_SDA
I2C1_AOP_SDA
PP1V8_S2
PP1V8_S2SWD_AP_BI_NAND_SWDIOSWD_AOP_BI_BB_SWDIO
PMU_TO_AOP_CLK32K
PP1V8_S2
AOP_TO_TOUCH_PROX_STATE
PMU_TO_AOP_IRQ_L
I2S_AOP_TO_CODEC_ASP2_DOUT
HYDRA_TO_NUB_INT
CODEC_TO_AOP_GPIO2CODEC_TO_AOP_GPIO1
I2S_AOP_TO_CODEC_MCLK2
MESA_TO_AOP_FDINT
SPKRAMP_BOT_ARC_TO_AOP_INT_L
HYDRA_TO_NUB_DOCK_CONNECTUART_AOP_TO_BB_TXD
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
AOP_TO_DDR_SLEEP1_READY
SPI_AOP_TO_COMPASS_CS_L
SOC: AOPSYNC_DATE=04/14/2017SYNC_MASTER=sync
36
01005
1/32W5%
MF
ROOM=SOC
1.00K
01005
1/32W5%
1.00K
ROOM=SOC
MF
50
50
33
MF01005
2.2K5%
1/32W
ROOM=SOC
2.2K
ROOM=SOC
1/32W
01005
5%
MF
39 38 37 36
48 39 36
27 5
33
43
15 5
39 37
36
21
39 37
43
50 42 29 22 21
27 5
27
27
27
27
47
47
33
33
43
43 39 37
43 39 37
50
17 5
21
50 17 5
36
36
27 5
27 5
50
50
42
42
36
49.9
MF
ROOM=SOC
1/32W1%
01005
36
36
36
1/32W
33.2
1%
MF
ROOM=SOC01005
27 5
36
27 5
38 36 5
38 36
X5R-CERM
2.2UF20%6.3V
ROOM=SOC0201
0.1UF20%
ROOM=SOC
6.3VX5R-CERM01005
WLCSPTMIT78B1-C5
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
NCNC
OUT
OUT
NC
BI
IN
BI
OUT
IN
OUT
NC
OUT
IN
OUT
IN
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
IN
NC
OUT
BI
OUT
OUT
BI
NC
BI
BI
NC
IN
OUT
IN
IN
NC
IN
OUT
IN
OUT
IN
OUT
IN
IN
IN
OUT
OUT
OUT
IN
IN
IN
SYM 7 OF 16AOP_PDM_CLK0
RT_CLK32768
AOP_SWD_TCK_OUT
AOP_SWD_TMS0AOP_SWD_TMS1
AOP_PDM_DATA1
SWD_TMS2
DOCK_ATTENTION
AOP_PDM_DATA0
SWD_TMS3
AOP_I2CM0_SCL
AOP_I2CM1_SDAAOP_I2CM1_SCL
AOP_I2CM0_SDA
DOCK_CONNECT
AOP_FUNC_0AOP_FUNC_1
AON_DDR_RESET*
AOP_FUNC_2
AOP_FUNC_7AOP_FUNC_6
AOP_FUNC_12AOP_FUNC_11AOP_FUNC_10
AOP_FUNC_3
AOP_FUNC_9AOP_FUNC_8
AOP_FUNC_5AOP_FUNC_4
AOP_FUNC_19
AOP_FUNC_13
AOP_FUNC_18AOP_FUNC_17AOP_FUNC_16AOP_FUNC_15AOP_FUNC_14
AOP_FUNC_20AOP_FUNC_21AOP_FUNC_22AOP_FUNC_23AOP_FUNC_24
AOP_FUNC_26
AOP_SPI_MOSIAOP_SPI_MISO
AOP_FUNC_25
AOP_SPI_SCLK
AOP_UART2_RXDAOP_UART2_TXD
AOP_I2S0_BCLK
AOP_UART1_TXD
AOP_UART0_TXD
AOP_UART1_RXD
AOP_UART0_RXD
AOP_I2S0_DINAOP_I2S0_MCK
AOP_I2S0_DOUT
AOP_I2S0_LRCK
VDDI
O18
_AO
PVD
DIO
18_A
OP
VDDI
O18
_AO
PVD
DIO
18_A
OP
1.01V @ 2.1A MAX
0.7V @ 75mA MAX
0.575V @ 1.4A MAX0.8V @ 2.8A MAX
1.06V @ 1.1A MAX0.80V @ 0.63A MAX
0.735V @ 0.6A MAX
0.675V @ 0.19A MAX
0.575V @ 2.7A MAX
1.06V @ 11.0A MAX0.8V @ 6A MAX
0.8V @ 10.6A MAX0.575V @ 3.4A MAX
1.06V @ 18.3A MAX0.765V @ 4.9A MAX0.635V @ 2.6A MAX
SOC - CPU, GPU & SOC RAILS
1.06V @ 4.3A MAX
1.2V @ 7mA MAX (GPU)1.2V @ 20mA MAX (SOC)
1.2V @ 7mA MAX (CPU)
0.8V @ 6mA MAX
0.8V @ 6+10=16mA MAX
14 OF 81
10.0.0
17 OF 80
051-02159
2
1 C17232
1 C17222
1 C17212
1 C1720
2
1 C1794
4
3
2
1
C1712
4
3
2
1
C1713
2 1
XW1790
2
1 C17602
1 C1761
4
3
2
1
C1763
2
1 C17032
1 C1702
4
3
2
1
C1793
P23
Y27Y21Y25Y19W30W28W24W22W18V27V25V21V19U30U28U24U22U18U16T27T25T21T19T15T13R28R24R22R18R16R12R10P27P25P21P19P15P13N29N18N16N12N10M21M15M13L19J20G13
F22AN24AN22AN12AM25AM13AL30AL28AL24AL22AL18AL16AL12AK27AK25AK21AK19AK15AK13AJ28AJ24AJ22AJ18AJ16AH27AH25AG28AG24AG22AF27AF25AE28AE24AE22AD29AD27AD25AD21
AD9AC30AC28AC24AC22AB27AB25AB21AA30AA28AA24AA22AA18
AA9U1000
AN20AN18AN16AM21AM19AM17AM15
M29G30K23K19K11H25H21H17H13N26
N23
N28N24N22L24M23L28L22L18L12K29K17L16J30J26J24J22J18J12H31H23H19H15H11J28G26G24G22G20F31J16F25
L20K21
W14
Y15Y13V15V13U12U10AA10
U14AF14AE20AC14
AC9AB18AA12
AH21
AH20AH18AH16AH14AH12AH10AG15AG9
AF20AE14AD15AC20AB19AB17AB15AB13AB11AA16AA14
M20L21W16
U1000
2
1 C1750
4
3
2
1
C1764
4
3
2
1
C1738
4
3
2
1
C1739
4
3
2
1
C1737
4
3
2
1
C1736
4
3
2
1
C1709
4
3
2
1
C1708
4
3
2
1
C1704
4
3
2
1
C1705
4
3
2
1
C1791
4
3
2
1
C1792
4
3
2
1
C1772
4
3
2
1
C1781
21
XW1731
4
3
2
1
C1734
4
3
2
1
C1735
4
3
2
1
C1740
2
1 C1730
4
3
2
1
C1741
2
1 C1731
4
3
2
1
C1782
4
3
2
1
C1773
4
3
2
1
C1762
21
XW1760
2 1
XW1701
4
3
2
1
C1706
4
3
2
1
C1707
4
3
2
1
C1710
4
3
2
1
C1711
BUCK2_FB
TP_SOC_SENSE
BUCK0_FB
BUCK11_FB
PP1V2_SOC
AP_VDD_GPU_SENSE
AP_CPU_PCORE_SENSE
PP_GPU_SRAM
PP_CPU_SRAM
PP0V7_VDD_LOW_S2
PP0V8_SOC_FIXED_S1
PP0V8_SOC_FIXED_S1
PP_CPU_ECORE
BUCK1_FB
PP_SOC_S1PP_GPU
PP_CPU_PCORE
SOC: Power (1/3)SYNC_DATE=04/14/2017SYNC_MASTER=sync
5
21 5
21 5
2.2UF20%
0201
6.3VX5R-CERM
ROOM=SOC
20%6.3V
ROOM=SOC01005X5R-CERM
0.1UF20%
ROOM=SOC01005
0.1UF
X5R-CERM6.3V
20%6.3V
ROOM=SOC01005
0.1UF
X5R-CERM
20%4V
0201
4.7UF
CER-X5R
ROOM=SOC
0402-D2X-1X5R4V20%15UF
ROOM=SOC
20%15UF
X5R4V
ROOM=SOC
0402-D2X-1
ROOM=SOC
OMIT
SHORT-20L-0.05MM-SM
21 19
20%4V
0201
4.7UF
CER-X5R
ROOM=SOC
20%4V
0201
4.7UF
CER-X5R
ROOM=SOC
0402-D2X-1X5R4V
ROOM=SOC
15UF20%
0201ROOM=SOC
20%4V
4.7UF
CER-X5R
20%4V
0201CER-X5R
4.7UF
ROOM=SOC
18
18 5
18
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
ROOM=SOC
WLCSPTMIT78B1-C5
ROOM=SOC
WLCSPTMIT78B1-C5
ROOM=SOC
CER-X5R
4.7UF
0201
4V20%
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
15UF
ROOM=SOC
0402-D2X-1
20%
X5R4V
15UF20%
X5R0402-D2X-1
ROOM=SOC
4V
15UF4V
0402-D2X-1
20%
X5R
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
15UF20%
X5R4V
ROOM=SOC
0402-D2X-1
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
NO_XNET_CONNECTION
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
4.7UF20%4V
0201CER-X5R
ROOM=SOC
0402-D2X-1
4V20%15UF
X5R
ROOM=SOC
20%4V
0201
4.7UF
CER-X5R
ROOM=SOC
20%15UF4V
0402-D2X-1X5R
ROOM=SOC
20%15UF
0402-D2X-1X5R4V
ROOM=SOC
0402-D2X-1
20%15UF
X5R4V
ROOM=SOC
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
NO_XNET_CONNECTION
SHORT-20L-0.05MM-SM
ROOM=SOC
OMIT
15UF
0402-D2X-1X5R
20%4V
ROOM=SOC
0402-D2X-1X5R4V20%15UF
ROOM=SOC
0402-D2X-1
20%15UF
X5R4V
ROOM=SOC ROOM=SOC
X5R0402-D2X-1
20%4V
15UF
20 15 10 8
18
18
20
18 15 14 10 9 8 7
18 15 14 10 9 8 7
19
18 18
18 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 9 OF 16
VDD_SOC_SENSE
VDD_SOC
SYM 8 OF 16
VDD_GPU
VDD_ECPU
VDD_FIXED_PLL_GPUVDD_FIXED_PLL_SOC
VDD12_PLL_CPUVDD12_PLL_GPUVDD12_PLL_SOC
VDD_FIXED_CPU
VDD_CPU
VDD_LOW
VDD_CPU_SRAM
VDD_CPU_SENSE
VDD_GPU_SRAM
VDD_GPU_SENSE
1.8V @ 3.3mA MAX (SOC)
1.2V @ 16mA MAX
1.06V - 1.17V @ (inc in VDD2)
1.06V - 1.17V @ 2.2A MAX
0.6V @ 620mA MAX
0.875V @ 0.8A MAX0.730V @ 0.51A MAX0.600V @ 0.35A MAX
1.8V @ 5.3mA MAX (CPU)1.8V @ 1.1mA MAX (GPU)
1.8V @ 1mA MAX1.8V @ 1mA MAX
1.8V @ 200mA MAX
Place one cap per SoC corner
Place one cap per SoC corner0.8V @ 0.9A MAX
DDR IMPEDANCE CONTROL
SOC - POWER SUPPLIES
1.8V @ 60mA MAX
15 OF 81
10.0.0
18 OF 80
051-02159
21
XW1870
2
1 C188121
R1880
2
1 C1870
2
1 C1880
2
1 C18602
1 C18612
1 C18622
1 C1863
2
1 C18052
1 C18042
1 C18032
1 C1802
2
1 C1810
2
1 C18332
1 C18322
1 C18312
1 C1830
V9AF9
D23F21
Y31V31
AB31
AP25AP23
J31AD30AJ12
G21
Y16AJ9AF21T12
AN19AN13AT6H12
U1000
2
1R1871
2
1R1870
V39T39P39P31K31F39D39
C4V1T1K9H1F9F1D1
AV39AT39AP39AK31AF39AF31AD39
AV1AT1AP9AK9AH1AF1AD1
T29D9
AK29AJ11
G34E6
AN34AR6
R30K30
A4L10F10
AK30AE30
AP10AJ10
W1P1N39M1K39J1H39D38C38C3C2AW38AW2AV37AV2AP1AN39AM1AK39AJ1AH39AC39AA38AA2
Y37Y3B37B3
AW37AW3
AB37AB3
N38
H34
H35
G35
E4
E5
E3
AM34
AN35
AM35
AJ2
AP6
AP5
AR5
U1000
R29D8AJ29AK11
Y29Y23Y17Y9W26W20V29V23V17
U26U20T31T23T17T11R26R20R14P29P17P11N20N14M17M11F23F19
AP24AP21AP11AM23AM11AL26AL20AL14AK23AK17AJ26AJ20AJ14AH29AH23AG26AF29AF23AE26AD31AD23AC26AB29AB23
AB9AA26AA20
BA19AY20
U1000
2
1 C18112
1 C18122
1 C1813
2
1 C18402
1 C18412
1 C18422
1 C1843
2
1 C18502
1 C18512
1 C18522
1 C1853
2
1R1863
2
1R1862
2
1R1861
2
1R1860
4
3
2
1
C1801
TP_VDDQL_SENSE
LPADC_GND
PP1V2_LPADC
PP0V8_SOC_FIXED_S1
PP0V6_VDDQL_S1
PP1V8_IO
PP0V6_VDDQL_S1
AOP_TO_DDR_SLEEP1_READY
DDR3_RREFDDR2_RREFDDR1_RREFDDR0_RREF
DDR3_ZQDDR0_ZQ
PP1V8_S2
PP1V2_SOC
PP1V1_S2
TP_VDD_DCS_SENSE
SYSTEM_ALIVE
PP1V1_S2
PP_DCS_S1
PP1V8_IOPP1V8_LPOSC_S2 PP1V8_S2
PP1V8_IO
PP0V8_SOC_FIXED_S1
SOC: Power (2/3)SYNC_DATE=04/14/2017SYNC_MASTER=sync
5
OMIT
SHORT-20L-0.05MM-SM
ROOM=PMU
13 5
24 21 17
0.47UF20%6.3VX5R01005ROOM=SOC
5%1/32WMF
01005
300
ROOM=SOC
0.1UF20%6.3V
01005X5R-CERM
NP0-C0G-CERM01005
25V5%56PF
ROOM=SOC
ROOM=SOC0201
4.7UF
CER-X5R4V20%
CER-X5R
ROOM=SOC0201
4.7UF4V20%
CER-X5R
4.7UF
ROOM=SOC0201
4V20%
ROOM=SOC
CER-X5R0201
4.7UF4V20%
ROOM=SOC0201
4.7UF
CER-X5R4V20%
ROOM=SOC0201
4.7UF
CER-X5R4V20%
ROOM=SOC
20%4V
0201
4.7UF
CER-X5R
ROOM=SOC0201
4.7UF
CER-X5R4V20%
ROOM=SOC0402-0.1MM-1
6.3V
15UF
X5R
20%
0201
4.7UF
CER-X5RROOM=SOC
4V20%
0201
4.7UF
CER-X5RROOM=SOC
4V20%
0201
4.7UF
CER-X5RROOM=SOC
4V20%
4.7UF
CER-X5R0201ROOM=SOC
4V20%
ROOM=SOC
WLCSPTMIT78B1-C5
01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC
ROOM=SOC
WLCSPTMIT78B1-C5
ROOM=SOC
WLCSPTMIT78B1-C5
4.7UF4VCER-X5R0201ROOM=SOC
20%
CER-X5R
ROOM=SOC0201
4.7UF4V20%
4.7UF
ROOM=SOC0201CER-X5R4V20%
4.7UF
0201CER-X5RROOM=SOC
4V20%
ROOM=SOC
4.7UF
0201CER-X5R4V20%
0201
4.7UF
CER-X5RROOM=SOC
4V20%
4.7UF
ROOM=SOC0201CER-X5R4V20%
0201
4.7UF
CER-X5R
ROOM=SOC
4V20%
ROOM=SOC
CER-X5R0201
4.7UF4V20%
0201
4.7UF
CER-X5R
ROOM=SOC
4V20%
0201
4.7UF
CER-X5R4V20%
ROOM=SOC
01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC01005MF1/32W1%240
ROOM=SOC
ROOM=SOC
4VX5R
0402-D2X-1
15UF20%
5
20
18 15 14 10 9 8 7
19 15
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
19 15
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
20 14 10 8
20 18 15
20 18 15
18
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
42
40 33
31 30 29
28 18
17 15 11 9 8 7 6
18
15 14 10 9 8 7
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
IN
SYM 12 OF 16
VDD18_TSADC_CPU0VDD18_TSADC_CPU1
VDD18_LPOSCVDD18_FMON
VDD18_EFUSE2VDD18_EFUSE1
VDD18_TSADC_SOC2
VDD18_TSADC_SOC0VDD18_TSADC_SOC1
VDD18_TSADC_GPU0
VDD18_TSADC_CPU3VDD18_TSADC_CPU2
VDDIO18_GRP1
VDDIO18_GRP2
VDDIO18_GRP3
VDDIO18_GRP4
SYM 11 OF 16DDR3_RREF
DDR1_RET*DDR0_RET*
DDR2_RREFDDR1_RREFDDR0_RREF
DDR3_RET*DDR2_RET*
DDR0_ZQDDR3_ZQ
DDR1_SYS_ALIVEDDR2_SYS_ALIVEDDR3_SYS_ALIVE
DDR0_SYS_ALIVE
VDD1
VDD2
VDDQL_DDR0
VDDQL_DDR1
VDDQL_DDR2
VDDQL_DDR3
VDDIO11_RET_DDR0VDDIO11_RET_DDR1
VDDIO11_RET_DDR3VDDIO11_RET_DDR2
VDDIO12_PLL_DDR1VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR3VDDIO12_PLL_DDR2
VDD_DCS_DDR0
VDD_DCS_DDR1
VDD_DCS_DDR2
VDD_DCS_DDR3
SYM 10 OF 16
VDD_FIXED_PLL_DDR3VDD_FIXED_PLL_DDR2VDD_FIXED_PLL_DDR1VDD_FIXED_PLL_DDR0
LPADC_REF_MLPADC_REF_P
VDD_FIXED
SOC - POWER SUPPLIES
16 OF 81
10.0.0
19 OF 80
051-02159
P24
AG21
Y39Y35Y30Y28Y26Y24Y22Y20Y18Y14Y5Y1W39W38W37W34W31W29W27W25W23W21W19W17W15W13W9W6W3W2V37V35V30V28V26V24V22V20V18V16V14V6U39U34U31U29U27U25U23U21
U19U17U15U13U11U9U5U3U1
T38T36T34T30T28T26T24T22T20T18T16T14T10T6
R39R34R31R27R25R23R21R19R17R15R13R11R6R1
P37P35P30P28P26P22P20P18P16P14P12P10
P5P3
N34N27N25N21N19N17N15N13N11N9N6N5N4N3N2N1
M39M38M36M34M28M24M22M6M5M2
M19U1000
M18M16M14M12M10L39L38L34L29L23L17L11L9L6L3L2L1K37K35K28K24K22K20K18K16K12K10K6K5K2K1J39J38J37J36J35J34J29J27J25J23J21J19J17J11J6J3J2H38H37H36H30H26H24H22H20H18H16H14H5H4H2G39G38G37G36G31G25G23G19G17G15G11G6G3G2
G1F38F37F36F35F34F30F26F24F20
F6F5F4F3F2
F18F14F12E39E38E37E36E35E34
E2E1
D37D36D35D34D27D26D25D24D22
D7D6D5D4D3D2
D14D10C39C37C36C35C33C31C29C27C26C25C24C23C22C21C20C19C18C17C16C15C14C13C12C11C10
C9C8C7C6C5C1
BA39U1000
BA38BA37BA35BA33BA31BA29BA26BA25BA23BA7BA5BA3BA2BA1B39B38B36B35B27B18B11B5B4B2B1AY39AY38AY37AY35AY33AY31AY29AY28AY27AY25AY23AY21AY18AY15AY12AY9AY7AY5AY3AY2AY1AW39AW36AW34AW32AW30AW28AW24AW4AW1AV38AV36AV34AV32AV30AV28AV26AV24AV4AV3AU39AU38AU37AU36AU35AU34AU33AU31AU9AU6AU5AU4AU3AU29
AU27AU26AU25AU24AU21AU18AU15AU12
AU2AU1
AT38AT37AT33AT32AT31AT29AT28
AT5AT4AT3AT2
AR39AR38AR37
AR4AR3AR2AR1
AP38AP37AP36AP35AP34AP28AP22AP20AP18AP16AP12
AP4AP3AP2
AN38AN37AN36AN31AN29AN25AN23AN21AN17AN11
AN6AN5AN4AN3AN2AN1
AM39AM38AM37AM36AM30AM28AM26AM24AM22AM20AM18AM16AM14AM12
AM6AM2
AL39AL36AL35AL34
U1000
AL31AL29AL27AL25AL23AL21AL19AL17AL15AL13AL11AL5AL3AL1AK36AK35AK34AK28AK26AK24AK22AK20AK18AK16AK14AK12AK10AK6AK2AK1AJ39AJ35AJ34AJ27AJ25AJ23AJ21AJ19AJ17AJ15AJ13AH37AH35AH28AH26AH24AH22AH19AH17AH15AH13AH11AH9AH5AH3AG39AG34AG29AG27AG25AG23AG20AG14AG6AG1AF37AF35AF30AF28AF26AF24AF22AF15AF6AE39AE34AE31AE29
AE27AE25AE23AE21AE15
AE9AE5AE3AE1
AD37AD35AD34AD28AD26AD24AD22AD20AD14
AD6AD4
AC35AC34AC31AC29AC27AC25AC23AC21AC15
AC6AC3AC1
AB39AB35AB30AB28AB26AB24AB22AB20AB16AB14AB12AB10
AB5AB1
AA39AA36AA34AA31AA29AA27AA25AA23AA21AA19AA17AA15AA13AA11
AA6AA1A39A38A37A36A35A33A31A29A27A18A11
A5A3A2A1
U1000
TP_VSS_SENSE
TP_VSS_CPU_SENSE
TP_DDR_VSS_SENSE
SOC: Power (3/3)SYNC_DATE=04/14/2017SYNC_MASTER=sync
5
5
5
ROOM=SOC
WLCSPTMIT78B1-C5
ROOM=SOC
WLCSPTMIT78B1-C5
WLCSP
ROOM=SOC
TMIT78B1-C5WLCSP
ROOM=SOC
TMIT78B1-C5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
SYM 16 OF 16
VSS_CPU_SENSE
VSS_SENSE
VSS
SYM 15 OF 16
VSSVSS
SYM 14 OF 16
VSS VSS
SYM 13 OF 16
VSSVSS
391mA MAX
932mA MAX
1300mA MAX (1us peak power)
17 OF 81
PP1V8_IO
MISS_P_DIFFPAIR
10.0.0
26 OF 80
051-02159
C10K3
G2
U12
U10U8U6U4U2T13T9T7T1R10
P13
P11P7P3P1N10N4M
13M7
M5
M1
L10
K13K7K5K1J10
H13
H11H9H5H3H1F13
F11F9F7F5F1D13
D11D1C12C2B13B1A12
A10A8A6A4A2
F3P9T5N2K9J2E10
E2 R4R8R6L8L6G8
G6
R2L12
G4
E12
D3
G10
L4
R12T11
M11N12
K11J12
P5
J8N8
H7
J6M9
N6
E4
E6
D7
E8
B11B9C8B7C6B5C4B3
D5
D9
T3
M3
L2 J4G12
U2600
2
1 C26112
1 C26012
1 C26172
1 C2623
2
1 C26032
1 C26062
1 C26092
1 C2614
2
1 C26152
1 C26182
1 C26312
1 C26362
1 C26322
1 C2634
2
1R2601
2
1R2600
2
1 C26222
1 C2627
2
1 C2641
2
1 C2652
2
1 C2635
2
1 C26472
1 C26452
1 C2643
2
1 C2612
2
1 C2630
2
1 C26202
1 C2628
2
1 C26402
1 C26422
1 C26442
1 C2646
2
1 C26492
1 C26502
1 C2651
2
1 C2629
2
1 C2626
2
1 C26212
1 C26192
1 C26162
1 C2613
2
1 C26052
1 C2602
2
1 C2610
2
1R2604
PP1V8_IO
PMU_TO_NAND_LOW_BATT_BOOT_LAP_TO_NAND_FW_STRAP
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SWD_AOP_TO_MANY_SWCLK
SWD_AP_BI_NAND_SWDIO
PCIE_AP_TO_NAND_RESET_L
SYSTEM_ALIVE
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2
AP_TO_NAND_RESET_L
NAND_ZQ_C
90_PCIE_NAND_TO_AP_RXD_N90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_AP_TO_NAND_TXD_N90_PCIE_AP_TO_NAND_TXD_P
PCIE_NAND_RESREF
PCIE_NAND_BI_AP_CLKREQ_L
90_PCIE_AP_TO_NAND_REFCLK_N90_PCIE_AP_TO_NAND_REFCLK_P
NAND_ANI1_VREFNAND_ANI0_VREF
AP_TO_NAND_SYS_CLK
PP0V9_NAND
PP1V8_IOMAKE_BASE=TRUE
NAND_ZQ_N
PP3V0_NAND
NANDSYNC_DATE=04/14/2017SYNC_MASTER=sync
H23Q2T8QK6MES-BCLGA
CRITICALBOMOPTION=OMIT_TABLE
5
5
39PF5%
NP0-C0G16V
ROOM=NAND01005
CERM16V5%
ROOM=NAND01005
22PF5%
ROOM=NAND
68PF16VNP0-C0G01005
16V5%
01005ROOM=NAND
NP0-C0G
100PF
ROOM=NAND
16V5%22PF
CERM01005
ROOM=NAND01005NP0-C0G16V5%68PF
NP0-C0G
5%16V
100PF
01005ROOM=NAND
01005
47PF
CERM
ROOM=NAND
5%16V
22PF
CERM
5%16V
ROOM=NAND01005
ROOM=NAND
5%39PF16VNP0-C0G01005
ROOM=NAND
16V
68PF5%
NP0-C0G01005
10VC0G-CERM01005
220PF5%
ROOM=NAND
5%
ROOM=NAND
47PF
CERM01005
16V
01005NP0-C0G
ROOM=NAND
16V
100PF5%
0.1%1/32
01005ROOM=NAND
300
MF
ROOM=NAND
MF
1000.1%1/32W
01005
11 6
11 6
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
11 6 5
24 21 15
8
50 13 5
13 5
7
21
7
8
8
8
8
8
8 5
8 5
11
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
ROOM=NAND
CER-X5R0201
3.9UF6.3V20%
10VC0G-CERM01005
220PF5%
ROOM=NAND
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
01005
5%220PF
C0G-CERM
ROOM=NAND
10V
ROOM=NAND
6.3VCER-X5R0402-0.1MM
18UF20%
10VC0G-CERM01005
5%220PF
ROOM=NAND
10V5%
01005C0G-CERM
ROOM=NAND
220PF
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
0201ROOM=NAND
4VCER-X5R
4.7UF20%
4VCER-X5R
4.7UF
ROOM=NAND0201
20%
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
3.9UF
CER-X5R
ROOM=NAND0201
6.3V20%
6.3VCER-X5R
ROOM=NAND0201
3.9UF20%
ROOM=NAND
CER-X5R0201
3.9UF6.3V20%
ROOM=NAND
6.3VCER-X5R0402-0.1MM
18UF20%
ROOM=NAND
4VCER-X5R
4.7UF
0201
20%
ROOM=NAND0402-0.1MMCER-X5R6.3V
18UF20%
ROOM=NAND
20%6.3VCER-X5R0402-0.1MM
18UF
CER-X5R
ROOM=NAND0402-0.1MM
6.3V
18UF20%
ROOM=NAND0402-0.1MM
18UF6.3VCER-X5R
20%
ROOM=NAND
22UF4VX5R0402-0.1MM
20%
ROOM=NAND
22UF4VX5R0402-0.1MM
20%
X5R-CERM
0.1UF
ROOM=NAND01005
6.3V20%
ROOM=NAND
MF1/32W1%3.01K
01005
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
20
42 40 33 31 30 29 28 18 17 15 11 9 8 7 6
20
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
AVDD
18_P
LL
CLK_IN
ANI0
_VRE
F
VSS
EXT_D2/BOOT2/SPINAND_SCLK
EXT_NCE/PERST*
EXT_NRE/JTAG_TMS
EXT_NWE/JTAG_TCK
EXT_RNB/JTAG_TDO
EXT_CLE/JTAG_TDI
EXT_ALE/JTAG_SEL
EXT_D1/BOOT1EXT_D0/BOOT0
EXT_D7/SPF
DROOP_N
WP_N
PCIE_REFCLK_M
PCIE_TX0_PPCIE_TX0_M
RESET*
TRST*
ZQ_CZQ_N
VPP
VDD_
PLL
VCC
VDDI
O
VDD
ANI1
_VRE
F
PCI_
VDD_
1PC
I_VD
D_2
PCI_
AVDD
_H
PCI_
AVDD
_CLK
_1PC
I_AV
DD_C
LK_2
EXT_D3/SWD_UID0/SPINAND_MISO
EXT_D6/UART_TX
EXT_D4/UART_RX
PCIE_REFCLK_P
PCIE_CLKREQ_N
PCI_RESREF
PCIE_RX0_PPCIE_RX0_M
EXT_D5/SWD_UID1/SPINAND_MOSI
OUT
OUT
NC
NCIN
IN
OUT
IN
IN
IN
BI
IN
IN
IN
OUT
OUT
IN
IN
BI
IN
IN
IN
NC
NC
0.625V - 1.06VBU
CK8
0.80V - 1.06V
0.80V - 0.92V
0.67V - 0.92V
BUCK
9
BUCK31.7A MAX
BUCK1BUCK0
BUCK
6BU
CK7
13.8A MAX13.8A MAX
BUCK24.9A MAX
1.2A MAX
2.1A MAX
2.1A MAX
1.2A MAX
1.03V for overdrive only
BUCK
44.9A MAX
#29079575: Add 22uF cap to BUCK2 and BUCK4
#29079575: Add 22uF cap to BUCK2 and BUCK4
1.7A MAX
BUCK
5
0.67V/0.80V
#30278265: Remove 4th phase on GPU buck
18 OF 81
VOLTAGE=1.8VVOLTAGE=1.8V
VOLTAGE=1.06V
VOLTAGE=0.875V
VOLTAGE=1.06V
VOLTAGE=1.8V
VOLTAGE=1.8V
VOLTAGE=1.1V
VOLTAGE=1.01V
VOLTAGE=1.25V
VOLTAGE=0.8V
VOLTAGE=1.03V
VOLTAGE=0.8V
10.0.0
27 OF 80
051-02159
2
1 C2745
2
1 C2724
2 1
L2790
2 1
L2780
2 1
L2770
2 1
L2760
2 1
L2750
21
L2741
2 1
L2740
21
L2730
2 1
L2721
21
L2720
21
L2712
2 1
L2711
21
L2710
2 1
L2703
21
L2702
2 1
L2701
21
L2700
2
1 C2732
2
1 C2790
2
1 C2706
21
XW2790
2
1 C2780
2
1 C2770
2
1 C27822
1 C2781
2
1 C27722
1 C2771
2 1
XW2780
2 1
XW2770
2
1 C27612
1 C27622
1 C2760
2 1
XW2760
2
1 C27522
1 C27512
1 C2750
2 1
XW2750
2
1 C2716
2
1 C2741
2
1 C27912
1 C27922
1 C2721
2
1 C2742
C2C1
B6A6
F4
B17A17
E17
W18W17W16
W14
H2H1
H4
Y3W3V3
T4
Y9W9V9
Y11W11V11
T8
D2D1
B2B1A2
F2F1
G4
Y7W7V7
Y5W5V5
T7
C9B9A9
C11B11A11
C13B13A13
B15A15
F15
U18U17U16
R18R17R16
N18N17N16
L18L17
R13
U2700
2 1
XW2740
2
1 C27442
1 C27432
1 C2740
21
XW2730 2
1 C2731
2
1 C27222
1 C2723
2
1 C2730
2
1 C2720
2
1 C27102
1 C27112
1 C27122
1 C27132
1 C27142
1 C2715
2
1 C27002
1 C27052
1 C27042
1 C27032
1 C27022
1 C2701
BUCK4_LX1
PP1V8_TOUCH
BUCK0_FB
PP1V8_IMU_S2
BUCK1_FBPP_GPU_SRAM
PP_DCS_S1
BUCK4_LX0 BUCK0_LX0
BUCK0_LX2
PP_CPU_PCORE
BUCK1_LX0
BUCK1_LX1
BUCK2_LX0
BUCK5_FB
BUCK3_LX0
BUCK3_FB
PP1V8_IO
PP1V8_S2
BUCK2_LX1
PP1V1_S2
BUCK6_LX0
BUCK9_LX
BUCK6_FB
BUCK9_FB
BUCK7_LX0
BUCK5_LX0
BUCK8_FB
BUCK8_LX0
BUCK7_FB
PP_CPU_SRAM
PP1V25_S2
PP0V8_SOC_FIXED_S1
BUCK4_FB
PP_GPU
BUCK1_LX2
BUCK2_FB
PP_SOC_S1
BUCK0_LX1
BUCK0_LX3
SYSTEM POWER: PMU Bucks (1/4)SYNC_DATE=04/14/2017SYNC_MASTER=sync
0402-0.1MMX5R4V20%22UF
ROOM=PMU
0402-0.1MMROOM=PMU
X5R
22UF20%4V
PIWA2012FE-SMROOM=PMUCRITICAL
1UH-20%-2.1A-0.1OHM
CRITICAL
1UH-20%-2.1A-0.1OHM
ROOM=PMUPIWA2012FE-SM
PIWA20160H-SMROOM=PMUCRITICAL
1UH-20%-2.5A-0.052OHM
PIWA2016FE-SMROOM=PMUCRITICAL
1UH-20%-2.4A-0.06OHM
CRITICALROOM=PMU
PIWA20160H-SM
1UH-20%-2.5A-0.052OHM
CRITICALROOM=PMU
PIWA2012FE-SM
0.47UH-20%-3.3A-0.053OHM
PIWA20160H-SM
1UH-20%-3.2A-0.06OHM
CRITICALROOM=PMU
PIWA2016FE-SMROOM=PMUCRITICAL
1UH-20%-2.4A-0.06OHM
0.47UH-20%-3.3A-0.053OHM
ROOM=PMUPIWA2012FE-SM
CRITICAL
1UH-20%-3.2A-0.06OHM
ROOM=PMUPIWA20160H-SM
CRITICAL
ROOM=PMUCRITICAL
0.1UH-20%-7.2A-0.021OHM
PINA2012-SM
0.47UH-20%-3.8A-0.055OHM
PIWA2012FE-SM
CRITICALROOM=PMU
1UH-20%-3.6A-0.062OHM
0806
CRITICALROOM=PMU
0.1UH-20%-6.1A-0.031OHM
CRITICALROOM=PMU
PINA1608-SM
0.1UH-20%-6.1A-0.031OHM
PINA1608-SMROOM=PMUCRITICAL
0.47UH-20%-3.3A-0.053OHM
PIWA2012FE-SMROOM=PMUCRITICAL
1UH-20%-3.2A-0.06OHM
PIWA20160H-SMROOM=PMUCRITICAL
4V
22UF20%
X5R0402-0.1MMROOM=PMU
14
14 5
14
5%220PF
01005C0G-CERM10V
ROOM=PMU
X5R
22UF20%4V
ROOM=PMU0402-0.1MM
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
5%220PF
01005C0G-CERM10V
ROOM=PMU
5%220PF
C0G-CERM10V
01005ROOM=PMU
X5R
ROOM=PMU
22UF20%4V
0402-0.1MMROOM=PMU
20%
X5R
22UF4V
0402-0.1MM
22UF
ROOM=PMU
X5R
20%
0402-0.1MM
4V
ROOM=PMU
X5R
22UF4V20%
0402-0.1MM
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
22UF
X5R4V
0402-0.1MM
20%
ROOM=PMU
X5R
20%4V
0402-0.1MM
22UF
ROOM=PMU ROOM=PMU01005C0G-CERM10V5%220PF OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
X5R
20%
0402-0.1MM
4V
22UF
ROOM=PMU ROOM=PMU
20%4VX5R0402-0.1MM
22UF
C0G-CERM
5%
ROOM=PMU01005
10V
220PFOMIT
SHORT-20L-0.05MM-SM
ROOM=PMU
ROOM=PMU
X5R
22UF20%
0402-0.1MM
4V
20%22UF
X5R0402-0.1MMROOM=PMU
4V
22UF20%
ROOM=PMU0402-0.1MMX5R4V
X5R
22UF20%4V
ROOM=PMU0402-0.1MM
ROOM=PMU
4VX5R
22UF20%
0402-0.1MM
4V20%
X5R
22UF
0402-0.1MMROOM=PMU
CRITICAL
ROOM=PMU
WLCSPD2422B0
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
0402-0.1MMX5R4V20%22UF
ROOM=PMU0402-0.1MM
22UF20%
ROOM=PMU
X5R4V
220PF
C0G-CERM
ROOM=PMU01005
5%10V
ROOM=PMU
SHORT-20L-0.05MM-SM
OMIT
ROOM=PMU
X5R
20%4V
22UF
0402-0.1MM
22UF
ROOM=PMU
X5R
20%4V
0402-0.1MM
4V20%22UF
X5R
ROOM=PMU0402-0.1MM
ROOM=PMU01005
5%10VC0G-CERM
220PF
5%
ROOM=PMU
220PF
01005C0G-CERM10V
5%220PF
01005C0G-CERM10V
ROOM=PMU 0402-0.1MMX5R
22UF4V
ROOM=PMU
20%
X5R0402-0.1MM
22UF20%4V
ROOM=PMU
X5R
ROOM=PMU
22UF20%4V
0402-0.1MM
20%22UF4VX5R0402-0.1MMROOM=PMU ROOM=PMU
X5R
22UF20%4V
0402-0.1MM
220PF5%
01005C0G-CERM10V
ROOM=PMU0402-0.1MMROOM=PMU
22UF20%4VX5R
0402-0.1MM
22UF20%
X5R4V
ROOM=PMU0402-0.1MMX5R
22UF20%4V
ROOM=PMU0402-0.1MM
20%4V
22UF
ROOM=PMU
X5R0402-0.1MMX5R
22UF20%4V
ROOM=PMU
43 42
27
14
15
14 5
42 40 33 31 30 29 28 17 15 11 9 8 7 6
50 48 47 46 45 43 41 36 25 23 21 15 13 11 5
20 15
14
28 20
15 14 10 9 8 7
14
14
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNCNC
IN
IN
IN
SW
ITC
H O
UT
PU
TS
SYM 2 OF 5
BUCK4_LX1
BUCK0_LX2
BUCK0_LX0
BUCK9_FB
BUCK9_LX0
BUCK8_FB
BUCK8_LX0
BUCK7_FB
BUCK7_LX0
BUCK6_FB
BUCK6_LX0
BUCK5_FB
BUCK5_LX0
BUCK4_FB
BUCK4_LX0
BUCK3_SW3BUCK3_SW2
BUCK3_SW1
BUCK3_FB
BUCK3_LX0
BUCK2_LX1
BUCK2_LX0
BUCK1_FB
BUCK1_LX3
BUCK1_LX2
BUCK1_LX1
BUCK1_LX0
BUCK0_FB
BUCK0_LX3
BUCK0_LX1
BUCK2_FB
VBUCK3_SW
3.0A MAX1.2A MAX
BUCK10BUCK11
19 OF 81
VOLTAGE=1.06V
VOLTAGE=0.875V
10.0.0
28 OF 80
051-02159
2
1 C2853
2 1
L2811
21
L2810
21
L2800
2
1 C28522
1 C2851
2
1 C28702
1 C28712
1 C2872
2
1 C28642
1 C28652
1 C28662
1 C2868
2
1 C2850
2
1 C2812
2
1 C2813
2
1 C28012
1 C2802
2
1 C2810
2
1 C2800
2 1
XW2800
2
1 C2811
2
1 C2874
2
1 C28592
1 C2860
2
1 C28542
1 C2855
2
1 C2862
2
1 C28562
1 C2857
2
1 C28752
1 C2876
2
1 C2863
2
1 C2858
P7
F14L14U14
R7K5E5
H18H17
B3A3
B7A7
C18B18
Y17Y16Y15
J2J1
Y2W2V2
Y10W10V10
E2E1
Y6W6V6
D10C10B10A10
D14C14B14A14
T18T17T16T15
M18M17M16M15
J18J17
G18G17
J15
B4A4
E4
U2700
VDD_MAIN_SNS
BUCK11_LX0
BUCK10_FB
BUCK11_LX1
BUCK11_FB
BUCK10_LX
PP_CPU_ECORE
PP0V6_VDDQL_S1
PP_VDD_MAIN
SYSTEM POWER: PMU Bucks (2/4)SYNC_DATE=04/14/2017SYNC_MASTER=sync
20%18UF
0402-0.1MMCER-X5R6.3V
ROOM=PMU
0.47UH-20%-3.3A-0.053OHM
ROOM=PMUCRITICAL
PIWA2012FE-SM
1UH-20%-3.2A-0.06OHM
PIWA20160H-SMROOM=PMUCRITICAL
1UH-20%-2.1A-0.1OHM
PIWA2012FE-SM
CRITICALROOM=PMU
21 14
OMIT_TABLE
20%6.3V
2.2UF
X5R-CERM0201ROOM=PMU
OMIT_TABLE
20%
0201ROOM=PMU
X5R-CERM6.3V
2.2UF
X5R-CERM0201
2.2UF6.3V20%
OMIT_TABLEROOM=PMU
OMIT_TABLE
20%6.3V
0201X5R-CERM
2.2UF
ROOM=PMU
20%6.3VX5R-CERM
ROOM=PMU0201
2.2UF
OMIT_TABLE OMIT_TABLE
2.2UF20%
X5R-CERM
ROOM=PMU0201
6.3V
ROOM=PMUOMIT_TABLE
2.2UF20%
X5R-CERM0201
6.3V
OMIT_TABLE
2.2UF20%6.3V
ROOM=PMU0201X5R-CERM
ROOM=PMUOMIT_TABLE
X5R-CERM0201
2.2UF6.3V20%
X5R-CERM0201
20%6.3V
ROOM=PMU
2.2UF
OMIT_TABLE
20%6.3V
ROOM=PMU
18UF
CER-X5R0402-0.1MM
20%6.3V
OMIT_TABLEROOM=PMU0201X5R-CERM
2.2UF
0402-0.1MM
20%
X5R
22UF4V
ROOM=PMU
20%
0402-0.1MMX5R4V
22UF
ROOM=PMU
ROOM=PMU
22UF
0402-0.1MM
4VX5R
20%
0402-0.1MM
20%
X5R4V
22UF
ROOM=PMU
10V5%
01005C0G-CERM
220PF
ROOM=PMU
C0G-CERM
220PF
ROOM=PMU01005
5%10V
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
20%6.3V
0201
OMIT_TABLEROOM=PMU
X5R-CERM
2.2UF
ROOM=PMU
22UF
0402-0.1MM
4VX5R
20%
X5R-CERM
OMIT_TABLE
20%6.3V
0201
2.2UF
ROOM=PMU
ROOM=PMU0201
OMIT_TABLE
2.2UF
X5R-CERM6.3V20%
0201ROOM=PMUOMIT_TABLE
X5R-CERM
2.2UF6.3V20%
6.3VX5R-CERM
ROOM=PMU
2.2UF20%
0201
OMIT_TABLE
X5R-CERM6.3V20%
ROOM=PMU
2.2UF
0201
OMIT_TABLE
OMIT_TABLE
20%6.3V
0201ROOM=PMU
X5R-CERM
2.2UF
OMIT_TABLE
2.2UF20%6.3V
0201ROOM=PMU
X5R-CERM0201
6.3V20%2.2UF
X5R-CERM
ROOM=PMUOMIT_TABLE
20
ROOM=PMUOMIT_TABLE
0201X5R-CERM
2.2UF6.3V20%
D2422B0
ROOM=PMU
WLCSP
14
15
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN SYM 3 OF 5
BA
T/U
SB
BU
CK
INP
UT
VDD_BUCK0_01
VDD_MAIN_6
BUCK10_LX0
VDD_BUCK11
VDD_BUCK10
VDD_BUCK9
VDD_BUCK8
VDD_BUCK7
VDD_BUCK6
VDD_BUCK5
VDD_BUCK4
VDD_BUCK3
VDD_BUCK2
VDD_BUCK1_23
VDD_BUCK1_01
VDD_BUCK0_23
VDD_MAIN_4VDD_MAIN_5
VDD_MAIN_2VDD_MAIN_3
VDD_MAIN_1
VDD_MAIN_SNS
BUCK11_LX0
BUCK10_FB
BUCK11_LX1
BUCK11_FB
VPUMP: 10nF min @4.6V
LDO14LDO13LDO12LDO11LDO10
LDO8
LDO6
LDO5
LDO3LDO2LDO1
LDO7
LDO9
VBUF_1V2
LDO4
20 OF 81
VOLTAGE=3.0V
VOLTAGE=3.0V
VOLTAGE=1.8V
VOLTAGE=1.2V
VOLTAGE=3.3V
VOLTAGE=1.8V
VOLTAGE=2.5V
VOLTAGE=1.8V
VOLTAGE=0.7V
VOLTAGE=3.0VVOLTAGE=0.9V
VOLTAGE=3.3V
VOLTAGE=3.0VVOLTAGE=1.2V
VOLTAGE=1.2V
10.0.0
29 OF 80
051-02159
2
1 C2915
2
1 C29062
1 C2913
2
1 C29122
1 C2907
2
1 C29922
1 C2990
2
1 C29712
1 C2970
2
1 C2900
2 1
XW2995
Y8Y4Y18Y14Y13Y12Y1W8W4W15W12N12V8V4V18V17V16V15V12U9U8U7U6U5U4U3U15U12U11U10T9T6T5T3R8R15P9P8P18P17P16P15P11P10N9N8N15N7M11M7L6L16K18K17
K16K14
J5J16J14J13H5H3
H16G5G3G2
G16G15
G1F5F3
F18F17F16E3
E18E13E12E11D9D8
D18D17D16D15D13D12D11
C8C7C6C5C4C3
C17C16C15C12
B8B5
B16B12
A8A5
A18A16A12
A1
U2700
D3
E14
T2P3L3P4P6
N6P2M2
L2
U1N2P5M3N3K3
M5
T1R3L4R4R6M6R2M1
L1W1V1N1R5M4N4K4
K1
J4
K2
N5T14
U2700
2
1 C2920
2 1
XW2991
2 1
XW2990
2
1C29812
1C2980
2
1 C2909
2
1 C2910
2
1 C2911
2
1 C2903
2
1 C2901
PP1V25_S2
PP_VDD_MAINPP_VDD_BOOST
PMU_VSS_RTC
PP1V1_S2
PMU_LDO5_UVLO_DET
PP_VDD_BOOST
PMU_PRE_UVLO_DET
VDD_MAIN_SNS
PP_VDD_MAIN
PP2V5_LDO0_S2
PP3V0_NAND
PP3V0_CONVOY
PP1V8_ALWAYS
PP1V2_CODEC_S2
PP3V3_USB
PP1V8_MESA_S2
PP2V5_LDO0_S2
PP1V8_AUDIO_VA_S2
PP0V7_VDD_LOW_S2
PP3V0_S2PP0V9_NAND
PP_ACC_VAR
PP3V0_MESA_S2PP1V2_SOC
PP1V2_LPADC
PMU_VPUMP
SYSTEM POWER: PMU LDOs (3/4)SYNC_DATE=04/14/2017SYNC_MASTER=sync
21
21
19
ROOM=PMU01005
6.3VX5R20%0.22UF
OMIT_TABLEROOM=PMU
6.3V20%2.2UF
0201X5R-CERM
20%6.3V
0201
2.2UF
ROOM=PMUOMIT_TABLE
X5R-CERM
20%6.3V
0201
2.2UF
X5R-CERM
ROOM=PMUOMIT_TABLE
0201
OMIT_TABLE
X5R-CERM6.3V20%
ROOM=PMU
2.2UF
20%18UF
CER-X5R6.3V
ROOM=PMU0402-0.1MM
20%18UF
0402-0.1MMCER-X5R6.3V
ROOM=PMU
X5R-CERM
20%6.3V
0201ROOM=CAM_PMU
OMIT_TABLE
2.2UF
OMIT_TABLE
ROOM=CAM_PMU
0201
6.3V20%2.2UF
X5R-CERM
2.2UF20%6.3VX5R-CERM
OMIT_TABLEROOM=PMU0201
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
ROOM=PMU
WLCSPD2422B0
D2422B0WLCSP
ROOM=PMU
CRITICAL
47NF
ROOM=PMU
X5R-CERM01005
6.3V20%
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
0201
OMIT_TABLE
6.3V20%
2.2UF
X5R-CERM
ROOM=PMU
20%6.3V
ROOM=PMU
X5R-CERM0201
2.2UF
OMIT_TABLE
20%
X5R6.3V
0201-1ROOM=PMU
1.0UF
6.3VX5R-CERM0201ROOM=PMUOMIT_TABLE
20%2.2UF
20%6.3V
2.2UF
0201X5R-CERM
ROOM=PMUOMIT_TABLE
OMIT_TABLE
0201X5R-CERM
ROOM=PMU
2.2UF20%6.3V
X5R-CERM
OMIT_TABLE
0201
2.2UF6.3V20%
ROOM=PMU
28 18
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
50 43 41 36 28 22 20
21
18 15
50 43 41 36 28 22 20
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
20
17
33
24 21
36
7
43
20
39 38 37 36
14
50 48 47 46 44 33 5
17
47 45
43
15 14 10 8
15
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
NC
SYM 5 OF 5
VSS VSSLD
O
SYM 1 OF 5
LDO
INP
UT
VLDO0
TP_DET
VPP_OTP
VCC_LDOG
VDD_VBUF
VDD_LDO12
VDD_LDO14VDD_LDO13
VDD_LDO11VDD_LDO10
VDD_LDO8VDD_LDO9
VDD_LDO7
VDD_BYPASS
VDD_LDO6
VDD_LDO5VDD_LDO5
VDD_LDO4VDD_LDO3VDD_LDO2VDD_LDO1VDD_LDO0
VPUMP
VLDO14VLDO13
VLDO7VLDO8
VLDO6
VBYPASS
VLDO5VLDO4
VLDO2VLDO3
VLDO1
VBUF_1V2
VLDO9
VLDO12
VLDO10VLDO11
NC
CHARGER NTC (IN SIP)
#25244799:OTP-AJ Connects XTAL1 to GND
#28748132:CHESTNUT AMUX AND PWR_EN SWAP BETWEEN A6/B6
#29312542:REPLACE PMU XTAL WITH XO
#29300440:Connection Not Needed
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC
#25244799:CHESTNUT AMUX AND PWR_EN ON SAME CHANNEL
FOREHEAD NTC
#25244799:200K pull-down
RADIO PA NTC
REAR CAMERA NTC
NTCs
Chestnut / Ansel AMUX#28476673:1000PF CAP ON ANSEL AMUX
COLD_RESET & SYSTEM_ALIVE
To Senna
#29404057:Damping R for ACTIVE_RDY
#27852679:No SDA R, PoR is SPMI
#29300440:Connect PMU crash to SoC
AP NTC
21 OF 81
10.0.0
30 OF 80
051-02159
3
1
4
2
Y3000
21
R3009
2
1 C3000
21
R3000
2
1
XW3000
2
1 C3071
2
1R3011
21
R3071
2
1 C3031 21R3070
21
XW3045
2
1 C3070
P1R1
R9
K15
L15
E15
E16
R14
P14
L5
J3
T10
W13V13U13T13T12
V14
K13
G6
H15
L7
L8K7
M8
N13P12P13
R12
L13
M14
H6
U2
N14
R10
T11
M10M9L11L10L9K12K11K10K9K8J12J11J10J9J8H12H11H10H9G12G11G10G9F12F11
M13
H13
L12
J6J7K6
G13F13H14G14
N10N11
H8H7F8
E10E9F7G8G7F6
E8E7E6
F10F9D7D6D5D4
R11
M12
U2700
2
1R3061
2
1R3062
21
C3010
21R3010
2
1 C3030
2
1 C3020
2
1R3020
2
1
R3044
2
1
R3043
2
1
R3042
2
1C3041
2
1C3042
2
1C3043
2
1C3044
2
1
R3041
21
XW3044
21
XW3043
21
XW3041
21
XW3042
TIGRIS_TO_PMU_INT_L
PMU_XTAL2
PMU_TO_WLAN_CLK32KAP_TO_PMU_TEST_CLKOUT
PMU_TO_WLAN_REG_ONPMU_TO_BB_USB_VBUS_DETECT
PMU_TO_AP_FORCE_DFU_R
PMU_PRE_UVLO_DET
BUCK11_FB
PMU_VDD_TCXO
HYDRA_TO_PMU_HOST_RESET
PMU_LDO5_UVLO_DET
REAR_CAMERA_NTC
PMU_HYDRA_TO_AP_FORCE_DFU
SYSTEM_ALIVE
PMU_TO_BBPMU_RESET_L
PP1V8_S2
PMU_TO_SYSTEM_COLD_RESET_L
PMU_IREF
AP_CPU_PCORE_SENSE
AP_TO_PMU_SOCHOT_L
DISPLAY_TO_MANY_BSYNC
PMU_VDD_REF
PMU_VREF
AP_TO_PMU_WDOG_RESET
PMU_TO_AP_HYDRA_ACTIVE_READY_R
SYSTEM_ALIVE
PMU_TO_AOP_CLK32K
PMU_TO_SYSTEM_COLD_RESET_L
PMU_TO_WLAN_CLK32K
CHESTNUT_TO_PMU_AMUXCAMPMU_TO_PMU_AMUX
PP1V8_ALWAYS
PMU_VSS_RTC
RCAM_NTC_RETURN
PMU_TO_AP_HYDRA_ACTIVE_READY
PMU_TO_AP_THROTTLE_PCORE_L
PMU_TO_IKTARA_RESET_L
PMU_TO_DISPLAY_PANICB
PMU_TO_CCG2_RESET_L
PMU_TO_IKTARA_EN_EXT_1P8VPMU_TO_BOOST_EN
PMU_TO_NAND_LOW_BATT_BOOT_LBB_TO_PMU_PCIE_HOST_WAKE_L
PMU_TO_BBPMU_RESET_R_L
FOREHEAD_NTC
FOREHEAD_NTC_RETURN
PMU_TO_AOP_IRQ_L
I2C0_AP_SCLI2C0_AP_SDASPMI_PMGR_TO_PMU_SCLKSPMI_PMU_BI_PMGR_SDATA
AP_TO_PMU_AMUX_OUT
RADIO_PA_NTC
PMU_VDD_RTC
I2C0_AP_SCL
HYDRA_TO_PMU_USB_BRICK_ID
AP_TO_PMU_AMUX_SYNCCAMPMU_TO_PMU_AMUXPMU_ADC_IN
CHESTNUT_TO_PMU_AMUX
PMU_AMUX_BY
AP_NTCCHARGER_NTCPMU_TCAL
AP_VDD_GPU_SENSE
PMU_TO_AP_THROTTLE_ECORE_LPMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_PRE_UVLO_L
FOREHEAD_NTCREAR_CAMERA_NTCRADIO_PA_NTC
DISPLAY_TO_CHESTNUT_PWR_EN
PMU_TO_NFC_EN
CHARGER_NTC
CHARGER_NTC_RETURN
AP_NTC_RETURN
PA_NTC_RETURN
AP_NTC
ACC_BUCK_TO_PMU_AMUXPMU_AMUX_AY
IKTARA_TO_PMU_OVP
CODEC_TO_PMU_WAKE_L
PMU_TO_AP_THROTTLE_GPU1_L
BUTTON_POWER_KEY_L
HYDRA_TO_PMU_USB_BRICK_ID
BUTTON_VOL_DOWN_L
PMU_TO_AP_BUTTON_POWER_KEY_LPMU_TO_AP_BUTTON_VOL_DOWN_L
BUTTON_RINGER_ABUTTON_VOL_UP_L
PMU_ADC_IN
BT_TO_PMU_HOST_WAKEPMU_TO_BT_REG_ON
PMU_TO_GNSS_EN
NFC_TO_PMU_HOST_WAKEWLAN_TO_PMU_HOST_WAKE
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SYSTEM POWER: PMU (4/4)
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
ROOM=PMU
32.768KHZ-10PPMCRITICAL
CSP
25
34
47 41 7
1/32W
1005%
ROOM=PMUMF01005
01005ROOM=PMU
6.3VX5R-CERM
0.1UF20%
ROOM=PMU
0.00
1/32W0%
MF01005
SHORT-20L-0.05MM-SM
ROOM=PMUOMIT
41 21
42 41
01005
10V10%X5R
ROOM=PMU
1000PF
7 5
11 5
50 21
200K
ROOM=PMU01005
MF1/32W
1%
20.0K
1/32W01005
ROOM=PMU5% MF
24
6.3V
0201-1ROOM=PMU
1.0UF
X5R
20%
50
50
36
5%
1.00K
1/32WMF
01005ROOM=PMU
7 5
50
17
19 14
20
45 41 21 11
25
22
25
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
42
10V1000PF10%X5R
ROOM=PMU01005
45
7
46
50
50
12
12
7
7
12 7
50
50
50
34
34
34
47 21
20
14 5
14 5
29 21
45 41 11
45 41 21 11
5
5
13
24 21 17 15
13
21 7
50 21
47 21
12
7
11
50 42 29 22 13
7 5
47
7
WLCSP
ROOM=PMU
D2422B0
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
1/32W5%100K
MF01005ROOM=PMU
1/32W
ROOM=PMU
100K
MF01005
5%
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
0.22UF
0201ROOM=PMU
6.3V20%
X5R
1/20W1%
200K
ROOM=PMU201MF
ROOM=PMU
0201
6.3V0.22UF20%X5R100PF
16VNP0-C0G
01005ROOM=PMU
5%
16V100PF
NP0-C0G5%
ROOM=PMU
010051/20W0.1%
ROOM=PMU
3.92K
MF0201
10KOHM-1%
ROOM=SOC
01005
0100510KOHM-1%
ROOM=RADIO_PAD
ROOM=B2B_WIDE_RCAM
0100510KOHM-1%
ROOM=PMU
16VNP0-C0G
01005
5%100PF
5%
ROOM=PMU
16VNP0-C0G
01005
100PF
01005
100PF
ROOM=PMU
16VNP0-C0G
5%
ROOM=NEO
0100510KOHM-1%
ROOM=PMU
OMIT
SHORT-20L-0.05MM-SM
21
47 12 5
24 21 17 15
50
50 48 47 46 45 43 41 36 25 23 18 15 13 11 5
21 7
41 21
29 21
24 20
20
21
21
21
21
40 21
21
21
21
40 21
40
21
21
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
VDD
CLKOUT
GND
NC
IN
NC
NC
IN
NC
NC
OUT
NC
NC
NC
IN
IN
IN
BI
NC
NC
NC
OUT
IN
NC
IN
OUT
IN
OUT
OUT
NC
OUT
IN
NC
IN
OUT
OUT
OUT
OUT
OUT
IN
OUT
NC
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
INSYM 4 OF 5
AD
C
XT
AL
RE
FS
BU
TT
ON
S
AM
UX
GP
IO
NT
CR
ES
ET
S
CO
MP
AR
AT
OR
SLEEP_32K
SYS_ALIVEFORCE_SYNCDBL_CLICK_DET
GPIO9GPIO10
SCLSDA
IREF
IBAT
BRICK_ID2BRICK_ID1
VDROOP11
PRE_UVLO
BUTTONO1BUTTONO2BUTTONO3
LDO5_UVLO_DETPRE_UVLO_DET
VDROOP11_DETVDROOP1_DETVDROOP0_DET
VREF
VDROOP0VDROOP1
ADC_IN
VBAT
BUTTON1BUTTON2BUTTON3BUTTON4
FAULT_OUT*
GPIO4GPIO3
GPIO5
GPIO2GPIO1
GPIO7GPIO8
GPIO6
GPIO11
GPIO13GPIO12
GPIO14GPIO15GPIO16
GPIO19GPIO20
GPIO17GPIO18
GPIO21
GPIO24GPIO23GPIO22
GPIO25
RESET_IN1
RESET_IN3RESET_IN2
RESET*SHDN
ACTIVE_RDY
OUT_32K
IRQ*
SCLKSDATA
AMUX_A0AMUX_A1AMUX_A2AMUX_A3
AMUX_A5AMUX_A6
AMUX_A4
AMUX_A7AMUX_AY
AMUX_B0AMUX_B1AMUX_B2AMUX_B3AMUX_B4AMUX_B5AMUX_B6AMUX_B7AMUX_BY
TDEV2TDEV1
TDEV3
TDEV5TDEV4
TCAL
XTAL1XTAL2
VDD_REF
VDD_RTC
NC
NC
NC
BOOST353S01124
When VDD_MAIN < 3.4, boosts to 3.4Otherwise tracks VDD_MAIN
22 OF 81
VOLTAGE=4.3V
10.0.0
31 OF 80
051-02159
2
1R3100
B1
B4B3
A4A3
C4C3
C2
B2
D4D3D2
A2
A1
C1
D1
U31002
1
L3100
2
1 C31132
1 C31142
1 C3115
2
1 C3190
2
1 C31102
1 C31122
1 C3111
DISPLAY_TO_MANY_BSYNC
PP_VDD_BOOST
PP_VDD_MAIN
I2C0_SMC_SCL
PMU_TO_BOOST_EN
SYS_BOOST_LX
I2C0_SMC_SDA
SYSTEM POWER: BoostSYNC_DATE=04/14/2017SYNC_MASTER=sync
10V5%220PF
01005C0G-CERM
ROOM=BOOST
18UF
CER-X5R
ROOM=BOOST
6.3V
0402-0.1MM
20%
ROOM=BOOST
20%
X5R6.3V
15UF
0402-0.1MM-1
20%
X5R6.3V
15UF
ROOM=BOOST0402-0.1MM-1
01005MF
1/32W
511K1%
ROOM=BOOST
21
CSPSN61280E
ROOM=BOOST
0.47UH-20%-4A-0.048OHMPIWA20120H-SMCRITICAL
46 25 24 23 11
46 25 24 23 11
50 42 29 21 13
15UF20%
X5R6.3V
ROOM=BOOST0402-0.1MM-1
20%
X5R6.3V
15UF
ROOM=BOOST0402-0.1MM-1
20%
X5R6.3V
15UF
ROOM=BOOST0402-0.1MM-1
50 43 41 36 28 20
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
VOUT
AGNDPGND
SCL
BYP*
EN
SW
VOUT
SW
GPIO
VIN
VIN
SDA
VSEL
BI
IN
IN
516S00232THIS ONE ON MLB --->
#29490552: I2C0 SMC Topology for D2x P2
Battery Connector
Changed BOM to ESD202 APN for fab release
Gas gauge I2C level translator#31734657:Replace battery I2C FETs with 376S00134#32515053:Add DZ3200/DZ3201 on I2C CONN with 377S00001
23 OF 81
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
VOLTAGE=4.3V
10.0.0
32 OF 80
051-02159
2
1
DZ3200
2
1
DZ3201
2 1
R3202
2
1 C3202
2
1 C3201
2
1
3
Q3201
2
1
3
Q3200
2 1
R3201
2
1 C3293
2 1
XW3200
2
1 C32922
1 C3294
10
9
87
65
4
321
J3200
PP1V8_S2
I2C0_SMC_SDA
I2C0_SMC_SCLI2C0_SMC_SCL_R
VBATT_SENSE
I2C0_SMC_BI_GG_SDA_CONN
I2C0_SMC_TO_GG_SCL_CONN
I2C0_SMC_BI_GG_SDA_CONN
I2C0_SMC_TO_GG_SCL_CONN
I2C0_SMC_SDA_R
PP_BATT_VCC
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SYSTEM POWER: B2B Battery
SG-WLL-2-2ESD202-B1-CSP01005
SG-WLL-2-2ESD202-B1-CSP01005
RV3C002UNDFN
46 25 24 22 11
46 25 24 22 11
33
MF01005
1/32W5%
ROOM=B2B_BATTERY
5%1/32WMF
01005
33
ROOM=B2B_BATTERY
ROOM=B2B_BATTERY01005NP0-C0G-CERM
56PF5%25V
ROOM=B2B_BATTERY
5%
01005
25V
56PF
NP0-C0G-CERM
DFNRV3C002UN
NP0-C0GROOM=B2B_BATTERY
100PF
01005
16V5%
24
NO_XNET_CONNECTION=1PLACE_NEAR=J3200:2mmROOM=B2B_BATTERY
SHORT-20L-0.05MM-SM
25V
01005
5%56PF
ROOM=B2B_BATTERY
NP0-C0G-CERM01005
10VC0G-CERM
5%220PF
ROOM=B2B_BATTERY
B2B-BATT-RCPT
ROOM=B2B_BATTERY
F-ST-SM
50 48 47 46 45 43 41 36 25 21 18 15 13 11 5
23
23
23
23 24 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SD
SY
M_V
ER
_1
G
BI
IN
SD
SY
M_V
ER
_1
G
OUT
#31097491:Change C3301/C3420 to ZRB
#29536266:10ohm between AUX1 and P_IN
APN:152S00683 (0.47UH-20%-7.2A-0.028OHM)
C3318 is only on D21x
#26845160:Charge Sharing on PMID caps
Tigris 2APN:343S00170
BATTERY NTC
#29546692:Move DZ3300 to PMID1Additional Cap for D21/D211 MLB
Inductor in Niki SIP
#29277790:Nostuff C3317/C3327
#29745777:Conn VDD_MAIN5 to PP_VDD_MAIN
138S00140/138S00141/138S00142 are alts#29536225:4UF for Better Derating#30208688:Update C3342/C3360/C3294 to 131S00053
#31097491:Charge C3310/C3320 to ZRB
Grounded for thermals
24 OF 81
10.0.0
33 OF 80
051-02159
2
1
0402-4
PP_VBUS2_IKTARA
X5R
F2E2D2C2B2A2
B3
H5G5F5
B4
C4
E5D5C5B5A5
D4
F4
F3G2
H6G6F6
E6D6C6B6A6
E4 H2H1G1D3
H3
E3
G3G4
H8G8F8E8D8C8A8
H7G7F7E7D7C7B7A7
H4
F1
E1D1C1B1A1
A4
B8
A3
U3300C3301
K
A
DZ33002
1 C3318
21
R3335
2
1 C3320
2
1 C33132
1 C33122
1 C3311
2
1R3311
2
1 C3317
2
1 C3327
2
1 C3316
2
1 C3326
2
1 C3315
2
1 C3325
2
1 C3310
2
1 C3350
2
1 C3306
2
1 C33032
1 C3302
2
1 C3305
2
1 C3353
2
1C3343
2
1 C3360
2
1C33412
1C3342
2
1C33912
1C3390
21
XW3370
2
1
R33702
1C3370
2
1R3350
21
C3340
B3B2B1A3A2
A1
C3C2C1
Q3350
21R3332
21R3331
2
1 C33522
1 C3351
2
1 C3361
2
1R3330
PP_VAR_USB_RVP
USB_VBUS_DETECT
BATTERY_NTC_RETURNBATTERY_NTC
TIGRIS_TO_PMU_INT_L
PP1V8_ALWAYS
TIGRIS_VBUS_DETECT
SYSTEM_ALIVE
VBATT_SENSE
BATTERY_NTC
TIGRIS_ACTIVE_DIODE
PP_VAR_USB_RVP_TIGRIS_R
HYDRA_TO_TIGRIS_VBUS1_VALID_L
TIGRIS_TO_PMU_INT_R_L
TIGRIS_PMID1
PP_VBUS1_E75
I2C0_SMC_SDAI2C0_SMC_SCL
TIGRIS_PMID2TIGRIS_LDO
TIGRIS_BOOT
PP_BATT_VCC
TIGRIS_LX
PP_VDD_MAIN
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SYSTEM POWER: Charger
1/32WMF
ROOM=CHARGER
100K
01005
5%
ROOM=CHARGER
CRITICAL
SN2501A1WCSP
25V20%2.2UF
ROOM=CHARGER
OMIT_TABLE
DFN10062BZT52C20LP
0402-4
25V20%X5R
ROOM=CHARGER
2.2UF
ROOM=CHARGER01005MF
1/32W5%
10
0603ROOM=CHARGER
X5R
4.7UF20%25 V
0402X5R
4.7UF20%16V
ROOM=CHARGERROOM=CHARGER0402X5R
4.7UF16V20%
ROOM=CHARGER0402X5R16V20%4.7UF50K
1/32W
01005MF
ROOM=CHARGER
1%
NOSTUFF
25V
ROOM=CHARGER01005COG5%220PF
NOSTUFF
COG25V
ROOM=CHARGER
220PF5%
01005
220PF
01005ROOM=CHARGER
25VCOG5%
COG5%
01005
25V220PF
ROOM=CHARGER
COG25V5%220PF
01005ROOM=CHARGER
COG01005
5%25V220PF
ROOM=CHARGER
X5R25 V
0603ROOM=CHARGER
4.7UF20%
ROOM=CHARGER
330PF
CER-X7R16V10%
01005
220PF5%COG01005
25V
ROOM=CHARGER
220PF5%25VCOG01005
ROOM=CHARGER
220PF
01005COG5%25V
ROOM=CHARGER
X5R402
ROOM=CHARGER
25V10%1UF
10VC0G-CERM5%
01005ROOM=CHARGER
220PF
330PF10%
CER-X7R
ROOM=CHARGER
16V
01005
ROOM=CHARGER01005
5%
C0G-CERM10V
220PF
C0G-CERM01005
ROOM=CHARGER
220PF10V5% 5%
10V
01005ROOM=CHARGER
C0G-CERM
220PF
0402-0.1MMROOM=CHARGER
6.3VCERM
15UF20%
0402-0.1MMCERM6.3V20%
15UF
ROOM=CHARGER
OMIT
ROOM=CHARGER
SHORT-20L-0.05MM-SM
01005ROOM=B2B_BATTERY
10KOHM-1%C0G-CERM
220PF5%
01005
10V
ROOM=CHARGER
23
21
7
47 5
21 17 15
46 25 23 22 11
46 25 23 22 11
NOSTUFF
100K
ROOM=CHARGER
5%1/32W
MF01005
10%
0201
0.047UF
16VX5R
NO_XNET_CONNECTIONROOM=CHARGER
CSD68841W
CRITICAL
BGAROOM=CHARGER
1%1/32W
30.1K
MF01005
ROOM=CHARGER
100
MF
1%1/32W
01005ROOM=CHARGER
OMIT_TABLE
20%6.3V
ROOM=CHARGER
X5R-CERM
2.2UF
0201
OMIT_TABLEROOM=CHARGER
20%6.3V2.2UF
0201X5R-CERM
CER-X5R
3.9UF
0201
20%
ROOM=CHARGER
6.3V
47 46 44
24
21 20
24
48 5
25 5
23 5
40
50 48 47 45 44 42 41 40 39 38 37 32 28 25 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VBUS1_DET
SYS_ALIVE
VBUS1
BATT_SNS
PMID1
PMID2PMID2
BUCK_SW
NTC
HDQ_GAUGEHDQ_HOST
ACT_DIODE
VBUS2BATT
BUCK_SW
PMID1
PMID1
NC2
AUX1
NC3
NC1
VBUS2_VALID*VBUS1_VALID*
TEST
NC0
GND AGND
BATT
INT*
BOOT
LDO
BUCK_SW
BUCK_SW
BUCK_SWBUCK_SW
BATT
BUCK_SW
BATT
BATT
PMID1PMID1
VBUS1
VBUS1VBUS1
VBUS1
VBUS2VBUS2
SDASCL
PMID2BUCK_SW
VDD_
MAI
N5
VDD_
MAI
NVD
D_M
AIN
VDD_
MAI
NVD
D_M
AIN
VDD_
MAI
N
IN
OUT
OUT
IN
IN
IN
BI
G
S
D
#30823904: Add 1kohm to GPIO6 for product ID
101 <- SELECTED (D21x)110 RESERVED FOR OTHER PROGRAMS
#29223315: Add series R to EN_EXT_1P8 and RESET*
#29706561: Add connection from Iktara GPIO to PMU
Note: Iktara GPIOs 5-7 reserved for product ID
011 RESERVED FOR OTHER PROGRAMS
NOTE: PU only at RESET* not GPIO2
#30023781: Connect ANA3 to VDD_MAIN
#30624018: Update C3425 to 2.2UF
#30188057: Add 0201 PU to VDD_MAIN
Pull-Ups
Iktara
#29302816: Remove reset connection to Iktara GPIO
Iktara Debug
To Coil
To Coil
#31871684: Per Kieran/Pratik, Updating Low Dk Caps for Iktara in Carrier#29235539: D21x EVT updates for resonant caps
25 OF 81
VOLTAGE=1.8V
VOLTAGE=1.5V
VOLTAGE=19V VOLTAGE=19V
VOLTAGE=16V
VOLTAGE=5.0V
VOLTAGE=5.0V
10.0.0
34 OF 80
051-02159
01005
25V5%
COG
ROOM=IKTARA
220PF25V
ROOM=IKTARA
COG01005
5%220PF
25V220PF
01005COG5%
ROOM=IKTARA
25V20%X5R0402-4
ROOM=IKTARA
2.2UF
ROOM=IKTARA
OMIT
SHORT-20L-0.05MM-SM
OMIT
ROOM=IKTARA
SHORT-20L-0.05MM-SM
ROOM=IKTARA
SHORT-20L-0.05MM-SM
OMIT
21
P2MM-NSMSM
ROOM=TEST
ROOM=TESTSM
P2MM-NSM
ROOM=TESTSM
P2MM-NSM
100
5% MF
ROOM=IKTARA010051/32W
MF01005
100
ROOM=IKTARA1/32W5%
21
ROOM=IKTARA
X5R6.3V20%
ROOM=IKTARA
20%X5R25V
2.2UF
0402-40402-4ROOM=IKTARA
20%X5R25V
2.2UF2.2UF20%
ROOM=IKTARA0402-4
X5R25V
ROOM=IKTARA0402-4
X5R25V
2.2UF20%
1.0UF
ROOM=IKTARA
X5R6.3V20%
2M5%
MF201
ROOM=IKTARA
1/20W
ROOM=IKTARA01005MF
1/32W0%
0.00
X7R0402
10%50V
ROOM=IKTARA
0.033UF 16V
0201ROOM=IKTARA
X5R-CERM
0.1UF
10%
50V10%2200PF
X5R0201ROOM=IKTARA
10%16V
0201X5R-CERM
ROOM=IKTARA
0.1UF
10%
ROOM=IKTARA0402X7R50V
0.033UF
MF
5%
ROOM=IKTARA01005
1/32W
10K20%6.3VX5R-CERM
ROOM=IKTARA0201
2.2UF
01005MF5%
ROOM=IKTARA1/32W
1.00K
SNSR20F30WCNXROOM=IKTARA
DSN2
OMIT_TABLE
DSN2
ROOM=IKTARASNSR20F30WCNX
OMIT_TABLE
DSN2
ROOM=IKTARA
SNSR20F30WCNX
OMIT_TABLE
DSN2
OMIT_TABLE
ROOM=IKTARA
SNSR20F30WCNX
X5R25V
2.2UF20%
ROOM=IKTARA0402-4
1/20W1%100K
201MF
ROOM=IKTARA
10%50V
0402
100NF
X7S X7S
47NF
0402
10%
ROOM=IKTARA
50V
68NF50V
0402X7S
ROOM=IKTARA
10%
201
1%1/20WMF
100K
X7S10%
0402
50V
ROOM=IKTARA
68NF10%50V
47NF
X7S
ROOM=IKTARA0402
0402
50V10%X7S
ROOM=IKTARA
68NF
ROOM=IKTARA
X7S
NOSTUFF
0402
50V
68NF10%
ROOM=IKTARA0402
50VX7S10%68NF
50VX7S0402
ROOM=IKTARA
10%68NF
0201X5R
NOSTUFF
2200PF10%
ROOM=IKTARA
50V
50VX7S0402
68NF
ROOM=IKTARA
10%
NOSTUFF
X7S50V10%100NF
0402ROOM=IKTARA
MF
CRITICAL
0.02
1%1/6W
0402
50V10%68NF
X7S
ROOM=IKTARA0402
21
WLCSPBC59355A2
ROOM=IKTARA
CRITICAL
PP_IKTARA_VMID_SENSE
11 22 23 24 46
11 22 23 24 46
11 25
2.2UF
ROOM=IKTARA
20%25VX5R0402-4
ROOM=IKTARA
20%6.3VCER-X5R0201
3.9UF
SYSTEM POWER: IktaraSYNC_DATE=04/14/2017SYNC_MASTER=sync
IKTARA_AC2
IKTARA_BOOT1
IKTARA_GPIO3
PP5V0_VDD_IKTARA
PP5V0_VMID_AUX_IKTARA
PP_VBUS2_IKTARA
PMU_TO_IKTARA_RESET_R_L
IKTARA_TO_PMU_OVP
IKTARA_COIL1_CONN
IKTARA_AC1
IKTARA_COMM1
IKTARA_COIL2_CONN
PP_IKTARA_VMID
IKTARA_GPIO4
PP_VDD_MAIN
PMU_TO_IKTARA_RESET_L
PMU_TO_IKTARA_EN_EXT_1P8VPP_VDD_MAIN
PP1V8_IKTARA
IKTARA_TO_SMC_INT
IKTARA_COMM2
PP1V8_S2
PP_VDD_MAIN_IKTARA
IKTARA_VOUT_SNS
I2C0_SMC_SCLIKTARA_TO_SMC_INT
NC_IKTARA_PRODUCT_ID_0IKTARA_GPIO4
PMU_TO_IKTARA_EN_EXT_1P8V_R
PP_VDD_MAIN
NC_IKTARA_PRODUCT_ID_2IKTARA_PRODUCT_ID_1
IKTARA_GPIO3
PP_IKTARA_VRECT_SENSE
PP_IKTARA_VRECT
IKTARA_BOOT2
I2C0_SMC_SDA
PP1V5_VDIG_CORE_IKTARA
PP1V8_IKTARA
C34151
2
C3422 R34211
2
U3400
B6B7C6
B1B2C2
E2F2G3G2
C4 G4 H3 L7 F5 F4
C7
C1
H2
B5
B3
C5
C3
G5
E7
H6L6J6K5J5K7K6
H4H5
K4
J7
J3 K3 L3G6
J4
A1 A2 A3 A4 A5 A6 A7 B4
L5L4
J2K2L2
G7
E3
H7
F7
E6E5
E4F1 H1 J1 K1 L1
G1
E1D1 D2 D3 D4 D5 D6 D7
F6
F3
C34161
2
C34241
2
C3414 1
2
C34171
2
C34211
2
XW34011
2
XW34001
2
XW34021 2
PP34031
PP34041
PP34051
R34221 2
R34231 2
C3413 1
2
C3412 1
2
C3411 1
2
C3410 1
2
R34201
2
R34301 2
C34071
2
C34051 2
C34031
2
C34041 2
C34061
2
C34251
2
R34241 2
D3400A
K
D3402A
K
D3401A
K
D3403A
K
C34201
2
R34601
2
C34611
2
C34621
2
C34631
2
R34501
2
C34511
2
C34521
2
C34641
2
C34651
2
C34551
2
C34561
2
C3402 1
2
C34531
2
C34541
2
R34101 2
C34661
2
0201-1
1
2
C34231.0UF
0201-1
1
2
25
5 24
5 26
5 26
25
5 19 20 22 24 25 28 32 37 38 39 40 41 42 44 45 47 48 50
5 19 20 22 24 25 28 32 37 38 39 40 41 42 44 45 47 48 50
25
11 25
5 11 13 15 18 21 23 36 41 43 45 46 47 48 50
25
5 19 20 22 24 25 28 32 37 38 39 40 41 42 44 45 47 48 50
25
25
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
BI
IN
NC
BOOT1_VDD
AC1AC1
BOOT2_VDD
COMM2
CLAMP2
GPIO3/SWDIO
VMID_AUX_SW_VDD
SW
OTP_WREN
AC1
AC2
AC2AC2
COMM1
VDIG_CORE_VDD
VDD5V
SDASCLINT
RESET*
GPIO1GPIO2
GPIO6GPIO7
VSYS_ANA_VDD
AVSSPGNDRGND
VMID_AUX_VDD
GPIO5
EN_EXT_1P8
VDDO
VSYS_1P8_VDD
GPIO4/SWCLK
CLAMP1
VREC
T_VD
DVR
ECT_
VDD
VREC
T_VD
DVR
ECT_
VDD
VREC
T_S
VREC
T_VD
D
VREC
T_VD
DVR
ECT_
VDD
VMID
_S
VMID
_R_V
DD
VMID
_VDD
VMID
_VDD
VMID
_VDD
VMID
_VDD
VAUX_1P8_VDD
ANA3ANA2ANA1
ANA4
REFBP
DIGTEST
BOOTB_VDD
SWSW
VOUT
HV_GPO2HV_GPO1
IN
NCNC
NC
NC
OUT
NC
PP
PP
PP
IN
NC
NC
516S00311
Cyclone connectorTHIS ONE ON MLB --->
#31690340:Remove XWs on Iktara Coil Paths
26 OF 81
10.0.0
35 OF 80
051-02159
1211
109
87
65
4321
J3500
2
1C35112
1 C35102
1C35002
1 C3501IKTARA_COIL2_CONN
IKTARA_COIL1_CONN
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SYSTEM POWER: B2B Cyclone
F-ST-SM
CRITICAL
CPBC102-0101E
ROOM=B2B_CYCLONE
ROOM=B2B_CYCLONE
C0G0201
50V2%
220PF 220PF2%50V
0201ROOM=B2B_CYCLONE
C0G
C0G0201
ROOM=B2B_CYCLONE
50V2%
220PF 220PF2%50V
0201ROOM=B2B_CYCLONE
C0G
25 5
25 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
Phosphorus
#30844258:Pin14 to GND
APN:338S00334
#29695424: Stuff PU for Graphite CS
APN: 338S00304 (A1) Shared decoupling with Phosphorus
Magnesium - CompassAPN:338S00084
1.09M INT PU 114K INT PD
114K INT PU
Graphite - Accel & Gyro
North Speaker Compass Compensation Coil
27 OF 81
10.0.0
36 OF 80
051-02159
68
534 7
1
2
U3620
2
1R3616
2
1R3615
116
152
7
346
141312111098
5
U3600
2
1
XW3615
2
1R3601
2
1 C3611
2
1 C36152
1 C3616
2
1R3620
2
1 C3622
2
1 C3610
2
1 C3620
2
1 C36022
1 C36012
1 C3600
C1
C2
C4
C3
B4
A4
A3
D2D1B3B1
D4
A1
A2
U3610
PP1V8_IMU_S2SPI_AOP_TO_IMU_SCLK
PP1V8_IMU_S2
PP1V8_IMU_S2
SPI_IMU_TO_AOP_MISO
PP1V8_IMU_S2
POS_COMPASS_COIL_COMP
PP1V8_IMU_S2
SPI_AOP_TO_IMU_MOSI
SPI_AOP_TO_IMU_SCLK
SPI_AOP_TO_COMPASS_CS_L
PP1V8_IMU_S2
SPI_AOP_TO_IMU_MOSICOMPASS_TO_AOP_INT
SPKRAMP_TOP_TO_COIL_OUT_POS
ACCEL_GYRO_TO_AOP_DATARDYACCEL_GYRO_TO_AOP_INT
SPI_IMU_TO_AOP_MISO
SPI_IMU_TO_AOP_MISO
SPKRAMP_TOP_TO_COIL_OUT_NEG
NEG_COMPASS_COIL_COMP
SPI_AOP_TO_PHOSPHORUS_CS_L
SPI_AOP_TO_IMU_MOSISPI_AOP_TO_IMU_SCLK PHOSPHORUS_TO_AOP_INT
SPI_AOP_TO_ACCEL_GYRO_CS_L
SYNC_MASTER=sync SYNC_DATE=04/14/2017
SENSORS
CRITICALROOM=PHOSPHORUS
BMP284BALGA
1.1K
MF1/32W1%
01005ROOM=SPKAMP2
CRITICAL
1.1K
MF1/32W1%
01005ROOM=SPKAMP2
CRITICAL
CRITICAL
ROOM=CARBON
LGABMI262BB
SHORT-20L-0.05MM-SM
ROOM=MAGNESIUMNO_XNET_CONNECTION
OMIT
100K
MF1/32W
5%
01005ROOM=CARBON
X5R-CERM
2.2UF
0201
20%6.3V
ROOM=PHOSPHORUS
OMIT_TABLE
ROOM=SPKAMP2
220PF5%
01005C0G-CERM10V
ROOM=SPKAMP201005C0G-CERM
5%10V
220PF
1/32W
01005
NOSTUFF
100K
ROOM=PHOSPHORUS
5%
MF
13
13 5
27 13 5
13
27 13 5
27 13 5
13 5
13 5
27 13 5
27 13 5
27 13 5
27 13 5
27 13 5
27 13 5
13
13
0201ROOM=PHOSPHORUSOMIT_TABLE
2.2UF20%6.3VX5R-CERM
0.1UF20%6.3V
ROOM=MAGNESIUM
01005X5R-CERM
01005ROOM=PHOSPHORUS
0.1UF6.3VX5R-CERM20%
0201
20%2.2UF6.3V
ROOM=CARBONOMIT_TABLE
X5R-CERM
0.1UF20%X5R-CERM6.3V
01005ROOM=CARBON
20%
01005X5R-CERM6.3V
ROOM=CARBON
0.1UF
LGA
HSCDTD601A-2A
ROOM=MAGNESIUM
CRITICAL
27 18
27 18
27 18
27 18
27 18
27 18
38 33 38 33
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
CS*
SDI SDO
VDD VDDIO
IRQ
GND
SCK
CSB
INT
SM
MOTION_INT
VDD
VDDI
O
MISOMOSI
GND
GND
GND
GND
GND
GND
GND
SCLK
OUT
OUT
OUT
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT
IN
IN
OUT
INNCNC
NC
VPP
RSVRSV
RSV
VDD
VSS
SDO
SCL/SCK
SDA/SDI
CSB
TRG/SE
DRDY
RSV
RST*
NC
NC
NC
D21:152S00622 (Lower)
C LDO4: 300mA maxCX LDO9: 390mA max
D LDO15: 400mA maxActual Load: 390mA
For GPIO pullups only
LAYOUT: C3790 shared with NFC BOOST
C LDO20: 300mA max
Camera PMU
D20:152S00626
D LDO18: 400mA maxC LDO17: 300mA max
/1.95V
Cx LDO22: 390mA maxC LDO21: 300mA max
C LDO19: 300mA max
Ga LDO10: 1300mA max
#31766720:Add 0402 Footprint Connector#31710713:C3704 to 4UF to mitigate RnR
/1.95V
#32596057:Increase C3722 to 3.9UF to Help RCAM ONZ
28 OF 81
VOLTAGE=2.85V
VOLTAGE=2.85V
VOLTAGE=2.6V
VOLTAGE=1.8VVOLTAGE=2.85V
VOLTAGE=1.15VVOLTAGE=1.15V
VOLTAGE=1.15VVOLTAGE=2.85V
VOLTAGE=2.6VVOLTAGE=3.3V
10.0.0
37 OF 80
051-02159
2
1 C3720
2
1 C37032
1 C3704
2
1 C3702
21
L3700
2
1 C37982
1 C3797
2
1 C37112
1 C3710
2
1 C3796
2
1 C37912
1 C3790
2
1 C3795
21
XW3700
2
1C3750
2
1 C37222
1 C3721
2
1 C3719
2
1 C37182
1 C3717
2
1 C3715
2
1 C3709
2
1 C37012
1 C3700
J4
G1B7
B8A3
A4B1
A5A6
J2B2
H1A8
A7B3
B4
B5B6
H2
A2
A1
H3
F2
J3
U3700
G4E2C5
J8J7
H8H7
H5
U3700
PP2V85_FCAM_AVDD
PP_VDD_MAIN
PP2V85_VAR_CAM_VCM_PVDDCAMPMU_BUCK_LX0
PP1V8_IO
PP_VDD_BOOST
CAMPMU_ON_BUF
PP1V25_S2
CAMPMU_BUCK_FB
PP_CAM_WIDE_ADC
PP1V8_HAWKINGPP2V85_CAM_WIDE_AVDD
PP1V1_CAM_TELE_DVDDPP1V1_FCAM_DVDD
PP1V1_CAM_WIDE_DVDDPP2V85_CAM_TELE_AVDD
PP_CAM_TELE_ADCPP3V3_SVDD
SYNC_MASTER=sync SYNC_DATE=04/14/2017
CAMERA: PMU (1/2)
2.2UF20%6.3VX5R-CERM0201ROOM=CAM_PMU
20%3.9UF6.3VCER-X5R0201ROOM=CAM_PMU
0201X5R-CERM
2.2UF20%6.3V
ROOM=CAM_PMU
CER-X5R6.3V20%18UF
0402-0.1MMROOM=CAM_PMU
3.9UF20%CER-X5R0201
6.3V
ROOM=CAM_PMU
CER-X7R01005
16V
ROOM=CAM_PMU
330PF10%
1UH-20%-2.1A-0.1OHM
PIWA2012FE-SMROOM=CAM_PMU
20%6.3VX5R-CERM0201
2.2UF
ROOM=CAM_PMUOMIT_TABLE
20%6.3V
0201X5R-CERM
ROOM=CAM_PMU
2.2UF
OMIT_TABLE
2.2UF6.3V20%
0201X5R-CERM
ROOM=CAM_PMU
2.2UF
X5R-CERM0201
6.3V20%
ROOM=CAM_PMU
20%18UF
0402-0.1MMCER-X5R6.3V
ROOM=CAM_PMU
20%6.3V
2.2UF
0201X5R-CERM
ROOM=CAM_PMUOMIT_TABLE
20%
ROOM=CAM_PMU
0402-0.1MMCER-X5R6.3V
18UF
20%6.3V
2.2UF
X5R-CERM0201ROOM=CAM_PMUOMIT_TABLE
20%18UF
0402-0.1MMCER-X5R6.3V
ROOM=CAM_PMU
20%6.3VX5R-CERM0201
2.2UF
ROOM=CAM_PMUOMIT_TABLE
SHORT-20L-0.05MM-SM
ROOM=B2B_WIDE_RCAM
OMIT
WLCSP
D2462-AVAE
20%X5R6.3V
ROOM=CAM_PMU01005
0.22UF
0201ROOM=CAM_PMU
6.3V20%
CER-X5R
3.9UF20%
ROOM=CAM_PMU0201X5R-CERM6.3V
2.2UF
6.3V
0201ROOM=CAM_PMU
X5R-CERM
20%2.2UF
20%6.3V
0201ROOM=CAM_PMU
X5R-CERM
2.2UF
ROOM=CAM_PMU0201
6.3V20%
CER-X5R
3.9UF
D2462-AVAEWLCSP
CRITICALROOM=CAM_PMU
33
50 48 47 45 44 42 41 40 39 38 37 32 25 24 22 20 19 5
30
42 40 33 31 30 29 18 17 15 11 9 8 7 6
50 43 41 36 22 20
20 18
30
34
30
31
33
30
31
31
31 30
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
NC
SW OUTPUTSW INPUT
SYM 2 OF 4
LDO OUTPUTLDO INPUT
VLDO9VLDO4
VLDO15VLDO10
VLDO18VLDO17
VLDO20VLDO19
VLDO22VLDO21
ON_BUF
BUCK3_SW1
VDD_LDO9VDD_LDO4_17
VDD_LDO4_17
VDD_LDO19
VDD_LDO18
VDD_LDO20_21
VDD_LDO22VDD_LDO20_21
VDD_LDO10VDD_LDO15
VBUCK3
VPUMP
BUCKS
SYM 1 OF 4
VCC MAIN
VDD_BUCK9
VDD_MAINVDD_MAIN
VDD_MAIN
VDD_BUCK9BUCK9_LX0BUCK9_LX0BUCK9_FB
#30505664:Remove Ansel TDEV Routing
#29220631: Connect Neon to other side of R3802 and change to 49.9 ohms
PU on AP GPIO
29 OF 81
PP1V8_IO
10.0.0
38 OF 80
051-02159
2
1R3801
21
R3802
21
R3840
2
1 C3810
2
1R3800
2
1 C3800
F4J6J1H6H4G8G7G6
F1E5D5D2C7C4C3C2
U3700
E1
C1
G5J5
C6
F8E8
F5
D8
D1E3G2G3F3F7D3D4E4D7E6F6
D6
E7
C8
U3700
AP_TO_CAMPMU_RESET_L DISPLAY_TO_MANY_BSYNC
I2C3_ISP_SDA_R
I2C3_ISP_SDA
CAMPMU_TO_STROBE_DRIVER_HWEN_R
MAKE_BASE=TRUE
PP1V8_IO
CAMPMU_TO_STROBE_DRIVER_HWEN
I2C3_ISP_SCL
CAMPMU_TO_PMU_AMUX
CAMPMU_TO_AP_IRQ_L
CAMPMU_VREF
CAMPMU_IREF
CAMPMU_VRTC
CAMERA: PMU (2/2)SYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=CAM_PMU01005MF
5%1/32W
100K
12
ROOM=CAM_PMU
1%
49.9
MF1/32W
01005
32
9
MF1/32W
01005ROOM=B2B_FOREHEAD
100
5%
12
6.3V20%
X5R-CERM
ROOM=CAM_PMU01005
0.1UF1%
MF
ROOM=CAM_PMU01005
200K1/32W
ROOM=CAM_PMU01005
20%
X5R
0.22UF6.3V
21
32 9
32
D2462-AVAEWLCSP
D2462-AVAEWLCSP
50 42 22 21 13
42 40 33 31 30 28 18 17 15 11 9 8 7 6
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNCNC
NC
NC
IN
BI
BI
OUT NC
OUT
IN
OUT
NC
NC
NCNCNC
SYM 4 OF 4
VSSVSS
VSSVSSVSSVSSVSS
VSS
VSSVSSVSSVSSVSSVSSVSS
VSS
NC
TEMPERATURE
REFERENCE
RESET
I2C
SYM 3 OF 4
GPIO
GPIO1
GPIO3GPIO4GPIO5GPIO6
GPIO2
GPIO9GPIO10GPIO11GPIO12GPIO15
SCL
IRQ*
SDA
CRASH*
VREF
IREF
VRTC
RESET_IN
TCAL
TDEV2TDEV1
AMUX_AY
ATM
Power Filtering
#27431370
#27431370
ISP I2C
516S00309/P2 PLUG (USED ON FLEX)516S00310/P2 RCPT (USED ON MLB)
Wide Camera ConnectorTHIS ONE --->
LPDP Filters
Desense for Wifi
IO Filters
30 OF 81
GND_VOID=TRUE
CKPLUS_WAIVE=I2C_PULLUP
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
39 OF 80
051-02159
21
R3905
30
29
2827
2625
242322212019181716151413121110987654321
J3900
21
R3908
21
R3907
2
1 C3906
2
1 C39282
1 C39262
1 C3925
2
1 C390921
FL3901
2
1 C39962
1 C399521
FL3995
2
1 C39902
1 C39912
1 C39922
1 C39932
1 C3994
21
C3950
21
C3951
21
R3901
2
1 C3901
2
1 C390021
R3900
21
C3960
2
1 C3961
21
C3940
21
C3941
21
C3930
21
C3931
2
1 C3908
2
1 C3907
21
FL3903
ISP_TO_WIDE_SHUTDOWN_CONN_L
90_LPDP_WIDE_TO_AP_D1_N
90_LPDP_WIDE_TO_AP_D1_P
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
PP_CAM_WIDE_ADC
PP1V1_CAM_WIDE_DVDD_CONN
LPDP_WIDE_BI_AP_AUX_CONN90_LPDP_WIDE_TO_AP_D2_CONN_P
PP3V3_SVDDPP1V1_CAM_WIDE_DVDD_CONNPP2V85_CAM_WIDE_AVDD
PP_CAM_VCM_PVDD_CONNPP2V85_VAR_CAM_VCM_PVDD
PP1V1_CAM_WIDE_DVDD PP1V1_CAM_WIDE_DVDD_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D2_P
90_LPDP_WIDE_TO_AP_D0_P
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
I2C0_ISP_SCL
90_LPDP_WIDE_TO_AP_D2_CONN_P
90_LPDP_WIDE_TO_AP_D0_CONN_PI2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN
LPDP_WIDE_BI_AP_AUX_CONNLPDP_WIDE_BI_AP_AUX
90_LPDP_WIDE_TO_AP_D2_N 90_LPDP_WIDE_TO_AP_D2_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P
90_LPDP_WIDE_TO_AP_D0_N
PP_CAM_VCM_PVDD_CONN
PP1V8_IO
PP_CAM_WIDE_ADCPP_CAM_VCM_PVDD_CONN
90_LPDP_WIDE_TO_AP_D1_CONN_N PP1V8_CAM_WIDE_VDDIO_CONNWIDE_TO_TELE_SYNC_J3900_CONN
I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN
AP_TO_WIDE_CLK_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_P
90_LPDP_WIDE_TO_AP_D2_CONN_N
PP3V3_SVDD
ISP_TO_WIDE_SHUTDOWN_CONN_L
I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN
90_LPDP_WIDE_TO_AP_D0_CONN_N
90_LPDP_WIDE_TO_AP_D1_CONN_P
PP2V85_CAM_WIDE_AVDD PP1V8_CAM_WIDE_VDDIO_CONN
AP_TO_WIDE_CLK
I2C0_ISP_SDA I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN
ISP_TO_WIDE_SHUTDOWN_L
AP_TO_WIDE_CLK_CONN
CAMERA: B2B Wide (KY)SYNC_DATE=04/14/2017SYNC_MASTER=sync
20%
X5R-CERM6.3V
GND_VOID=TRUEROOM=B2B_WIDE_RCAM
0.1UF
01005
20%
X5R-CERM6.3V
GND_VOID=TRUE
0.1UF
ROOM=B2B_WIDE_RCAM
01005
20%
X5R-CERM6.3V
ROOM=B2B_WIDE_RCAM
0.1UF
GND_VOID=TRUE
01005
20%
X5R-CERM6.3V
GND_VOID=TRUE
01005
ROOM=B2B_WIDE_RCAM
0.1UF
ROOM=B2B_WIDE_RCAM
10VC0G-CERM01005
220PF5%
ROOM=B2B_WIDE_RCAM01005
5%
C0G-CERM10V
220PF
1/32W0%
MF
0.00
ROOM=B2B_WIDE_RCAM01005
AA27DK-S024VA1F-ST-SM
01005MF
0.00
0%1/32W
ROOM=B2B_WIDE_RCAM
0%
0.00
1/32W
ROOM=B2B_WIDE_RCAM01005MF
56PF25V5%
01005ROOM=B2B_WIDE_RCAM
I193
NP0-C0G-CERM
ROOM=B2B_WIDE_RCAM
15PF
NP0-C0G-CERM16V
01005
5%
OMIT_TABLE
20%2.2UF
0201X5R-CERM6.3V
ROOM=B2B_WIDE_RCAMOMIT_TABLE
20%2.2UF
0201X5R-CERM6.3V
ROOM=B2B_WIDE_RCAM
OMIT_TABLE
20%2.2UF
0201X5R-CERM6.3V
ROOM=B2B_WIDE_RCAM
0201ROOM=B2B_WIDE_RCAM
33-OHM-25%-1500MA
5%220PF
01005C0G-CERM10V
ROOM=B2B_WIDE_RCAM
20%X5R-CERM6.3V
ROOM=B2B_WIDE_RCAM01005
0.1UFROOM=B2B_WIDE_RCAM
10-OHM-750MA
01005-1
220PF
C0G-CERM
ROOM=B2B_WIDE_RCAM
5%10V
01005
5%10V
220PF
C0G-CERM01005
ROOM=B2B_WIDE_RCAM
220PF5%10V
01005ROOM=B2B_WIDE_RCAM
C0G-CERM
ROOM=B2B_WIDE_RCAM01005
220PF5%
C0G-CERM10V
ROOM=B2B_WIDE_RCAM
5%220PF
01005C0G-CERM10V
10
32
9
9
9
9
10
10
10
10
10
10
20%
X5R-CERM6.3V
GND_VOID=TRUE
01005
0.1UF
ROOM=B2B_WIDE_RCAM
20%
X5R-CERM6.3V
GND_VOID=TRUE
ROOM=B2B_WIDE_RCAM
0.1UF
01005
0.00
MF
0%1/32W
01005ROOM=B2B_WIDE_RCAM
ROOM=B2B_WIDE_RCAM
25V
56PF
01005
5%
NP0-C0G-CERM
NP0-C0G-CERM25V
56PF
ROOM=B2B_WIDE_RCAM01005
5%ROOM=B2B_WIDE_RCAM
MF
0%
0.00
1/32W
01005
20%
X5R-CERM6.3V
ROOM=B2B_WIDE_RCAM
0.1UF
01005
ROOM=B2B_WIDE_RCAM
25VNP0-C0G-CERM
56PF
01005
5%
ROOM=B2B_WIDE_RCAM
33-OHM-25%-1500MA
0201
30
31 30
30 28
30
30
30
31 30 28
30
30 28
30 28
28 30
30
31 30
30
30
30
30
30
30
30
30
42
40 33 31 29 28 18 17 15 11 9 8 7 6
30 28
30
30 30
31
30
30
30
30
31 30 28
30
30
30
30
30 28 30
30
30
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
BI
OUT
IN
IN
BI
IN
IN
IN
IN
IN
BI
BI
IO Filters
Tele Camera Connector516S00310/P2 RCPT (USED ON MLB)516S00309/P2 PLUG (USED ON FLEX)
THIS ONE --->
#29487888
#27431370
Desense for Wifi frequencies
#27431370
ISP I2C
Power Filtering
LPDP
31 OF 81
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
40 OF 80
051-02159
21
R4005
30
29
2827
2625
242322212019181716151413121110987654321
J4000
2
1 C4096
21
R4010
21
R4007
2
1 C4093
2
1 C4095
2
1 C402621
FL4003
2
1 C40282
1 C4025
21
FL4095
2
1 C40912
1 C40922
1 C4094
21
C4050
21
C4051
21
C4060
2
1 C4061
21
R4000
2
1 C4001
2
1 C4000
21
R4001
21
C4041
21
C4040
21
C4031
21
C4030
2
1 C4006
2
1 C4008
2
1 C4010
2
1 C4007ISP_TO_TELE_SHUTDOWN_CONN_L
I2C1_ISP_BI_TELE_SDA_CONN
PP1V1_CAM_TELE_DVDD_CONN
90_LPDP_TELE_TO_AP_D2_CONN_N90_LPDP_TELE_TO_AP_D2_CONN_P
AP_TO_TELE_CLK_CONN
PP2V85_CAM_TELE_AVDDPP_CAM_TELE_ADC
PP1V8_CAM_TELE_VDDIO_CONN
PP1V1_CAM_TELE_DVDD_CONN
PP3V3_SVDDPP1V8_CAM_TELE_VDDIO_CONN
WIDE_TO_TELE_SYNC_J4000_CONNISP_TO_TELE_SHUTDOWN_CONN_L
LPDP_TELE_BI_AP_AUX_CONN
90_LPDP_TELE_TO_AP_D1_CONN_P
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
90_LPDP_TELE_TO_AP_D0_N
90_LPDP_TELE_TO_AP_D1_P
PP2V85_CAM_TELE_AVDD
PP1V8_CAM_TELE_VDDIO_CONNPP1V8_IO
PP3V3_SVDD
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
WIDE_TO_TELE_SYNC_J3900_CONN WIDE_TO_TELE_SYNC_J4000_CONN
LPDP_TELE_BI_AP_AUX
90_LPDP_TELE_TO_AP_D2_CONN_N90_LPDP_TELE_TO_AP_D2_N
90_LPDP_TELE_TO_AP_D2_CONN_P90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D1_CONN_N
90_LPDP_TELE_TO_AP_D1_CONN_P
90_LPDP_TELE_TO_AP_D0_CONN_N
90_LPDP_TELE_TO_AP_D0_CONN_P90_LPDP_TELE_TO_AP_D0_P
LPDP_TELE_BI_AP_AUX_CONN
PP1V1_CAM_TELE_DVDD
PP_CAM_TELE_ADC
I2C1_ISP_SDA
I2C1_ISP_SCL
I2C1_ISP_BI_TELE_SDA_CONN
I2C1_ISP_TO_TELE_SCL_CONN
90_LPDP_TELE_TO_AP_D1_N
90_LPDP_TELE_TO_AP_D0_CONN_N
AP_TO_TELE_CLK AP_TO_TELE_CLK_CONN
90_LPDP_TELE_TO_AP_D0_CONN_PI2C1_ISP_TO_TELE_SCL_CONN
90_LPDP_TELE_TO_AP_D1_CONN_N
ISP_TO_TELE_SHUTDOWN_L
CAMERA: B2B Tele (TN)SYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=B2B_TELE_RCAM
1/32W0%
0.00
MF01005
F-ST-SMAA27DK-S024VA1
5%220PF
01005C0G-CERM10V
ROOM=B2B_TELE_CAM
ROOM=B2B_TELE_RCAM
1/32W0%
0.00
MF01005
1/32WMF
01005ROOM=B2B_TELE_RCAM
0.00
0%
01005C0G-CERM
5%220PF10V
ROOM=B2B_PEARL
0201-1X5R
1.0UF
ROOM=B2B_TELE_CAM
6.3V20%
ROOM=B2B_TELE_CAM
6.3VX5R-CERM0201
2.2UF20%
OMIT_TABLE
ROOM=B2B_TELE_CAM
33-OHM-25%-1500MA
0201
01005ROOM=B2B_TELE_CAM
15PF5%16VNP0-C0G-CERM
ROOM=B2B_TELE_CAM
6.3VX5R-CERM0201
2.2UF20%
OMIT_TABLE
ROOM=B2B_TELE_CAM
0201
33-OHM-25%-1500MA
C0G-CERM10V
01005
220PF5%
ROOM=B2B_TELE_CAM
10VC0G-CERM01005
220PF5%
ROOM=B2B_TELE_CAM
5%
C0G-CERM10V
01005ROOM=B2B_TELE_CAM
220PF
10
10
10
10
10
10
10
30
31 30
9
9
9
9
01005
0.1UF
ROOM=B2B_TELE_RCAMGND_VOID=TRUE
6.3VX5R-CERM
20%
01005
0.1UF
ROOM=B2B_TELE_RCAM GND_VOID=TRUE6.3V
X5R-CERM
20%
01005
0.1UF
ROOM=B2B_TELE_RCAM
6.3VX5R-CERM
20%
5%
01005NP0-C0G-CERM
56PF25V
ROOM=B2B_TELE_RCAM
01005
1/32WMF
0%
0.00
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
5%
01005NP0-C0G-CERM25V
56PF
5%
01005
25V
56PF
NP0-C0G-CERM
ROOM=B2B_TELE_RCAM
01005
0%
MF1/32W
ROOM=B2B_TELE_RCAM
0.00
01005
GND_VOID=TRUEROOM=B2B_TELE_RCAM
0.1UF
6.3VX5R-CERM
20%
01005
ROOM=B2B_TELE_RCAM
0.1UF
GND_VOID=TRUE6.3V
X5R-CERM
20%
01005
0.1UF
GND_VOID=TRUEROOM=B2B_TELE_RCAM
6.3VX5R-CERM
20%
01005
0.1UF
ROOM=B2B_TELE_RCAMGND_VOID=TRUE
6.3VX5R-CERM
20%
56PF5%
NP0-C0G-CERM25V
01005ROOM=B2B_TELE_RCAM
220PF
ROOM=B2B_TELE_RCAM
5%
01005C0G-CERM10V
01005
10V
ROOM=B2B_TELE_RCAM
5%
C0G-CERM
220PF
NOSTUFF
5%
ROOM=B2B_TELE_RCAM
10V
220PF
01005C0G-CERM
31
31
31
31
31
31
31 28
31 28
31
31
31 30 28
31
31
31
31
31
31 30 31 28
31 42 40 33
30 29 28 18 17 15 11 9 8 7 6
31
30 28
31
31
31
31
31
31
31
31
28
31 28
31
31
31
31
31
31
31
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
BI
IN
IN
BI
IN
NEON1APN:353S00558
LED STROBE DRIVERS (NEON)
#29230367: Change net names for Capella strobe module
NEON2APN:353S00868
I2C ADDRESS: 0x63
I2C ADDRESS: 0x67
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
INT 300K PD
32 OF 81
10.0.0
41 OF 80
051-02159
E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1D19D18D17D16D15D14D5D4D1C20C19C18C17C16C15C14
C7C6C5C4C3C2C1
B20B17B16
B7B6B5B4B3B2
A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2
D20
E20B1A1
M4100
D13B19B18
C13
D12
D11
C11
B15B14
B12B11
C12
B13
M4100
D3D2B8
C8
B9
B10
C10
D7D6
D10D9
C9
D8
M4100
2
1C41952
1C41972
1C4196
2
1C41902
1C41912
1C4192
I2C3_ISP_SDA_R
BB_TO_STROBE_DRIVER_GSM_BURST_IND
I2C3_ISP_SCL
STROBE_MODULE_NTC
PP_STROBE_DRIVER2_COOL_LED
PP_STROBE_DRIVER2_WARM_LED
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE
CAMPMU_TO_STROBE_DRIVER_HWEN
STROBE_MODULE_NTC
PP_STROBE_DRIVER1_WARM_LED
PP_STROBE_DRIVER1_COOL_LED
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE
I2C3_ISP_SDA_R
PP_VDD_MAIN
CAMPMU_TO_STROBE_DRIVER_HWEN
BB_TO_STROBE_DRIVER_GSM_BURST_IND
I2C3_ISP_SCL
PP_VDD_MAIN
CAMERA: Strobe DriversSYNC_DATE=04/14/2017SYNC_MASTER=sync
C0G-CERM01005
ROOM=STROBE
220PF5%10V
0402-0.1MMCERM-X5R
ROOM=STROBE2
10UF20%6.3V
ROOM=STROBE0402-0.1MMCERM-X5R
6.3V20%
10UF 10UF
ROOM=STROBE
CERM-X5R0402-0.1MM
20%6.3V
ROOM=STROBE
220PF
C0G-CERM
5%
01005
10V HUNT-ASIP
HUNT-ASIP
HUNT-ASIP
32 29
32 30
50 41 32
32 29
32 29 9
32 29 9
32 29
50 41 32
32 30
32 29
ROOM=STROBE20402-0.1MM
10UF
CERM-X5R
20%6.3V
34 32
34
34
34 32
34
34
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 3 OF 3
GND
GNDGNDGNDGND
GND
GNDGND
GNDGNDGND
GNDGNDGNDGND
GND
GNDGNDGND
GND
GND
GNDGNDGND
GNDGNDGND
GND
GND
GND
GND
GNDGND
GNDGND
GND
GND
2
GND
1
GND
2S
GND
1S
GNDGND
GNDGND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GNDGNDGNDGND
GND
GNDGND
GNDGND
GND
GND
GNDGND
GND
GND
GND
GNDGNDGND
GND
SYM 2 OF 3
LED1LED1
LED2LED2
NTC
VDDVDD
VDD
HWEN0
SDA2
GSM0
STB0
SCL2
SYM 1 OF 3
HWEN1
LED1
LED2
LED1
LED2
NTC
VDDVDD
VDD
GSM1
SDA1
STB1
SCL1
IN
IN
IN
BI
IN
IN
BI
IN
IN
IN
#28225348: Change FL4260 to low-DCR part
PROX + ALS + CONVOY POWER
MIC3
FOREHEAD CONNECTOR
CONVOY I/O
APN: 516S00146
FCAM I/O
#29487888
NORTH SPEAKER
FCAM POWER
#27431370
PROX + ALS I/O
#30299013:Change C4274 to 18pF to reduce FCAM coupling
R4287/R4288 to 100ohm to reduce Xtalk
#30299013:Stuff 100pF at C4287/C4288
33 OF 81
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
42 OF 80
051-02159
2
1 C4288
2
1 C4287
21
R4230
21
FL4260
21
FL4220
21
R4232
21
R4273
21
R4272
2
1 C4284
2
1 C4285
2
1 C4286
21
R4270
21
R4275
21
R4242
21
R4240
21
FL4200
2 1XW4200
2
1 C4273
2
1 C4272
2
1 C4242
2
1 C4240
21
R4236
21
R4234
2
1 C4236
2
1 C4234
363534333231302928272625242322212019181716151413121110987654321
42
41
4039
3837
J4200
21
R4288
21
R4287
2
1C42502
1 C4251
2
1C42612
1 C4262
2 1
FL4282
21
FL4281
21
FL4280
2
1 DZ4282
2
1 DZ4281
2
1 DZ4280
21
FL4271
2
1 C4271
2
1 C4270
21
FL4274
2
1 C4221
2
1 C4211
2
1 C4201
21
FL4210
2
1 C4232
2
1 C4230
2
1 C4220
2
1 C4200
2
1 C4210
2
1 C4275
21
FL4250
2
1 C4274
COIL_TO_SPKRAMP_TOP_VSENSE_CONN_P
ISP_TO_FCAM_SHUTDOWN_CONN_L
SPKRAMP_TOP_TO_COIL_OUT_NEG
I2C2_AP_BI_CONVOY_SDA_CONN
PDM_CONVOY_TO_SPKRAMP_TOP_DATA_CONN
COIL_TO_SPKRAMP_TOP_VSENSE_CONN_P
I2C0_AOP_TO_PROX_ALS_SCL_CONNPP_CODEC_TO_FRONTMIC3_BIAS_CONNFRONTMIC3_TO_CODEC_AIN3_CONN_P
FRONTMIC3_TO_CODEC_BIAS_FILT_RET
FRONTMIC3_TO_CODEC_AIN3_CONN_P
PP2V85_FCAM_AVDD_CONN
PP2V85_FCAM_AVDD PP2V85_FCAM_AVDD_CONN
I2C2_ISP_SDA I2C2_ISP_BI_FCAM_SDA_CONN
PP1V8_IO
I2C2_AP_SDA
I2C2_AP_SCL I2C2_AP_TO_CONVOY_SCL_CONN
I2C2_AP_BI_CONVOY_SDA_CONN
PDM_SPKRAMP_TOP_TO_CONVOY_CLK PDM_SPKRAMP_TOP_TO_CONVOY_CLK_CONN PP_CODEC_TO_FRONTMIC3_BIAS
FRONTMIC3_TO_CODEC_AIN3_P
90_MIPI_FCAM_TO_AP_DATA0_P90_MIPI_FCAM_TO_AP_DATA0_N
90_MIPI_FCAM_TO_AP_CLK_P90_MIPI_FCAM_TO_AP_CLK_N
I2C0_AOP_SCLPP_CODEC_TO_FRONTMIC3_BIAS_CONN
I2C0_AOP_SDA
PP1V1_FCAM_DVDD
PP3V0_CONVOY_CONN
PP1V1_FCAM_DVDD_CONN
PDM_CONVOY_TO_SPKRAMP_TOP_DATA PDM_CONVOY_TO_SPKRAMP_TOP_DATA_CONN
PP1V8_FCAM_IO_CONN
ISP_TO_FCAM_SHUTDOWN_CONN_L
AP_TO_FCAM_CLK_CONN
I2C2_ISP_BI_FCAM_SDA_CONN
90_MIPI_FCAM_TO_AP_DATA1_N90_MIPI_FCAM_TO_AP_DATA1_P
PP1V1_FCAM_DVDD_CONN
I2C2_AP_TO_CONVOY_SCL_CONN
COIL_TO_SPKRAMP_TOP_VSENSE_CONN_N
FRONTMIC3_TO_CODEC_AIN3_CONN_N
PP3V0_CONVOY_CONN
ALS_TO_AOP_INT_CONN_LSPKRAMP_TOP_TO_COIL_OUT_POS
I2C0_AOP_BI_PROX_ALS_SDA_CONN
I2C2_ISP_TO_FCAM_SCL_CONN
FRONTMIC3_TO_CODEC_AIN3_N FRONTMIC3_TO_CODEC_AIN3_CONN_N
PP3V0_PROX_ALS_CONN
PP1V8_FCAM_IO_CONN
PP3V0_CONVOY
PP3V0_S2
I2C0_AOP_BI_PROX_ALS_SDA_CONN
I2C0_AOP_TO_PROX_ALS_SCL_CONN
AP_TO_FCAM_CLK_CONN
PP3V0_PROX_ALS_CONN
I2C2_ISP_SCL
ISP_TO_FCAM_SHUTDOWN_L
AP_TO_FCAM_CLK
I2C2_ISP_TO_FCAM_SCL_CONN
ALS_TO_AOP_INT_L ALS_TO_AOP_INT_CONN_L
PROX_BI_AOP_INT_L_PWM
SPKRAMP_TOP_TO_COIL_OUT_POS
PROX_BI_AOP_INT_PWM_CONN_L
PDM_SPKRAMP_TOP_TO_CONVOY_CLK_CONN
SPKRAMP_TOP_TO_COIL_OUT_NEG
COIL_TO_SPKRAMP_TOP_VSENSE_P
PROX_BI_AOP_INT_PWM_CONN_L
COIL_TO_SPKRAMP_TOP_VSENSE_CONN_NCOIL_TO_SPKRAMP_TOP_VSENSE_N
SYNC_MASTER=sync SYNC_DATE=04/14/2017
CAMERA: FCAM + FOREHEAD
01005ROOM=B2B_FOREHEAD
NP0-C0G16V5%100PF
01005
5%16V
100PF
NP0-C0G
ROOM=B2B_FOREHEAD
0%
ROOM=B2B_FOREHEAD
MF01005
0.00
1/32W
10-OHM-750MA
01005-1ROOM=B2B_FOREHEAD
10-OHM-750MA
01005-1ROOM=B2B_FOREHEAD
0.00
01005MF
ROOM=B2B_FOREHEAD
0%1/32W
0.00
1/32W
01005ROOM=B2B_FOREHEAD
0%
MF
0%
ROOM=B2B_FOREHEAD
MF01005
1/32W
0.00
220PF
ROOM=B2B_FOREHEAD
C0G-CERM01005
10V5%
5%
01005
10V
220PF
ROOM=B2B_FOREHEAD
C0G-CERM
220PF
ROOM=B2B_FOREHEAD01005C0G-CERM10V5%
01005MF
1/32W
ROOM=B2B_FOREHEAD
100
5%
0%
01005
0.00
1/32WMF
ROOM=B2B_FOREHEAD
01005
1/32WMF
0%
ROOM=B2B_FOREHEAD
0.00
MF
ROOM=B2B_FOREHEAD01005
1/32W0%
0.00
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_FOREHEAD
ROOM=B2B_FOREHEADSHORT-20L-0.05MM-SM
OMIT
01005
5%56PF
NP0-C0G-CERM25V
ROOM=B2B_FOREHEAD
25VNP0-C0G-CERM01005ROOM=B2B_FOREHEAD
5%56PF
NP0-C0G-CERM
56PF5%
01005
25V
ROOM=B2B_FOREHEAD
01005
25V
56PF5%
ROOM=B2B_FOREHEAD
NP0-C0G-CERM
01005MF
ROOM=B2B_FOREHEAD
0.00
0%1/32W
01005ROOM=B2B_FOREHEAD
0.00
1/32W0%
MF
56PF5%
ROOM=B2B_FOREHEAD
NP0-C0G-CERM25V
01005
ROOM=B2B_FOREHEAD01005NP0-C0G-CERM
5%25V
56PF
245858036201829
ROOM=B2B_FOREHEAD
CRITICAL
F-ST-SM
1/32WMF
100
5%
ROOM=B2B_FOREHEAD01005
01005MF
1/32W5%
ROOM=B2B_FOREHEAD
100
ROOM=B2B_FOREHEAD0201
6.3V20%
2.2UF
OMIT_TABLE
X5R-CERM10V5%220PF
01005C0G-CERM
ROOM=B2B_FOREHEAD
2.2UF20%
6.3VX5R-CERM
0201
OMIT_TABLEROOM=B2B_FOREHEAD
5%
ROOM=B2B_FOREHEAD
220PF10VC0G-CERM01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_FOREHEAD01005
01005ROOM=B2B_FOREHEAD
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_FOREHEAD
150OHM-25%-200MA-0.7DCR
ROOM=B2B_FOREHEAD01005
NO_XNET_CONNECTION=1
6.8V-100PF
ROOM=B2B_FOREHEAD01005
NO_XNET_CONNECTION=1
6.8V-100PF
6.8V-100PFROOM=B2B_FOREHEAD01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_FOREHEAD01005
01005
5%25V
56PF
NP0-C0G-CERM
ROOM=B2B_FOREHEAD
25VNP0-C0G-CERM01005ROOM=B2B_FOREHEAD
5%56PF
150OHM-25%-200MA-0.7DCR
ROOM=B2B_FOREHEAD01005
5%
C0G-CERM10V
220PF
01005ROOM=B2B_FOREHEAD
10V
220PF
ROOM=B2B_FOREHEAD
5%
01005C0G-CERM
5%220PF
01005C0G-CERM10V
ROOM=B2B_FOREHEAD
33-OHM-25%-1500MA
ROOM=B2B_FOREHEAD0201
220PF
C0G-CERM01005
5%10V
ROOM=B2B_FOREHEAD
01005
5%
NP0-C0G-CERM
ROOM=B2B_FOREHEAD
56PF25V
0.1UF20%6.3VX5R-CERM01005
ROOM=B2B_FOREHEAD
01005ROOM=B2B_FOREHEAD
6.3V20%0.1UF
X5R-CERM
ROOM=B2B_FOREHEAD01005X5R-CERM6.3V
0.1UF20%
56PF
01005
5%
NP0-C0G-CERM25V
ROOM=B2B_FOREHEAD
ROOM=B2B_FOREHEAD
150OHM-25%-200MA-0.7DCR
01005
ROOM=B2B_FOREHEAD
18PF
CERM16V
01005
5%
33
33
38
33 27
33
33
33
33
33
33
36
33
33
28 33
9 33
42 40 31
30 29 28 18 17 15 11 9 8 7 6
38 11
38 11 33
33
38 33 36
35
9
9
9
9
13 33
13
28
33
33
38
33
33
33
33
9
9
33
33
33
33
33
33
38 33 27
33
33
35 33
33
33
20
50 48 47 46 44 20 5
33
33
33
33
9
9
9
33
13 33
13
38 33 27
33
33
38 33 27
38
33
33 38
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
BUTTON
MIC2 (ANC REF)
HAWKING
Strobe Filtering
Strobe Connector
34 OF 81
CKPLUS_WAIVE=MISS_N_DIFFPAIR
GND
10.0.0
43 OF 80
051-02159
21
R4311
2
1R4330
2
1 C4330
21
FL4330
21
R4313
21
R431221
R4310
2221
2019
1817
1615
1413121110987654321
J4300
21
XW4300
21
R4309
21
R4308
2
1C4326
2
1C4324
2
1C4322
2
1C4320
2 1
FL4307
2 1
FL4306
21
FL4303
2 1
FL4305
2
1 C43032
1 C4304
2
1 C4307
2
1 C4306
2
1 C4305
21
C4301
21
C4300
21
FL4301
2
1 C4302
2
1 C4309
2
1 C4308
2
1C4313
2
1C4312
2
1C4311
2
1C4310
2
1 DZ4313
2
1 DZ4312
2
1
DZ4311
2
1
DZ4310
I2C1_AP_TO_MIC2_SCL
I2C1_AP_BI_MIC2_SDA
PP_STROBE_DRIVER1_WARM_LED
BUTTON_VOL_DOWN_CONN_L BUTTON_POWER_KEY_L
PP1V8_HAWKING
CHASSIS_GND_BS401
CHASSIS_GND_BS401
PP_CODEC_TO_REARMIC2_BIAS
REARMIC2_TO_CODEC_AIN2_P
REARMIC2_TO_CODEC_AIN2_N I2C1_AP_SDA
HAWKING_TO_CODEC_AIN5_C_P
CHASSIS_GND_BS401
BUTTON_POWER_KEY_CONN_L
CHASSIS_GND_BS401
BUTTON_VOL_UP_CONN_L
BUTTON_VOL_DOWN_L
HAWKING_TO_CODEC_AIN5_N HAWKING_TO_CODEC_AIN5_N_CONN
HAWKING_TO_CODEC_AIN5_P
BUTTON_VOL_UP_L
HAWKING_TO_CODEC_AIN5_P_CONN
HAWKING_TO_CODEC_AIN5_N_CONN
HAWKING_TO_CODEC_AIN5_P_CONN
BUTTON_VOL_DOWN_CONN_L
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER2_WARM_LED
BUTTON_VOL_UP_CONN_LBUTTON_RINGER_A_CONN
BUTTON_POWER_KEY_CONN_L
PP_STROBE_DRIVER2_COOL_LED
PP1V8_HAWKING_CONNSTROBE_MODULE_NTC_CONN
STROBE_MODULE_NTC STROBE_MODULE_NTC_CONN
PP_STROBE_DRIVER2_COOL_LED
I2C1_AP_SCL
BUTTON_RINGER_A BUTTON_RINGER_A_CONN
I2C1_AP_TO_MIC2_SCLPP_CODEC_TO_REARMIC2_BIAS_CONN
PP_STROBE_DRIVER2_WARM_LED
PP_STROBE_DRIVER1_COOL_LED
PP_STROBE_DRIVER1_WARM_LED
REARMIC2_TO_CODEC_BIAS_FILT_RETREARMIC2_TO_CODEC_AIN2_CONN_N
I2C1_AP_BI_MIC2_SDA
REARMIC2_TO_CODEC_AIN2_CONN_P
REARMIC2_TO_CODEC_AIN2_CONN_P
REARMIC2_TO_CODEC_AIN2_CONN_N
PP_CODEC_TO_REARMIC2_BIAS_CONN
PP1V8_HAWKING_CONN
MAKE_BASE=TRUE
CAMERA: B2B Strobe + ButtonsSYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=B2B_STROBE
AA37D-S014VA1F-ST-SM
ROOM=B2B_STROBEOMIT
SHORT-20L-0.05MM-SM
01005MF
1/32W
0.00
0%
ROOM=B2B_STROBE
01005
0.00
1/32WMF
ROOM=B2B_STROBE
0%
12V-33PFROOM=B2B_BUTTON01005-1
01005ROOM=B2B_STROBE
10VC0G-CERM
220PF5%
01005ROOM=B2B_STROBE
10VC0G-CERM
5%220PF
01005ROOM=B2B_STROBE
10VC0G-CERM
5%220PF
01005C0G-CERM
ROOM=B2B_STROBE
10V5%
220PF
ROOM=B2B_BUTTON
12V-33PF01005-1
35
35
35
35
01005
ROOM=B2B_STROBE
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_STROBE
150OHM-25%-200MA-0.7DCR
0201ROOM=B2B_BUTTON
5.5V-6.2PF
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_STROBE
01005ROOM=B2B_STROBE
150OHM-25%-200MA-0.7DCR
20%6.3V
ROOM=B2B_STROBEOMIT_TABLE
X5R-CERM0201
2.2UF
01005C0G-CERM
220PF5%10V
ROOM=B2B_STROBE
01005ROOM=B2B_STROBE
56PF25VNP0-C0G-CERM
5%
01005ROOM=B2B_STROBE
NP0-C0G-CERM25V
56PF5%
01005C0G-CERM10V5%220PF
ROOM=B2B_STROBE
20%
0.22UF
01005-1X5R6.3V
ROOM=B2B_STROBE
20%
0.22UF
01005-1X5R6.3V
ROOM=B2B_STROBE
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_STROBE
02015.5V-6.2PFROOM=B2B_BUTTON
01005NP0-C0G-CERM
ROOM=B2B_STROBE
5%25V
56PF
48 11
48 11
01005ROOM=B2B_STROBE
NP0-C0G-CERM
56PF25V5%
01005NP0-C0G-CERM25V56PF5%
ROOM=B2B_STROBE
01005C0G-CERM
ROOM=B2B_BUTTON
220PF5%
10V
01005
10V
220PF5%
C0G-CERM
ROOM=B2B_BUTTON
6.3V5%
ROOM=B2B_BUTTON0201
NP0-C0G
27PF
6.3V5%
NP0-C0G
27PF
0201ROOM=B2B_BUTTON
01005
5%
MF
100
ROOM=B2B_BUTTON
1/32W
01005
1/32W0.5%27K
ROOM=B2B_STROBE
MF01005
ROOM=B2B_STROBE
10VC0G-CERM
220PF5%
01005
ROOM=B2B_STROBE
150OHM-25%-200MA-0.7DCR01005
ROOM=B2B_BUTTON
MF
100
5%1/32W
01005
100
ROOM=B2B_BUTTON
MF1/32W5%
01005
5%
MF
100
ROOM=B2B_BUTTON
1/32W
34
34
34 32
34 21
28
34 4
34 4
36
34 4
34
34 4
34
21
34
21
34
34
34
34
34 32
34 32
34
34
34
34
34
32 34
34 32
21 34
34
34
34 32
34 32
34 32
36
34
34
34
34
34
34
34
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
IN
IN
CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS)
#27799524: Use 100pF
35 OF 81
10.0.0
47 OF 80
051-02159
2
1R4710
F9F10
B9A10
B10B11
G1
E1F1
F8E9
D9D10
E10E11
D8B8
K8L8
C2D3
F4E3
F3G4
G3G2
K5L5
K6L6
K4L4
K3L3
U4700
21
C4701
21
R4701
21
R4700
21
C4700
FRONTMIC3_TO_CODEC_AIN3_P
LOWERMIC1_TO_CODEC_AIN1_PLOWERMIC1_TO_CODEC_AIN1_N
REARMIC2_TO_CODEC_AIN2_PREARMIC2_TO_CODEC_AIN2_N
FRONTMIC3_TO_CODEC_AIN3_N
LOWERMIC4_TO_CODEC_AIN4_P
HAWKING_TO_CODEC_AIN5_PHAWKING_TO_CODEC_AIN5_N
PDM_CODEC_TO_SPKRAMP_TOP_CLK
PDM_CODEC_TO_ARC_CLKPDM_CODEC_TO_ARC_DATA
LOWERMIC4_TO_CODEC_AIN4_N
90_MIKEYBUS_CODEC_DATA_P90_MIKEYBUS_CODEC_DATA_N
MIKEYBUS_REFERENCE
90_MIKEYBUS_DATA_P
90_MIKEYBUS_DATA_N
PDM_CODEC_TO_SPKRAMP_TOP_DATA
AUDIO: CODEC (1/2)SYNC_DATE=04/14/2017SYNC_MASTER=sync
16V5%
100PF
01005ROOM=CODEC
NP0-C0G
MF1/32W
20.0
5%
01005ROOM=CODEC
ROOM=CODEC
MF1/32W
20.0
01005
5%
100PF
5%16V
NP0-C0G
ROOM=CODEC01005
34
34
39
39
48 47
47
38
38
33
33
34
34
48
48
48
48
01005ROOM=CODEC
5%1/32WMF
100
ROOM=CODEC
WLCSP
CRITICAL
CS42L75
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
NCNC
NCNC
IN
IN
OUT
OUT
NCNC
INBI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
NCNC
NCNC
SYM 1 OF 3
AOUT-AOUT+
AIN3+
MBUS_REF
DNDP
AIN1+AIN1-
AIN2+AIN2-
AIN3-
AIN4+
AIN5+AIN5-
AIN6+AIN6-
AIN7+AIN7-
AIN8+AIN8-
DMIC1_CLKDMIC1_DATA
DMIC3_DATA
DMIC2_CLK
DMIC3_CLK
DMIC2_DATA
DMIC4_CLKDMIC4_DATA
PDMOUT1_CLKPDMOUT1_DATA
PDMOUT2_CLKPDMOUT2_DATA
PDMOUT3_CLKPDMOUT3_DATA
AIN4-
NCNC
NCNC
NCNC
#29527815: Series R on ASP1 BCLK, LRCLK#30638490: Route U1000/U5000 ASP1 BCLK, LRCLK with _R
CALLAN AUDIO CODEC (POWER & I/O)
#28287605: [P2] Add PU and connect to AOP
36 OF 81
VOLTAGE=2.86V
VOLTAGE=2.86V
VOLTAGE=2.86V
VOLTAGE=2.86V
10.0.0
48 OF 80
051-02159
2
1 C4820
21
R4801
21
R4830
21
R4802
2
1R4800
2
1 C4808
2
1 C4822
2
1 C48232
1 C4824
2
1 C4825
2 1
XW4802
2
1 C4821
H3
J5J3G10
B2B3
C3A3
J4
C8B7
A5B4A4
E7
F7E8D7
D4
E5E6
E4J8J7J6H7H6H2H1G7G6G5F5H4
H5
C7
F6
A7
D11C10
C11C9
C5D6
C4D5
B6B5
A6C6
U4700
F2L9A2 A9G11
B1C1 K2J2J1
G9G8
H10H11
H8H9
J9K9
J10J11
K10K11
D1D2
L11
L10L7L1K7F11E2A11A8A1
K1L2
U4700
2
1 C4805
2
1 C4809
2
1 C48122
1 C4814
2
1 C4817
21
C4802
2
1 C48152
1 C48132
1 C4811
21
C4801
21
C4804
21
C4803
CODEC_AGND
AOP_TO_CODEC_CLP_EN
CODEC_TO_AOP_GPIO2CODEC_TO_AOP_GPIO1
CODEC_FILTP
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_RI2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP2_TO_AOP_DIN
I2S_AP_TO_CODEC_ASP3_DOUTI2S_CODEC_ASP3_TO_AP_DIN
I2S_AP_TO_CODEC_ASP3_LRCLKI2S_AP_TO_CODEC_ASP3_BCLK
I2S_AOP_TO_CODEC_ASP2_DOUTI2S_AOP_TO_CODEC_ASP2_LRCLKI2S_AOP_TO_CODEC_ASP2_BCLK
AOP_TO_CODEC_RESET_L
CODEC_TO_PMU_WAKE_L
CODEC_TO_AP_INT_L
SPI_CODEC_TO_AP_MISO
CODEC_TO_SPKRAMP_BOT_ARC_MCLK_RI2S_AOP_TO_CODEC_MCLK2
SPI_AP_TO_CODEC_SCLKSPI_AP_TO_CODEC_CS_L
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
PP1V8_S2
PP_VDD_BOOST
CODEC_LP_FILTP
LOWERMIC1_TO_CODEC_BIAS_FILT_RET
REARMIC2_TO_CODEC_BIAS_FILT_RET
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
CODEC_TO_SPKRAMP_BOT_ARC_MCLK CODEC_TO_SPKRAMP_BOT_ARC_MCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_AP_TO_CODEC_MCLK1
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
SPI_AP_TO_CODEC_MOSI
PP1V2_CODEC_S2
FRONTMIC3_TO_CODEC_BIAS_FILT_RET
LOWERMIC4_TO_CODEC_BIAS_FILT_RET
CODEC_AGND
PP1V8_AUDIO_VA_S2
PP1V8_S2
LOWERMIC1_BIAS_FILT_IN
REARMIC2_BIAS_FILT_IN
PP_CODEC_TO_FRONTMIC3_BIAS
PP_CODEC_TO_REARMIC2_BIAS
FRONTMIC3_BIAS_FILT_IN
PP_CODEC_TO_LOWERMIC1_BIAS
PP_CODEC_TO_LOWERMIC4_BIASLOWERMIC4_BIAS_FILT_IN
CODEC_LP_FILTN
AUDIO: CODEC (2/2)SYNC_DATE=04/14/2017SYNC_MASTER=sync
OMIT_TABLEROOM=CODEC
2.2UF20%
0201
6.3VX5R-CERM
OMIT_TABLE
0201
2.2UF
ROOM=CODEC
X5R-CERM6.3V20%
ROOM=CODEC
0.1UF20%
01005
6.3VX5R-CERM
ROOM=CODEC
X5R-CERM
0.1UF6.3V
01005
20%
1.0UF
ROOM=CODEC0201-1X5R6.3V20%
20%
4.7UF
X5R-CERM16.3V
402ROOM=CODEC
ROOM=CODEC
X5R-CERM20%
01005
6.3V0.1UF
ROOM=CODEC
0.1UF
X5R-CERM6.3V20%
01005ROOM=CODEC0402-0.1MMCERM6.3V20%15UF
4.7UF
6.3VX5R-CERM1
402ROOM=CODEC
20%
ROOM=CODEC
4.7UF
20%6.3V
402X5R-CERM1
X5R-CERM1
4.7UF
20%
ROOM=CODEC
6.3V
402
ROOM=CODEC
20%0.1UF
01005X5R-CERM6.3V
38 36 13
38 36 13 5
36
38 36 13
38 36 13 5
36
48 39 37
48 39 37
ROOM=CODEC
20.0
010055%
1/32WMF
39 37
ROOM=CODEC
1%01005MF
1/32W
33.2
01005
20.0
ROOM=CODEC
MF1/32W5%
ROOM=CODEC
1/32W5%
MF01005
100K
13
ROOM=CODEC0402-0.1MM
6.3V
10UF
CERM-X5R
20%
13
13
39 38 37 13
48 39 13
13
13
11
11
13
13
13
13
11
11
11
11
21
11
11
11
11
48
33
34
48
ROOM=CODEC
20%6.3V1.0UF
X5R0201-1
ROOM=CODEC
1.0UF
X5R20%
0201-1
6.3V
ROOM=CODEC
X5R0201-1
6.3V20%1.0UF
ROOM=CODEC
1.0UF6.3V20%
0201-1X5R
ROOM=CODEC
SHORT-10L-0.1MM-SM
1.0UF
X5R6.3V20%
0201-1ROOM=CODEC
CRITICALROOM=CODEC
CS42L75WLCSP
CRITICAL
WLCSPCS42L75
ROOM=CODEC
36
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
50 43 41 28 22 20
20
36
39 38 37 20
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
33
34
48
48
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
IN
OUT
IN
IN
OUT
NCNC
NCNC
OUT
OUT
IN
IN
IN
IN
OUT
IN
NCNC
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
NCNC
SYM 3 OF 3
GNDAGNDAGNDA
TSTITSTI
GNDAGNDA
GNDAGNDA
GNDAGNDA
GNDA
GNDAGNDA
RESET*
ASP2_SDOUT
ASP3_SDOUT
GPIO2GPIO1
JTAG_TDIJTAG_TDO
CLP_EN
SW2_CLKSW2_SD
SW1_SDSW1_CLK
DIGLDO_PULLDNDIGLDO_EN
ASP3_SDIN
ASP3_SCLK
CCLKCS*
INT*
WAKE*
JTAG_TCKJTAG_TMS
ASP3_LRCK/FSYNC
ASP2_SDINASP2_LRCK/FSYNCASP2_SCLK
ASP1_SDOUT
ASP1_LRCK/FSYNCASP1_SDIN
MCLK_OUT
ASP1_SCLK
MOSI
TSTIMCLK2_IN
MISO
MCLK1_IN
SYM 2 OF 3
FILT-FILT+
LP_FILT-LP_FILT+
VP_M
BUSVAVAVAVP
VD_F
ILT
VD_F
ILT VLVD
VL_S
W
MIC2_BIAS
MIC1_BIAS_FILT
GNDD
MIC2_BIAS_FILT
MIC5_BIASMIC5_BIAS_FILT
MIC4_BIASMIC4_BIAS_FILT
MIC6_BIAS_FILTMIC6_BIAS
MIC3_BIASMIC3_BIAS_FILT
MIC1_BIAS
GNDP
NCNCNCNC
#29343419: Change C4910 to ceramic part
APN:152S00652/152S00654 (1.2UH-20%-3A-0.077OHM)
Inductor in SIP
I2C ADDRESS: 1000 000x0x80
South Speaker AmplifierAPN: 338S00143
#31657976: Change C4922/C4934 to 220PF Based on DOE
37 OF 81
VOLTAGE=8.0V
VOLTAGE=8.0VVOLTAGE=8.0V
10.0.0
49 OF 80
051-02159
P4N4M4
P2N2M2
M5500
2
1 C49102
1 C49312
1 C4904
2
1 C4929
E2E3
A5
B1A1
D1C1
F5
B2A2
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2C2
B7
C6
F1E1
A7
D4D3C5C4C3B4B3A4A3 F2E4B5
F4
F6
F3
E5
U4900
2
1 C4930
2
1C49072
1C49052
1C49092
1C4914
2
1 C4927
2
1 C49252
1 C4926
2
1 C49282
1 C4903
2
1C49222
1 C4934
PP1V8_AUDIO_VA_S2
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
PP_SPKRAMP_BOT_VBOOST
SPKRAMP_BOT_ISENSE_P
COIL_TO_SPKRAMP_BOT_VSENSE_P
PP_VDD_MAIN
SPKRAMP_BOT_ARC_TO_AOP_INT_L
I2C1_AOP_SDA
SPKRAMP_BOT_ISENSE_N
COIL_TO_SPKRAMP_BOT_VSENSE_N
SPKRAMP_BOT_FILT
CODEC_TO_SPKRAMP_BOT_ARC_MCLK
SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC
AOP_TO_SPKRAMP_BOT_ARC_RESET_L
I2C1_AOP_SCL
SPKRAMP_BOT_LX
SPKRAMP_BOT_TO_COIL_OUT_NEGSPKRAMP_BOT_TO_COIL_OUT_POS
AUDIO: Speaker Amp BottomSYNC_DATE=04/14/2017SYNC_MASTER=sync
SIPNIKI-A
17UF
1206X5R
20%16V
ROOM=SPKAMP1
CRITICAL
X5R-CERM10V20%10UF
0402-0.1MMROOM=SPKAMP1OMIT_TABLE
0402-0.1MMROOM=SPKAMP1
10VX5R-CERM
10UF20%
OMIT_TABLE
5%220PF
C0G-CERM10V
ROOM=SPKAMP101005
48
48
39 38 36 13
48 39 36
48 39 36
39 36
38
39 13
C0G-CERM
ROOM=SPKAMP1
220PF5%10V
01005
39 13
43 39 13
43 39 13
2.2UF
ROOM=SPKAMP1OMIT_TABLE
6.3V20%
X5R-CERM0201
ROOM=SPKAMP1
CS35L26B-A1
CRITICAL
WLCSP
NO_XNET_CONNECTIONROOM=SPKAMP1X5R01005
10%6.3V
0.01UF
X5R-CERM10V
10UF
0402-0.1MM
20%
OMIT_TABLEROOM=SPKAMP1
6.3V
ROOM=SPKAMP1
CERM
15UF20%
0402-0.1MM
20%
ROOM=SPKAMP1
6.3VCERM
0402-0.1MM
15UF 2.2UF
0201
20%6.3V
X5R-CERM
ROOM=SPKAMP1OMIT_TABLE
220PF5%
01005
10VC0G-CERM
ROOM=SPKAMP1
01005
0.1UF
X5R-CERM6.3V20%
ROOM=SPKAMP1
6.3V
0201
20%2.2UF
X5R-CERM
ROOM=SPKAMP1OMIT_TABLE
0.1UF
X5R-CERM
10%16V
0201ROOM=SPKAMP1
OMIT_TABLE
ROOM=SPKAMP10402-0.1MMX5R-CERM
10UF10V20%
39 38 36 20 50 48 47 45 44 42 41 40
39 38 32 28 25 24 22 20 19 5
48
48
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 2 OF 6SPKSPKSPK
VDD_SVDD_SVDD_S
NC
NC
IN
IN
BI
IN
IN
IN
BI
IN
BI
IN
BI
VP
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SWSW
FILT+
GNDP GNDA
ISNS+ISNS-
VSNS+VSNS-
OUT+OUT-
VBST_A
VBST_BVBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1 AD1
INT*
RESET*
North Speaker Amplifier
Pull Downs
#30638490: Route U1000/U5000 ASP1 BCLK, LRCLK with _R
APN: 338S00295
I2C ADDRESS: 1000 000x (0x80)
38 OF 81
VOLTAGE=8.0VVOLTAGE=8.0V
VOLTAGE=8.0V
10.0.0
50 OF 80
051-02159
2
1C50262
1C50292
1C50282
1C5027
21
L5000
2
1 C5018
E2E3
A5
B1A1
D1C1
F5
B2A2
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2C2
B7
C6
F1E1
A7
D4D3C5C4C3B4B3A4A3 F2E4B5
F4
F6
F3
E5
U5000
2
1R5004
2
1R5001
2
1 C5019
2
1C50002
1 C5001
2
1 C50112
1 C50122
1 C50242
1 C50252
1 C50062
1 C5008
2
1 C50162
1 C5015
SPKRAMP_TOP_TO_COIL_OUT_NEG
COIL_TO_SPKRAMP_TOP_VSENSE_N
SPKRAMP_TOP_ISENSE_PSPKRAMP_TOP_ISENSE_N
SPKRAMP_TOP_FILT
COIL_TO_SPKRAMP_TOP_VSENSE_P
SPKRAMP_TOP_TO_COIL_OUT_POS
PP1V8_AUDIO_VA_S2
PP_SPKRAMP_TOP_VBOOST
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
PDM_CONVOY_TO_SPKRAMP_TOP_DATA
SPKRAMP_TOP_TO_AP_INT_L
PDM_SPKRAMP_TOP_TO_CONVOY_CLK
PDM_SPKRAMP_TOP_TO_CONVOY_CLKAP_TO_SPKRAMP_TOP_RESET_L
AP_TO_SPKRAMP_TOP_RESET_L
SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC
PDM_CODEC_TO_SPKRAMP_TOP_CLK
PDM_CODEC_TO_SPKRAMP_TOP_DATA
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_AP_TO_SPKRAMP_TOP_MCLK
SPKRAMP_TOP_LX
I2C2_AP_SDA
I2C2_AP_SCL
PP_VDD_MAIN
AUDIO: Speaker Amp TopSYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=SPKAMP20402-0.1MM-1
20%6.3V
15UF
X5R
ROOM=SPKAMP2OMIT_TABLE
0201
6.3V20%
X5R-CERM
2.2UFX5R
6.3V
ROOM=SPKAMP20402-0.1MM-1
15UF20%
15UF
ROOM=SPKAMP20402-0.1MM-1
6.3VX5R
20%
35
MEHK2016T-SM
1.2UH-20%-3A-0.077OHM
ROOM=SPKAMP2
38 33
35
33
33
33
38 12
36 13
36 13 5
39 37 36 13
12
33 11
33 11
11
37
ROOM=SPKAMP2OMIT_TABLE
2.2UF
X5R-CERM6.3V
0201
20%
WLCSP
CS35L26B-A1
ROOM=SPKAMP2
CRITICAL
ROOM=SPKAMP201005MF
100K1/32W5%
ROOM=SPKAMP2
1/32W
100K
01005MF
5%
ROOM=SPKAMP2
6.3V
01005
10%
X5R
NO_XNET_CONNECTION
0.01UF
ROOM=SPKAMP2
X5R10V10%
470PF
01005ROOM=SPKAMP2
10V10%470PF
X5R01005
0.1UF10%16VX5R-CERM
ROOM=SPKAMP20201
ROOM=SPKAMP2
5%220PF
01005
10VC0G-CERM
20%
X5R-CERM
10UF
ROOM=SPKAMP20402-0.1MM
10V20%
X5R-CERM
ROOM=SPKAMP2
10UF10V
0402-0.1MMX5R-CERM0402-0.1MMROOM=SPKAMP2
20%10UF10V
20%
X5R-CERM
10UF10V
ROOM=SPKAMP20402-0.1MM
OMIT_TABLEROOM=SPKAMP2
20%6.3VX5R-CERM
2.2UF
0201ROOM=SPKAMP2
0.1UF20%
X5R-CERM6.3V
01005
33 27
33 27
39 37 36 20
38 33
38 12
50 48 47 45 44 42 41 40 39 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
OUT
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
BI
IN
BI
VP
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SWSW
FILT+
GNDP GNDA
ISNS+ISNS-
VSNS+VSNS-
OUT+OUT-
VBST_A
VBST_BVBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1 AD1
INT*
RESET*
#28947109: Arc TDM support
ARC DRIVER
Pull Downs
I2C ADDRESS: 1000 001x (0x82)APN: 338S00295
39 OF 81
VOLTAGE=8.0V
VOLTAGE=8.0V
PP1V8_AUDIO_VA_S2
VOLTAGE=8.0V
10.0.0
51 OF 80
051-02159
21
L5100
2
1 C5136
E2E3
A5
B1A1
D1C1
F5
B2A2
B6
D7
D6
C7
E6
A6
D5
E7
F7
D2C2
B7
C6
F1E1
A7
D4D3C5C4C3B4B3A4A3 F2E4B5
F4
F6
F3
E5
U5100
2
1 C5128
2
1R5108
2
1C51302
1C51312
1C5125
2
1 C5126
2
1 C51272
1 C5134
2
1 C5135
2
1 C51372
1 C51242
1 C5138
2
1C51292
1 C5142
2
1 C5139
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
ARC1_ISENSE_N
ARC1_FILT
ARC1_TO_SOLENOID1_OUT_NEGARC1_TO_SOLENOID1_OUT_POS
CODEC_TO_SPKRAMP_BOT_ARC_MCLK
PDM_CODEC_TO_ARC_DATA
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
PDM_CODEC_TO_ARC_CLK
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
PP1V8_AUDIO_VA_S2
I2C1_AOP_SDA
PP1V8_AUDIO_VA_S2MAKE_BASE=TRUE
I2C1_AOP_SCL
AOP_TO_SPKRAMP_BOT_ARC_RESET_LAOP_TO_SPKRAMP_BOT_ARC_RESET_L
ARC1_ISENSE_P
PP_ARC1_VBOOST
SOLENOID1_TO_ARC1_VSENSE_PSOLENOID1_TO_ARC1_VSENSE_N
ARC1_LX
SPKRAMP_BOT_ARC_TO_AOP_INT_L
PP_VDD_MAIN
ARC: DriverSYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=ARC_CTRL01005
470PF
X5R10V10%
48 36 13
1.2UH-20%-3A-0.11OHM
MEFE2016T-SM
ROOM=ARC_CTRL
35
35
38 37 36 13
48 37 36
48 37 36
37 36
39 37 13
48
48
37 13
43 37 13
43 37 13
OMIT_TABLEROOM=ARC_CTRL0201X5R-CERM6.3V
2.2UF20%
CRITICAL
WLCSP
ROOM=ARC_CTRL
CS35L26B-A1
20%10UF10VX5R-CERM0402-0.1MMROOM=ARC_CTRL
ROOM=ARC_CTRL
0.01UF
X5R
10%
01005
6.3V
NO_XNET_CONNECTIONROOM=ARC_CTRL
1/32W
100K
MF01005
5%
10V
0402-0.1MMX5R-CERM
10UF20%
ROOM=ARC_CTRLROOM=ARC_CTRL
6.3V
15UF20%
CERM0402-0.1MM
ROOM=ARC_CTRL
20%15UF
CERM6.3V
0402-0.1MM
220PF5%
ROOM=ARC_CTRL
C0G-CERM01005
10V
ROOM=ARC_CTRL
6.3VX5R-CERM
20%
01005
0.1UF
OMIT_TABLE
ROOM=ARC_CTRL
2.2UF
X5R-CERM0201
6.3V20%
10%
X5R-CERM
0.1UF
0201
16V
ROOM=ARC_CTRL
10UF
ROOM=ARC_CTRL0402-0.1MMX5R-CERM10V20%
ROOM=ARC_CTRL0402-0.1MMX5R-CERM10V
10UF20%
ROOM=ARC_CTRL0402-0.1MMX5R-CERM10V
10UF20%
ROOM=ARC_CTRL01005
470PF
X5R10V10%
48
48
39 38 37 36 20
39 38 37 36 20
39 37 13
50 48 47 45 44 42 41 40 38 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
NC
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
IN
BI
VP
PDM_CLK0
AD0/PDM_CLK1
VBST_A
SWSW
FILT+
GNDP GNDA
ISNS+ISNS-
VSNS+VSNS-
OUT+OUT-
VBST_A
VBST_BVBST_B
SDA
ALIVE/SYNC
MCLK
SCLK
LRCK/FSYNC
SDIN
SDOUT
SCL
VA
PDM_DATA0
PDM_DATA1 AD1
INT*
RESET*
APN:152S00683 (0.47UF-20%-7.2A-0.028OHM)
Note: inductors in SIP used for bottom speaker amplifier and backlightSee pages 49, and 56
Niki SIP
40 OF 81
CKPLUS_WAIVE=I2C_PULLUP
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
55 OF 80
051-02159
AE5AE4AE3AE2AE1AD4AD1AC4AC1AB7AB4AB1AA7AA4AA1Y7Y6Y5Y4Y1W7W4W1V7V4V1U7U4U1T7T4T1R7R5R4R3R2R1P7P5P3P1N7N5N3
N1M7M3M1L7L6L5L4L3L2L1K7K4K1J7J4J1H7H4H1G7G4G1F7F6F5F4F3F2F1E7E4E1D7D4D1C7C4B7B4A7A6
AE7
AD7
AE6
AC7
A5
B1A2 C1A1
A4A3 M5500
M6M5
N6R6P6
M5500
W6W5V6V5U6U5T6T5
AB6AB5AA6AA5AD6AD5AC6AC5
AD3AD2AC3AC2AB3AB2AA3AA2
Y3Y2W3W2V3V2U3U2T3T2
M5500
TIGRIS_LX
CHARGER_NTCCHARGER_NTC_RETURN
I2C4_AP_SDAPP1V8_IOI2C4_AP_SCL
TIGRIS_MID PP_VDD_MAIN
CG: NikiSYNC_DATE=04/14/2017SYNC_MASTER=sync
SIPNIKI-A
NIKI-ASIP
SIPNIKI-A
24
21
21
11
42 33 31 30 29 28 18 17 15 11 9 8 7 6
11
50 48 47 45 44 42 41 39 38 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 6 OF 6
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
2_SR
_TO
P_FR
C2G
ND2_
SR_T
OP_
SNS2
GND
2_SR
_TO
P_SN
S1G
ND2_
SR_T
OP_
FRC1
GND
1_SR
_TB_
FRC2
GND
1_SR
_TB_
SNS2
GND
1_SR
_TB_
SNS1
GND
1_SR
_TB_
FRC1
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GNDGNDGNDGND
GND
GNDGNDGNDGNDGND
GNDGNDGNDGNDGND
GNDGNDGNDGNDGND
GNDGNDGNDGNDGND
GNDGNDGNDGND
SYM 5 OF 6
SCLVDD_18SDA
NTC_RETNTC
SYM 1 OF 6
VDD_T
TIG_MID
TIGRIS_LX6TIGRIS_LX7
TIGRIS_LX3TIGRIS_LX4TIGRIS_LX5
TIGRIS_LX1TIGRIS_LX2
TIGRIS_LX0
TIG_MIDTIG_MIDTIG_MIDTIG_MIDTIG_MIDTIG_MID
VDD_TVDD_TVDD_T
TIG_MID VDD_T
VDD_T
VDD_TVDD_T
TIG_MID
TIG_MIDTIG_MIDTIG_MID
TIG_MIDTIG_MID
TIG_MIDTIG_MID
TIG_MIDTIG_MID
#28282573: Update C5606/C5607 to match D1xLED BACKLIGHT DRIVER
25V
APN:152S00248/152S00603 (12.5UH-15%-1.1A-0.66OHM)
APN:152S00248/152S00603 (12.5UH-15%-1.1A-0.66OHM)
6LED
4LED
25V
APN:353S00671MOJAVE MESA BOOST
25V
CHESTNUT DISPLAY PMU
APN:338S1172
200K INT PD
NO INT PULL
NO INT PULL
APN:353s00640
APN:353s00640
25V
41 OF 81
VOLTAGE=-6.0V
VOLTAGE=6.0V
VOLTAGE=16.0V
VOLTAGE=17.0V
VOLTAGE=5.1V
VOLTAGE=5.7V
10.0.0
56 OF 80
051-02159
E3E2D3D2C3C2B3B2
E6E5D6D5C6C5B6B5
M5500
K3K2J3J2H3H2G3G2
K6K5J6J5H6H5G6G5
M5500
21
L5651
2
1 C56062
1 C5607
21
R5600
21
L5661
2
1C5611
2
1C561021
L5610
C3A2
B1
C1
A1
C2
A3B2
B3
U5610
2
1 C5614
2
1 C5612
2
1 C5615
2
1 C5613
2
1C5696
D3
D1
A4A3
C4
C2
B2A2
C3
A1
B1C1
D2
D4
B4B3
U5660
A K
D5660
2
1 C5660
KA
D5661
2
1 C5661
2
1 C5662
2
1 C5663
2
1 C5664
2
1 C5665
2
1 C5655
2
1 C5654
2
1 C5653
2
1 C5652
2
1 C5651
2
1R5650
2
1C5690
2
1 C5650
KA
D5651
A K
D5650
2
1C5695
D3
D1
A4A3
C4
C2
B2A2
C3
A1
B1C1
D2
D4
B4B3
U5650
2
1 C5608
2
1
L5600
2
1 C56012
1 C56022
1 C56032
1 C5604
E2
E3
D1
A2
B2
D2
D3
C2
D4B1
B3
C3
A1
A3
A4
B4
E4C4
C1
E1
U5600
2
1 C5600
PN_CHESTNUT_CN
PP_CHESTNUT_CP
PP_VDD_MAIN
I2C0_AP_SCL
DISPLAY_TO_CHESTNUT_PWR_EN
I2C0_AP_SDA
I2C3_AP_SDA
PP_DISPLAY_BL34_CAT2PP_DISPLAY_BL34_CAT1I2C0_AP_SDA_CHESTNUT_R
PP1V8_S2
DWI_PMGR_TO_BACKLIGHT_DATADWI_PMGR_TO_BACKLIGHT_CLK
I2C0_AP_SCL
AP_TO_MUON_BL_STROBE_EN
BB_TO_STROBE_DRIVER_GSM_BURST_IND
PP16V0_MESA
PP17V0_MOJAVE_LDOIN
PP_VDD_MAIN
MESA_TO_BOOST_EN
CHESTNUT_TO_PMU_AMUX
PP_VDD_BOOST
POS18V0_MESA_LX
DWI_PMGR_TO_BACKLIGHT_CLKDWI_PMGR_TO_BACKLIGHT_DATA
BB_TO_STROBE_DRIVER_GSM_BURST_IND
AP_TO_MUON_BL_STROBE_EN
BL12_SW2_LX
PP_DISPLAY_BL12_CAT1
PP_DISPLAY_BL34_ANODE
PP6V0_DISPLAY_BOOST
CHESTNUT_LX
I2C0_AP_SDA_CHESTNUT_R
BL34_SW1_LX
BL12_SW1_LX
PP_VDD_MAIN
BL34_SW2_LX
PP_DISPLAY_BL12_CAT2I2C3_AP_SCL
PP1V8_S2
PP_VDD_MAIN PP_DISPLAY_BL12_ANODE
PMU_TO_AP_HYDRA_ACTIVE_READY
PP5V1_TOUCH_VDDH
PP5V7_DISPLAY_AVDDH
PP5V7_MESON_AVDDH
PN5V7_DISPLAY_MESON_AVDDN
CG: PMUs
SYNC_DATE=04/14/2017SYNC_MASTER=sync
10V
10UF20%
X5R-CERM0402-0.1MM
OMIT_TABLEROOM=CHESTNUT
SIPNIKI-A
SIPNIKI-A
1UH-20%-2.8A-0.1OHM
PINA2016FE-SMROOM=BACKLIGHT
ROOM=CHESTNUT0402
20%10V
4.7UF
X5R-CERM X5R-CERM
4.7UF10V20%
0402ROOM=CHESTNUT
43
50 41 32
41 9
45 41 21 11
41 11 5
41 11 5
48 42 11
48 42 11
50
41 32
41 9
41 11 5
41 11 5
21
47 21 7
42 21
45 21 11
45 41 21 11
100
1/32W5%
01005MF
ROOM=CHESTNUT
1UH-20%-2.8A-0.1OHM
PINA2016FE-SMROOM=BACKLIGHT
ROOM=MOJAVE
20%6.3V
2.2UF
X5R-CERM0201
OMIT_TABLE
ROOM=MOJAVE
15UF20%
CERM0402-0.1MM
6.3V
1.0UH-20%-0.4A-0.636OHM
ROOM=MOJAVE
CRITICAL
0403
ROOM=MOJAVE
LM3638A0BGA
CRITICAL
PLACE_NEAR=U5610:0.5MM
ROOM=MOJAVE
220PF
COG25V5%
01005
01005ROOM=MOJAVE
5%220PF25VCOG
ROOM=MOJAVE
X5R35V20%2.2UF
0402
20%
ROOM=MOJAVE
35VX5R
2.2UF
0402
0402-0.1MMROOM=BACKLIGHT
CERM
20%6.3V
15UF
ROOM=BACKLIGHT
DSBGA
LM3539A1
CRITICAL
ROOM=BACKLIGHT
NSR0530P2T5G
CRITICAL
SOD-923-1
COG25V
220PF5%
01005
ROOM=BACKLIGHTPLACE_NEAR=U5660:2MM
ROOM=BACKLIGHTNSR05F30NXT5G
DSN2
CRITICAL
2.2UF20%
ROOM=BACKLIGHT
35VX5R0402
35V20%
0402X5R
ROOM=BACKLIGHT
2.2UF
0402X5R35V
2.2UF20%
ROOM=BACKLIGHT
ROOM=BACKLIGHT
20%2.2UF35VX5R0402
2.2UF20%35VX5R0402
ROOM=BACKLIGHT
2.2UF35VX5R0402
20%
ROOM=BACKLIGHT
ROOM=BACKLIGHT
0402
35VX5R
2.2UF20%
X5R
ROOM=BACKLIGHT
2.2UF20%35V
0402
35V
2.2UF
0402
20%
X5R
ROOM=BACKLIGHT
2.2UF
ROOM=BACKLIGHT
X5R
20%
0402
35V
ROOM=BACKLIGHT
1/32WMF
1%
01005
200K
15UF6.3VCERM
20%
0402-0.1MMROOM=CHESTNUT
220PF25V5%
PLACE_NEAR=U5650:2MM
01005COG
ROOM=BACKLIGHT
DSN2
CRITICAL
ROOM=BACKLIGHTNSR05F30NXT5G
CRITICAL
SOD-923-1ROOM=BACKLIGHT
NSR0530P2T5G
0402-0.1MM
15UF
ROOM=BACKLIGHT
CERM6.3V20%
ROOM=BACKLIGHT
CRITICALDSBGA
LM3539A1
C0G-CERM
ROOM=CHESTNUT
5%10V
01005
220PF
ROOM=CHESTNUTPIXB2016FE-SM
CRITICAL
1.0UH-20%-2.25A-0.15OHM
16VCER-X5R
ROOM=CHESTNUT
20%
0201
1UF 10UF
X5R-CERM
20%10V
0402-0.1MMROOM=CHESTNUTOMIT_TABLE
10UF
0402-0.1MMROOM=CHESTNUTOMIT_TABLE
20%10VX5R-CERM
10VX5R-CERM
20%
ROOM=CHESTNUT0402-0.1MM
10UF
CRITICAL
TPS65730A0PYFF
ROOM=CHESTNUTBGA
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
42
42 41
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
43
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
50 43 36 28 22 20
42
42
41
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
42
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5 42
42
42
42
42
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 4 OF 6
VDD34VDD34
VDD34VDD34VDD34VDD34
VDD34VDD34
BL34BL34
BL34BL34BL34BL34BL34BL34
SYM 3 OF 6
VDD12VDD12
VDD12VDD12VDD12VDD12
VDD12VDD12
BL12BL12
BL12BL12BL12BL12BL12BL12
IN
IN
IN
IN
IN
IN
IN
BI
IN
IN
IN
IN
OUT
IN
IN
BI
IN
PMID
VOUT
EN_S
LDOIN
EN_M
SW
VIN
PGND
AGND
SDI
VIO/HWEN
SCK
SDA
TRIG
SW2_1SW2_2
SCL
SW1
IN OUT
LED1LED2
INHIBIT
GND
GND
SDI
VIO/HWEN
SCK
SDA
TRIG
SW2_1SW2_2
SCL
SW1
IN OUT
LED1LED2
INHIBIT
GND
GND
HVLDO3
HVLDO2
HVLDO1
VNEG(SUB)
VNEG
AGND
PGND
2PG
ND1
CPUMPLCMBST
CF1CF2
ADCMUX
RESET*
LCM_EN
SDA
SCL
SYNC
SW
VIN
AOP/TOUCH INTERFACE
Per #27955644:Use 100pF to match D1x
DISPLAY CONTROL SIGNALS
28463617: Update to 25V Tolerant Cap
#27428158:Ground J5700.12
AC return path (LCM MIPI):GND/VDD_MAIN reference
AP/TOUCH INTERFACE
#27978784:Add GND_VOID=TRUE to MIPI pins
#27428548:Add R5787
DISPLAY + TOUCH CONNECTORTOUCH POWERDISPLAY POWERMLB: 516S00168
BACKLIGHT
To J5700 DISP/TOUCH B2B
#28227044:Have cap on each side of R5787
Stuff 10k PU with 200k to meet spec
DISPLAY MIPI
ORB/TOUCH INTERFACE
#32464647:C5730 to 56PF to Improve GPS L1 Desense
42 OF 81
CKPLUS_WAIVE=I2C_PULLUP
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
CKPLUS_WAIVE=I2C_PULLUP
10.0.0
57 OF 80
051-02159
1MF
56PF5%25V
PP_DISPLAY_BL12_ANODE_CONN
11 I2C_DISP_EEPROM_SDA_CONN
C57551
5%
01005ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY1 C5730
PP_DISPLAY_BL12_CAT1_CONN
SPI_AP_TO_TOUCH_MOSI
SPI_AP_TO_TOUCH_SCLK
1C5756
01005ROOM=B2B_DISPLAY
25V5%56PF
NP0-C0G-CERM
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
01005
5%25V
56PF
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
01005
25V
56PF5%
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DISPLAY
GND_VOID=TRUE
TAM060565OHM-0.7-2GHZ-3.4OHM
CRITICAL
ROOM=B2B_DISPLAY
TAM060565OHM-0.7-2GHZ-3.4OHM
GND_VOID=TRUE
CRITICAL
ROOM=B2B_DISPLAY
TAM060565OHM-0.7-2GHZ-3.4OHM
GND_VOID=TRUE
CRITICAL
0201ROOM=B2B_DISPLAY
240-OHM-25%-0.42A-0.31DCR
X5R-CERM
2.2UF20%
6.3V
OMIT_TABLE
0201ROOM=B2B_DISPLAY
01005
10V5%
C0G-CERM
ROOM=B2B_DISPLAY
220PF
01005
5%220PF10VC0G-CERM
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY0201
240-OHM-25%-0.42A-0.31DCR
ROOM=B2B_DISPLAY0201
240-OHM-25%-0.42A-0.31DCR
240-OHM-25%-0.42A-0.31DCR
0201ROOM=B2B_DISPLAY
01005
5%
C0G-CERM10V
220PF
ROOM=B2B_DISPLAY
OMIT_TABLEROOM=B2B_DISPLAY
6.3VX5R-CERM0201
2.2UF20%
20%6.3VX5R-CERM
OMIT_TABLE
0201
2.2UF
ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
C0G-CERM
5%220PF10V
01005
5%
ROOM=B2B_DISPLAY
10VC0G-CERM
220PF
ROOM=B2B_DISPLAY
C0G-CERM10V
220PF
01005
5%
01005ROOM=B2B_DISPLAY
5%
MF1/32W
10
01005ROOM=B2B_DISPLAY
1/32WMF
5%100K
01005
5%10VC0G-CERM
ROOM=B2B_DISPLAY
220PF
01005
5%10V
ROOM=B2B_DISPLAY
C0G-CERM
220PF
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DISPLAY
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DISPLAY
01005
5%10V
ROOM=B2B_DISPLAYC0G-CERM
220PF
01005
5%16VNP0-C0G
100PF
ROOM=B2B_DISPLAY
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
01005
10V5%220PF
C0G-CERM
ROOM=B2B_DISPLAY
01005
25V5%56PF
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DISPLAY
01005
56PF25V5%
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005
25V5%
NP0-C0G-CERM
ROOM=B2B_DISPLAY
56PF
01005
56PF25V5%
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005
5%10V
ROOM=B2B_DISPLAY
220PF
C0G-CERM
01005ROOM=B2B_DISPLAY
150OHM-25%-200MA-0.7DCR
01005
220PF
C0G-CERM10V5%
ROOM=B2B_MAMBA_MESA
01005ROOM=B2B_DISPLAY
MF
0%1/32W
0.00
33-OHM-25%-1500MA
0201ROOM=B2B_DISPLAY
01005ROOM=B2B_DISPLAY
MF
1%1/32W
33.2
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
GND_VOID=TRUE
F-ST-SM
GND_VOID=TRUE
GND_VOID=TRUE
BB35C-RA48-3A
ROOM=B2B_DISPLAY
01005
5%25V
56PF
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005
ROOM=B2B_MAMBA_MESA
1/32WMF
5%10K
BOMOPTION=NOSTUFF01005
10K
MF
ROOM=B2B_MAMBA_MESA
1/32W5%
TAM0605
ROOM=B2B_DISPLAY
65OHM-0.7-2GHZ-3.4OHMCRITICAL
GND_VOID=TRUE
65OHM-0.7-2GHZ-3.4OHM
ROOM=B2B_DISPLAY
TAM0605
GND_VOID=TRUE
CRITICAL
01005NP0-C0G-CERM
25V
56PF
ROOM=B2B_DISPLAY01005
25V5%56PF
NP0-C0G-CERM
ROOM=B2B_DISPLAY
01005
5%10V
ROOM=B2B_DISPLAY
C0G-CERM
220PF
01005
10V5%
C0G-CERM
ROOM=B2B_DISPLAY
220PF
01005ROOM=B2B_DISPLAY
10V5%
C0G-CERM
220PF
01005ROOM=B2B_DISPLAY
220PF
C0G-CERM10V5%
01005ROOM=B2B_DISPLAY
220PF10VC0G-CERM
5%
01005
5%
C0G-CERM
220PF10V
ROOM=B2B_DISPLAY
01005
10V5%220PF
ROOM=B2B_DISPLAY
C0G-CERM
ROOM=TEST
SMP2MM-NSM
01005ROOM=B2B_DISPLAY
0%1/32WMF
0.00
0%
MF1/32W
0.00
ROOM=B2B_DISPLAYOMIT_TABLE
20%
X5R-CERM0402-0.1MM
10UF10V
01005ROOM=B2B_DISPLAY
1%
MF1/32W
200
01005
10VX5R
10%1000PF
NOSTUFF
ROOM=B2B_DISPLAY
OMIT_TABLE
20%
0201X5R-CERM6.3V
ROOM=B2B_DISPLAY
2.2UF
ROOM=B2B_DISPLAYOMIT_TABLE
0402-0.1MMX5R-CERM
10V
10UF20%
01005COG25V5%220PF
ROOM=B2B_DISPLAY
COG25V5%220PF
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY01005
5%
COG25V
220PF
01005COG25V5%220PF
ROOM=B2B_DISPLAY
NP0-C0G-CERM
ROOM=B2B_DISPLAY01005
240OHM-25%-0.2A-0.9OHM
01005ROOM=B2B_DISPLAY
01005
5%25VCOG
01005NP0-C0G-CERM
56PF
ROOM=B2B_MAMBA_MESA
25V5%
01005
10V5%
ROOM=B2B_DISPLAY
C0G-CERM
220PF
11 41 48
43
42 43
9
9
9
9
9
9
9
9
9
9
12
11
11
11
11
12
13
13
13 21 22 29 50
11 41 48
21
12
21 41
01005
10V5%
ROOM=B2B_DISPLAY
C0G-CERM
220PF
01005ROOM=B2B_DISPLAY
5%10VC0G-CERM
220PF
01005ROOM=B2B_DISPLAY
10V5%220PF
C0G-CERM
1/20W1%
0.00
ROOM=B2B_DISPLAY0201MF
0.00
0201ROOM=B2B_DISPLAY
1/20W1% MF
1%1/20W
ROOM=B2B_DISPLAY
0.00
0201MF
1/20W 0201
0.001% MF
1%
0.00
0201
1%1/20W
0.00
ROOM=B2B_DISPLAY0201MF
SYNC_MASTER=sync SYNC_DATE=04/14/2017
CG: B2B DISPLAY + TOUCH
SPI_AP_TO_TOUCH_CS_L
PP1V8_TOUCH
TOUCH_TO_AOP_GPO_CONN
PP5V7_DISPLAY_AVDDH_CONN
PN5V7_DISPLAY_MESON_AVDDN_CONN
I2C_DISP_EEPROM_SCL_CONN
PN5V7_DISPLAY_MESON_AVDDN
PP_DISPLAY_BL34_CAT1
PP_DISPLAY_BL34_ANODE
PP_DISPLAY_BL12_CAT2
PP_DISPLAY_BL12_ANODE
I2C3_AP_SDA
I2C3_AP_SCL
PMU_TO_DISPLAY_PANICB
I2C_DISP_EEPROM_SCL_CONN
PP5V7_MESON_AVDDH
AP_TO_DISPLAY_RESET_L
DISPLAY_TO_CHESTNUT_PWR_EN
PP_DISPLAY_BL34_ANODE_CONN
PP_DISPLAY_BL12_CAT2_CONN
PMU_TO_DISPLAY_PANICB_CONN
AP_TO_DISPLAY_RESET_CONN_L
DISPLAY_TO_CHESTNUT_PWR_EN_CONN
PP5V7_MESON_AVDDH_CONN
PP1V8_IO
PP5V7_DISPLAY_AVDDH
PP1V8_DISPLAY_CONN
AP_TO_TOUCH_CLK32K_RESET_L
TOUCH_TO_AP_INT_L
AOP_TO_TOUCH_PROX_STATE
DISPLAY_TO_MANY_BSYNC
TOUCH_TO_AOP_GPO
PP5V1_TOUCH_VDDH
SPI_TOUCH_TO_AP_MISO
I2C_TOUCH_BI_MAMBA_SDA
PP1V8_TOUCH
I2C_TOUCH_TO_MAMBA_SCL_R
SPI_TOUCH_TO_AP_MISO_CONN
AP_TO_TOUCH_MAMBA_RESET_CONN_L
SPI_AP_TO_TOUCH_MOSI_CONN
SPI_AP_TO_TOUCH_SCLK_CONN
SPI_AP_TO_TOUCH_CS_CONN_L
AP_TO_TOUCH_CLK32K_RESET_CONN_L
TOUCH_TO_AP_INT_CONN_L
AOP_TO_TOUCH_PROX_STATE_CONN
I2C_TOUCH_TO_MAMBA_SCL
PP_VDD_MAIN
90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA3_N
90_MIPI_AP_TO_DISPLAY_CLK_CONN_N90_MIPI_AP_TO_DISPLAY_CLK_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA0_P
90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_DATA1_N
90_MIPI_AP_TO_DISPLAY_DATA2_P
90_MIPI_AP_TO_DISPLAY_CLK_P
90_MIPI_AP_TO_DISPLAY_CLK_N
90_MIPI_AP_TO_DISPLAY_DATA0_N
PP_DISPLAY_BL34_CAT2_CONNPP_DISPLAY_BL34_ANODE_CONNPP_DISPLAY_BL34_CAT1_CONNPP_DISPLAY_BL12_CAT2_CONNPP_DISPLAY_BL12_ANODE_CONNPP_DISPLAY_BL12_CAT1_CONN
DISPLAY_TO_MANY_BSYNC_CONN
PP5V1_TOUCH_VDDH_CONN
PP1V8_TOUCH_CONN
TP_GALILEO_PHOTON_PIFA_CONN
PP5V7_MESON_AVDDH_CONN
TOUCH_TO_AOP_GPO_CONN
DISPLAY_TO_MAMBA_MSYNC_CONN
PP1V8_TOUCH_CONN
I2C_TOUCH_TO_MAMBA_SCL_RSPI_TOUCH_TO_AP_MISO_CONNSPI_AP_TO_TOUCH_CS_CONN_L
PP5V1_TOUCH_VDDH_CONN
PN5V7_DISPLAY_MESON_AVDDN_CONN
AP_TO_TOUCH_CLK32K_RESET_CONN_LSPI_AP_TO_TOUCH_SCLK_CONN
AP_TO_DISPLAY_RESET_CONN_L
TOUCH_TO_AP_INT_CONN_LSPI_AP_TO_TOUCH_MOSI_CONN
I2C_TOUCH_BI_MAMBA_SDA
AP_TO_TOUCH_MAMBA_RESET_CONN_L
PP1V8_DISPLAY_CONN
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P
AOP_TO_TOUCH_PROX_STATE_CONNPMU_TO_DISPLAY_PANICB_CONN
PP5V7_DISPLAY_AVDDH_CONNDISPLAY_TO_CHESTNUT_PWR_EN_CONN
DISPLAY_TO_MANY_BSYNC_CONN
90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
90_MIPI_AP_TO_DISPLAY_CLK_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P
90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N
90_MIPI_AP_TO_DISPLAY_CLK_CONN_N
PP_DISPLAY_BL34_CAT2 PP_DISPLAY_BL34_CAT2_CONN
PP_DISPLAY_BL34_CAT1_CONN
PP_DISPLAY_BL12_CAT1
I2C_DISP_EEPROM_SDA_CONNMAMBA_TO_DISPLAY_MDRIVE
AP_TO_TOUCH_MAMBA_RESET_L
C57601
2
FL576012
C57641
2
FL576412
C57621
2
FL576212
L57541
23
4
L57501
23
4
L57511
23
4
FL572512
C5721 1
2
C57201
2
C57151
2
FL571512
FL570512
FL570012
C57101
2
C57051
2
C57001
2
C57061
2
C57011
2
C57251
2
R57541 2
R57531
2
C57541
2
C57521
2
FL575212
FL575012
C57501
2
C57681
2
FL576612
FL577612
C57661
2
C57761
2
FL577412
FL577012
C57741
2
C57721
2
C57701
2
C57781
2
FL577812
C57791
2
R57721 2
FL57201 2
R576812
J5700
1 23 45 67 89 10
11 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 4041 4243 4445 4647 48
49 50
51 52
53
54
C57881
2
R57861
2
R57851
2
L57521
23
4
L57531
23
4
2 2
C57411
2
C57421
2
C57431
2
C57441
2
C57451
2
C57461
2
C57471
2
PP57001
R57551 2
R57561 2
C5703 1
2
R57871 2
C57511
2
C57161
2
C5702 1
2
C57311
2
C57321
C57341
2
C57351
2
2
FL571012
1
2
C5787 1
2
C57481
2
C57901
2
C57491
2
C57911
2
R57341 2
R57331 2
1 2
1 2
R57302
R57351 2
ROOM=B2B_DISPLAY
220PFC5733
010052
R5732
ROOM=B2B_DISPLAY
R5731
1/20W
5 42
5 42
18 42 43
42
42
42
42
41
41
41
41
41
42
41
5 42
5 42
42
42
42
42
6 7 8 9 11
15 17
18 28
29 30
31 33
40
41
42 41
18 42 43
42 43
42
42 43
42
42
42
42
42
42
5 19 20 22 24 25 28 32 37 38 39 40 41 44 45 47 48 50
42
42
5 42
5 42
5 42
5 42
5 42
5 42
42
42
42
42
42
43
42
42 43
42
42
42
42
42
42
42
42
42
42 43
42 43
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
41 5 42
5 42
41
42
43
42
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
IN
IN
OUT
OUT
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
BI
BI
IN
IN
BI
OUT
BI
PP
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
SYM_VER-2
#29189177: Move C5785 to other side of resistor
To J5800 MAMBA/MESA B2B
IN ORDER TO MEET CAP ESR REQUIREMENT PER LDO SPEC.
NOTE: OUTPUT IMPEDANCE MUST BE >0.005-OHM
VENDOR ALSO RECOMMENDS CIN = COUT FOR STABILITY
MAMBA DIGITAL I/O
#27956171: Stuff only 1 set to meet rise time specStuff C5787/C5788 or C5785/C5786
MESA DIGITAL I/O
#31201019: Change R5842 to 50 ohms
#30272427: Change FL5800 to 155S00067MESA POWER
MAMBA POWER
GUARD
MLB: 516S00273MAMBA AND MESA CONNECTOR
43 OF 81
VOLTAGE=2.75V
10.0.0
58 OF 80
051-02159
21
R5842
2
1R1632
2
1R1631
2
1C57852
1 C5786
21
R5844
21
FL5820
21
FL5810
2
1 C5820
2
1 C5872
2
1 C5870
21
R5854
21
R5852
2
1 C5863
1
PP5800
30
29
2827
2625
242322212019181716151413121110987654321
J5800
2
1R1633
4 1
3
5
6
2
U1602
4 1
3
5
6
2
U1601
2
1 C5840
2
1C58642
1 C5854
2
1 C5852
21
FL5800
2
1R5843
2
1R5841
21
XW5890
21
FL5850
2
1 C5850
21
FL5864
2
1 C5860
2
1 C5862
21
FL5860
2
1C5861
21
R5846
21
R5848
2
1 C5846
2
1 C58482
1 C5842
2
1 C5844
21
FL5840
2
1 C5896
2
1 C58812
1 C5880
2
1 C5895
21
R5880
14
52
3
U58902
1C5890
2
1 C58012
1 C58002
1 C58042
1 C58032
1 C5802
2
1 C58102
1 C5811
SPI_AP_TO_MESA_MOSI_CONN
PP3V0_MESA_CONN
MAMBA_TO_DISPLAY_MDRIVE
MESA_TO_AOP_FDINT_CONN
MAMBA_TO_DISPLAY_MDRIVE_CONN
MESA_TO_AOP_FDINT
PP16V0_MESA_CONN
PP2V75_MAMBA_CONN
I2C1_AOP_TO_MESA_TURTLE_SCL_CONNI2C1_AOP_BI_MESA_TURTLE_SDA_CONN
PP3V0_MESA_CONN
MAMBA_TO_DISPLAY_MDRIVE_CONNDISPLAY_TO_MAMBA_MSYNC_CONN
AP_TO_TOUCH_MAMBA_RESET_CONN_L
MESA_TO_BOOST_EN
I2C1_AOP_BI_MESA_TURTLE_SDA_CONN
MESA_TO_AOP_FDINT_CONN
PP1V8_MESA_CONN
MESA_TO_BOOST_EN_CONNPP1V8_MESA_CONN
PP1V8_TOUCH_TO_MAMBA_CONN
PP3V0_MESA_S2
SPI_AP_TO_MESA_SCLK_CONN
SPI_MESA_TO_AP_MISO_CONN AOP_TO_MESA_BLANKING_EN_CONN
MESA_TO_BOOST_EN_CONN
MESA_TO_AP_INT_CONN
PP1V8_S2
I2C1_AOP_TO_MESA_TURTLE_SDA
PP1V8_S2
SPI_AP_TO_MESA_MOSI
AOP_TO_MESA_I2C_ISO_EN
I2C1_AOP_SDA
SPI_AP_TO_MESA_SCLK
SPI_MESA_TO_AP_MISO
I2C1_AOP_SCL I2C1_AOP_TO_MESA_TURTLE_SCL
MESA_TO_AP_INT
AOP_TO_MESA_BLANKING_EN
PP1V8_MESA_S2
I2C1_AOP_TO_MESA_TURTLE_SCL_CONNDISPLAY_TO_MAMBA_MSYNC_CONN
PP1V8_TOUCH MAMBA_LDO_EN
PP_VDD_BOOST
PP1V8_TOUCH
TP_MAMBA_HINT_L
PP1V8_TOUCH_TO_MAMBA_CONNI2C_TOUCH_TO_MAMBA_SCLI2C_TOUCH_BI_MAMBA_SDA
MESA_TO_AP_INT_CONN
SPI_MESA_TO_AP_MISO_CONNPP2V75_MAMBA_CONN
AOP_TO_MESA_BLANKING_EN_CONNSPI_AP_TO_MESA_MOSI_CONNSPI_AP_TO_MESA_SCLK_CONN
PP16V0_MESA_CONN
PP1V8_MESA_S2
PP16V0_MESA
I2C_TOUCH_BI_MAMBA_SDA
I2C_TOUCH_TO_MAMBA_SCL_R
CG: B2B ORB + MESASYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=B2B_MAMBA_MESA01005MF
1%1/32W
49.9
ROOM=MAMBA_MESA
1.00K5%1/32WMF01005
ROOM=MAMBA_MESA
1.00K
01005MF1/32W5%
13
42
43 42
43 42
42
41
11
11 13
11
11
NOSTUFF
56PF
NP0-C0G-CERM01005
ROOM=B2B_DISPLAY
25V5%
NOSTUFF
ROOM=B2B_MAMBA_MESA
5%56PF
NP0-C0G-CERM01005
25V
33.2
ROOM=B2B_MAMBA_MESA01005
1%1/32WMF
150OHM-25%-200MA-0.7DCR
ROOM=B2B_MAMBA_MESA01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_MAMBA_MESA01005
COG25V
ROOM=B2B_MAMBA_MESA
220PF5%
01005
0.1UF6.3V
01005
20%
ROOM=SOC
X5R-CERM
ROOM=SOC
0.1UF
X5R-CERM20%6.3V
01005
13
0.00
MF
0%1/32W
01005ROOM=B2B_MAMBA_MESA
ROOM=B2B_MAMBA_MESA01005MF
0.00
0%1/32W
39
37 13
39
37 13
ROOM=B2B_DISPLAY
25V
56PF
NP0-C0G-CERM
5%
01005
ROOM=TEST
SMP2MM-NSM
F-ST-SMBB35K-RB24-3A
ROOM=B2B_MAMBA_MESA
511K1/32W
01005ROOM=SOC
1%
MF
74LVC1G3157GXX2SON6
CRITICALROOM=SOC
CRITICALROOM=SOC
74LVC1G3157GXX2SON6
NP0-C0G-CERM
ROOM=B2B_MAMBA_MESA
56PF
01005
5%25V
220PF
ROOM=B2B_MAMBA_MESA
10VC0G-CERM
01005
5%
ROOM=B2B_MAMBA_MESA01005NP0-C0G-CERM25V5%56PF
ROOM=B2B_MAMBA_MESA
56PF25V
01005
5%
NP0-C0G-CERM
240-OHM-25%-0.42A-0.31DCR
ROOM=B2B_MAMBA_MESA0201
ROOM=B2B_MAMBA_MESA
1%1/32W
MF
511K
01005
ROOM=B2B_MAMBA_MESA01005
511K1%
MF1/32W
OMIT
ROOM=PMU
SHORT-20L-0.05MM-SM
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_MAMBA_MESA
ROOM=B2B_MAMBA_MESA
NP0-C0G-CERM25V
56PF
01005
5%
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_MAMBA_MESA
56PF25V
01005ROOM=B2B_MAMBA_MESA
NOSTUFF
5%
NP0-C0G-CERM
25V5%56PF
ROOM=B2B_MAMBA_MESA
NP0-C0G-CERM01005
ROOM=B2B_MAMBA_MESA01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_MAMBA_MESA01005
56PF
NP0-C0G-CERM25V5%
1/32W1%
681
MF01005
ROOM=B2B_MAMBA_MESA
01005ROOM=B2B_MAMBA_MESA
681
MF1/32W1%
ROOM=B2B_MAMBA_MESA
5%
01005C0G-CERM10V
220PF
ROOM=B2B_MAMBA_MESA
220PF
C0G-CERM01005
5%10V
ROOM=B2B_MAMBA_MESA
NP0-C0G-CERM
56PF
01005
5%25V
ROOM=B2B_MAMBA_MESA
5%56PF25VNP0-C0G-CERM01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_MAMBA_MESA01005
ROOM=B2B_MAMBA_MESA
10VC0G-CERM01005
220PF5%
ROOM=B2B_MAMBA_MESA
10VC0G-CERM
220PF5%
010050201
6.3V
ROOM=B2B_MAMBA_MESA
2.2UF20%
X5R-CERM
OMIT_TABLE
10V
ROOM=B2B_MAMBA_MESA
X5R-CERM
20%10UF
0402-0.1MM
1/32W0%
MF
0.00
ROOM=B2B_MAMBA_MESA01005
LP5907SNX-2.75
CRITICAL
X2SON
ROOM=B2B_MAMBA_MESA
0201
20%6.3V
X5R-CERM
ROOM=B2B_MAMBA_MESA
2.2UF
OMIT_TABLE
5%220PF
01005C0G-CERM10V
ROOM=B2B_MAMBA_MESA
X5R-CERM
ROOM=B2B_MAMBA_MESA
0.1UF6.3V20%
01005ROOM=B2B_MAMBA_MESAOMIT_TABLE
20%6.3V
2.2UF
X5R-CERM0201
OMIT_TABLEROOM=B2B_MAMBA_MESA
X5R-CERM6.3V20%
0201
2.2UF
OMIT_TABLEROOM=B2B_MAMBA_MESA0201
20%2.2UF6.3VX5R-CERM
ROOM=B2B_MAMBA_MESA
C0G-CERM01005
220PF5%10V
OMIT_TABLEROOM=B2B_MAMBA_MESA
2.2UF6.3V20%
X5R-CERM0201
43
43
43
43
43 5
43
43
43
43
43
43 42
42
43
43
43
43 5 43
43
20
43
43 43
43 5
43
50 48 47
46 45 43 41 36 25 23 21 18 15 13 11 5
50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
43 20
43
43 42 18
50 41 36 28 22 20
43 42 18
43
42
43 42
43
43
43
43
43
43
43 5
43 20
41
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
IN
BI
IN
OUT
OUT
OUT IN
IN
IN
IN
IN
BI
PP
GND
S
VCC
Z
Y0
Y1
NC
GND
S
VCC
Z
Y0
Y1
NC
VIN
ENEPADGND
VOUT
#29697484: Add 15pF cap in parallel with R5902
#29546629:Ground INA
To Hydra and E75
VDD_MAIN OV CUT-OFF CIRCUIT
#29546665:Change to 0201
44 OF 81
10.0.0
59 OF 80
051-02159
2
1R5902
2
1R5901
2
1 C5902
2 1XW5900
2
1C5900 K A
DZ5900
21
R5903
2
1
6
3
4
5
U5900
PP_VDD_MAIN_VMON
OV_VMON_INA
PP_HYDRA_ACC1
PP3V0_S2
PP_VAR_USB_RVPPP_VDD_MAIN
PP_HYDRA_ACC1_R
I/O: Overvoltage Cut-Off Circuit
SYNC_DATE=04/14/2017SYNC_MASTER=sync
1/32W
100K1%
MF01005ROOM=OV_CUTOFF
MF1/20W1%1.3M
0201ROOM=OV_CUTOFF
5%16V
01005
NOSTUFF
ROOM=OV_CUTOFF
NP0-C0G-CERM
15PF
OMIT
ROOM=SOC
SHORT-20L-0.05MM-SM
0201
25V
ROOM=OV_CUTOFF
X5R
20%0.47UF
0201
RB521ES-30
1/32WMF
0%
0.00
01005ROOM=OV_CUTOFF
ROOM=OV_CUTOFF
WSONTPS3700DSE
48 47
50 48 47 46 33 20 5
47 46 24 50 48 47 45 42 41 40 39
38 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
INA
INB
GND
OUTB
OUTA
VDD
To Hydra
ACCESSORY BUCK
I2C0 address: 0x52
45 OF 81
10.0.0
61 OF 80
051-02159
A2
B2A1
B1
C2
C1
U6110
2
1 C6100
2
1 C6112
21
R61162
1 C61112
1 C61102
1
XW6110
21
L6110
A1A2
B2
B1
U6100
ACC_BUCK_SW
ACC_BUCK_FB
PP_VDD_MAIN
PP1V8_S2
PP_VDD_MAIN_ACC_BUCK_VIN
ACC_BUCK_TO_PMU_AMUX
PP_ACC_VAR
I2C0_AP_SCL
I2C0_AP_SDA
I/O: Accessory BuckSYNC_DATE=04/14/2017SYNC_MASTER=sync
CSP
ROOM=ACC_BUCK
FAN53741
6.3V
0201
20%X5R-CERM
2.2UF
ROOM=ACC_BUCK
X5R6.3V20%
0402-0.1MM-1
15UF
ROOM=SOC
10K
1/32W5%
01005ROOM=ACC_BUCKMF
20%6.3VX5R-CERM01005
0.1UF
ROOM=ACC_BUCK
5%10VC0G-CERM01005
220PF
ROOM=ACC_BUCK
OMIT
SHORT-20L-0.05MM-SMROOM=ACC_BUCK
PIGA1608-SMROOM=ACC_BUCK
CRITICAL0.47UH-20%-2.52A-0.08OHM
41 21 11
41 21 11
FPF1204UCXWLCSP-COMBO
ROOM=ACC_BUCK50 48 47 44 42 41 40 39
38 37 32 28 25 24 22 20 19 5
50 48 47 46 43 41 36 25 23 21 18 15 13 11 5
21
47 20
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
VIN
FB
SW
GND
SDA
SCLIN
BI
VIN
GND
VOUT
ON
USB-PD
#29590414: Update CCG2 resistor divider values#30199192: R6210 change to 0201 to prevent Dendrite
46 OF 81
10.0.0
62 OF 80
051-02159
2
1R6211
2
1R6210
2
1 C621121
R6200 B1
D4 C1
E1E3 C4 E4A1
E2D1
B3
A2A3
D3
D2
C3
C2
B2
A4B4
U6200
2
1 C6200
2
1 C62922
1 C62912
1 C6290
PP_VAR_USB_RVP
PMU_TO_CCG2_RESET_LI2C0_SMC_SCLI2C0_SMC_SDA_CCG2_R
CCG2_TO_SMC_INT_L
AP_BI_CCG2_SWDIOAP_TO_CCG2_SWCLK
PP5V0_USB_RVP_R
CCG2_TO_HYDRA_CC
PP1V8_S2
PP1V8_VCCD_CCG2
PP3V0_S2
I2C0_SMC_SDA
I/O: USB PDSYNC_DATE=04/14/2017SYNC_MASTER=sync
ROOM=USBPD0201-1X5R6.3V20%1.0UF
ROOM=USB_PD01005
50K1/32W1%
MF
499K
ROOM=USB_PD
1%
MF1/20W
201
22NF20%
01005X5R-CERM6.3V
ROOM=USB_PD
25 24 23 22 11
25 24 23 22 11
01005ROOM=USB_PD
43.2
MF
1%1/32W
CG8740AAT
CRITICALROOM=USBPD
CSP 220PF5%
C0G-CERM
ROOM=USBPD01005
10V
11 5 47
21
11
11
ROOM=USBPD
X5R
1.0UF6.3V20%
0201-1
1.0UF20%
X5R6.3V
0201-1ROOM=USBPD
47 44 24
50 48 47 45 43 41 36 25 23 21 18 15 13 11 5
50 48 47 44 33 20 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
NC
IN
BI
VSS
XRES
VDDI
O
VDDD
VCCD
VCO
NN2
VCO
NN1
GPIO_C3GPIO_D3GPIO_C2GPIO_D2GPIO_B2
I2C_0_SCLI2C_0_SDA
SWD_IOSWD_CLK
VSS
RD1
CC2CC1
NC
OUT
NCOUT
NC
IN
BI
IN
NC
NC
UART TX/RX pin names on Hydra match signal names (i.e. TX pin is input and connects to TX signal)
#29289485: Add PP to HYDRA_TO_NUB_DOCK_CONNECT
12C ADDRESS: 0011010X
HYDRA
MIPIMIKEYBUSBB USBD20x Stiching AC Cap: AP USBx7
47 OF 81
VOLTAGE=3.0V
VOLTAGE=4.3V
VOLTAGE=4.3V
10.0.0
63 OF 80
051-02159
2
1 C6336
1
PP6300
2
1 C63232
1 C63242
1 C63222
1 C63212
1 C6320
2
1R6301
2
1 C63122
1 C6311
H5H4
D3D4
B3B4
B1A1
F2E2
D1C1
E4
G5G4
H3
G6
F1E1
F7
F6
H2
G2
H7H6H1G7E3 F4
A3
C3
G1
A4
C4
C2D2
G3
A2B2
F5
F3
E6D6C6B6A6
E7D7C7B7A7E5D5C5B5A5
U6300
2
1 C63332
1 C63342
1 C63352
1 C63312
1 C6301
2
1 C6330
2
1 C63912
1 C6390
2
1 C6395
21
L6300
21
L6301
2
1 C6300
21R6300
2
1 C63042
1 C6303
2
1 C63322
1 C6302
HYDRA_TO_NUB_DOCK_CONNECT
90_USB_AP_DATA_P
HYDRA_CC1CCG2_TO_HYDRA_CC
PMU_HYDRA_TO_AP_FORCE_DFU
HYDRA_TO_PMU_USB_BRICK_ID_R
90_USB_BB_DATA_P
90_MIKEYBUS_DATA_P
PP3V0_S2
PP1V8_S2
90_USB_AP_DATA_L_N
HYDRA_CON_DETECT_L
PP_VAR_USB_RVP
HYDRA_TO_TIGRIS_VBUS1_VALID_L
HYDRA_TO_PMU_USB_BRICK_ID
90_USB_AP_DATA_N
SWD_DOCK_TO_AP_SWCLK
90_USB_AP_DATA_L_P
90_USB_BB_DATA_N
UART_AP_TO_ACCESSORY_TXD
UART_AP_DEBUG_TXDUART_AP_DEBUG_RXD
90_MIKEYBUS_DATA_N
UART_ACCESSORY_TO_AP_RXD
SWD_DOCK_BI_AP_SWDIO
HYDRA_TO_PMU_HOST_RESET
HYDRA_TO_NUB_INT
PP_HYDRA_ACC1
90_HYDRA_DP2_CONN_P
HYDRA_BYPASS
PMU_TO_AP_HYDRA_ACTIVE_READY
I2C1_SMC_SCLI2C1_SMC_SDA
90_HYDRA_DP1_CONN_P90_HYDRA_DP1_CONN_N
90_HYDRA_DP2_CONN_N
PP_HYDRA_ACC2
PP_ACC_VAR
PP_VDD_MAINI/O: Hydra
SYNC_DATE=04/14/2017SYNC_MASTER=sync
10VC0G-CERM
ROOM=HYDRA01005
5%220PF
ROOM=HYDRA
P2MM-NSMSM
6.3V20%2.2UF
X5R-CERM0201ROOM=HYDRAOMIT_TABLE
6.3V
ROOM=HYDRA0201
2.2UF20%
X5R-CERM
OMIT_TABLE
6.3V20%
OMIT_TABLE
X5R-CERM
ROOM=HYDRA0201
2.2UF2.2UF20%
X5R-CERM0201ROOM=HYDRAOMIT_TABLE
6.3V
0201
6.3V20%2.2UF
ROOM=HYDRA
X5R-CERM
OMIT_TABLE
MF01005
1%1/32W
100K
ROOM=HYDRA
25V20%
X5R0201ROOM=HYDRA
0.47UF
X5R
0.47UF20%25V
ROOM=HYDRA0201
7
12
12
13
46
12
12
7
13
41 21 7
48
21
35
35 WLCSPCBTL1612A1
50
50
5%10V
01005C0G-CERM
220PF
ROOM=HYDRA
220PF10VC0G-CERM
5%
01005ROOM=HYDRA
220PF5%10VC0G-CERM01005ROOM=HYDRA
5%220PF10V
01005C0G-CERM
ROOM=HYDRA
C0G-CERM10V
01005
5%220PF
ROOM=HYDRA
20%6.3V1.0UF
X5R0201-1ROOM=HYDRA
20%6.3V0.1UF
X5R-CERM01005ROOM=HYDRA
1.0UF6.3V
0201-1X5RROOM=HYDRA
20%
ROOM=HYDRA01005X5R6.3V10%0.01UF
GND_VOID=TRUEROOM=HYDRA
15NH-250MA
0201
GND_VOID=TRUE 0201ROOM=HYDRA
15NH-250MA
7
7
21
0.01UF6.3V10%
ROOM=HYDRA
X5R01005
1%1/32W
01005MF
ROOM=HYDRA
6.34K
48 5
48 5
48 5
48 5
24 5
11
11
220PF
C0G-CERM01005ROOM=CAM_PMU
10V5%
C0G-CERM10V5%
01005ROOM=CODEC
220PF10V
220PF5%
01005C0G-CERM
ROOM=HYDRA
220PF10V
01005C0G-CERM
5%
ROOM=BASEBAND
50 48 46 44 33 20 5
50 48 46 45 43 41 36 25 23 21 18 15 13 11 5
46 44 24
48 44
48
45 20
50 48 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
PPOUT
IN
IN
OUT
OUT
IN
OUT
OUT
BI
OUT
IN
IN
OUT
BI
BI
NC
VDD1V8ACC_PWR
DVSS1
VDD3V0
UART1_TXUART1_RX
ACC2ACC2
POW_GATE_EN*
CC0
DIG_DPDIG_DN
USB1_DP
BRICK_ID
USB1_DN
USB0_DNUSB0_DP
UART0_RXUART0_TX
UART2_TXUART2_RX
JTAG_CLKJTAG_DIO
EXT_SW_EN
FORCE_DFU
DOCK_CONNECT
CC1
DVSS
P_INACC1
ACC1ACC1
ACC1ACC1
ACC2
ACC2ACC2
DN1DP1
DN2DP2
CON_DET_L
SWITCH_ENHOST_RESET
SCLSDA
INTBYPASS
BI
BI
NC
BI
BI
OUT
BI
BI
BI
BI
OUT
BI
BI
#30657902: Update C6494 to 0.1UF per EMC/Densence#30797674: Update C6496/C6494 per EMC/Desense feedback
#29332151: No-stuff C6480 and C6482
#31609563: Update C6434/C6436 to 33pF (D21)
HYDRA
ARCANTENNA
MICS
APN: 516S00276DOCK FLEX CONNECTOR
SOUTH SPEAKER
AC return path (USB):GND/VDD_MAIN reference
NOTE:Another 100pF on dock flex[P1.5] Use 16V Part
#28565582:[P2] Reduce to 100pF
#31347215: [CRB] Revert to 220pF[P1.5] Use 16V Part
48 OF 81
VOLTAGE=16.0V
10.0.0
64 OF 80
051-02159
2
1C64942
1C64962
1C64932
1C64922
1C64912
1C6490
2 1
R6410
2 1
R6421
2 1
R6420
2 1
R6419
2
1 C6413
21
R6436
21
R6434
2
1 C64162
1 C6415
56
55
5453
5251
5049484746454443424140393837363534333231302928272625242322212019181716151413121110987654321
J6400
2
1 C6436
2
1 C6434
21
R6424
21
R6422
21
R6456
21
R6466
2
1 C6419
21
FL6413
2
1 C6466
2
1 C6456
2
1 C6420
2
1 C6421
21
FL6444
21
FL6442
2
1 C6444
2
1 C6442
21
FL6440
21
FL6438
2
1 C6440
2
1 C6438
2
1 C6424
2
1 C6422
2
1 C6482
2
1C64892
1C6488
2 1
FL6482
2
1C64702
1C6471
2
1 C6450
2
1 C6452
2 1
FL6450
2 1
FL6452
2 1
FL6454
2
1 C6454
2
1 C6460
2
1 C6462
2 1
FL6460
2 1
FL6462
2 1
FL6464
2
1 C6464
2
1 C64802 1
FL6480
2
1 C6430
2
1 C6432
2 1
FL6430
2 1
FL6432
2
1 C6410
2
1 C641121
FL6411
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN
BB_TO_LAT_GPO1_CONN
COIL_TO_SPKRAMP_BOT_VSENSE_CONN_P
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN
90_HYDRA_DP2_CONN_NLAT_TUNER_RFFE1_CLK_CONN
LAT_TUNER_RFFE1_DATA LAT_TUNER_RFFE1_DATA_CONN
I2C1_AP_BI_MIC1_SDA_CONN
90_HYDRA_DP1_CONN_P90_HYDRA_DP1_CONN_N
PP_HYDRA_ACC1_CONN
PP_HYDRA_ACC2_CONN
ARC1_TO_SOLENOID1_OUT_POS
COIL_TO_SPKRAMP_BOT_VSENSE_CONN_N
BB_TO_LAT_GPO2
BB_TO_LAT_GPO4
PP3V0_S2
BB_TO_LAT_GPO3_CONN
BB_TO_LAT_GPO2_CONN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
PP_CODEC_TO_LOWERMIC4_BIAS_CONN
HYDRA_CON_DETECT_L
BB_TO_LAT_GPO1
BB_TO_LAT_GPO3
LOWERMIC1_TO_CODEC_AIN1_CONN_P
I2C3_AP_TO_SAKONNET_SCL_CONN
I2C3_AP_BI_SAKONNET_SDA_CONN
PP1V8_LAT_ARC_CONN
LOWERMIC1_TO_CODEC_AIN1_CONN_N
PP_CODEC_TO_LOWERMIC1_BIAS
PP_CODEC_TO_LOWERMIC4_BIAS
PP1V8_S2
LOWERMIC4_TO_CODEC_AIN4_CONN_PLOWERMIC4_TO_CODEC_AIN4_P
PP3V0_LAT_CONN
BB_TO_LAT_GPO4_CONN
PP_HYDRA_ACC2
LOWERMIC1_TO_CODEC_AIN1_N
I2C3_AP_SCL
I2C3_AP_SDA
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
LOWERMIC4_TO_CODEC_AIN4_CONN_NLOWERMIC4_TO_CODEC_AIN4_N
PP_CODEC_TO_LOWERMIC1_BIAS_CONN
COIL_TO_SPKRAMP_BOT_VSENSE_P
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT
LAT_TUNER_RFFE1_CLK
ARC1_TO_SOLENOID1_OUT_NEGARC1_TO_SOLENOID1_OUT_POS
I2C1_AP_TO_MIC1_SCL_CONN
I2C1_AP_BI_MIC1_SDA_CONN
I2C1_AP_SCL
I2C1_AP_SDA
COIL_TO_SPKRAMP_BOT_VSENSE_N
ARC1_TO_SOLENOID1_OUT_NEG
PP3V0_LAT_CONN
LOWERMIC1_TO_CODEC_AIN1_CONN_NLOWERMIC4_TO_CODEC_BIAS_FILT_RET
PP_CODEC_TO_LOWERMIC1_BIAS_CONNLOWERMIC1_TO_CODEC_AIN1_CONN_P
I2C1_AP_TO_MIC1_SCL_CONN
I2C3_AP_TO_SAKONNET_SCL_CONN
SOLENOID1_TO_ARC1_VSENSE_N
LAT_TUNER_RFFE1_CLK_CONNLAT_TUNER_RFFE1_DATA_CONNHYDRA_CON_DETECT_CONN_L
LOWERMIC1_TO_CODEC_BIAS_FILT_RETMIKEYBUS_REFERENCE
BB_TO_LAT_GPO4_CONN
PP_CODEC_TO_LOWERMIC4_BIAS_CONN
LOWERMIC4_TO_CODEC_AIN4_CONN_NLOWERMIC4_TO_CODEC_AIN4_CONN_P
BB_TO_LAT_GPO1_CONNBB_TO_LAT_GPO2_CONN
SPKRAMP_BOT_TO_COIL_OUT_NEGCOIL_TO_SPKRAMP_BOT_VSENSE_CONN_N
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONNI2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN
BB_TO_LAT_GPO3_CONN
PP1V8_LAT_ARC_CONN
HYDRA_CON_DETECT_CONN_L
PP_VDD_MAIN
PP_HYDRA_ACC1_CONN
90_HYDRA_DP2_CONN_P
SOLENOID1_TO_ARC1_VSENSE_PI2C3_AP_BI_SAKONNET_SDA_CONN
SPKRAMP_BOT_TO_COIL_OUT_POS
PP_VBUS1_E75
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN
LOWERMIC1_TO_CODEC_AIN1_P
PP_HYDRA_ACC1
PP_HYDRA_ACC2_CONN
SPKRAMP_BOT_TO_COIL_OUT_NEGSPKRAMP_BOT_TO_COIL_OUT_POS
COIL_TO_SPKRAMP_BOT_VSENSE_CONN_P
SYNC_DATE=10/10/2016SYNC_MASTER=sync
I/O: B2B DOCK
56PF
NP0-C0G-CERM
5%
01005
25V
ROOM=B2B_DOCK
ROOM=B2B_DOCK
56PF5%25V
01005NP0-C0G-CERM
ROOM=B2B_DOCK01005
150OHM-25%-200MA-0.7DCR
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_DOCK
01005ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR
C0G-CERM01005ROOM=B2B_DOCK
220PF10V5%
25V5%
NP0-C0G-CERM
56PF
01005ROOM=B2B_DOCK
5%56PF
01005ROOM=B2B_DOCKNP0-C0G-CERM25V
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_DOCK
01005ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR
150OHM-25%-200MA-0.7DCR
01005ROOM=B2B_DOCK
5%10V
220PF
C0G-CERM01005ROOM=B2B_DOCK
01005ROOM=B2B_DOCK
5%10VC0G-CERM
NOSTUFF
220PF
01005ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR
5%10V
01005C0G-CERM
220PF
ROOM=B2B_DOCK
ROOM=B2B_DOCK01005
10-OHM-1.1A
ROOM=B2B_DOCK01005C0G-CERM10V
220PF5%
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DOCK
01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DOCK
25V10%
X5R
0.1UF
0201ROOM=B2B_DOCK
X5R25V10%
0.1UF
0201ROOM=B2B_DOCK
COG25V5%
01005ROOM=B2B_DOCK
220PF
ROOM=B2B_DOCK
10%25V
0.1UF
X5R0201
25V10%
X5R0201
ROOM=CHARGER
0.1UF10%25VX5R
0201
0.1UF
ROOM=CHARGER
MF01005
100
1%1/32W
ROOM=B2B_DOCK
1%
MF01005
1/32W
100
ROOM=B2B_DOCK
100
1/32W
01005
1%
MF
ROOM=B2B_DOCK
100
1%1/32W
01005ROOM=B2B_DOCK
MF
ROOM=B2B_DOCK01005
5%25VCOG
220PF
0.00
ROOM=B2B_DOCK
1/32WMF
01005
0%
ROOM=B2B_DOCK01005
1/32W0%
MF
0.00
39 36 13
10V
01005ROOM=B2B_DOCKC0G-CERM
5%220PF220PF
5%
01005
10VC0G-CERM
ROOM=B2B_DOCK
CRITICALROOM=B2B_DOCK
BB35L-RA50-3AF-ST-SM
ROOM=B2B_DOCK
5%33PF
NP0-C0G-CERM01005
16V
5%33PF
NP0-C0G-CERM
ROOM=B2B_DOCK
16V
01005
ROOM=B2B_DOCK01005
0.00
MF1/32W0%
0.00
0%1/32W
01005MF
ROOM=B2B_DOCK
0.00
01005
0%1/32WMF
ROOM=B2B_DOCK
0.00
01005
0%1/32WMF
ROOM=B2B_DOCK
NP0-C0G-CERM25V5%
01005ROOM=B2B_DOCK
NOSTUFF
56PF
22-OHM-25%-1800MA
ROOM=B2B_DOCK0201
01005ROOM=B2B_DOCKNP0-C0G-CERM25V5%56PF
5%
01005NP0-C0G-CERM25V
ROOM=B2B_DOCK
56PF
NOSTUFF
01005NP0-C0G-CERM
5%25V
56PF
ROOM=B2B_DOCK
5%25V
56PF
NP0-C0G-CERM
ROOM=B2B_DOCK
NOSTUFF
01005
39 37 36
39 37 36
ROOM=B2B_DOCK01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DOCK01005
150OHM-25%-200MA-0.7DCR
56PF5%25V
01005ROOM=B2B_DOCKNP0-C0G-CERM
56PF5%25V
01005ROOM=B2B_DOCKNP0-C0G-CERM
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DOCK01005
ROOM=B2B_DOCK01005
150OHM-25%-200MA-0.7DCR
ROOM=B2B_DOCK01005
5%
NP0-C0G-CERM25V
56PF
5%56PF25VNP0-C0G-CERM01005ROOM=B2B_DOCK
ROOM=B2B_DOCK01005
56PF
NP0-C0G-CERM25V5%
NP0-C0G-CERM
ROOM=B2B_DOCK
25V5%
01005
56PF
5%27PF
ROOM=B2B_DOCK01005NP0-C0G16V
5%
01005
10VC0G-CERM
220PF
ROOM=B2B_DOCK
NOSTUFF
10V
01005
1000PF10%
ROOM=B2B_DOCKX5R
ROOM=B2B_DOCK01005
10VX5R
1000PF10%
01005ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR
01005
5%10V
220PF
C0G-CERM
ROOM=B2B_DOCKROOM=B2B_DOCK01005
220PF
C0G-CERM10V5%
100PF
NP0-C0G
ROOM=B2B_DOCK
5%
01005
16V
48
48
48
48
47 5
48
50 48
48
47 5
47 5
48 5
48 5
48 39
48
50
50
50 47
46
44 33 20 5
48
48
48
47
50
50
48
48
48
48
48
36
36
50
47
46 45
43
41 36
25
23 21
18
15 13 11 5
48 35
48
48
47
35
42 41 11
42 41 11
48 35
48
37
50
48 39
48 39
48
48
34 11
34 11
37
48 39
48
48
36
48
48
48
48
39
48
48
48 5
36
35
48
48
48
48
48
48
48 37
48
48
48
48
48
48
48 5
50 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
48 5
47 5
39
48
48 37
24 5
48
35
47 44
48 5
48 37
48 37
48
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
IN
IN
(see #28857723 updates)
I2C MAP
49 OF 81
10.0.0
65 OF 80
051-02159
SYSTEM: I2C MAPSYNC_DATE=04/14/2017SYNC_MASTER=sync
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
50 OF 81
10.0.0
80 OF 80
051-02159
SWD_AOP_BI_BB_SWDIO
PP1V8_S2
PP_VDD_BOOST
90_USB_BB_DATA_PNFC_SWPPCIE_BB_BI_AP_CLKREQ_L
90_USB_BB_DATA_N
AP_TO_BB_MESA_ONAP_TO_BB_COREDUMPAP_TO_BB_IPC_GPIO1
PP_VDD_MAIN
50_UAT_TRX_LB_MCW
SWD_AOP_TO_MANY_SWCLK
DISPLAY_TO_MANY_BSYNC
LAT_TUNER_RFFE1_DATA
UART_BB_TO_AOP_RXD
I2S_BB_TO_AP_DINI2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_BCLKBB_TO_STROBE_DRIVER_GSM_BURST_IND
UART_BB_TO_WLAN_COEX
BB_TO_NFC_CLKBB_TO_AP_RESET_DETECT_L
90_PCIE_AP_TO_BB_TXD_P
BB_TO_LAT_GPO1
UART_NFC_TO_AP_CTS_LUART_AP_TO_NFC_RTS_L
PP1V8_S2PP_VDD_MAIN
BB_TO_NFC_CLKPMU_TO_NFC_EN
NFC_TO_BB_CLK_REQAP_TO_NFC_FW_DWLD_REQAP_TO_NFC_DEV_WAKENFC_TO_PMU_HOST_WAKE
UART_AP_TO_NFC_TXDUART_NFC_TO_AP_RXD
90_PCIE_AP_TO_BB_REFCLK_N
UAT_TUNER_RFFE_DATAUAT_TUNER_RFFE_CLK
50_UAT_TRX_MLB_MB_HB_MCW
NFC_SWP
50_DSM_HB_IN_TRX_UHB
50_UAT_WLAN_2G_WEST
50_DSM_HB_IN_TRX_UHB
50_UAT_TRX_UHB_MCW
50_LAT_DRX_MLB_MB_HB_MCW50_LAT_DRX_LB_MCW
50_UAT_TRX_LB_MCW
50_UAT_TRX_MLB_MB_HB_MCW
LAT_TUNER_RFFE1_CLK
AP_TO_BBPMU_RADIO_ON_LPMU_TO_BBPMU_RESET_L
90_PCIE_AP_TO_BB_REFCLK_P90_PCIE_AP_TO_BB_TXD_N
UART_AOP_TO_BB_TXDI2S_AP_TO_BB_DOUTPMU_TO_BB_USB_VBUS_DETECTUART_WLAN_TO_BB_COEX
PCIE_AP_TO_BB_RESET_LNFC_TO_BB_CLK_REQ
90_PCIE_BB_TO_AP_RXD_N90_PCIE_BB_TO_AP_RXD_P
50_UAT_TRX_UHB_MCS50_UAT_TRX_MLB_MB_HB_MCS50_UAT_TRX_LB_MCS50_LAT_DRX_MLB_MB_HB_MCS50_LAT_DRX_LB_MCS50_UAT_TRX_UHB_MCW
50_LAT_DRX_MLB_MB_HB_MCW50_LAT_DRX_LB_MCW
50_LHB_LAT1
AP_TO_BB_RESET_L
BB_TO_LAT_GPO2BB_TO_LAT_GPO3BB_TO_LAT_GPO4
PP1V8_S2
LAT_TUNER_RFFE1_CLKUAT_TUNER_RFFE_DATAUAT_TUNER_RFFE_CLK
PP3V0_S2
50_LHB_LAT1
50_LAT_DRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCS50_LAT_DRX_MLB_MB_HB_MCS
50_UAT_TRX_LB_MCS50_UAT_TRX_UHB_MCS
50_UAT_WLAN_2G_WEST
AP_TO_BB_TIME_MARK
BB_TO_PMU_PCIE_HOST_WAKE_L
LAT_TUNER_RFFE1_DATA
PP1V8_S2
50_LMHGW_UAT150_LMHGW_UAT1
PP1V8_S2
AP_TO_BT_WAKEAP_TO_WLAN_DEVICE_WAKE
UART_AP_TO_BT_RTS_LUART_AP_TO_BT_TXD
UART_BT_TO_AP_CTS_LUART_BT_TO_AP_RXD
BT_TO_PMU_HOST_WAKE
50_LAT_WLAN_NORTH50_LAT_WLAN_SOUTH
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_MLC
50_UAT_WLAN_2G_EAST
UART_WLAN_TO_BB_COEX
AOP_TO_WLAN_CONTEXT_A
PP_VDD_MAIN90_PCIE_AP_TO_WLAN_REFCLK_P
UART_BB_TO_WLAN_COEX
90_PCIE_AP_TO_WLAN_REFCLK_N90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_WLAN_TO_AP_RXD_N
PCIE_AP_TO_WLAN_RESET_L
90_PCIE_AP_TO_WLAN_TXD_N90_PCIE_WLAN_TO_AP_RXD_P
PCIE_WLAN_BI_AP_CLKREQ_L
WLAN_TO_PMU_HOST_WAKE
AOP_TO_WLAN_CONTEXT_B
PMU_TO_WLAN_CLK32KPMU_TO_WLAN_REG_ON
UART_WLAN_TO_AP_CTS_LUART_WLAN_TO_AP_RXD
WLAN_TO_AP_TIME_SYNC
UART_AP_TO_WLAN_TXDUART_AP_TO_WLAN_RTS_L
PMU_TO_BT_REG_ON
SYNC_MASTER=D21_MLB_DOE SYNC_DATE=07/18/2016
RADIOS
I8SUBDESIGN_SUFFIX=W
SUBDESIGN_SUFFIX=EF
I6
SUBDESIGN_SUFFIX=E
I5
SUBDESIGN_SUFFIX=S
I4
58 13
80 78 77 59 52 50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
73 43 41 36 28 22 20
73 47
73 52 50
59 8
73 47
59 12
59 12
59 12
80 73 52
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
76 67 50
58 17 13 5
56 42 29 22 21 13
78 60 50 48
59 13
59 11
59 11
59 11
59 41 32
80 73 50
56 52 50
59 12
58 8
78 48
52 12
52 12
80 78 77 59 52 50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
80 73 52
50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5
56 52 50
52 21
56 52 50
52 12 5
52 12
52 21
52 12
52 12
74 8
77 50 5
77 50 5
76 68 50
73 52 50
76 68 50
76 71 50
76 68 50
76 68 50
76 68 50
76 67 50
76 67 50
76 68 50
78 60 50 48
56 12
56 21
74 8
58 8
59 13
59 11
73 21
80 73 50
59 8
56 52 50
58 8
58 8
76 65 50
76 69 50
76 69 50
76 69 50
76 69 50
76 68 50
76 68 50
76 67 50
76 70 50
73 12
78 48
78 48
78 48
80 78 77 59 52 50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
78 60 50 48
77 50 5
77 50 5
77 48 47 46 44 33 20 5
76 70 50
76 69 50
76 69 50
76 69 50
76 69 50
76 65 50
76 71 50
59 12
59 21
78 60 50 48
80 78 77 59 52 50
48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
76 71 50
76 71 50
80 78 77 59 52 50 48 47 46 45 43 41 36 25 23 21 18 15 13 11 5
80 12
80 12
80 12
80 12
80 12
80 12
80 21
81 76
81 76
81 76
81 76
81 76
80 73 50
80 13
80
73 52 50 48 47 45 44 42 41 40 39 38 37 32 28 25 24 22 20 19 5 80 8
80 73 50
80 8
80 8
80 8
80 8
80 8
80 8
80 8
80 21
80 13
80 21
80 21
80 12
80 12
80 12 5
80 12
80 12
80 21
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
wifi_mlb
PP1V8_SDRAM
WLAN_TIME_SYNC
UART_AP_TO_WLAN_TXD
UART_WLAN_TO_AP_CTS_LUART_WLAN_TO_AP_RXDUART_AP_TO_WLAN_RTS_L
AP_TO_BT_WAKEAP_TO_WLAN_DEV_WAKE
UART_AP_TO_BT_RTS_LUART_AP_TO_BT_TXD
UART_BT_TO_AP_CTS_LUART_BT_TO_AP_RXD
BT_TO_PMU_HOST_WAKE
PMU_TO_WLAN_REG_ON
50_L
AT_W
LAN_
NORT
H50
_LAT
_WLA
N_SO
UTH
50_U
AT_W
LAN_
5G_E
AST
50_L
AT_W
LAN_
MLC
50_U
AT_W
LAN_
2G_E
AST
PMU_TO_WLAN_32KPMU_TO_BT_REG_ON
UART_WLAN_TO_BB_COEX
90_PCIE_AP_TO_WLAN_TX_P
PCIE_AP_BI_WLAN_CLKREQ_L
AOP_TO_WLAN_CONTEXT_BAOP_TO_WLAN_CONTEXT_A
PCIE_WLAN_TO_PMU_WAKEPCIE_AP_TO_WLAN_PERST_L
90_PCIE_WLAN_TO_AP_RX_N90_PCIE_WLAN_TO_AP_RX_P90_PCIE_AP_TO_WLAN_TX_N
PP_VDD_MAIN90_PCIE_AP_TO_WLAN_REFCLK_N90_PCIE_AP_TO_WLAN_REFCLK_P
UART_BB_TO_WLAN_COEX
radio_mlb_ff
PP1V8_SDRAM
50_LHB_LAT150_DSM_HB_IN_TRX_UHB
50_LMHGW_UAT150_LAT_DRX_LB_MCS
50_LAT_DRX_MLB_MB_HB_MCS50_UAT_TRX_MLB_MB_HB_MCS
PP3V0_TRISTAR_ARC_PROXVDD_TUNER_RFFE_VIO_1V8
UAT_TUNER_RFFE4_CLKUAT_TUNER_RFFE4_DATA
LAT_TUNER_RFFE1_CLKLAT_TUNER_RFFE1_DATA
BB_TO_LAT_GPO1BB_TO_LAT_GPO2
50_UAT_TRX_LB_MCS50_UAT_TRX_UHB_MCS
50_LAT_DRX_LB_MCW
50_UAT_TRX_UHB_MCW50_UAT_TRX_MLB_MB_HB_MCW
50_UAT_TRX_LB_MCW50_LAT_DRX_MLB_MB_HB_MCW
50_L
AT_W
LAN_
MLC
50_L
AT_W
LAN_
NORT
H50
_LAT
_WLA
N_SO
UTH
50_U
AT_W
LAN_
2G_E
AST
BB_TO_LAT_GPO4BB_TO_LAT_GPO3
50_U
AT_W
LAN_
5G_E
AST
50_U
AT_W
LAN_
2G_W
EST
radio_mlb
SWD_AP_TO_BB_CLK
PCIE
_AP_
BI_B
B_CL
KREQ
_L
AP_TO_BB_COREDUMP_TRIGAP_TO_BB_MESA_ON_LAP_TO_BB_TIME_MARK
50_UAT_TRX_LB_MCS50_UAT_TRX_MLB_MB_HB_MCS
PCIE0_BB_TO_AP_TX_P
PCIE0_AP_TO_BB_RX_N
PCIE0_AP_TO_BB_REFCLK_N
LAT_TUNER_RFFE1_CLKLAT_TUNER_RFFE1_DATA
UAT_TUNER_RFFE4_DATAUAT_TUNER_RFFE4_CLK
UART_BB_TO_AOP_RXDI2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_DINI2S_BB_TO_AP_BCLK
BB_TO_AP_GSM_TXBURST
PCIE0_AP_TO_BB_REFCLK_P
PCIE0_AP_TO_BB_RX_P
90_U
SB_B
B_N
90_U
SB_B
B_P
BB_TO_AP_RESET_DETECT_L
PCIE_BB_TO_PMU_WAKE_LBB_TO_NFC_CLK
UART_AOP_TO_BB_TXDTOUCH_TO_BBPMU_FORCE_PWM
50_UAT_TRX_UHB_MCS
AP_TO_BBPMU_RADIO_ON_L
UART_BB_TO_WLAN_COEX
PCIE0_BB_TO_AP_TX_N
AP_TO_BB_IPC_GPIO
PP_VDD_BOOST_RF
PP1V8_S2PP_VDD_MAIN
50_UAT_WLAN_2G_WEST
PCIE_AP_TO_BB_PERST_LNFC_TO_BB_CLKREQAP_TO_BB_RESET_L
50_LHB_LAT1
50_LMHGW_UAT1
50_LAT_DRX_LB_MCW
50_UAT_TRX_LB_MCW
50_UAT_TRX_UHB_MCW50_LAT_DRX_LB_MCS50_LAT_DRX_MLB_MB_HB_MCS
SWD_
AP_B
I_BB
_IO
BB_S
IM1_
SWP
PMU_TO_BBPMU_RESET_L
50_UAT_TRX_MLB_MB_HB_MCW
50_LAT_DRX_MLB_MB_HB_MCW
50_DSM_HB_IN_TRX_UHB
I2S_AP_TO_BB_DOUTUSB_BB_VBUSUART_WLAN_TO_BB_COEX
nfc_mlb
UART_NFC_TO_AP_CTS_LUART_AP_TO_NFC_RTS_LUART_NFC_TO_AP_RXDUART_AP_TO_NFC_TXD
NFC_TO_PMU_HOST_WAKEAP_TO_NFC_DEV_WAKE
NFC_SWP1
PP1V8_SDRAMPP_VDD_MAIN
BB_TO_NFC_CLKPMU_TO_NFC_EN
NFC_TO_BB_CLK_REQAP_TO_NFC_FW_DWLD
NFC_MLB D20/D21MAY 15, 2017
51 OF 81
PP1V8_S2
AP_TO_NFC_FW_DWLD_REQ
NFC_SWP
051-02159
2017-06-06000892701210 ENGINEERING RELEASED
1 OF 75
10.0.0
SCH,MLB,D21
PP_VDD_MAIN
PMU_TO_NFC_EN
AP_TO_NFC_DEV_WAKE
NFC_TO_PMU_HOST_WAKE
BB_TO_NFC_CLK
NFC_TO_BB_CLK_REQ
UART_AP_TO_NFC_TXD
UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_RTS_L
UART_NFC_TO_AP_CTS_L
470PF, 0201, 2%, 25V131S00016 D2011 C7514_S
T7500_SMURATA, BALUN, 11T157S00023 1 D21_JPN
680PF, 0201, 2%, 25V131S00033 C7513_S1 D21_JPN
157S00023 MURATA, BALUN, 11T T7500_S D21_ROW1
C7514_S D211270PF, 0201, 2%, 25V1131S00081
131S00033 C7510_S D21_JPN680PF, 0201, 2%, 25V1
C7518_S D21_JPN150PF, 0201, 2%, 50V1131S00019
TDK, BALUN, 11T157S00022 D20_JPN1 T7500_S
131S00025 1000PF, 0201, 2%, 25V D20_JPN1 C7513_S
39PF, 0201, 2%, 50V D21_ROWC7512_S1131S00138
39PF, 0201, 2%, 50V C7512_S D21_JPN131S00138 1
270PF, 0201, 2%, 25V C7514_S D21_JPN131S00081 1
C7515_S D21_JPN1000PF, 0201, 2%, 25V131S00025 1
680PF, 0201, 2%, 25V C7516_S D21_JPN131S00033 1
D21_ROW150PF, 0201, 2%, 50V C7518_S131S00019 1
C7512_S D2111 39PF, 0201, 2%, 50V131S00138
C7516_S680PF, 0201, 2%, 25V D2111131S00033
C7518_S131S00019 D211150PF, 0201, 2%, 50V1
680PF, 0201, 2%, 25V C7510_S D2111131S00033820PF, 0201, 2%, 25V131S00026 D2011 C7510_S
page1
D201131S00138 39PF, 0201, 2%, 50V1 C7512_S
157S00023 T7500_S D211MURATA, BALUN, 11T1
680PF, 0201, 2%, 25V C7513_S D2111131S00033
C7515_S D2111000PF, 0201, 2%, 25V1131S00025
D21_ROW680PF, 0201, 2%, 25V C7513_S1131S00033
680PF, 0201, 2%, 25V131S00033 D21_ROWC7510_S1
C7515_S131S00025 1000PF, 0201, 2%, 25V D21_ROW1
131S00033 680PF, 0201, 2%, 25V1 D21_ROWC7516_S
270PF, 0201, 2%, 25V131S00081 D21_ROWC7514_S1
131S0882 390PF, 0201, 2%, 25V D20_JPN1 C7514_S
131S00025 D2011 1000PF, 0201, 2%, 25V C7515_S
131S0825 560PF, 0201, 2%, 25V D2011 C7516_S
131S0883 220PF, 0201, 2%, 50V D2011 C7518_S
131S00026 820PF, 0201, 2%, 25V D2011 C7513_S
157S00022 TDK, BALUN, 11T D2011 T7500_S
131S00026 820PF, 0201, 2%, 25V D20_JPN1 C7515_S
131S00025 1000PF, 0201, 2%, 25V D20_JPN1 C7510_S
680PF, 0201, 2%, 25V D20_JPN1131S00033 C7516_S
131S0883 220PF, 0201, 2%, 50V D20_JPN1 C7518_S
C7512_S1 39PF, 0201, 2%, 50V131S00138 D20_ROW
C7514_S1 470PF, 0201, 2%, 25V131S00016 D20_ROW
C7515_S1000PF, 0201, 2%, 25V1131S00025 D20_ROW
C7518_S1 220PF, 0201, 2%, 50V131S0883 D20_ROW
C7516_S1 560PF, 0201, 2%, 25V131S0825 D20_ROW
C7510_S1 820PF, 0201, 2%, 25V131S00026 D20_ROW
C7513_S1 820PF, 0201, 2%, 25V131S00026 D20_ROW
T7500_S1 TDK, BALUN, 11T157S00022 D20_ROW
C7500_S,C7502_S, C7505_S SOFT_CAP138S00159 CRITICALCAP,SOFT TERM,2.2UF,6.3V,02013
TYPICAL_CAPCRITICALC7500_S,C7502_S,C7505_S138S0831 3 CAP,TYPICAL,2.2UF,6.3V,0201
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
52 50
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART# DESCRIPTIONQTYTABLE_5_HEAD
BOM OPTIONREFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
IO
IN
NFC FRONT END
15UF MIN BULK CAP PROVIDED ON MAIN BOARD
NFC CONTROLLER
STOCKHOLM 5V BOOSTER
75 OF 75
051-02159
52 OF 81
10.0.0
NFC_S
T750
0_S
L7503_S
C7507_S
C7513_S
L7501_S
C7517_S
TP7506_S
C7523_S
VDD_NFC_5V_S52
C7505_S
C7520_S
L7502_S NFC_DCDC_S
PP7513_S
TP7500_S
PP7512_S
PP7511_S
Q7501_S
NFC_FETB0_S
Q7502_SQ7502_SQ7501_S
C7533_SC7532_SC7531_SC7530_S
C7518_S
C7512_S
C7514_S
C7510_S
R7508_S
PP7509_S
PP7508_S
PP7507_S
PP7506_S
PP7505_S
PP7504_S
PP7503_S
C7506_S C7526_S
C7516_SC7515_S
TP7505_S
C7504_S
C7503_S
C7500_S
R7502_S
C7502_S
L7500_S
VDD_NFC_AVDD_S52 VOLTAGE=1.80V
VDD_NFC_TVDD_S
NFC_ANT_S
NFC_BOOST_SW_S
NFC_RXP_CAP_S
VDD_NFC_5V_S52
NFC_BAL1_S
NFC_FETB1_S
NFC_DCDC_OUT_S
NFC_TUNE_B3_S52
NFC_FETB3_S
NFC_TUNE_B1_S52
NFC_TEST_OUT_S52
NFC_ADC_I_TEST_S52
NFC_FETB2_S
VDD_NFC_AVDD_S52
NFC_TUNE_B0_S52
NFC_TXP_S52
NFC_TXN_S52
NFC_BOOST_EN_S 52
NFC_TUNE_B3_S 52
VDD_NFC_DVDD_S VDD_NFC_ESE_SVOLTAGE=1.80V
NFC_SWP
NFC_RXP_S 52
NFC_TUNE_B1_S 52
NFC_TXN_S 52
NFC_TXP_S 52
NFC_RXN_S
NFC_ADC_I_TEST_S 52
NFC_TEST_OUT_S 52
NFC_TUNE_B0_S 52
NFC_DWP_TX_TP_S
NFC_TUNE_B2_S 52
NFC_DWP_RX_TP_S
PP1V8_S250 51
AP_TO_NFC_FW_DWLD_REQ
NFC_BOOST_EN_S52
NFC_TUNE_B2_S52
NFC_RXP_S52
NFC_BAL2_S
NFC_ANT_MATCH_S
PP_VDD_MAIN
PMU_TO_NFC_ENUART_NFC_TO_AP_RXD
UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_TXD
UART_AP_TO_NFC_RTS_L
NFC_TO_PMU_HOST_WAKE
AP_TO_NFC_DEV_WAKE
PP_VDD_MAIN
AP_TO_NFC_DEV_WAKE
UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD
PMU_TO_NFC_EN
UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L
BB_TO_NFC_CLK
NFC_TO_BB_CLK_REQ
NFC_TO_PMU_HOST_WAKE
NFC
D8
A1
H3
H4
H1
C7 E8
D1E1
C3E2
A2
H7G8
H8
G7
B8 A8A5A6A3
A7A4
H5H6
C1
D2
F1G2H2F2F3B2C2
C8
E3
F7E7D6B6B3G4F8F6F5F4E6E4D5C4B5
G1
B4C5
E5
D4B7
D3
C6
B1
G6
G5
G3
D7
UFLGAPN80VEU3-C004B014
234
1
SMAT
B121
006F
-200
11-T
11
OMIT_TABLE
21
0201
10OHM-50%-1A-0.05OHM
21
01005
10%6.3V
1000PF
X5R-CERM
2
1820PF
NFC0201C0G-NP025V2%
OMIT_TABLE
21
0402NFC
106NH-5%-0.85A-0.144OHM
2
1
X5R0402-0.1MM-1
20%6.3V
NFC
15UF
1TP-P55OMITNFC
2
1
X5R-CERM0201
20%6.3V
NFC
2.2UF
2
1
20%6.3V
OMIT_TABLENFC0201X5R-CERM
2.2UF
2
1
X5R-CERM0201
20%6.3V
NFC
2.2UF
21
PIGA1608-SM
0.47UH-20%-2.52A-0.08OHM
A2A1
B2B1
A3
C1C2
C3B3
WLCSP
FAN48680UC08X
1SM
OMIT
P2MM-NSM
1SM-TP1P25-TOP
OMIT
1SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1
2
6
XLLGANTND3184NZTAG
NOSTUFF
4
5
3
XLLGANTND3184NZTAG
NOSTUFF
1
2
6
XLLGANTND3184NZTAG
NOSTUFF
4
5
3
XLLGA
NOSTUFF
NTND3184NZTAG
2
1
C0G01005
5%25V
NOSTUFF
150PF
2
1
C0G01005
5%25V82PF
NOSTUFF
2
1
01005NP0-C0G
NOSTUFF
25V5%39PF
2
1
2%
01005CERM16V
NOSTUFF
18PF
2
1
2%220PF
0201C0G50V
OMIT_TABLE21
2%50V
39PF
0201CER-C0G
OMIT_TABLE
21
25V2%
0201C0G
390PF
OMIT_TABLE
2
1
C0G-NP00201
2%25V820PF
OMIT_TABLENFC
21
1/20WMF201
1%
1K
NFC
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
1 SM
OMIT
P2MM-NSM
2
1
X5R-CERM20%6.3V2.2UF
02012
1
X5R-CERM0201
20%6.3V2.2UF
51 50
2
1
C0G-NP00201
2%25V
NFC
820PF
OMIT_TABLE
2
1
C0G-NP00201
2%25V820PF
NFCOMIT_TABLE
1TP-P55OMITNFC
2
10.22UF
NFC
6.3V20%X5R01005-1
2
1
X5R-CERM01005
20%6.3V
NFC
0.1UF
52 51 50
52 51 50
52 51 50
52 51 50
52 51 50
52 51 50
51 50
51 50
51 50
52 51 50
2
1
X5R-CERM0201
20%6.3V
OMIT_TABLE
NFC
2.2UF
21
1/32WMF
01005
0%
NFC
0.00
2
1
X5R-CERM0201
20%6.3V
OMIT_TABLE
NFC
2.2UF
21
0402NFC
106NH-5%-0.85A-0.144OHM
52 51 50
52 51 50 52 51 50
52 51 50
52 51 50
52 51 50
52 51 50
52 51 50
52 51 50
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TX_PWR_REQ_P
NFC_GPIO6
XTAL2
ESE_
VDD
ESE_
VSS
PVSS
TVSS
DVSS
AVSS
AVSS
AVSS
VDD
SIM
_VCC
2SI
M_V
CC1
GPI
OVD
D
SVDD
AVDD
TVDDVU
P
PVDD
SIM
_PM
U_VC
C_2
VBAT
SIM_SWIO_1
ESE_GPIO
ESE_DWPS_DBGESE_DWPM_DBG
RX-RX+
SIM_SWIO_2
NFC_GPIO4
TX2TX1
VMID
WKUP_REQ
NFC_GPIO1NFC_GPIO0
NFC_GPIO3NFC_GPIO2
NFC_GPIO5
IRQ
DWL
UART_TXUART_RX
VEN
UART_RTSUART_CTS
IC5IC4
IC1
IC3IC2
IC6IC7IC8IC9
IC0
NFC_CLK_XTAL1
IC14IC13IC12
IC10
CLK_REQ
IC11
SIM
_PM
U_VC
C_1
PORT
1PO
RT2
PORT
3G
ND
NC
NC
NCNCNCNC
NC
A
SWSW
PVIN
VOUTVOUT
MODE0MODE1
PGND
PP
A
PP
PP
D
S
G
D
S
G
D
S
G
D
S
G
NC
NCNCNCNCNCNCNC
NCNC
PP
PP
PP
PP
PP
PP
PP
BI
NCNC
A
IN
IN
OUT
OUT
IN
IN
IN
OUT
IN
OUT
NCNC
D21 RADIO_MLB06/06/2017
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
0.122.0
BOM #: 939-02493PCB #: 920-02293SCH #: 951-03059
(MAV17.2/3)
53 OF 81
LAST_MODIFICATION=Tue Jun 6 18:57:01 2017
HIERARCHY
BB: GPIOS & QLINKBB: CONTROL & HS PERIPHERALS [6]
57
XCVR
PMIC: CLOCKS & CONTROLPMIC: BUCKS & LDOS
XCVR
LB DSM
HB PAD
QPOET MODULE
UHB PAD
HB DSMCOUPLER2
545556
58596061626364
666768697071727374
5678
101112
15
2122 PROBE POINTS
9
4
153
TEST POINTSSIM, DEBUG CONN
LB PAD
2
65 1314 2G PA
LOWER ANTENNA
2019181716
GNSS
07/18/2016
FRONT PAGE
3
UPPER ANTENNA
BB: POWER
ALTERNATES
051-02159
2017-06-06000892701210 ENGINEERING RELEASED
1 OF 22
10.0.0
SCH,MLB,D21
BOM_TABLE_ALTS
BOM_TABLE_ALTSIC, EEPROM
FRONT PAGE
XTAL, 38P4MHZ
U_EEPROM_E
Y401_E
XTAL, 38P4MHZY401_E BOM_TABLE_ALTS197S00067
BOM_TABLE_ALTSU_QET_E ET MODULE, QPOET
197S00065
353S01109
197S00093
335S00013 335S0894
197S00065
353S01287
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
DATESYNCCONTENTSCSAPAGE
DESCRIPTION BOM OPTIONREFERENCE DESIGNATOR(S)PART NUMBERALTERNATE FORPART NUMBER
POWER
AUDIO
AOP
SWD/USB
TUNER/DOCK
RF SIGNALS
STOCKHOLM
PCIE UAT_TUNER_RFFE_CLK7
UAT_TUNER_RFFE_DATA7
DISPLAY_TO_MANY_BSYNC
AP_TO_BB_COREDUMP
AP_TO_BB_MESA_ON
AP_TO_BB_IPC_GPIO1
90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_TXD_N
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P
UAT_TUNER_RFFE_DATAUAT_TUNER_RFFE_CLK
PMU_TO_BB_USB_VBUS_DETECT
SWD_AOP_TO_MANY_SWCLK
90_USB_BB_DATA_N
SWD_AOP_BI_BB_SWDIO
90_USB_BB_DATA_P
BB_TO_PMU_PCIE_HOST_WAKE_L
PCIE_BB_BI_AP_CLKREQ_L
PCIE_AP_TO_BB_RESET_L
PP_VDD_BOOST
NFC_TO_BB_CLK_REQ
NFC_SWP
BB_TO_STROBE_DRIVER_GSM_BURST_IND
MAKE_BASE=TRUE
PP_VDD_BOOST
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UART_AOP_TO_BB_TXD
50_LHB_LAT1
AP_TO_BB_TIME_MARK
LAT_TUNER_RFFE1_CLKLAT_TUNER_RFFE1_DATA
PP1V8_S2
50_DSM_HB_IN_TRX_UHB
UART_WLAN_TO_BB_COEX
UART_BB_TO_WLAN_COEX
PMU_TO_BBPMU_RESET_LAP_TO_BBPMU_RADIO_ON_L
AP_TO_BB_RESET_L
50_LMHGW_UAT1
50_UAT_WLAN_2G_WEST
50_LAT_DRX_LB_MCW50_LAT_DRX_MLB_MB_HB_MCW50_UAT_TRX_LB_MCW
50_UAT_TRX_UHB_MCW50_UAT_TRX_MLB_MB_HB_MCW
50_LAT_DRX_LB_MCS50_LAT_DRX_MLB_MB_HB_MCS50_UAT_TRX_LB_MCS
50_UAT_TRX_UHB_MCS50_UAT_TRX_MLB_MB_HB_MCS
PP_VDD_MAIN
BB_TO_AP_RESET_DETECT_L
BB_TO_NFC_CLK
I2S_BB_TO_AP_DIN
I2S_BB_TO_AP_LRCLK
I2S_AP_TO_BB_DOUT
I2S_BB_TO_AP_BCLK
UART_BB_TO_AOP_RXD22 7
22 7
22 7
22 7
22 7
22 7
21
4
22 4
22 7
21 10 3
7
7
7
21 6
6
21 6
6
21 4
17
13
17
17
17
16
16
15
16
15
19
19
21 4
4
4
6
6
6
6
22 6
22 6
7
22 7
21 7
22 7
21 7
19 16
7
8 7
8 7
22 4
22 7
18
22 7
21 3
1245678
B
D
8 7 6 5 4 3
C
B
A
C
A
D
2 1
3
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
OUT
OUT
IN
IN
IN
IO
OUT
IO
IO
IO
IN
IN
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IN
IN
IN
OUT
OUT
IN
IN
IN
IN
IO
IN
OUT
IN
IN
IO
IN
IO
OUT
IN
IN
IO
IN
RF PMIC: SWITCHERS & LDOS
1.20V/523.3MA1.20V/695MA1V/431MA0.90V/128MA1.80V/272.4MA1.80V/221.6MA
1.8V/60MA3.00V/30MA
1.2V/1366MA
0.80V/2898MA
NEED 0.8MM PARTS STILL
1.0V/1972MA
SWITCHERS BULK CAPS
0.80V/1250MA
1.80V/509MA
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
2.7V/69MA1.8V/60MA
0.80V/1045MA1.00V/368.3MA2.7V/5MAPP_2V7_LDO7
VIO TX & RX
55 OF 81
C309_E
C14_E
C319_E
C322_E
C323_E
C324_E
C325_E C327_E
C326_EC321_E
C320_E
C318_E
C317_E
C316_EC315_EC314_EC313_E
C305_E
C301_E
C304_E
C303_E
C302_E
C312_EC308_EC307_EC306_E
R301_E
C1114_E
C311_EC310_E
U_PMIC_E
XW301_E
XW302_E
XW303_E
L304_E
L305_E
L301_E
XW304_E
XW305_E
L302_E
L303_E
U_PMIC_E
PP_1V0_SMPS3_E
PP_1V2_SMPS2_E3
VSW_SMPS2_E
PP_VDD_MAIN 3
PP_VDD_MAIN 3
PP_VDD_MAIN 3
VSW_SMPS3_E
GND3
GND3
VSW_SMPS4_EPP_VDD_MAIN3
PP_1V2_SMPS2_SNS_EVOLTAGE=1.20V
PP_1V0_SMPS3_SNS_EVOLTAGE=1.00V
PP_VDD_MAIN 3
PP_VDD_BOOST 11 12 13 17
VOLTAGE=4.3V
VSW_SMPS5_E
PP_1V8_SMPS4_SNS_EVOLTAGE=1.80V
GND3
PP_1V8_LDO6_E 16
PP_1V8_LDO6_E
3 4 5 6 7 8 10 21
PP_0V8_SMPS5_SNS_EVOLTAGE=0.80V
PP_1V0_SMPS3_E
GND
PP_VDD_MAIN 3
GND
PP_VDD_MAIN 3
GND3
GND
PP_VDD_MAIN 3
GND
PP_VDD_MAIN 3
VSW_SMPS1_E
PP_0V8_SMPS1_SNS_EVOLTAGE=0.80V
PP_1V8_VIO_RX_E 11 12 13
PP_1V8_LDO6_E
11 12 13 17
PP_0V8_SMPS1_EVOLTAGE=0.80V
GND 3
GND 3
GND 3
PP_1V2_SMPS2_E 3 VOLTAGE=1.20V
GND 3
PP_1V0_SMPS3_EVOLTAGE=1.00V
PP_1V8_SMPS4_EVOLTAGE=1.80V
PP_0V8_SMPS5_EVOLTAGE=0.80V
GND 3
GND3
PP_VDD_MAIN3
PP_VDD_MAIN3
GND3
PP_VDD_MAIN3
PP_VDD_MAIN 3
PP_VDD_MAIN 3
VOLTAGE=4.3V
PP_1V2_LDO1_EVOLTAGE=1.20V
PP_1V8_LDO5_EVOLTAGE=1.80V
PP_0V8_LDO9_EVOLTAGE=0.80V
PP_1V0_LDO8_EVOLTAGE=1.00V
PP_1V0_LDO3_EVOLTAGE=1.00V
PP_1V0_SMPS3_E
PP_1V8_SMPS4_E
PP_VDD_MAIN3
PP_0V9_LDO4_EVOLTAGE=0.90V
PP_1V2_LDO2_EVOLTAGE=1.20V
VOLTAGE=3.00V PP_UIM2_LDO13_E
VOLTAGE=2.70V PP_2V7_LDO12_E
PP_UIM1_LDO11_EVOLTAGE=3.00V
PP_3V0_LDO10_EVOLTAGE=3.00V
PP_1V8_LDO6_EVOLTAGE=1.8V
10.0.0
3 OF 22
051-02159
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
10219193223310785423242
2998
2013349614125231
2 1
2 1
2 1
2 1
21
21
2 1
2 1
21
21
112101
109
656454
7363
11510494
99
86
23
41
72
111100
108
4443
74
114103
93
113102
110
7675
53
116105
9584
PP_VDD_MAIN
PP_VDD_MAINMAKE_BASE=TRUE
MAKE_BASE=TRUEPP_VDD_MAIN
PP_VDD_MAINMAKE_BASE=TRUE
PP_VDD_MAIN
MAKE_BASE=TRUE
PP_VDD_MAIN
PP_VDD_BOOSTMAKE_BASE=TRUE
PP_VDD_BOOST
PP_VDD_BOOST
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PMIC: BUCKS & LDOS
21 10 3 2
21 10 3 2
21 10 3 2
21 10 3 2
21 10 3 2
6.3VCERM-X5R0201
4UF20%
6.3V20%4UF
CERM-X5R0201
4V20%
X5R0402-0.1MM
26UF
0402-0.1MMX5R4V20%26UF
26UF
0402-0.1MMX5R
20%4V
26UF
0402-0.1MMX5R
20%4V
26UF
0402-0.1MMX5R
20%4V
0402-0.1MM
26UF
X5R
20%4V
26UF
0402-0.1MMX5R
20%4V
0402-0.1MM
26UF
X5R
20%4V
26UF
0402-0.1MMX5R
20%4V
26UF
0402-0.1MMX5R
20%4V
0402-0.1MM
26UF
X5R
20%4V
0201X5R-CERM
2.2UF20%6.3V
0201
6.3V20%2.2UF
X5R-CERM
2.2UF20%
0201
6.3VX5R-CERM
0402-0.1MM
15UF6.3V20%
CERM
10UF
0402-0.1MM-1
10V20%
X5R-CERM
10UF
0402-0.1MM-1
10V20%
X5R-CERM
10UF
0402-0.1MM-1
10V20%
X5R-CERM
X5R-CERM
20%10V
0402-0.1MM-1
10UF
10UF
0402-0.1MM-1
10V20%
X5R-CERM
4.7UF
X5R0402-0.1MM
20%6.3
4.7UF
0402-0.1MMX5R
20%6.3
0402-0.1MM
4.7UF
X5R
20%6.3
0402-0.1MM
6.320%4.7UF
X5R
1/32W
0.00
MF01005
0%
21 3 2
CERM16V47PF5%
01005
12 8
5
8
5
20 16 15 13 12 11 8 5 4
21 10 8 7 6 5 4 3
8
5
5
21 5
5
4.7UF20%6.3V
402X5R-CERM1
6.3V4.7UF20%
402X5R-CERM1
PDM9655BGA
21 10 3 2
3
3
3
4 3
5
3
4 3
5
SHORT-10L-0.1MM-SM
ROOM=PMU
SHORT-10L-0.1MM-SM
ROOM=PMU
ROOM=PMU
SHORT-10L-0.1MM-SM
1UH-20%-3.6A-0.035OHM
2016
RADIO_PMIC
2.2UH-20%-2.7A-0.09OHM
2016
2016
2.2UH-20%-2.7A-0.09OHM
SHORT-10L-0.1MM-SM
ROOM=PMU
ROOM=PMU
SHORT-10L-0.1MM-SM
2.2UH-20%-2.7A-0.09OHM
2016
2.2UH-20%-2.7A-0.09OHM
2016
PDM9655BGA
21 3 2
21 3 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SYM 4 OF 6
LREG
VREG_L1VREG_L2VREG_L3VREG_L4VREG_L5VREG_L6VREG_L7VREG_L8VREG_L9
VREG_L10VREG_L11
VREG_L13VREG_L12
VDD_L4VDD_L3_8
VDD_L1_2VDD_L1_2
VIN_VPH1VIN_VPH2
VDD_L5_6VDD_L7VDD_L9VDD_L10_11_12_13
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
SREG
SYM 6 OF 6
GND_S1GND_S1GND_S1
VDD_S1
VDD_S1VDD_S1
GND_S1
GND_S2
VDD_S2
VDD_S3
GND_S3GND_S3
VDD_S3
GND_S4
VDD_S4
GND_S5GND_S5
VDD_S5VDD_S5
VREG_S1
VSW_S1VSW_S1VSW_S1
VREG_S2
VSW_S2
VSW_S3VSW_S3VSW_S3
VREG_S3
VSW_S2
VREG_S4
VSW_S4
VREG_S5
VSW_S5VSW_S5
MAV PLATFORMMAV17.0MAV17.1MAV17.2MAV17.3
2 ROW
ROW 4
51.1K180K
9 A
SKU
28K CARRIER/DEV5
66.5K
R408
PA_THERM2
0.55V-0.65V
51.1K16.5K7.87K 51.1K
NOSTUFF
3
51.1KR431
10K
SPARE
0.15V-0.25V
51.1K105K0.75V-0.85V
PROTO2/DEV4
NOSTUFF
422KROW
3
EVT
51.1K0.35V-0.45V
105K
3RD TYPE
SPARE
51.1K
0.35V-0.45V
NOSTUFF10K1.75V-1.85V
HW_REV_ID
0.15V-0.25V
0.55V-0.65V PROTO1/DEV3PROTO2.5/DEV251.1K
51.1K
180K422KNOSTUFF
R407<0.10V
51.1K
0.95V-1.05V1.15V-1.25V
1.35V-1.45V
7 6
5
1
6
51.1K
8
44.2K66.5K
16.5K7.87K
1.55V-1.65V
1.35V-1.45V
1.15V-1.25V
JPN_ROW_SEL
1.75V-1.85V
<0.10V0.15V-0.25V
51.1K51.1K
1.15V-1.25V
1.55V-1.65V
1.35V-1.45V
51.1K 7
MLBJPN
JPNROWJPN 9
51.1K28K
0.95V-1.05V
0.55V-0.65V
MAV17.8MAV17.9
JPN
0.00V-0.10V
ROW
0.35V-0.45V
MAV17.7MAV17.6MAV17.5MAV17.4
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
JPN
Y 0
51.1K
R430
R410
28K0.95V-1.05V
7.87KNOSTUFF
POR MLB (FF)
5 4
SPARE
44.2K0.75V-0.85V
16.5K51.1K
PRODUCT TYPERADIO DEV
2
COMPARED TO PREVIOUS SCH
51.1K
51.1K51.1K
DVT/DEV6PVT/DEV7
Y 1
MLB/RADIO_DEVT500/DEV1PROTO1.5
51.1K
SPARESPARESPARE
51.1K51.1K
180K105K
44.2K66.5K
422KNOSTUFF
8
RF PMIC: XTAL, CLOCKS AND MISCELLANEOUS
NOTE XTAL SYMBOL MIRRORED10K1.55V-1.65V
1.75V-1.85V
R40951.1K51.1K51.1K
SPARESPARE
51.1K0.75V-0.85V
56 OF 81
R407_E
C404_E
R408_E
R413_E
Y401_E
C401_E
XW2_E
R430_E
R431_E
R409_E
R410_E
R411_ER412_E
R416_E
R417_E
R418_E
R422_E
XW1_E
R403_E
R401_E
R402_E
R415_E
XW3_E XW404_E
R405_E
C407_E
U_PMIC_E
U_PMIC_E
U_PMIC_E
C403_E
C402_E
R404_E
C405_E
C406_E
U_PMIC_EXO_OUT_D0_EN_E22 6
PP_1V8_LDO5_E13 3 4 5 8 11 12 15 16 20
BOARD_REV_ID_E 4
OPT_1_E 4
NFC_TO_BB_CLK_REQ2
XO_GND_E
JAPAN_ROW_SEL_E 4
PP_1V8_LDO5_E20 16 15 13 12 11 8 5 4 3
XTAL_38P4M_OUT_E
PP_1V8_LDO5_E20 16 15 13 12 11 8 5 4 3 BOARD_REV_ID_E4
DISPLAY_TO_MANY_BSYNC22 2
JAPAN_ROW_SEL_E4
PP_1V8_SMPS4_E3
XO_THERM_E
50_SLEEP_CLK_32K_E 22 6
OPT_2_E 4
BB_SIM1_REMOVAL_ALARM_E 7
PON_E4
GND_RF_CLK_XW_E
50_WTR_38P4M_CLK_R_E 4
PMIC_CBLPWR_L_E4
PON_E4
SPMI_DATA_E22 6
PMIC_CBLPWR_L_E4
PS_HOLD_E6 OPT_2_E4
VREG_RF_PMIC_E
REF_BYP_PMIC_E
PS_HOLD_PMIC_E
PMU_TO_BB_USB_VBUS_DETECT21 2
PMIC_RESOUT_L_E22 6
SPMI_CLK_E22 6
VREF_DAC_E 9
VREF_PX_BIAS_E 5
XTAL_38P4M_IN_E
VREG_XO_PMIC_E
OPT_1_E4
DVDD_BYP_PMIC_E4
50_MDM_19P2M_CLK_E 22 6
GND_XO_XW_E
PMIC_PA_THERM1_E 4
PP_1V8_LDO5_E
QPOET_PMIC_ADC_E10
50_WTR_38P4M_CLK_E 8 50_WTR_38P4M_CLK_R_E4
PP_1V8_LDO6_E 21 10 8 7 6 5 3
BB_VREF_LPDDR2_E 6
PMIC_ECM_ADC_IN_E
PMIC_PA_THERM1_E4
PRODUCT_TYPE_E4
PRODUCT_TYPE_E 4
GND_REF_XW_E
VREF_LPDDR_E
DVDD_BYP_PMIC_E4
AVDD_BYP_PMIC_E
10.0.0
4 OF 22
051-02159
2
1
2
1
2
1
2
1
4
3
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
21
21
21
2
1
2 1
21
21
21
21
2
1
2
1
21
2
1
80
839282
91
81
4645
37
26
7167
70
516261
47
25
27
40
38
56
60 17
715
35
50394930
48
18 16
8
28
2
1
2
1
21
2
12
1
8887
56557877
896636975724
1067969595811
16890
PDM9655BGA
RADIO_PMIC
X5R-CERM
0.1UF20%6.3V
01005
X5R-CERM20%6.3V
01005
RADIO_PMIC
0.1UF
0.00
0%
MF1/32W
RADIO_PMIC
01005
CER-X6S16V
0402RADIO_PMIC
1UF10%
X5R-CERM
0.1UF20%
RADIO_PMIC
6.3V
01005
PDM9655BGA
BGA
PDM9655
BGA
PDM9655
NOSTUFFRADIO_PMIC
CERM5%47PF16V
01005
1/32WMF
0%
0.00
RADIO_PMIC01005
ROOM=PMUSHORT-10L-0.1MM-SM
SHORT-10L-0.1MM-SMROOM=PMU
1/32W0%
MF
RADIO_PMIC
0.00
01005
RADIO_PMIC
MF1/32W5%
20.0K
01005
NOSTUFF
1.00K
1%1/32WMF
RADIO_PMIC
01005
MF
RADIO_PMIC
0.00
0%1/32W
NOSTUFF01005
RADIO_PMIC
SHORT-10L-0.1MM-SM
10K
RADIO_BB
1%
MF01005
0.00
1/32WMF
NOSTUFF0%
RADIO_PMIC01005
RADIO_PMIC
0%
MF
0.00
1/32W
01005
0%
0.00
NOSTUFF1/32WMF
RADIO_PMIC01005
1501/32W
RADIO_PMIC
1%
MF
NOSTUFF
01005
RADIO_PMIC
1%150
MF1/32W
NOSTUFF
01005
1/32WMF
1%
01005
5%1/32W
180K
MF01005
1/32W1%51.1K
MF
5%1/32W
180K
1000PF
38.4MHZ-10PPM-7PF
RADIO_PMIC
1.6X1.2-SM
RADIO_PMIC
MF1/32W1%100K
NOSTUFF 01005
1%
MF1/32W
51.1K
01005
X5R6.3
RADIO_PMIC
4.7UF20%
0402-0.1MM
PMIC: CLOCKS & CONTROL
CRITICAL ROW1
JPNCRITICAL1
BB_TO_NFC_CLK
AP_TO_BBPMU_RADIO_ON_L
AP_TO_BB_RESET_L
PMU_TO_BBPMU_RESET_L
PMU_TO_BBPMU_RESET_L
PMU_TO_BBPMU_RESET_L
10%6.3VX5R-CERM01005RADIO_PMIC
SHORT-10L-0.1MM-SM
R430_E
R430_E
01005OMIT_TABLE
01005MF
51.1K
117S0197
118S0686
ROOM=PMU
1/32W
16.5K1%1/32WMF01005
RESISTOR, 01005, 180K OHMS
RESISTOR, 01005, 105K OHMS
2 22
2
2 21
2 4
2 4
2 4
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
NC
NC
NC
NC
SYM 3 OF 6
GPIO
OPT_1OPT_2
GPIO_07GPIO_08GPIO_09GPIO_10
GPIO_02GPIO_01
GPIO_04GPIO_03
GPIO_05GPIO_06
SYM 5 OF 6
MISC
PON_1RESIN*
BAT_ID_THERM
PA_THERM3PA_THERM2PA_THERM1
VBUS_DET
EXT_ECM
PON_RST*
SPMI_CLKSPMI_DATA
KPD_PWR*
PS_HOLD
VREF_MDM
AVDD_BYP
DVDD_BYP
VDD_MDM_IO
REF_BYP
GND_REF
VREF_LPDDR
VREF_WTR
CLKS
SYM 1 OF 6
BB_CLK_EN
XTAL_OUT
GND_XO_CLK
GND_XOADC
XO_THERM
XTAL_IN
VDD_XO_RF VREG_RF
LN_BB_CLKRF_CLK1RF_CLK2RF_CLK3
GND_RF_CLK
GND_XO
VREG_XO
SLEEP_CLK
GND
SYM 2 OF 6GNDGND
GNDGNDGND
GNDGND
GNDGND
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
DO WE NEED TO POWER VDD_P2 FOR SECURE DIGITAL?
BB:POWER
57 OF 81
C535_E
C530_E
C503_E
C540_E
C536_EC556_E
C515_E
C518_E
C511_E
C517_E
C541_E
C505_E
C520_E
C522_E
C521_E
P501_E
C534_EC528_E
XW501_E
C527_E
XW502_E
C524_E
C514_EC510_EC508_E
U_MDM_E
C519_EC516_E
C513_E
C512_EC509_EC506_EC504_E
C507_E
C502_EC501_E
C554_E
C555_E
C551_EC548_EC545_E
C552_E
C553_E
C549_E
C550_E
C546_E
C547_EC544_E
C542_E
C543_E
U_MDM_E
C537_EC531_EC525_E
C538_E
C539_E
C532_E
C533_E
C526_E
C529_EC523_E
U_MDM_E
PP_0V8_SMPS1_E 3 5
PP_VDD_AON_EVOLTAGE=1.00V
PP_1V2_LDO2_E 3 5
PP_1V8_LDO6_E 3 4 5 6 7 8 10 21
PP_0V9_LDO4_E 3 5 PP_UIM1_LDO11_E3 21
PP_3V0_LDO10_E 3
QLINK_0V9_E
PP_0V9_LDO4_E3 5
PP_1V8_LDO6_E3 4 5 6 7 8 10 21
PP_1V2_LDO2_E3 5
PP_1V8_LDO6_E3 4 5 6 7 8 10 21
VOLTAGE=1.8V
PP_0V9_LDO4_E 3 5
VREF_PX_BIAS_E 4
VDD_DDR_CORE_1P2_G1_E
PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 16 20
PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 16 20
PP_UIM2_LDO13_E3
PP_0V8_LDO9_E3 5
PP_0V8_SMPS5_E3 5
PP_0V8_SMPS1_E 3 5
PP_0V8_LDO9_E 3 5
PP_0V8_LDO9_E3 5
PP_0V8_SMPS5_E3 5
PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 16 20
10.0.0
5 OF 22
051-02159
2
1
2
12
1
21
2
1
2
1
2
1
2
1
2
1
2
1
2
12
1
2
1
2
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
W11U16
C15
C13B14
B17
E16
C16
C8B7
F17
F12
E12
C11B10
AA19AA7
AA10
AA12
AA17AA4U21
T2L1E2
C10A3
AA15
N21N20
N2M2
K21K20F21F20B21B20
T1H21E1A20
P1N1M21J20G1C20
T11
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
P10P9N9N8M8M7M6L7K10K9K6J9J8H8H7H6G10G9F7F6
U17U15U12T17T12T6R17P6N17N16M19M16M15M12M11M5L15L11
L10K17
K5J19J17J16H16H15H12H11
H5G15G11F11
F9F8F5
E19D19
T16T15
T8T7
R15R14R11R10
R7P14P13N13N12L14K14K13J13J12H13G14F16F15
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
AA21AA20
AA18AA14AA11AA9AA8AA5AA1V21U1T14T13T10T9T5R16R13R12R9R8R6R5R1P21P17P16P15P12P11P8P7N19N15N14N11N10N7N6M20M17M14M13M10M9M1L21L20L19L17L16L13L12L9
L8L6L5
K16K15K12K11K8K7K1
J21J15J14J11J10
J7J6J5
H20H14H10
H9G21G20G19G17G16G13G12
G8G7G6G5
F19F14F13F10
F1E21E20E15E10D4D1
C21C19C18C14C12
C9C7
B19B18B16A21A19A18A16A12A7A4A1
CAP,TYPICAL,2.2UF,6.3V,0201,MURATA2138S0831 C520_E,C521_E,C522_E TYPICAL_CAP
CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C520_E,C521_E,C522_E SOFT_CAP2138S00159 BB: POWER
10%6.3V
1.0UF
X5R-CERM0201-1
10%6.3V
1.0UF
X5R-CERM0201-1
10%6.3VX5R-CERM0201-1
1.0UF
10%6.3V
0201-1
1.0UF
X5R-CERM
10%6.3V
0201-1X5R-CERM
1.0UF10%6.3V
0201-1X5R-CERM
1.0UF
10%6.3V
1.0UF
X5R-CERM0201-1
10%6.3V
0201-1X5R-CERM
1.0UF
10%6.3VX5R-CERM0201-1
1.0UF
10%6.3V
0201-1X5R-CERM
1.0UF
10%6.3V
0201-1
1.0UF
X5R-CERM
10%6.3V
1.0UF
0201-1X5R-CERM
6.3V
OMIT_TABLE0201
20%2.2UF
X5R-CERM
6.3V
2.2UF20%
0201OMIT_TABLE
X5R-CERM
6.3VX5R-CERM
OMIT_TABLE
20%
0201
2.2UF
SMP2MM-NSM
01005
6.3VX5R-CERM20%0.1UF
01005
6.3VX5R-CERM
0.1UF20%
SHORT-10L-0.1MM-SM
ROOM=PMU
6.3VX5R
0.22UF20%
01005-1
SHORT-10L-0.1MM-SM
ROOM=PMU
01005
6.3V0.1UF
X5R-CERM20%
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
BGA
MDM9655
01005
6.3V20%0.1UF
X5R-CERM01005
6.3V0.1UF20%X5R-CERM
01005
6.3VX5R-CERM
0.1UF20%
01005
6.3V0.1UF
X5R-CERM20%
01005
6.3VX5R-CERM
0.1UF20%
01005
6.3VX5R-CERM
0.1UF20%
01005
6.3VX5R-CERM
0.1UF20%
01005
6.3V20%X5R-CERM
0.1UF
01005
6.3VX5R-CERM
0.1UF20%
01005
6.3V20%X5R-CERM
0.1UF
01005X5R-CERM6.3V0.1UF20%
01005
6.3V0.1UF20%X5R-CERM
6.3VX5R-CERM01005
0.1UF20%
0.1UF
01005
6.3V20%X5R-CERM
0.1UF
01005
6.3V20%X5R-CERM
01005
6.3V0.1UF20%X5R-CERM
01005
6.3V0.1UF20%X5R-CERM
01005
6.3V0.1UF20%X5R-CERM
01005
6.3V0.1UF20%X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3VX5R-CERM
0.1UF20%
X5R-CERM01005
6.3V0.1UF20%
6.3VX5R20%0.22UF
01005-1
6.3VX5R
0.22UF20%
01005-1
BGA
MDM9655
0.22UF20%X5R6.3V
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
6.3VX5R
0.22UF20%
01005-1
BGA
MDM9655
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_5_ITEM
PP
SYM 8 OF 8PWM2
VDD_QLINK_CLK_0P9
VDD_DDR_CORE_1P8VDD_DDR_CORE_1P8
VDD_PCIE_1P8
VDD_P1
VDD_P3
VDD_PCIE_0P9
VDD_P1
VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2
VDD_USB_HS_3P1
VDD_DDR_CORE_1P8
VDD_USB_HS_1P8
VDD_USB_SS_1P8
VDD_DDR_CORE_1P8
VDD_DDR_CORE_1P2VDD_DDR_CORE_1P2
VREF_SDCVREF_UIM
VDD_QLINK_IO_0P9
VDD_PLL
VDD_QFPROM_PRG
VDD_ALWAYS_ON
VDD_P1
VDD_P1VDD_P1
VDD_P1
VDD_P2
VDD_P3VDD_P3
VDD_P3
VDD_P1VDD_P1VDD_P1VDD_P1
VDD_P4
VDD_P5
VDD_P3VDD_P3VDD_P3VDD_P3
VDD_P7VDD_P7
VDD_PCIE_0P9
VDD_USB_HS_0P9
VDD_USB_SS_0P9VDD_USB_SS_0P9
PWM1
SYM 7 OF 8
VDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEM
VDD_MODEMVDD_MODEMVDD_MODEM
VDD_MODEMVDD_MODEM
VDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEM
VDD_MEMVDD_MEM
VDD_MEM
VDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEMVDD_MODEM
VDD_MEM
VDD_MEM
VDD_MEMVDD_MEM
VDD_MEM
VDD_MEM
VDD_MEMVDD_MEM
VDD_MEMVDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEMVDD_MEM
VDD_COREVDD_COREVDD_COREVDD_COREVDD_CORE
VDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_COREVDD_CORE
VDD_MEMVDD_MEMVDD_MEM
VDD_MEMVDD_MEMVDD_MEM
VDD_MEMVDD_MEM
VDD_MEMVDD_MEMVDD_MEM
VDD_MEMVDD_MEM
VDD_MEMVDD_MEM
VDD_MEM
VDD_MEMVDD_MEM
VDD_MEM
SYM 4 OF 8
GNDGNDGND
GNDGNDGND
GNDGND
GNDGND
GND
GNDGNDGND
GNDGND
GNDGND
GNDGND
GND
GND
GNDGND
GNDGNDGND
GND
GND
GNDGND
GNDGND
GNDGNDGND
GNDGND
GND
GNDGND
GNDGND
GNDGND
GND
GNDGND
GND
GNDGNDGND
GND
GNDGND
GNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GND
GNDGND
GNDGND
GND
GNDGND
GNDGND
GND
GNDGND
GNDGND
GND
GNDGND
GNDGND
GND
GNDGND
GND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GND
PCIE_BB_TO_AP_TX CAPS ARE MOVED TO AP PAGE TO BE CONSISTENT WITH D1X
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
NOTE: NO STUFF BUFFER FOR EUREKA CONFIG
BB: CONTROL & HS PERIPHERALS
58 OF 81
C603_E
P601_E
U2_E
R606_E
R607_E
U_MDM_E
R605_ER604_E
R603_E
U_MDM_E
R602_E
U_MDM_E
R601_E
BB_JTAG_TMS_E6 21
BB_JTAG_TRST_L_E
90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P
BB_BDM_ZQ_E90_PCIE_AP_TO_BB_REFCLK_P
BB_JTAG_TCK_E6 21
PP_1V8_LDO6_E3 4 5 7 8 10 21
PS_HOLD_E 4
BB_JTAG_TCK_E 6 21 SWD_AOP_TO_MANY_SWCLK2
BB_JTAG_TMS_E 6 21 SWD_AOP_BI_BB_SWDIO2
BB_EBI1_CAL_E
BB_USB_HS_TXRTUNE_E
90_USB_BB_DATA_N2 21
PCIE_CAL_RES_E
90_PCIE_AP_TO_BB_REFCLK_N
90_USB_BB_DATA_P2 21
50_SLEEP_CLK_32K_E4 22
PMIC_RESOUT_L_E4 22
BB_JTAG_RST_L_E21
50_MDM_19P2M_CLK_E4 22
XO_OUT_D0_EN_E4 22
SPMI_DATA_E 4 22
SPMI_CLK_E 4 22
90_PCIE_BB_TO_AP_RXD_N 2 6 90_PCIE_BB_TO_AP_RXD_N6
90_PCIE_BB_TO_AP_RXD_P6 90_PCIE_BB_TO_AP_RXD_P 2 6
90_PCIE_AP_TO_BB_REFCLK_P 2 6 22
90_PCIE_AP_TO_BB_REFCLK_N 2 6 22
90_PCIE_AP_TO_BB_TXD_P 2 6
90_PCIE_AP_TO_BB_TXD_N6
90_PCIE_AP_TO_BB_TXD_P6
90_PCIE_AP_TO_BB_REFCLK_P6
90_PCIE_BB_TO_AP_RXD_N
90_PCIE_BB_TO_AP_RXD_P
90_PCIE_AP_TO_BB_TXD_N
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_REFCLK_N
90_PCIE_AP_TO_BB_REFCLK_P
SS_CAL_RES_E
90_PCIE_AP_TO_BB_REFCLK_N6
BB_VREF_LPDDR2_E4
90_PCIE_AP_TO_BB_TXD_N 2 6
10.0.0
6 OF 22
051-02159
2
1
1
4
51
3
2
21
21
N5 H19
H17K19
P5
D2
2
1
2
1
2
1
B13A13
A15B15
A14A17
E17C17
A11B11
A9B9
A10
E13E14
B12
2
1
W14Y12
W13U14
U13
V20
AA13Y13
Y2
W16AA16Y15W15Y14Y16
N3
P3
M3
R3R2
L2E11
2
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BB: CONTROL & HS PERIPHERALS [6]
6.3V
RADIO_BB
X5R-CERM01005
20%0.1UF
22 6 2
22 6 2
6 2
6 2
6 2
6 2
SMP2MM-NSM
74AUP1G34GXSOT1226
NOSTUFF
0.00
0%1/32W
01005MF
RADIO_PMIC
01005
1/32WMF
0%
RADIO_PMIC
0.00
BGA
MDM9655
6
6
1/32WMF01005
1%
RADIO_BB
2401/32WMF01005
1%
RADIO_BB
240
6
6
6
6
RADIO_BB
1%1/32W
100
01005MF
RADIO_BB
BGA
MDM9655
1/32WMF01005
1%
RADIO_BB
4.02K
BGA
MDM9655
1/32WMF01005
1%
RADIO_BB
100
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
OUT
OUT
OUT
OUT
OUT
OUT
PP
NCNC
NC
NC
MEMORYSYM 6 OF 8
VREF_DQ_BDM
BDM_ZQ
EBI1_CALVREF_DQ1VREF_DQ0VREF_LPDDR2
IN
IN
OUT
OUT
IN
IN
NC
NC
NCNC
NC
NCNC
NCNC
NCNC
NC
USB_PCIE
SYM 1 OF 8
USB_HS_DP
PCIE_REFCLK_PPCIE_REFCLK_M
PCIE_TX_PPCIE_TX_M
PCIE_RX_PPCIE_RX_M
PCIE_REXT
USB_HS_DM
NC
USB_SS_TX_PUSB_SS_TX_M
USB_SS_RX_PUSB_SS_RX_M
USB_SS_REXTUSB_HS_REXT
CONTORL
SYM 3 OF 8
SDC1_CLKSDC1_CMD
SDC1_DATA_0
SDC1_DATA_2SDC1_DATA_3
SPMI_CLKSPMI_DATA
SDC1_DATA_1
RESOUT*PS_HOLDCXO_EN
CXO
SRST*RESIN*
SLEEP_CLK
MODE_0MODE_1
TCKTRST*TMSTDITDO
NCNC
DEFAULT CONFIG
EUREKA CONFIG
DEVIATE FROM MAV13
I2C MOVE PER EUREKA
PER EUREKA
PER RFSW. MOVED TO PIN50
MPM
NOR SPI STATUS - RF DEV ONLY
PCIE_AP_TO_BB_DEV_WAKE
CONFIGURABLE BY DIP SWITCH
BB EEPROM
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUESTBB:GPIOS & QLINK
59 OF 81
PP702_E
PP701_E
R715_E
R714_E
U_MDM_E
U_MDM_E
R702_EC701_E
R701_E
U_EEPROM_E
R801_E
R713_E
R716_E
R717_E
75_RFFE2_SDATA_E75_RFFE2_SDATA_E7
75_RFFE2_SCLK_E75_RFFE2_SCLK_E7
BB_TO_PMU_PCIE_HOST_WAKE_L 2 7
BB_SIM1_REMOVAL_ALARM_E
UAT_TUNER_RFFE_CLK 2
PP_1V8_LDO6_E3 4 5 6 7 8 10 21
PP_1V8_LDO6_E3 4 5 6 7 8 10 21
UAT_TUNER_RFFE_DATA 2 UAT_TUNER_RFFE_DATA7
UAT_TUNER_RFFE_CLK7
75_RFFE3_SDATA_E 11 12 13 22 75_RFFE5_SDATA_E7
FAST_BOOT_SELECT1_E 7
UAT_TUNER_RFFE_CLK 7
UAT_TUNER_RFFE_DATA 7
75_RFFE3_SDATA_E 7
FAST_BOOT_SELECT0_E7
75_RFFE6_SDATA_E7
WMSS_RESET_L_E8
75_RFFE6_SCLK_E7 AP_TO_BB_MESA_ON
PCIE_AP_TO_BB_RESET_L
AP_TO_BB_IPC_GPIO1
BB_EEPROM_I2C_SDA_E7
BB_EEPROM_I2C_SCL_E7
PCIE_BB_BI_AP_CLKREQ_L
QLINK_REQ_W0_E 7
BB_GNSS_LNA_EN_E
QLINK_EN_W0_E 7
AP_TO_BB_COREDUMP
QLINK_EN_W0_R_E
QLINK_REQ_W0_R_E
BB_TO_PMU_PCIE_HOST_WAKE_L2 7
QLINK_EN_W0_E7
QLINK_REQ_W0_E7
QLINK_CLK_N_E
QLINK_CLK_P_E
75_RFFE6_SDATA_E 10 11 12 13 22
75_RFFE6_SCLK_E 10 11 12 13
75_RFFE6_SDATA_E7
75_RFFE5_SCLK_E7
BB_TO_STROBE_DRIVER_GSM_BURST_IND
75_RFFE6_SCLK_E7
75_RFFE5_SDATA_E 17
75_RFFE5_SCLK_E 17
FAST_BOOT_SELECT1_E7
QLINK_DL1_P_E
QLINK_DL0_N_E
QLINK_UL0_N_E
QLINK_UL0_P_E
QLINK_DL2_N_E
QLINK_DL2_P_E
QLINK_DL1_N_E
PP_1V8_LDO6_E3 4 5 6 7 8 10 21
FAST_BOOT_SELECT0_E7
75_RFFE2_SDATA_E 7
75_RFFE2_SCLK_E 7
LAT_TUNER_RFFE1_CLK 7
BB_SIM1_DATA_E
BB_SIM1_DETECT_E
BB_SIM1_RST_E
BB_SIM1_CLK_E
LAT_TUNER_RFFE1_DATA 7
LAT_TUNER_RFFE1_CLK7
LAT_TUNER_RFFE1_DATA7
75_RFFE3_SCLK_E7 75_RFFE3_SCLK_E 11 12 13
75_RFFE3_SDATA_E7
PCIE_BB_BI_AP_CLKREQ_L2 7
PP_1V8_LDO6_E 3 4 5 6 7 8 10 21
BB_EEPROM_I2C_SDA_E 7 BB_EEPROM_I2C_SCL_E7
75_RFFE3_SCLK_E 7
75_RFFE5_SDATA_E 7
75_RFFE5_SCLK_E 7
QLINK_DL0_P_E
10.0.0
7 OF 22
051-02159
1
12
1
2
1
Y11U11T19W12K2L3J1J3Y4Y19U19H3R21W20Y17W17V19P19Y3W6R19Y20R20W21P20Y21W19G3W18Y18T3U2U3V2V1V3B3B8A8A2
G2F3B2B1C1C2C3D3E3F2H2H1J2K3
T21T20W9W7Y7Y9
AA6Y6U7U9W4Y5U6W5U8W8U5Y8W1W2W3Y1
U10W10U20Y10
2
1
2
1
2
1
A2A1
B2B1
2
1
2
1
21
21
E6E7
B6A6
C6C5
A5B5
E9E8
AA3AA2P2
D21D20
C4B4
MAKE_BASE=TRUE
MAKE_BASE=TRUE
UART_BB_TO_WLAN_COEX
AP_TO_BB_TIME_MARK
UART_WLAN_TO_BB_COEX
BB_TO_AP_RESET_DETECT_L
I2S_AP_TO_BB_DOUT
I2S_BB_TO_AP_DINI2S_BB_TO_AP_BCLK
UART_AOP_TO_BB_TXD
UART_BB_TO_AOP_RXD
I2S_BB_TO_AP_LRCLK
UART_WLAN_TO_BB_COEX
LAT_TUNER_RFFE1_DATAMAKE_BASE=TRUE
LAT_TUNER_RFFE1_CLKMAKE_BASE=TRUE
PP1V8_S2
UART_BB_TO_WLAN_COEX
BB: GPIOS & QLINK
22 8
22 8
22 8
22 8
22 8
22 8
22 8
22 8
22 8
22 8
SMP2MM-NSM
P2MM-NSMSM
8 2
8 2
16
16
RADIO_BB01005
1%10K1/32WMF
NOSTUFF
10K1/32W
RADIO_BB
MF01005
1%
22 2
RADIO_BB
BGA
MDM9655
22 20
22 2
22 2
22 2
2
7 2
2
4
21
21
21
21
22 2
22 2
22 2
MDM9655BGA
22 2
22 2
1/32W
RADIO_BB
1%10K
01005MF
1UF
RADIO_BB
X5R0201
10V20%10K
1/32WMF
1%
01005RADIO_BB
CAT24C08C4A
RADIO_BBWLCSP
MF
100K5%1/32W
01005
100K5%
MF1/32W
01005
8
8
0.00
1/32WMF
0%
01005
RADIO_WTR
RADIO_WTR1/32WMF
01005
0%
0.00
21 7 2
21 7 2
22 2
22 2
21 7 2
2
21 7 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNC
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
PP
PP
OUT
BI
OUT
BI
IN
NC
GPIO
SYM 5 OF 8
GPIO_13GPIO_12
GPIO_46
GPIO_59GPIO_60GPIO_61
GPIO_54
GPIO_21GPIO_22
GPIO_55
GPIO_11GPIO_10GPIO_9
GPIO_14
GPIO_58GPIO_57GPIO_56
GPIO_70GPIO_71GPIO_72
GPIO_36
GPIO_79GPIO_78GPIO_77GPIO_76GPIO_75GPIO_74GPIO_73
GPIO_69GPIO_68GPIO_67GPIO_66GPIO_65GPIO_64GPIO_63GPIO_62
GPIO_53GPIO_52GPIO_51GPIO_50GPIO_49GPIO_48GPIO_47
GPIO_45GPIO_44GPIO_43GPIO_42GPIO_41GPIO_40
GPIO_39GPIO_38GPIO_37
GPIO_35GPIO_34GPIO_33GPIO_32GPIO_31GPIO_30GPIO_29GPIO_28GPIO_27GPIO_26GPIO_25GPIO_24GPIO_23
GPIO_20GPIO_19GPIO_18GPIO_17GPIO_16GPIO_15
GPIO_8GPIO_7GPIO_6GPIO_5GPIO_4GPIO_3GPIO_2GPIO_1GPIO_0 OUT
OUT
OUT
IN
BI
BI
IN
BI
BI
IN
OUT
OUT
NC
NC
NCNCNCNC
OUT
IN
IN
NC
NC
NCNC
NCNC
SYM 2 OF 8
ANALOG_RF
NCNC
NCNC
NCNCNC
QLINK_DL0_M
QLINK_CLK_PQLINK_CLK_MQLINK_DL0_P
QLINK_DL1_P
QLINK_UL0_PQLINK_UL0_M
QLINK_DL1_MQLINK_DL2_PQLINK_DL2_M
NC
NCNC
NC
NC
NC
NCNC
NCNC
NC
NC
NCNCNC
NCNC
NCNC
NCNC
NC
NC
OUT
OUT
VCC
VSS
SDASCL
NC
OUT
OUT
NCNC
TRANSCEIVER: QLINK & POWER
C801 AND C803 TO 0.1UF PER EUREKA
SHARE WITH PIN 233
SHARE WITH PIN 233
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
ROUTING
PLACE C827 ATCENTER OF STAR
REMOVE 1.2V OPTION PER EUREKA
60 OF 81
R808_E
C819_E
C820_EC821_E
C826_E
C823_E
C817_E
C825_E
C824_E
C827_E
C818_E
C822_E
R807_E
C807_E
R806_E
C804_E
C815_E
C812_E
C814_E
C811_E
C805_E
C810_E
C806_E
C808_E
C816_E
C809_E
C802_E
R812_E
R811_E
U_WTR_E
U_WTR_E
R810_E
C801_E
C803_E
WMSS_RESET_L_E7
75_RFFE1_SDATA_WTR_E
QLINK_EN_W0_R_E7
75_RFFE1_SCLK_WTR_E
QLINK_UL0_N_E 7 22
QLINK_CLK_P_E 7 22
QLINK_CLK_N_E 7 22
QLINK_DL0_N_E 7 22
QLINK_DL2_P_E 7 22
PP_1V0_LDO8_E
PP_1V0_LDO3_E3 8
VOLTAGE=1.0VPP_1V0_LDO8_FILT_E
PP_1V0_LDO3_E3 8
PP_1V0_LDO3_E3 8
PP_1V0_LDO3_FILT_EVOLTAGE=1.0V
PP_1V0_LDO3_E3 8
WTR_VDD_1P0_RX0_E
PP_1V2_LDO1_E3 8 12
ETDAC_QPOET1_N_E10
ETDAC_QPOET1_P_E10
50_GNSS_WTR_IN_E20
50_WTR_38P4M_CLK_E4
PP_1V0_LDO8_E 3 8
PP_1V2_LDO1_E 3 8 12 PP_1V0_LDO3_E 3 8
PP_1V8_LDO5_E3 4 5 8 11 12 13 15 16 20
PP_1V0_LDO3_E3 8
PP_1V0_LDO8_E3 8
QLINK_UL0_P_E 7 22
QLINK_DL1_P_E 7 22
QLINK_DL1_N_E 7 22
QLINK_DL0_P_E 7 22
PP_1V2_LDO1_E 3 8 12
PP_1V2_LDO1_E3 8 12
PP_1V2_LDO1_E3 8 12
PP_1V8_LDO5_E 3 4 5 8
11
12
13
15
16
20 PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 16
20
PP_1V0_LDO3_E 3 8
PP_1V8_LDO5_E
PP_1V8_LDO5_E3 4 5 8 11 12
13 15
16
20
PP_1V0_LDO3_E 3 8
PP_1V2_LDO1_E3 8 12
PP_1V2_LDO1_E3 8 12
PP_1V2_LDO1_E3 8 12
PP_1V8_LDO5_E3 4 5 8 11 12 13 15 16 20
PP_1V2_LDO1_E3 8 12
PP_1V8_LDO5_FILT_EVOLTAGE=1.8V
PP_1V0_LDO3_E3 8
QLINK_DL2_N_E 7 22
PP_1V8_LDO6_E3 4 5 6 7 10 21
PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 16 20
PP_1V0_LDO3_E3 8
QLINK_REQ_W0_R_E7
10.0.0
8 OF 22
051-02159
21
21
251
2
91137 233
67
58
69
44
162
146
125179
192
18
49
218
37
77
13056
184
121
20831
215150
117
9351
41
222
114
50
212211200199167188198177166123
155
232110187
144164
210
197
209231219196186165
175153
20
247
244243242220
207
17817615414513412211110099
57
3422
1110
75
2342467587
253
252
241230
229
135
113
112101
19
21
2
1
2
1
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1 2
121
2
1
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
LAT_TUNER_RFFE1_DATA
LAT_TUNER_RFFE1_CLK
XCVR
01005
0%
MF
0.00
1/32W
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
NOSTUFF
01005
6.3V20%0.1UF
X5R-CERM
NOSTUFF
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
NOSTUFF
6.3V4.7UF20%X5R-CERM1402
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM01005
0.00
0%
MF1/32W
6.3V4.7UF20%
402X5R-CERM1
01005
0%
MF1/32W
0.00
6.3V4.7UF20%
402X5R-CERM1
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
NOSTUFF
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
01005
0.00
MF1/32W0%
01005MF
1/32W0%
0.00
WTR5975CSP
WTR5975CSP
01005MF
1/32W0%
0.00
01005
6.3V20%0.1UF
X5R-CERM
01005
6.3V20%0.1UF
X5R-CERM
7 2
7 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NCNCNCNCNCNCNC
NC
NC
NC
NCNCNCNC
NC
NC
NCNC
NC
NC
NCNC
SYM 2 OF 5
DNC
VDD_1P2_ANA
VDD_1P2_STG
VDD_1P0_TX0
VDD_1P2_TX0
VDD_1P8_TX0
VDD_1P8_ANA0
VDD_1P0_TX1
VDD_1P8_TX1
VDD_1P8_ANA1
VDD_1P0_TX
DNC
VDD_1P0_XO
VDD_1P0_QLINKVDD_1P0_GNSS
VDD_1P0_RX0
DNCVDD_1P0_RX2
VDD_1P0_RX
VDD_1P2_ANA4VDD_1P2_ANA3
VDD_1P0_RX1
DNCDNCDNC
VDD_1P2_RX0VDD_1P2_ANA1VDD_1P2_RX1VDD_1P2_ANA2
VDD_1P8_FBRXVDD_1P8_ANA2
SYM 1 OF 5
GNDGNDGND
GND
GND
DNC
W_GRFC_9W_GRFC_8W_GRFC_7W_GRFC_6W_GRFC_5W_GRFC_4
W_GRFC_1
W_GRFC_3W_GRFC_2
W_GRFC_0
WMSS_RESET*
QLINK_EN
QLINK_REQ
ETDAC_CH0+ETDAC_CH0-
ETDAC_CH1-ETDAC_CH1+
DNCDNC
DNC
DNCDNC
GNSS_IN
DNCDNC
GND
GNDGNDGNDGND
GNDGNDGNDGNDGND
GND
GNDGND
GNDGNDGND
QLINK_DL0-QLINK_DL0+QLINK_DL1-QLINK_DL1+QLINK_DL2-QLINK_DL2+
DNC
QLINK_UL0+QLINK_UL0-
QLINK_CLK+QLINK_CLK-
DNCVDD_1P8_DIG
VDD_1P0_DIGVDD_1P0_DIGVDD_1P0_DIG
GNDGND
XO_IN
NC
NCNCNC
JPN = STUFF
STRIPLINE
ROW = STUFF
JPN = STUFF
TRANSCEIVER: TX & RX
ROW = STUFF
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
61 OF 81
U_WTR_E
U_WTR_E
U_WTR_E
R920_E
R922_E
R918_E
R919_E
R901_E
50_DRX_LHB_WTR_IN_E9
50_CPL2_CPLOUT_E17
50_DRX_HB_OUT2_UHB_LTEU_A_WTR_IN_E 16
50_DRX_HB_OUT1_MBHB_WTR_IN_E16
50_PRX_MLB1_DRX_MB_LHB_WTR_IN_E13
50_PRX_MB2_PAD_MB_B_WTR_IN_E12
50_PRX_MB1_PAD_MB_A_WTR_IN_E12
50_TX_UHB_WTR_E 13
50_PRX_LB2_WTR_IN_E11
50_PRX_UHB1_PAD_UHB_A_WTR_IN_E13
50_PRX_HB2_PAD_HB_A_WTR_IN_E12
50_PRX_HB1_PAD_LHB_WTR_IN_E12
50_FBRX_TERM_E
50_DRX_HB_WTR_IN_E 9
50_DRX_LHB_WTR_IN_E 9
50_DRX_LB_WTR_IN_E 20
50_DRX_MB_B_WTR_IN_E 9
VREF_DAC_E 4
50_TX_HB_WTR_E 12
50_TX_MB_WTR_E 12
50_TX_LB_WTR_E 11
50_TX_MLB_2G_WTR_E 13
50_DRX_MB_B_WTR_IN_E9
50_DRX_HB_WTR_IN_E9
10.0.0
9 OF 22
051-02159
92
103
115
163
74132
64131
66
84
248214
195194
193
190
182181
174
173172
161
160
159
158140
139
129128
127118
106
104
102
9583
81
79
71
63
62
53
52
43
38
3332
29
219
143
98108
65107
109
85
236224
202191
180157
116105
2827176
245
237
221
213
201
189
185
183
171
170
169168156
152
151
149148147
142
141
138136
133
126124
120
119
97
9694
90
89
88
868280
76
73
72
70
6160
55
54
42
40
39
30
8
235
238
249
225
216
250
226
153
416
3523
240239
228217
206205
204
203
7868
5948
474645
36
26
25
1413
227
223
24
121
21
2
1
21
21
21
01005 OR CRITICAL1 JPNR918_E117S0161
R919_E01005 OR117S0161 CRITICAL1 ROW
01005 OR R922_E117S0161 ROW1 CRITICAL
117S0161 1 01005 OR R920_E CRITICAL JPN
XCVR
CSPWTR5975
CSPWTR5975
WTR5975CSP
0.00
MF
OMIT_TABLE01005
0%1/32W
1/32W0.00
MFOMIT_TABLE01005
0%
1/32W
0.00
MF
OMIT_TABLE
0%
01005
MF1/32W0%
OMIT_TABLE01005
0.00
01005
1/32WMF
1%
49.9
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
SYM 4 OF 5
DNC
TX_FBRX-
DNC
DNCDNC
DNCDNC
DRX_MB_BDRX_UHB_LTEU_A
DNCDNC
DNCDNC
DRX_LB
DNC
DRX_UHB_LTEU_BDRX_MB_A
DRX_LHBDRX_HB
GNDGNDGNDGND
GNDGND
GND
GNDGNDGNDGNDGNDGND
GND
GNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGND
PRX_LBPRX_UHB_LTEU_APRX_MB_B
GND132
TX_FBRX+
PRX_HBPRX_LHB
GNDGND
GND
PRX_MB_APRX_UHB_LTEU_B
GND
GNDGND
GNDGND
GND
GND
GNDGND
GNDGNDGND
DNC
SYM 5 OF 5
GNDGNDGNDGND
GNDGND
GNDGND
GND
GNDGNDGND
GND
GNDGNDGND
GNDGND
GND
GNDGND
GND
GND
GND
GND
GNDGND
GND
GND
GNDGNDGNDGND
GND
GNDGND
GNDGND
GNDGND
GNDGNDGNDGNDGNDGNDGNDGNDGND
SYM 3 OF 5
TX_CH1_LTEUTX_CH1_MB2
TX_CH1_LMB1
TX_CH1_UHBTX_CH1_MB
TX_CH1_HB1
TX_CH0_LMBTX_CH0_LB2
TX_CH0_MB2TX_CH0_MB1
TX_CH0_HB2TX_CH0_HB1
DNCDNC
DNC
VREF_DACDNC
DNC
GND
GND
GNDGND
GND
GNDGND
GND
GND
GNDGND
GND
GNDGND
GNDGND
GNDGND
GNDGND
NC
NC
NC
NC NCNC
NC
NC
NC
NC
NC
NC
NC
NC
NCNCNCNCNCNCNCNCNCNCNCNC
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUESTQET:MODULE
62 OF 81
C1000_E
R1001_E
U_QET_EU_QET_E
C1001_E
R1006_E
PP_1V8_LDO6_E 3 4 5 6 7 8 21
PP_VDD_MAIN 10
ETDAC_QPOET1_N_E8
QPOET_VDD_1P8_E
PP_VDD_MAIN 10
QPOET_PMIC_ADC_E 4
VDD_AMP_DECOUPLING_E
PP_VDD_MAIN10
ETDAC_QPOET1_P_E8
QPOET_USID_E PP_QET_PA_E 11 12 13 VOLTAGE=4.0V
75_RFFE6_SCLK_E7 11 12 13
75_RFFE6_SDATA_E7 11 12 13 22
10.0.0
10 OF 22
051-02159
E9E8
E7E6E5
E4E3
E2
E1D9
D6D3D1
C9
C7C4C2C1B9B4B1A9A8A7A6A5A4A3A2A1
B3
D7B7
D5C6
D8C8
D2D4
B8
C3 B2
B6
C5B5
2
1
2
1
2
1
21
MAKE_BASE=TRUEPP_VDD_MAIN
QPOET MODULE
01005X5R10%6800PF6.3V
0.00
0%
01005MF
1/32W
P215LGA-1
P215LGA-1
0402-10
6.3VX5R
10UF20%
01005MF1/32W0%0.00
21 3 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
NC
SYM 2 OF 2
GNDGND
SYM 1 OF 2
DAC-
VCC_PA_GSM1VCC_PA_GSM0
SCLK
VDD_
1P8
VBAT
_SW
VBAT
SDAT
A
ECM_OUT
VCC_PA_ET1
VDD_
AMP
VIN_BOB
DAC+
USID_LSB VCC_PA_ET0
NC
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
LB PAD
63 OF 81
C1102_E
L1101_E
C1116_E
L1102_E
R1108_E
R1105_E
C1111_ER1103_E
C1109_EC1104_EC1115_E
R1107_E
C1107_E
C1105_E
C1103_E
R1101_E
R1104_E
L1103_E
PA_LB_E
PA_LB_E
C1112_E
C1110_E
PP_QET_PA_E10 12 13
PP_VDD_BOOST3 12 13 17
PP_1V8_LDO5_E 3 4 5 8 12 13 15 16 20
50_LBPAD_2G_OUT_E
75_RFFE3_SCLK_E7 12 13
LB_SNUBBER_E
50_PRX_LB2_WTR_IN_E9
50_TX_LB_WTR_E9
75_RFFE3_SDATA_E7 12 13 22
PP_1V8_VIO_RX_E3 12 13
75_RFFE6_SDATA_E7 10 12 13 22
50_PAD_ANT_LB_E
50_LBPAD_2G_OUT_2G_CPL_IN_JPN_E 17
50_PAD_ANT_LB_CPL2_IN_E 17
PP_1V8_LDO6_E3 12 13 17 VOLTAGE=1.8V
75_RFFE6_SCLK_E7 10 12 13
PP_V
CC1_
LB_P
A_E
VOLTAGE=4.0V
50_TX_LB_PA_IN_E
PP_1V8_VDD_LNA_LB_PAD_EVOLTAGE=1.8V
10.0.0
11 OF 22
051-02159
21
2
1
G14G13G12G11G10G9G8G7G6G5G4G3G2F14F13F12F11F10F9F8F7F6F5F4F3F2E14E13E12E11E10E9E8E7E6E5E4E3E2D14D13D12D11D10D9D8D7D6D5D4D3C14C13C12C11C10C9C8C7C6C5C4C3C2B15B14B13B11B10B9B8B7B6H14H13H11H10H9H8H7H6H5H4H3
J16J15J14J13J12J11J10
J9J8J7J6J5J4J3J2J1
H16H1
G16G1
F16F1
E16E1
D16D1
C16C1
B16B1
A16A15A14A13A12A11A10
A9A8A7A6A4A5A3A2A1
H15
B4 B2C15
D15
E15
B12
G15
B3 F15
B5
D2
H2
H12
2
1
2
1
2
1
2
1
2
1
2
1
21
21
2
1
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
21
1 CRITICAL JPNR1108_E118S0724 2G LB MATCH, 0 OHMS
JPNCRITICALR1104_E1152S00021 6.8NH UHQ, LB ANT MATCH
LB PAD
ROWCRITICALR1104_E152S2006 1 6.2NH UHQ, LB ANT MATCH
CRITICAL JPN1131S0555 L1101_E1PF, LB ANT MATCH
1 JPNCRITICAL131S0176 L1102_E2.4PF, 2G LB MATCH
10%
01005
10V
180PF
CERM
25VCOG-CERM0201RADIO_LB_PADOMIT_TABLE
+/-0.05PF0.5PF
01005CERM
RADIO_LB_PAD
16V
NOSTUFF
5%47PF
020110NH-3%-250MA
RADIO_LB_PAD
OMIT_TABLE
0.00
MF1/20W
0201OMIT_TABLE
RADIO_LB_PAD
1%
01005
1%
MF1/32W
1.00
01005NOSTUFF
RADIO_LB_PAD
47PF
CERM16V5%
01005
0.000%
MF1/32W
RADIO_LB_PAD01005
RADIO_LB_PAD
47PFCERM5%16V
01005
6.3V20%0.1UF
RADIO_LB_PAD
X5R-CERM10%
01005
10V470PF
X5R
01005MF
1/32W1%
1.00 NOSTUFF
01005
16VCERM
NOSTUFFRADIO_LB_PAD
47PF5%
01005CERM
NOSTUFF
16V5%47PF
RADIO_LB_PAD
01005
RADIO_LB_PADNOSTUFF
16V47PF
CERM5%
01005
RADIO_LB_PAD
0.00
1/32W0%
MF
0201OMIT_TABLE
6.8NH-3%-0.4A-0.3OHM
0201
1.8PF+/-0.05PF25VC0G-CERM
SKY78140LGA
LGASKY78140
6.3VX5R
0.22UF20%
01005-1
10%
01005CERM
180PF10V
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
SYM 2 OF 2
GND
THRM_PADTHRM_PAD
THRM_PAD
GNDGND
GND
GNDGND
GNDGNDGNDGNDGND
GND
GNDGND
GNDGND
GNDGND
GND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GND
GNDGND
GNDGNDGNDGNDGNDGND
GNDGNDGND
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
SYM 1 OF 2
PRX_LB
LB_ANT
TX_LB_IN
VDD_
LNA
VCC1
VBAT
T
SCLK
_RX
SDAT
A_RX
VCC2
LB_2G_ANT
SDAT
A_TX
SCLK
_TX
VIO
_TX
VIO
_RX
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
HB PAD
64 OF 81
PA_HB_E
PA_HB_E
PA_HB_E
C1212_E
R1211_E
C1209_E
R1210_E
R1206_E
R1202_E
C1202_E
C1201_E
R1209_E
C1205_ER1203_E
C1211_E
R1207_E
C1204_E
C1200_E
C1207_E
R1201_E
C1203_E
C1206_E C1208_E
R1205_E
PP_1V2_LDO1_E 3 8
50_TX_HB_WTR_E9
HB_SNUBBER_EPP_1V8_LDO5_E 3 4 5 8 11 13 15 16 20
50_PAD_ANT_HB_CPL2_IN_E 17 50_PAD_ANT_HB_MATCH_E
VOLTAGE=1.2VPP_1V2_VDD_LNA_HB_PAD_E
75_RFFE3_SDATA_E7 11
13
22
50_HBPAD_2G_OUT_E
50_TX_MB_PA_IN_E
50_TX_HB_PA_IN_E
PP_1V8_VIO_RX_E3 11 13
75_RFFE3_SCLK_E7 11 13
PP_1V8_LDO6_E3 11 13 17
75_RFFE6_SDATA_E7 10 11 13 22
75_RFFE6_SCLK_E7 10 11 13
PP_VDD_BOOST3 11 13 17
PP_VCC1_HB_PA_EVOLTAGE=4.0V
PP_QET_PA_E10 11 13
PP_1V8_VDD_LNA_HB_PAD_EVOLTAGE=1.8V
50_PRX_MB1_PAD_MB_A_WTR_IN_E9
50_PAD_ANT_HB_E
50_2G_HB_PA_OUT_CPL2_IN_E17
50_TX_MB_WTR_E9
50_HBPAD_2G_OUT_MATCH_E
50_PRX_HB1_PAD_LHB_WTR_IN_E9
50_PRX_HB2_PAD_HB_A_WTR_IN_E9
50_PRX_MB2_PAD_MB_B_WTR_IN_E9
10.0.0
12 OF 22
051-02159
390389388387386385384383382381380379378377376375374373372371370369368367366365364363362361360359358357356355354353352351350349348347346345344343342341340339338337336335334333332331330329328327326325324323322321320319318317316315314313312311310309308307306305304303302301300299298297296295294293
292291290289288287286285284283282281280279278277276275274273272271270269268267266265264263262261260259258257256255254253252251250249248247246245244243242241240239238237236235234233232231230229228227226225224223222221220219218217216215214213212211210209208207206205204203202201200199198197196195
194193192191190189188187186185184183182181180179178177176175174173172171170169168167166165164163162161160159158157156155154153152151150149148147146145144143142141140139
138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108
107106105104103102101100
999897969594939291908988878685848382818079787776757473727170696867666564635861605957565554535251504948474645444342393735333127262221191615131110
97654321
2328 401718 4120
12
14 8
2530 2429
38
36
34
32
62
2
1
21
2
1
2121
21
21
2
1
21
2
1
21
21
2
1
2
1
2
121
2
1
2
121
152S2000 2.0NH UHQ, HB ANT MATCH R1210_E ROW1 CRITICAL
131S0329 ROWC1209_E1 0.4PF, HB ANT MATCH CRITICAL
CRITICAL1 JPN1.8NH UHQ, HB ANT MATCH152S2042 R1210_E
HB PAD
CRITICAL JPNR1209_E152S2023 3.2NH UHQ, 2G HB PAD MATCH1
131S0425 JPN1 CRITICALC1209_E0.5PF, HB ANT MATCH
JPNR1211_E1NH UHQ, 2G HB PAD MATCH152S00153 1 CRITICAL
LGAHB-PAD-AFEM-8072
HB-PAD-AFEM-8072LGA
HB-PAD-AFEM-8072LGA
0201
25V
1PF+/-0.05PF
C0G-CERM
OMIT_TABLERADIO_HB_PAD
0201
2.4NH+/-0.1NH-0.6A
0201
25VC0G
+/-0.05PF0.8PF
OMIT_TABLE
1.4NH+/-0.1NH-1.1A
0201OMIT_TABLE
RADIO_HB_PAD
01005MF
0%1/32W
0.00
MF1/20W5%
0
201
NOSTUFF
NP0-C0G16V
10PF
01005
5%
NOSTUFF
16VNP0-C0G01005
10PF5%
0.00
1/20W
0201RADIO_HB_PAD
OMIT_TABLE
MF
1%
RADIO_HB_PAD
47PF
01005CERM5%16V
NOSTUFF
RADIO_HB_PAD
0.00
0%
MF1/32W
01005
470PF
X5R10%10V
01005
1/32W
01005
1%
NOSTUFF1.00
MF
C0G-CERM
0.5PF+/-0.05PF
RADIO_HB_PAD
16V
NOSTUFF
01005
01005NP0-C0G
27PF
5%16V
RADIO_HB_PAD
10%
RADIO_HB_PAD
1000PF6.3VX5R-CERM01005
RADIO_HB_PAD
0.00
1/32W0%
MF01005
C0G-CERM+/-0.05PF0.5PF
01005RADIO_HB_PAD
NOSTUFF
16V
1UF
RADIO_HB_PAD
CER-X5R16V20%
0201
0.1UF
01005
20%X5R-CERM6.3V
RADIO_HB_PAD
1/32W0%
RADIO_HB_PAD
MF01005
0.00
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
SYM 3 OF 3
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PAD THRM_PAD
THRM_PADTHRM_PAD
SYM 2 OF 3
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PAD
THRM_PADTHRM_PADTHRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
THRM_PADTHRM_PADTHRM_PAD
THRM_PADTHRM_PAD
GNDGND
GNDGND
GNDGND
GND
GND
GND
GND
GNDGND
GND
GNDGND
GND
GNDGND
GND
GNDGNDGNDGNDGND
GNDGND
GND
GNDGND
GNDGNDGND
GNDGND
GNDGND
GNDGND
GNDGND
GND
GNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGNDGND
GNDGND
GNDGNDGND
GNDGND
GNDGND
GND
GNDGNDGNDGND
GNDGND
GND
GNDGND
GNDGND
GNDGND
GNDGND
GNDGNDGND
GNDGND
GND
GND
GNDGND
GND
GNDGND
GNDGNDGND
GND
GNDGNDGNDGNDGND
GNDGNDGND
GNDGND
GNDGNDGNDGND
GND
GNDGND
GNDGNDGND
GNDGNDGNDGND
SYM 1 OF 3
VDD_
LNA
SDAT
A_RX
PRX_HB2
PRX_HB1
PRX_MB2
TX_2GHB_OUT
TX_MB_IN
TX_HB_IN
VIO
_RX
SCLK
_RX
VIO
_TX
SDAT
A_TX
SCLK
_TX
VBAT
TVC
C1VC
C2
VBIA
S_LN
A
PRX_MB1
ANT
THESE ARE ONLY STUFFED FOR ROW CONFIG.
JPN = STUFF
UHB/2G PAD -JPNCONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
65 OF 81
C1320_E
PA_UHB_E
PA_UHB_E
C1319_E
C1321_E
L1310_E
C1318_E
C1312_E
R1305_E
C1323_E
L1302_E
R1309_E
L1301_E
R1300_E
C1316_E
C1322_E
R1308_E
C1301_E
R1303_E
C1308_E
C1307_E
R1302_E
C1305_E
C1302_E
C1306_E
C1311_E
R1307_E
R1304_E
R1306_E
C1317_E
PP_1V8_LDO5_E 3 4 5 8 11 12 15 16 20
UHB_SNUBBER_E
50_TX_UHB_WTR_E9
PP_1V8_VDD_LNA_UHB_PAD_EVOLTAGE=1.8V
PP_V
CC1_
UHB_
PA_E
VOLTAGE=4.0V
50_PAD_ANT_MLB1_E
50_TX_UHB_IN_E
50_PRX_MLB1_DRX_MB_LHB_WTR_IN_E9
50_PRX_UHB1_PAD_UHB_A_WTR_IN_E9 50_2G_LB_PA_OUT_E
75_RFFE3_SDATA_E7 11 12 22
PP_1V8_LDO6_E3 11 12 17
PP_VDD_BOOST 3 11 12 17
50_TX_MLB_2G_WTR_E9 50_TX_MLB_2G_IN_E
50_PAD_ANT_UHB2_E
50_UHBCPL_OUT_2G_CPL_IN_E 17
50_TRX_UHB_LAT_DIPLEXER_IN_E 18
75_RFFE3_SCLK_E7 11 12
75_RFFE6_SDATA_E7 10 11 12 22
75_RFFE6_SCLK_E7 10 11 12
50_PAD_ANT_UHB1_E
50_UHBPAD_2G_LB_PA_OUT_2G_CPL_IN_E 17
50_PAD_MLB1_2G_HB_CPL2_IN_E 17
PP_1V8_VIO_RX_E3 11 12
PP_QET_PA_E 10 11 12
10.0.0
13 OF 22
051-02159
K9K8K7K6K5K4K3J9J8J7J6J5J4J3I9I8I7I6I5I4I3H9H8H7H6H5H4H3G9G8G7G6G5G4G3F9F8F7F6F5F4F3E9E8E7E6E5E4E3D9D8D7D6D5D4D3C9C8C7C6C5C4C3
M11M10
M9M8M7M6M5M4M3M2M1
L11L7L3L1
K11K10
K2K1
J11J10
J1I11I2I1
H11H10
H2H1
G11G1
F11F2F1
E11E10
E1D11
D2D1
C11C1
B11B10
B9B8B7B5B3B1
A11A10
A9A8A7A6A5A4A3A2A1
L10
L4 B6G10
F10
I10
C10
D10
L8L6 L9L5
B2
B4
C2
J2
G2
E2
L2
2
1
2
1
2
1
2
1
2
1
21
2
1
2
1
21
2
1
21
2
1
2
1
21
2
1
21
2
1
2
1
21
2
1
2
1
2
1
21
2
1
21
2
1
2
1
2
1
50_UAT_TRX_UHB_MCS
1 R1307_E0 OHMS UHB2 OUT/DRX BP MCH1 CRITICAL JPN117S0002
C1312_EUHB LNA DECOUPLING, 0.1UF JPNCRITICAL1132S0316
R1300_E JPN1117S0161 CRITICALUHB LNA SUPPLY FILTER, 0OHMS
C1311_E JPN1131S0214 CRITICALVBAT DECOUPLING,18PF
C1323_E138S0692 VBAT DECOUPLING, 1UF CRITICAL JPN1
R1304_E117S0161 VCC2/VCC1 RESISTOR OPTION, 0 OHM JPNCRITICAL1
C1318_E22NH, MLB1 ANT MATCH152S1999 JPNCRITICAL1
152S1688 3.5NH, UHB1 ANT MATCH L1310_E1 CRITICAL JPN
131S0431 0.2PF, UHB TO METROCIRC C1320_E CRITICAL JPN1
CRITICAL1 JPNUHB PAD353S01243 PA_UHB_E
1 JPNCRITICAL117S0161 MLB/2GTX IN MCH2, 0 OHMS R1302_E
UHB PAD
117S0161 CRITICAL JPN1 R1303_EUHB INPUT MCH1, 0 OHMS
117S0002 1 R1305_E CRITICAL JPNMLB/2G MB OUT MCH1, 0 OHMS
R1306_E JPNCRITICAL2.7PF UHQ, UHB1 ANT MATCH1131S0552
0.5PF+/-0.05PF
NOSTUFF
25VCOG-CERM0201
RADIO_UHB_PAD
SKY78141LGA
OMIT_TABLE
LGASKY78141
OMIT_TABLE
7.5NH+/-0.3%-0.4AOMIT_TABLE0201
16V+/-0.1PF5PF
01005NP0-C0G
0201OMIT_TABLE
7.5NH+/-0.3%-0.4A
OMIT_TABLE020115NH-3%-0.3A-0.7OHM
6.3V20%
01005OMIT_TABLE
X5R-CERM
0.1UF
RADIO_UHB_PADOMIT_TABLE
2NH+/-0.1NH-0.6A
0201
6.3V1.0UF20%X5R0201-1
OMIT_TABLERADIO_2G_PA
10NH-5%-250MA
NOSTUFF0201
RADIO_2G_PA
1/20WMF0201
OMIT_TABLE
1%
RADIO_2G_PA
0.00
RADIO_2G_PA
NOSTUFF020110NH-5%-250MA
0%
MF
0.00
1/32W
01005OMIT_TABLE
6.3V20%0.1UF
01005X5R-CERM
01005X5R10V10%
NOSTUFF
470PF
1.00
01005
1/32W1%
MF
NOSTUFF
NOSTUFF
RADIO_UHB_PAD
CERM16V
01005
18PF5%
OMIT_TABLE
01005MF
1/32W0%
0.00
RADIO_UHB_PAD
+/-0.05PF
NOSTUFF01005C0G-CERM16V
RADIO_UHB_PAD
0.5PF
NOSTUFF
C0G-CERM16V0.5PF+/-0.05PF
RADIO_UHB_PAD
01005
OMIT_TABLE
1/32WMF
0%
RADIO_UHB_PAD
01005
0.00
RADIO_UHB_PAD
5%16V
01005CERM
18PF
NOSTUFF
01005NOSTUFF
18PF
CERM16V5%
RADIO_UHB_PAD
18PF
CERM5%
01005
RADIO_UHB_PAD
16V
NOSTUFF
RADIO_UHB_PAD
16V5%18PF
OMIT_TABLE01005CERM
RADIO_UHB_PAD
1/20W
0201OMIT_TABLE
0.00
1%
MF
01005OMIT_TABLE
RADIO_UHB_PAD
0.000%
MF1/32W
OMIT_TABLERADIO_UHB_PAD
0.00
1%
MF0201
1/20W
RADIO_UHB_PAD
5%CERM
18PF16V
01005NOSTUFF
2
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
SYM 2 OF 2
GND GND
SYM 1 OF 2VD
D_LN
A
VCC2
VBAT
TVC
C1
SDAT
A_TX
VIO
_TX
SCLK
_TX
SDAT
A_RX
VIO
_RX
SCLK
_RX
ANT_UHB1
ANT_UHB2
CPL_OUT3
ANT_MLB1
NC/GND
TX_MLB_IN
TX_UHB_IN
PRX_MLB1
PRX_UHB1
2G PA - ROWCONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
66 OF 81
10.0.0
14 OF 22
051-02159
ROWCRITICAL1 R1307_EUHB2 OUT/DRX BP MCH1, 0 OHMS118S0724
ROWCRITICAL1 R1304_EVCC2/VCC1 RESISTOR OPTION, 0 OHM117S0161
1 CRITICAL ROWC1323_EVBAT DECOUPLING, 1UF138S0692
CRITICAL ROWVBAT DECOUPLING,18PF C1311_E1131S0214
2G PA
50 OHM TERMINATION FOR ROW ONLY103S00089 ROWCRITICAL1 C1319_E
ROWCRITICALR1309_E1 4.7NH UHQ, 2G LB OUTPUT MCH2152S2053
ROWCRITICAL1 MLB/2G MB OUT MCH1, 0 OHMS R1305_E118S0724
ROWCRITICALUHB INPUT MCH1, 0 OHMS R1303_E1117S0161
R1302_E ROWCRITICAL117S0161 1 MLB/2GTX IN MCH2, 0 OHMS
2G PA1 PA_UHB_E ROWCRITICAL353S01247
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
METROCIRC
TO QUADPLEXER
TO DIPLEXERMETROCIRC
LB DSM
THEN MLB STRIPLINE
67 OF 81
C1504_E
L1504_E
R1506_E
L1502_E
DSM_LB_E
DSM_LB_E
FL1501_E
R1501_E
L1501_E L1503_E
R1508_E
R1507_E
50_DRX_LB_OUT_E
PP_1V8_LDO5_E 3 4 5 8 11 12 13 16 20
SDATA_HB_LB_DSM_FILT_E
50_DRX_LB_OUT_MATCH_E 50_DRX_LB_IN2_MATCH_E
PP_1V8_VDD_LNA_LBDSM_EVOLTAGE=1.8V
SCLK_HB_LB_DSM_FILT_E
VIO_HB_LB_DSM_FILT_E
50_DRX_LB_IN1_MATCH_E
50_DSM_TRX_LB_IN_LB_E50_DRX_LB_IN3_MATCH_E
10.0.0
15 OF 22
051-02159
2
1
21
2
1
20191816141211
65321
9 107 8
4
13
15
17
21
2
1
2
1
21
21
2
1
50_UAT_TRX_LB_MCW
50_LAT_DRX_LB_MCW
LB DSM
150PF
C0G25V5%
01005
19
20NH-3%-0.14A-2.26OHM01005
5%
12PF
16V
01005CERM
22NH-3%-0.14A-2.26OHM01005
BGASKY13760-19
SKY13760-19BGA
01005
0.00
0%
MF1/32W
20
0%1/32WMF
01005
0.00
16
010054.7NH-3%-0.270A
NOSTUFF
16
16
NOSTUFF
010054.7NH-3%-0.270A
MF
0%
0.00
1/32W
01005
MF
0%
0.00
1/32W
01005
2
2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
SYM 2 OF 2
GNDGND
GNDGNDGNDGNDGNDGNDGNDGND
GNDGND
SYM 1 OF 2
VDD
VIO
SDAT
ASC
LK
DRX_LB_IN_1
DRX_LB_IN_3
DRX_LB_OUT_1 DRX_LB_IN_2OUT
IN
IN
IN
TO METROCIRC
TO UAT4 ANTENNA
METROCIRC
METROCIRC
TO STRIPLINE
JPN = STUFF
STRIPLINE
ROW = STUFF
FROM HB_OUT1
METROCIRC
STRIPLINE
ROW = STUFF
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
TO QUADPLEXER
DECOUPLING SHARED WITH LB DSMHB DSM
JPN = STUFF
ROW = STUFF
68 OF 81
L1606_E
R1610_E
DSM_HB_E
DSM_HB_E
R1617_E
C1604_E
R1600_E
R1608_E
FL1601_E
R1607_E
L1602_E
R1602_E
R1601_E
L1601_E
R1603_E
L1603_E
R1609_E
C1601_E
C1603_E
C1602_E
L1604_E
L1605_E
L1607_E
R1612_E
R1611_E
R1615_E
L1608_E
R1613_E
50_DRX_HB_OUT1_MATCH_E
50_DRX_HB_OUT1_MBHB_WTR_IN_E
75_RFFE2_SDATA_E
PP_1V8_LDO6_E
PP_1V8_LDO5_E 3 4 5 8 11 12 13 15 20
75_RFFE2_SCLK_E
50_DRX_HB_OUT1_MBHB_WTR_IN_E
50_DRX_HB_OUT2_UHB_LTEU_A_WTR_IN_E
50_DRX_HB_OUT2_MATCH_E
50_DRX_HB_OUT3_MATCH_E
50_DRX_HB_IN1_MATCH_E
50_DRX_UHB_IN3_MATCH_E
VOLTAGE=1.8VPP_1V8_VDD_LNA_HBDSM_E
VIO_HB_LB_DSM_FILT_E15
SDATA_HB_LB_DSM_FILT_E15
50_DSM_HB_IN_TRX_MBHB_E
50_DRX_HB_IN2_MATCH_E
50_DRX_HB_IN3_MATCH_E
50_DRX_UHB_IN2_MATCH_E
50_DSM_HB_OUT1_MCU_ROW_E16
SCLK_HB_LB_DSM_FILT_E15
50_DSM_HB_OUT1_MCU_ROW_E 16
10.0.0
16 OF 22
051-02159
21
2
1
21
2
1
21
24221918171514121110
987531
26 2528 27
16
13
6
4
2
20
23
21
2
1
21
21
2
1
21
21
2
1
21
2
1
2
1
2
1
2
1
2
1
2
1
2
1
21
21
2
1
21
21
21
50_UAT_TRX_MLB_MB_HB_MCW
50_LAT_DRX_MLB_MB_HB_MCW
50_DSM_HB_IN_TRX_UHB
50_UAT_TRX_UHB_MCW
ROWCRITICAL01005 0R1117S0161 R1600_E
117S0161 1 01005 0R ROWR1602_E CRITICAL
01005 0R R1603_E1 JPNCRITICAL117S0161
CRITICAL JPN1 R1612_E152S1985 01005 1.7NH SHQ
R1617_E117S0161 1 01005 0R CRITICAL ROW
ROWCRITICAL1131S0639 01005 0.8PF L1606_E
1 JPNCRITICAL01005 0.6PF131S0616 L1606_E
HB DSM
0.8PF+/-0.05PF
01005C0G-CERM16V
OMIT_TABLE
1/32W
01005MF
0%
0.00
SKY13762BGA
BGASKY13762
0%
MF
0.001/32W
01005OMIT_TABLE
47PF16V5%
01005CERM
1/32W
0.00
OMIT_TABLE
0%
MF01005
01005
0%
MF1/32W
0.00
1/32W
01005
0%
MF
0.00
16 9
9
1/32W
0.00
0%
MF01005
16 9
4.7NH-3%-0.270A
NOSTUFF
01005
0%
0.00
MF1/32W
OMIT_TABLE01005
1/32W0%
01005MF
0.00
NOSTUFF
010054.7NH-3%-0.270A
0%1/32W
OMIT_TABLE01005MF
0.00
01005
NOSTUFF
4.7NH-3%-0.270A
0.00
01005
0%
MF1/32W
5%16VCERM
47PF
NOSTUFF
01005
25VCOG01005
120PF5%
01005
47PF5%16VCERM
NOSTUFF
4.7NH-3%-0.270A
NOSTUFF
01005
3
NOSTUFF
010054.7NH-3%-0.270A
01005
NOSTUFF
4.7NH-3%-0.270A
0%1/32WMF
0.00
OMIT_TABLE01005
7
0%
01005
1/32W
0.00
MF
19 2
19
0%1/32WMF
0.00
01005
0.4PF16V
NOSTUFF
+/-0.05PF
C0G01005
01005
1.0NH-+/-0.1NH-0.9A-0.05OHM
7
2
2
2
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALTABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 2 OF 2
GND
SYM 1 OF 2DRX_HB_IN1
VDD
VIO
SCLK
SDAT
A
DRX_HB_IN3
DRX_HB_IN2
DRX_UHB_IN3
DRX_UHB_IN2
DRX_HB_OUT1
DRX_HB_OUT2
DRX_HB_OUT3
OUT
OUT
OUT
IN
IN
IN
IN
IN
DUPLICATE SERIES TO PREVENT STUB
COUPLER2
METROCIRC
METROCIRC
METROCIRC
METROCIRC
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
69 OF 81
R1802_E
R1806_E
CPL2_E
CPL2_E
CPL2G_E
C1811_E
R1803_E
C1810_E
R1815_ER1812_E
R1807_E
L1802_E
C1803_E
R1808_E
L1801_E
C1804_E
R1814_E
R1813_E
R1810_E
R1809_E
C1805_E
R1804_E
C1801_E
C1802_E
C1806_E
R1801_E
C1807_E
C1808_E
C1809_E
50_2G_CPL_OUT_E
50_2G_HB_PA_OUT_ROW_E
PP_1V8_LDO6_E3 11 12 13
50_LBPAD_2G_OUT_2G_CPL_IN_JPN_E11 50_2G_LB_PA_OUT_CPL2_IN_E
50_2G_HB_PA_OUT_CPL2_IN_E12
PP_1V8_VIO_TX_CPL2_E
75_RFFE5_SDATA_E7
50_CPL2_CPLOUT_E9
50_CPL2_TRX_LB_E
50_PAD_MLB1_2G_HB_CPL2_IN_E13
50_UHBPAD_2G_LB_PA_OUT_2G_CPL_IN_E13
50_2G_CPL_OUT_CPL2_IN_E17
50_PAD_MLB1_CPL2_IN_E
PP_VDD_BOOST 3 11 12 13
50_CPL2_DRX_HB_E
50_TRX_LB_LAT_DIPLEXER_IN_E 18
50_TRX_HB_LAT_DIPLEXER_IN_E 18
50_2G_CPL_IN_E
50_UHBCPL_OUT_2G_CPL_IN_E13
75_RFFE5_SCLK_E7
50_CPL2_DRX_LB_E
50_PAD_ANT_HB_CPL2_IN_E12
50_2G_CPL_OUT_CPL2_IN_E17
50_TRX_HB_LAT_E
50_TRX_LB_LAT_E
50_PAD_ANT_LB_CPL2_IN_E11
50_CPL2_TRX_HB_E
10.0.0
17 OF 22
051-02159
21
21
36342928262524222117161514131210
854
3 7
19
31
33
11
18
20
30
23
32
2 1
27
6
35
9
4
12
3
2
1
21
2
1
2121
21
2
1
2
1
21
2
1
2
1
2
1
2
1
21
2
1
2
1
2
1
21
2
1
2
1
2
1
2
1
2
1
21 50_LAT_DRX_LB_MCS
50_UAT_TRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCS
50_LAT_DRX_MLB_MB_HB_MCS
131S0431 0.2PF, CPLR HB LAT MATCH1 L1801_E CRITICAL JPN
118S0724 ROWR1810_E1 0201 0R CRITICAL
R1813_E1 ROWCRITICAL150PF, DC BLOCK FOR GSM131S00142
L1801_E0.1PF, CPLR HB LAT MATCH1131S00001 ROWCRITICAL
2.2NH, CPLR HB LAT MATCH R1807_E CRITICAL ROW1152S2044
2.6NH, CPLR HB LAT MATCH R1807_E152S00055 1 CRITICAL JPN
R1809_E JPNCRITICAL118S0724 0201 0R1
2.2PF, 2G LB MATCH131S0249 1 C1810_E JPNCRITICAL
1 8.2NH 2G LB MATCH152S2007 R1812_E CRITICAL JPN
R1814_E ROW1 0201 0R118S0724 CRITICAL
COUPLER2
1/20WMF0201
1%
0.00
RADIO_CLP2
68PF
0201
5%50VC0G
SKY13770LGA
LGASKY13770
LGALDJ0Q869M30CG015
WIFI
0.5PF
NOSTUFF
0.05PF
NP0-C0G0201
25V
0201-1
2.2NH+/-0.1NH-0.6A
OMIT_TABLE
NP0-C0G
+/-0.1PF16V
01005
1.0PF0201MF
1/20W
RADIO_CPL2
0.00
1%
0.00
0201MF
OMIT_TABLE
RADIO_CPL2
1%1/20W
0201
1.0NH-+/-0.05NH-1.1A-0.04OHM
RADIO_CPL2
OMIT_TABLE
150NH-5%-0.08ARADIO_CPL20201
10%
01005
180PF
CERM10V
01005
0.00
MF
0%1/32W
0201OMIT_TABLE
15NH-3%-0.3A-0.7OHM
6.3V
RADIO_CPL2
20%
01005X5R-CERM
0.1UF
0.001%
RADIO_CPL2
0201MF1/20W
OMIT_TABLE
OMIT_TABLE
0.001%
0201MF1/20W
RADIO_CPL2
0201OMIT_TABLE
RADIO_CPL2
1%
MF1/20W
0.00
0201OMIT_TABLE
1/20W1%
MF
RADIO_CPL2
0.00
01005
RADIO_CPL2
16V5%47PFCERM
1/20W
0.00
RADIO_CLP2
1%
MF0201
47PF
CERM01005NOSTUFF
RADIO_CPL2
16V5%
01005
16VCERM5%47PF
NOSTUFF
RADIO_CPL2
RADIO_CPL2
NOSTUFF
201
1.3PF+/-0.25PF25VCOG-CERM
0201MF
1/20W
RADIO_CLP2
1%
0.00
1.3PF+/-0.25PFCOG-CERM
RADIO_CPL2NOSTUFF
25V
201
25VCOG-CERM
1.3PF
201
NOSTUFF
RADIO_CPL2
+/-0.25PF
COG-CERM201
RADIO_CPL2
NOSTUFF
1.3PF+/-0.25PF25V
2
2
2
2
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICALREFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
SYM 2 OF 2
GNDGND
GNDGNDGNDGNDGND
GNDGNDGNDGNDGND
GNDGNDGND
GNDGND
GNDGND
SYM 1 OF 2
CPL_
OUT
1
TRX_LB_IN
RFFE
_DAT VIO
RFFE
_CLK
VDD
TX_2GLB
TRX_HB_IN
TX_2GHB
TRX_MLB_IN
RF_CPL3_IN
DRX_HB_OUT
TRX_HB_UAT
TRX_HB_LAT
TRX_LB_LAT
TRX_LB_UAT
DRX_LB_OUT
COUPLED_OUT TERMINATE
MAIN_OUTIN
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUESTLOWER ANTENNA
70 OF 81
FLTRI_E R1903_E
C1901_EL1901_E
50_TRX_LB_LAT_DIPLEXER_IN_E17
50_LHB_LAT1_MATCH_E
50_TRX_HB_LAT_DIPLEXER_IN_E17
50_TRX_UHB_LAT_DIPLEXER_IN_E13
10.0.0
18 OF 22
051-02159
1
3
5
98642
7 21
2
1
2
1
50_LHB_LAT1
ROW1 0.1PF, TRI ANT MATCH CRITICALL1901_E131S00001
1 R1903_E0.8NH UHQ, TRI ANT MATCH152S00151 ROWCRITICAL
1 CRITICAL0.6NH UHQ, TRI ANT MATCH R1903_E152S00147 JPN
1155S00297 CRITICALDIPLEXER, L+MLBMHB ROWFLTRI_E
JPN1155S00298 FLTRI_E CRITICALTRIPLEXER, L+MLBMHB+UHB
LOWER ANTENNA
LGALFD2H829MMZ4E518
OMIT_TABLE
TRIPLEXER-LB-MB-HB 0.8NH-+/-0.05NH-1.1A-0.04OHM
0201OMIT_TABLE
020118NH+/-3%-0.250A
RADIO_CPL2NOSTUFF
25V+/-0.05PF
C0G-CERM0201RADIO_CPL2
0.3PF
OMIT_TABLE
2
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
ANT
UHBGND
LB
MLB-MB-HB
UAT & LB/UHB DIPLEXER CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
3 ELEMENT FOR 5GHZ ATTEN
71 OF 81
FLQPLX_E
R2002_E
L2011_E
C2001_E
C2002_E
50_GNSS_QPLEX_E
50_2G_WIFI_QPLEX_MATCH_E
50_DSM_HB_IN_TRX_MBHB_E
50_DSM_TRX_LB_IN_LB_E
10.0.0
19 OF 22
051-02159
1
17
13
9
15
1614121110876432
521
2
1
2
1
2
1
50_UAT_WLAN_2G_WEST
50_DSM_HB_IN_TRX_UHB
50_LMHGW_UAT1
UPPER ANTENNA
ACFM-W712-AP1LGA
01005
0.6NH-+/-0.1NH-0.95A-0.05OHM
18NH-3%-0.16A-1.63OHMNOSTUFF01005
15
20
16
01005CERM16V2%18PF
NOSTUFF
01005
16VCERM
18PF2%
NOSTUFF
16 2
2
2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
GNSS
MLB_MB_HBWIFI
ANT
LB
EPADGND
OUT
OUT
OUT
OUT
STRIPLINE
PLACE AT WTR END
GPS & GPS/LB DIPLEXER
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST 72 OF 81
C2101_E
R2103_E
FL2101_E
C2107_E
R2105_E
L2108_E
L2104_E
FL2102_E
C2102_E
L2106_E
L2105_E
LNA_GPS_E
L2101_E
R2101_E
L2103_E
L2102_E
R2102_E
L2109_E
BB_GNSS_LNA_EN_E
PP_1V8_LDO5_E
50_GNSS_QPLEX_E
VOLTAGE=1.8VPP_1V8_VDD_GLNA_E
50_GNSS_OUT_MATCH_E
50_DRX_LB_WTR_IN_E9
50_GNSS_DPLX_MCH_WTR_E
50_DRX_LB_DPLX_MCH_WTR_E
50_GNSS_IN_MATCH_E
50_GNSS_WTR_IN_E8
50_DRX_LB_GNSS_DPLX_E 50_DRX_LB_GNSS_DPLX_MATCH_E
50_DRX_LB_OUT_E
50_GNSS_DPLX_MATCH_E
10.0.0
20 OF 22
051-02159
46
5 3 1
2
2
1
21
21
2
164
531
2
2
1
2
1
4
5 7
3
9 8 6 2 1
2
1
21
2
1
2
1
21
2
1
21
2
1
21
GNSS
X5R-CERM01005
20%6.3V0.1UF
0.00
0%
01005MF
1/32W
15
DIPLEXER-LB-GNSS-MIRLGA
+/-0.1PF
NP0-C0G16V
010052.2PF
0.00
1/32W
01005
0%MF
01005-1
12NH-3%-140MA
1.0NH+/-0.1NH-0.580A01005NOSTUFF
LGADIPLEXER-LB-GNSS
NOSTUFF
18PF16V2%
01005CERM
1.0NH+/-0.1NH-0.580ANOSTUFF01005
010051.0NH+/-0.1NH-0.580A
NOSTUFF
22 7
LGASKY65790-11
1.0NH+/-0.1NH-0.580A01005NOSTUFF
19
01005
1/32W
0.00
0%
MF
16 15 13 12 11 8 5 4 3
NOSTUFF
1.0NH+/-0.1NH-0.580A01005
010051.0NH+/-0.1NH-0.580A
NOSTUFF
01005
0%
0.00
MF1/32W
1/32W
01005
0%
0.00
MF
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IN
COMMON
GND
GNSSLB
COMMON
GND
GNSSLB
IN
VCC
RFIN
LNA_EN
GND
RFOUT IN
IN
SELECT
FLEX 516S1184MLB 516S1185
DEBUG CONNECTOR
SIM CARD: CONNECTOR
SIM CARD
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE ONLY - NOT A CHANGE REQUEST
73 OF 81
R202_ER201_E
C3_EJ204_E
DZ202_E
C203_E
DZ203_E
DZ201_EJ_DEBUG_E
BB_SIM1_DETECT_E7 21
BB_SIM1_DATA_E7 21
BB_SIM1_CLK_E7 21 BB_SIM1_RST_E7 21
BB_SIM1_DATA_E7 21
PP_UIM1_LDO11_E3 5 21
PP_UIM1_LDO11_E 3 5 21
PP_1V8_LDO6_E3 4 5 6 7 8 10
BB_SIM1_CLK_E7 21
BB_SIM1_RST_E7 21
BB_SIM1_DETECT_E7 21
NFC_SWP
NFC_SWP
90_USB_BB_DATA_N 2 6
PP_UIM1_LDO11_E 3 5 21
BB_JTAG_RST_L_E
90_USB_BB_DATA_P 2 6
BB_JTAG_TMS_E6
BB_JTAG_TCK_E6
BB_SIM1_RST_EBB_SIM1_CLK_EBB_SIM1_DATA_ENFC_SWP 2 21
BB_SIM1_DETECT_E
PMU_TO_BB_USB_VBUS_DETECT2 4
10.0.0
21 OF 22
051-02159
5
4
32
1
363534333231302928272625242322212019181716151413121110987654321
42
41
4039
3837
2
1
2
1
2
1
1
6
9 8
2
7
161514131211105
3
2
12
1
2
1
UART_WLAN_TO_BB_COEX
PP_VDD_BOOST UART_BB_TO_WLAN_COEX
AP_TO_BB_RESET_L
PP_VDD_MAIN
SIM, DEBUG CONN
512S00017 SIMCRD,KYOCERABOM_TABLE_ALTS J204_E512S00026
1/32W1%
MF01005RADIO_BB
470K01005MF
RADIO_SIMCARD
1%15.00K1/32W
16V5%
RADIO_SIMCARD
100PF
NP0-C0G0100521 2
21 2
RCPT-WIDE-HSG-THICK-PIVOTF-RT-SM
01005RADIO_SIMCARD
12V-33PF20%6.3VX5R-CERM0201
2.2UF
RADIO_SIMCARD
5.5V-6.2PF0201
SMESDZV5-4BF4
6
21 7
21 7
21 7
21 7
20-5857-036-001-829F-ST-SM
NOSTUFF
7 2
3 2 7 2
4 2
10 3 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
IO
IO
GND
SIM_DETECTSIM_DETECT_GND
CLK
VCC
RESET
IO
SWP
GND
OUT
OUT
BI
IN
IN
OTHERS
UART
BB PROBE POINTS
RFFE
LAYOUT: VIA STUB AT WTR PINS
QLINK
SPMI
PWR SEQ
CTRL
LAYOUT: VIA STUB AT BB PINS
BASEBAND
I2S
CLKPCIE
LAYOUT: VIA STUB AT BB PINS
74 OF 81
PP35_E
PP41_E
PP22_E
PP20_E
PP23_EPP21_E
PP18_E
PP58_E
PP57_E
PP32_E
PP53_E
PP54_E
PP55_E
PP56_E
PP47_E
PP48_E
PP49_E
PP50_E
PP51_E
PP52_E
PP40_E
PP36_E
PP24_E
PP31_E
PP29_E
PP30_E
PP28_E
PP27_E
PP26_E
PP25_E
PP34_E
PP33_E
PP2_E
PP1_E
75_RFFE6_SDATA_E 7 10 11 12 13
75_RFFE3_SDATA_E 7 11 12 13
QLINK_UL0_P_E 7 8
QLINK_UL0_N_E 7 8
QLINK_CLK_P_E 7 8
QLINK_CLK_N_E 7 8
QLINK_DL0_P_E 7 8
QLINK_DL0_N_E 7 8
QLINK_DL1_P_E 7 8
QLINK_DL1_N_E 7 8
QLINK_DL2_P_E 7 8
QLINK_DL2_N_E 7 8
XO_OUT_D0_EN_E 4 6
50_SLEEP_CLK_32K_E 4 6
SPMI_CLK_E 4 6
SPMI_DATA_E 4 6
BB_TO_STROBE_DRIVER_GSM_BURST_IND2 7
PMIC_RESOUT_L_E 4 6
90_PCIE_AP_TO_BB_REFCLK_N2 6
AP_TO_BB_COREDUMP 2 7
AP_TO_BB_MESA_ON 2 7
BB_GNSS_LNA_EN_E 7 20 DISPLAY_TO_MANY_BSYNC
2 4
50_MDM_19P2M_CLK_E 4 6
90_PCIE_AP_TO_BB_REFCLK_P2 6
10.0.0
22 OF 22
051-02159
1
1
1
1
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I2S_BB_TO_AP_LRCLK
I2S_BB_TO_AP_DIN
UART_AOP_TO_BB_TXD
AP_TO_BB_TIME_MARK
I2S_AP_TO_BB_DOUT
I2S_BB_TO_AP_BCLK
BB_TO_AP_RESET_DETECT_L
UART_BB_TO_AOP_RXD
BB_TO_NFC_CLK
TEST POINTSSYNC_DATE=07/18/2016SYNC_MASTER=PROBE POINTS
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
P2MM-NSMSM
P2MM-NSMSMSM
P2MM-NSM
P2MM-NSMSM
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
SMP2MM-NSM
P2MM-NSMSM
P2MM-NSMSM
P2MM-NSMSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
SMP2MM-NSM
SMP2MM-NSM
P2MM-NSMSM
7 2
7 2
7 2
7 2
7 2
7 2
7 2
7 2
4 2
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
PP
PP
PP
PP
PPPP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
5/22/2017D21 RADIO_MLB_FF
75 OF 81
UAT_TUNER_RFFE_DATAPP1V8_S2
UAT_TUNER_RFFE_CLK
PP3V0_S2PP1V8_S2
051-02159
2017-06-06000892701210 ENGINEERING RELEASED
1 OF 4
10.0.0
SCH,MLB,D21
50_UAT_TRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCS
50_LAT_DRX_MLB_MB_HB_MCS
50_LMHGW_UAT1
50_LAT_DRX_LB_MCS
50_UAT_TRX_MLB_MB_HB_MCW
50_UAT_TRX_LB_MCW
50_LAT_WLAN_NORTH
50_UAT_TRX_UHB_MCS
50_UAT_TRX_UHB_MCW
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_SOUTH
50_UAT_WLAN_2G_WEST50_UAT_WLAN_2G_EAST
50_LAT_WLAN_MLC
BB_TO_LAT_GPO3BB_TO_LAT_GPO4
BB_TO_LAT_GPO1BB_TO_LAT_GPO2
LAT_TUNER_RFFE1_CLKLAT_TUNER_RFFE1_DATA
50_DSM_HB_IN_TRX_UHB
50_LAT_DRX_MLB_MB_HB_MCW
50_LAT_DRX_LB_MCW
50_LHB_LAT1
FRONT PAGE
76 50
78 50
78 50
78 50
78 50
78 50
78 50
78 50
76 50
76 50
76 50
76 50
77 50
78 77 50
77 50
78 77 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
76 50
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
IO
IO
IN
OUT
OUT
OUT
OUT
IN
IO
IO
IO
IO
IO
IN
IO
IO
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IN
IN
CHANGE TO 0.4NH
UHB/WIFI 5GHZ TEST
LB/MLB/MB/HB
METROCIRC
EAST MLB
UPPER MLB
NORTH-SOUTH METROCIRC
LOWER MLB
339S00297
LAT MLC
EAST-WEST METROCIRC
WEST MLB
WIFI 2.4GHZ TEST
339S00296
76 OF 81
L7751_EF
FL2002_EF
R7751_EF
MCNS_EF
L7753_EF
L7750_EFL7752_EF
JLAT_EF
MCEW_EF
R7752_EF
C7754_EFC7753_EF
C7751_EFC7752_EF
R7753_EF
JUAT2_EF
JUAT1_EF
50_W5G_DPX_IN_EF
50_UHB_W5G_UAT2_TEST_EF50_UHB_W5G_UAT2_EF
50_UAT_WLAN_5G_WEST_EF76
50_UAT2_M_EF 77
50_UAT1_TUNER_EF 77 50_LMHGW_UAT1_MATCH_EF 50_LMHGW_UAT1_TEST_EF
50_UAT_TRX_UHB_MCE_EF76
50_LAT_DRX_MLB_MB_HB_MCE_EF76
50_UAT_TRX_MLB_MB_HB_MCE_EF76
50_LAT_DRX_LB_MCE_EF76
50_UAT_TRX_LB_MCE_EF76
50_LAT_DRX_LB_MCE_EF76
50_LAT_DRX_MLB_MB_HB_MCE_EF76
50_UAT_WLAN_5G_WEST_EF 76
50_UAT_TRX_LB_MCE_EF76
50_UAT_TRX_UHB_MCE_EF76
50_UAT_TRX_MLB_MB_HB_MCE_EF76
10.0.0
2 OF 4
051-02159
50_DSM_HB_IN_TRX_UHB
50_UAT_TRX_MLB_MB_HB_MCS
50_LMHGW_UAT1
50_LHB_LAT1
50_LAT_WLAN_MLC
50_UAT_TRX_UHB_MCS
50_LAT_DRX_MLB_MB_HB_MCS
50_LAT_DRX_LB_MCS
50_LAT_WLAN_SOUTH
50_UAT_TRX_LB_MCS
50_UAT_TRX_UHB_MCW
50_LAT_DRX_MLB_MB_HB_MCW
50_UAT_TRX_LB_MCW
50_UAT_TRX_MLB_MB_HB_MCW
50_LAT_DRX_LB_MCW
50_UAT_WLAN_2G_WEST50_UAT_WLAN_2G_EAST
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_NORTH
METROCIRC
1 JPNB42/5G DIPLEXER 5G_IN MATCH131S0598 L7751_EF CRITICAL
1 ROWCRITICAL5G PASSTHROUGH INPUT MATCH131S0385 L7751_EF
ROWFL2002_EF1155S00275 5G PASSTHROUGH CRITICAL
155S00274 B42/5G DIPLEXER FL2002_EF1 CRITICAL JPN
MF1/32W
OMIT_TABLE
0.00
0%
01005
13
987542
6
LGA
OMIT_TABLEDPX255850DT-5156C1SJ
21
0201
1.3NH+/-0.1NH-1.1A
410286
12
201518231321
494847464544434241403938373635
343332312422191716141197531
SMFLTPSSL-516H
2
1
010051.0NH+/-0.1NH-0.22A-0.9OHMUATNOSTUFF
2
1
UATNOSTUFF
010051.0NH+/-0.1NH-0.22A-0.9OHM
2
1
1.0NH+/-0.1NH-0.22A-0.9OHM01005UATNOSTUFF
76
54321
M-ST-SMMM3929-2700A05
29272523211917
410
28
146
12
4241403938373635343332313028
262422201816151311
97531
FLTPSSL-515HSM
21 0
5%
201MF
1/20W
UAT
2
1
25V+/-0.05PF
0201UATNOSTUFF
0.5PF
COG-CERM2
1
+/-0.05PF0.5PF
0201
25V
UATNOSTUFF
COG-CERM
2
1
0201
NOSTUFF
+/-0.05PF
UAT
0.5PF25VCOG-CERM2
10.5PF
COG-CERM0201UAT
25V+/-0.05PF
NOSTUFF
21
201UAT
1/20W5%
MF
0
21
3
F-RT-SMMM8830-2600B
21
3
F-RT-SMMM8830-2600B
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50
75 50 75 50
75 50
75 50
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
GND
LBPHBP
COMMP
GNDGND
SIG1-S
SIG6-SSIG5-SSIG4-SSIG3-SSIG2-S
SIG6-NSIG5-NSIG4-NSIG3-NSIG2-NSIG1-N
SIGNAL3-WSIGNAL4-WSIGNAL5-W
SIGNAL7-WSIGNAL6-W
SIGNAL2-WSIGNAL1-W
SIGNAL7-ESIGNAL6-ESIGNAL5-ESIGNAL4-ESIGNAL3-ESIGNAL2-ESIGNAL1-E
GNDGND
C R
GND
C R
GND
UAT TUNER FLEX
COMPARED TO D20 & D201PINOUT IS ROTATED 180
FOR ANY COMPONENT CHANGE.
5G WIFI
ALT UAT1 GND
STANDOFFSTANDOFFLB/MLB/GNSS/MB/HB
GROUND RING
PLEASE CONTACT ANTENNA (MATT MOW)
UAT TUNER
77 OF 81
TUNFX_EF
FL6703_EFFL6700_EF
C6702_EF
C6701_EF
L7709_EF
C7731_EF
C7730_EF
L8004_EFL8003_EF
C6737_EF
L6701_EF
C6755_EF
SP2T1_EF
SP2T2_EF
L6753_EF
C6751_EF C6750_EF
L6750_EF
C6754_EF
L6752_EF
L6751_EF
C6753_EF
C6752_EF
L6702_EF
FL6701_EF
L8005_EF
L8007_EF
SUAT2_EF
SUAT1_EF
AGND_EF
FL6702_EF
UGND_EF
C6738_EF
C6733_EFC6732_EFC6731_EF
C6703_EF
C6736_EF
C6730_EFC6735_EFC6734_EF
C6705_EF
C8006_EFC8001_EF
C8005_EF
L8002_EF
C8004_EFC8003_EF
C8002_EF
L8001_EF
PP1V8_S250 75
UAT_TUNER_RFFE_CLK 50 75 78 UAT_TUNER_RFFE4_DATA_FILT_EF UAT_TUNER_RFFE4_CLK_FILT_EF
PP3V0_TRISTAR_UAT_TUNER_B2B_FILT_EFVOLTAGE=3.0V
PP3V0_S2 50 75 77 VOLTAGE=3.0V
UAT_TUNER_GPO1_EF78
PP3V0_S2 50 75 77 VOLTAGE=3.0V
UAT_TUNER_GPO4_EF78
UAT_TUNER_RFFE_DATA50 75 78
UAT_TUNER_GPO3_EF78
UAT_TUNER_GPO2_EF78
USP2T2_VDD_EF
USPST_VDD_EF
UAT_TUNER_GPO_FIL4_EF
USP2T2_RF2_EF
USP2T2_RF1_EF
UAT_TUNER_GPO_FIL3_EF
VDD_TUNER_RFFE_VIO_1V8_FILT_EF
50_UAT1_TUNER_EF 50_UAT1_FEED_EF
USPST_RF1_EF
ALT_GND_RF1_EF ALT_GND_RF2_EF
USPST_RF2_EF
ALT_GND_RF_EF
PP3V0_S250 75 77
50_UAT2_M_EF76 50_UAT2_FEED_EF
CHASSIS_GND_EF 77
USP2T2_RF2_NOTCH_EF
CHASSIS_GND_EF77
50_UAT1_NOTCH_EF
UAT_TUNER_GPO_FIL1_EF
UAT_TUNER_GPO_FIL2_EF
VOLTAGE=0V
10.0.0
3 OF 4
051-02159
4.3NH 03015 WW INDUCTOR L8005_EF152S1240 1 CRITICAL JPN
ROW152S00749 CRITICAL1 L8005_EF3.6NH 03015 WW INDUCTOR
UAT MATCH AND TUNER
UAT
505066-0620F-ST-SM
123456
78
910
150OHM-25%-200MA-0.7DCR
01005
1 2
150OHM-25%-200MA-0.7DCR
01005
1 2
NP0-C0G
27PF16V
UAT
5%
01005
1
2
01005
27PF16V5%NP0-C0G
UAT
1
2
NOSTUFF
0201UP_RFFE
1.5NH+/-0.1NH-1.0A
1
2
0.00
MF
1%1/20W
UP_RFFE0201
1 2
NOSTUFF
C0G-CERM
UP_RFFE
25V
0201
1.0PF+/-0.05PF
1
2
2.4NH+/-0.2NH-0.57A-0.07OHM03015
1
2
03015
1
2
1.6NH-+/-0.2NH-0.7A-0.06OHM
0.6PF1
20201CERM25V+/-0.05PF
1 2
1.6NH-+/-0.2NH-0.7A-0.06OHM
03015
0201
1.2PF+/-0.05PF25V
1
2 C0G-CERM
QM18147WLCSP
23
8 7
615
4
WLCSP
23
8 7
615
4QM18147
030155.1NH-+/-0.2NH-0.47A-0.12OHM
1
2
10V20%
0201-1X5R-CERM
1.0UF1
2
5%33PF
01005
16VNP0-C0G-CERM
1
2
270NH-3%-0.060A-15OHM
0201
1 2
18PF
C0H-CERM2%25V
0201
1
2
0201
120NH-5%-40MA1 2
120NH-5%-40MA
0201
1 2
NP0-C0G-CERM
33PF5%16V
01005
1
2
NP0-C0G-CERM
33PF5%16V
01005
1
2
1
12NH-3%-0.31A-0.28OHM03015
2
0.00
0%
MF1/32W
1 2
01005
03015
1
2
OMIT_TABLE
5.6NH-+/-0.2NH-0.47A-0.12OHM
0201
270NH-3%-0.060A-15OHM1 2
UP_RFFE
STDOFF-2.56OD1.4ID0.99H-SM1
UP_RFFE
STDOFF-2.56OD1.4ID0.99H-SM1
STDOFF-2.2OD0.25H-0.50-1.701
1/32W
0.00
MF
0%
01005
1 2
2.85R1.5-NSP
UP_RFFE
1
25V
UP_RFFE0201
2%
18PF1
C0H-CERM
2
5%CERM6.3V
01005
1
2
220PF16VNP0-C0G
UP_RFFE
4.0PF+/-0.1PF
01005
1
201005NP0-C0G16V5%56PF
1
2
16V5%NP0-C0G
UAT
27PF1
201005
76
UP_RFFENOSTUFF
1
2
NO_XNET_CONNECTION
0201C0G-CERM25V+/-0.05PF1.0PF
6.3VCERM5%220PF
01005
1
216VCERM5%
UP_RFFE
18PF
01005
1
216V
100PF
UP_RFFE
5%NP0-C0G01005
1
2
27PF16V5%
01005NP0-C0G
1
2
UAT
33PF5%NP0-C0G-CERM16V
01005
1
2
1.0UF10V20%
0201-1X5R-CERM
1
2
01005
33PF5%16V
1
2 NP0-C0G-CERM
0201
120NH-5%-40MA1 2
18PF
0201C0H-CERM2%25V
1
2C0H-CERM0201
18PF25V2%
1
2
16VNP0-C0G-CERM01005
5%
133PF
2
0201
120NH-5%-40MA1 2
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
VDD
CB2
RF1RF2
CB1
NC
GND
VDD
CB2
RF1RF2
CB1
NC
GNDNC
NC
BI
USID=0X8
USID=0X8
78 OF 81
C6916_EF
R6912_EF
R6913_EF
C6914_EF
C6910_EF
GPOLAT_EF
GPOUAT_EF
C6911_EF
R6910_EF
FL6901_EF
C6917_EF
C6912_EF
C6913_EF
R6911_EF
C6915_EF
FL6902_EF
PP1V8_GPOLAT_EF
PP1V8_GPOUAT_EFPP1V8_S250 75 78
GPOLAT_RFFE1_CLK_FILT_EF
GPOLAT_RFFE1_DATA_FILT_EF
UAT_TUNER_GPO1_EF 77
GPOUAT_RFFE4_DATA_FILT_EF
GPOUAT_RFFE4_CLK_FILT_EF
UAT_TUNER_GPO4_EF 77
UAT_TUNER_GPO3_EF 77
UAT_TUNER_GPO2_EF 77 UAT_TUNER_RFFE_CLK50 75 77
UAT_TUNER_RFFE_DATA50 75 77
PP1V8_S250 75 78
10.0.0
4 OF 4
051-02159
BB_TO_LAT_GPO1BB_TO_LAT_GPO2
BB_TO_LAT_GPO4BB_TO_LAT_GPO3
LAT_TUNER_RFFE1_CLK
LAT_TUNER_RFFE1_DATA
RFFE TO GPO TRANSLATOR
2
1
16V5%33PF
01005NP0-C0G-CERM
NOSTUFF
21
0%
MF
0.00
1/32W
01005
21 0.00
01005
0%
MF1/32W
2
1
0201
10V20%1UF
X5R
2
1
0201X5R
1UF20%10V
A3
B2
A2
A1
C3C4C2C1B4B1A4
B3
QM18099WLCSP
A3
A2
A1
B4B2B1A4
B3
WLCSPQM18098
2
133PF
NP0-C0G-CERM
5%
01005
16V
21
01005
1/32W
0.00
0%
MF
21
01005
10-OHM-1.1A
2
1
16VNP0-C0G-CERM
33PF5%
01005
NOSTUFF
2
1
NP0-C0G-CERM01005
16V5%
NOSTUFF
33PF
2
1
NP0-C0G-CERM
NOSTUFF
16V5%33PF
01005
21
MF1/32W0%
01005
0.00
2
1
NP0-C0G-CERM
5%16V
33PF
01005
21
01005
10-OHM-1.1A
75 50
75 50
75 50
75 50
75 50
75 50
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
GPO7GPO6GPO5GPO4GPO3GPO2GPO1
GND
VIO
SCLK
USID1
SDATA
VIO
SDATA
SCLK
GND
GPO1GPO2GPO3GPO4
NC
NCNC
NOV 28, 2016D21X WIFI_MLB (GUINNESS)
POWER
CLOCKS
AOP
COEX
ANTENNA
WLAN PCIE
CONTROL
BLUETOOTH UART
WLAN UART
79 OF 81
WLAN_TO_PMU_HOST_WAKE
90_PCIE_WLAN_TO_AP_RXD_N
90_PCIE_WLAN_TO_AP_RXD_P
AP_TO_WLAN_DEVICE_WAKE
PCIE_AP_TO_WLAN_RESET_L
90_PCIE_AP_TO_WLAN_TXD_N
90_PCIE_AP_TO_WLAN_TXD_P
PMU_TO_WLAN_CLK32K
PP1V8_S2
PCIE_WLAN_BI_AP_CLKREQ_L
WLAN_TO_AP_TIME_SYNC
051-02159
2017-06-06000892701210 ENGINEERING RELEASED
1 OF 5
10.0.0
SCH,MLB,D21
50_LAT_WLAN_MLC
50_LAT_WLAN_SOUTH
50_LAT_WLAN_NORTH
50_UAT_WLAN_5G_EAST
50_UAT_WLAN_2G_EAST
UART_WLAN_TO_BB_COEX
UART_BT_TO_AP_CTS_L
UART_BT_TO_AP_RXD
UART_WLAN_TO_AP_CTS_L
UART_WLAN_TO_AP_RXD
UART_BB_TO_WLAN_COEX
AOP_TO_WLAN_CONTEXT_B
AOP_TO_WLAN_CONTEXT_A
UART_AP_TO_BT_RTS_L
UART_AP_TO_BT_TXD
UART_AP_TO_WLAN_RTS_L
UART_AP_TO_WLAN_TXD
90_PCIE_AP_TO_WLAN_REFCLK_N
90_PCIE_AP_TO_WLAN_REFCLK_P
AP_TO_BT_WAKE
PMU_TO_BT_REG_ON
PMU_TO_WLAN_REG_ON
BT_TO_PMU_HOST_WAKE
PP_VDD_MAIN
3 77 WIFI FRONT-END
CONTENTSPDF PAGE CSA PAGE
SymbolPorts
762 GUINNESS
81 50
81 50
81 50
81 50
81 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
80 50
TABLE_TABLEOFCONTENTS_ITEM
BRANCH
8
REVISION
ECNREV DESCRIPTION OF REVISION2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
CKAPPD
2 1
124567
B
D
6 5 4 3
C
A
PAGE
C
A
D
DATE
SHEET
DSIZEDRAWING NUMBER
7
B
3
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
8
IV ALL RIGHTS RESERVED
II NOT TO REPRODUCE OR COPY IT
PROPRIETARY PROPERTY OF APPLE INC.
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
THE INFORMATION CONTAINED HEREIN IS THE
DRAWING TITLE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_TABLEOFCONTENTS_HEAD
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
TABLE_TABLEOFCONTENTS_ITEM
IO
IO
IO
IO
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IO
OUT
IN
OUT
TDI
TDO
WIFI/BT
80 OF 81
C7601_WC7600_W
R7600_W
WLAN_W
WLAN_W
C7609_WC7608_W
PP7625_W
PP7613_W
PP7620_W
PP7621_W
PP7622_W
PP7623_W
PP7624_W
PP7610_W
PP7611_W
PP7612_W
PP7614_W
PP7615_W
PP7616_W
PP7617_W
PP7618_W
PP7619_W
PP7600_W
PP7601_W
PP7603_W
PP7604_W
PP7605_W
PP7606_W
PP7607_W
PP7608_W
PP7609_W
C7603_W
C7604_WL7600_W
C7606_W C7607_W
90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_AP_TO_WLAN_TXD_N
SR_LVX_1_W
90_PCIE_AP_TO_WLAN_TXD_N50 79 80
PCIE_AP_TO_WLAN_RESET_L50 79 80 JTAG_WLAN_TMS_W80
JTAG_WLAN_TRST_L_W80
AP_TO_WLAN_DEVICE_WAKE50 79 80
JTAG_WLAN_TCK_W80
JTAG_WLAN_SEL_W80
PP1V8_S250 79 80
PMU_TO_WLAN_CLK32K50 79 80
WLAN_TO_PMU_HOST_WAKE50 79 80
90_PCIE_AP_TO_WLAN_TXD_P50 79 80
JTAG_WLAN_SEL_W80
LBIST_MBIST_W80
ANT_SW_CTRL_W
ANT_SW_3P3_W81
50_WLAN_A_1_W
50_WLAN_A_0_W
50_WLAN_G_0_W
50_WLAN_G_1_W
AP_TO_WLAN_DEVICE_WAKE
PP1V8_S250 79 80
JTAG_WLAN_TRST_L_W80
JTAG_WLAN_SEL_W80
JTAG_WLAN_TCK_W80
JTAG_WLAN_TMS_W80
PMU_TO_WLAN_CLK32K
SR_LVX_W
PCIE_AP_TO_WLAN_RESET_L
90_PCIE_AP_TO_WLAN_TXD_P
WLAN_TO_PMU_HOST_WAKE
PCIE_WLAN_BI_AP_CLKREQ_L
CBUCK_EXT_W
WLAN_TO_AP_TIME_SYNC
LBIST_MBIST_W 80
90_PCIE_WLAN_TO_AP_RXD_N
10.0.0
4 OF 5
051-02159
90_PCIE_AP_TO_WLAN_REFCLK_N
BT_TO_PMU_HOST_WAKE
AOP_TO_WLAN_CONTEXT_A
AOP_TO_WLAN_CONTEXT_B
UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD
90_PCIE_AP_TO_WLAN_REFCLK_P
PMU_TO_WLAN_REG_ON
PMU_TO_BT_REG_ON
UART_BT_TO_AP_RXD
UART_AP_TO_BT_RTS_L
AP_TO_BT_WAKE
UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_TXD
UART_AP_TO_WLAN_RTS_L
UART_WLAN_TO_AP_RXD
UART_WLAN_TO_AP_CTS_L
BT_TO_PMU_HOST_WAKE
UART_AP_TO_WLAN_TXD
PMU_TO_BT_REG_ON
UART_WLAN_TO_BB_COEX
PMU_TO_WLAN_REG_ON
UART_BB_TO_WLAN_COEX
AP_TO_BT_WAKE
UART_BT_TO_AP_CTS_L
UART_BT_TO_AP_RXD
UART_AP_TO_BT_RTS_L
PP_VDD_MAIN
UART_AP_TO_BT_TXD
90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N
AOP_TO_WLAN_CONTEXT_A
AOP_TO_WLAN_CONTEXT_B
339S00399 ALT WIFI/BT MODULEWLAN_WBOM_TABLE_ALTS339S00397
GuinnessSYNC_MASTER=WIFI SYNC_DATE=11/28/2016
10%0.01UF
WLAN
6.3V
01005X5R
1
2
27PF
WLAN
16V5%
01005NP0-C0G
1
2
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
79 50
79 50
80 79 50
80 79 50
80 79 50
79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
10K
WLAN
5%
01005
1/32WMF
NOSTUFF
1
2
LBEE5W11KN-040LGA
12456789
10111213141718212427283133343540414243444546474850515354555657585960616263646567686970717273747576777879808182838493949596
979899100101102103104105106107108109110112113114115116117118120130131132133134135136137138139140141142143144145146148154155156157158159160161162163164165166167168172173174175176177178179180181182183
LBEE5W11KN-040LGA
366
4952
111149
129
128
85
3638
3739
147
125123
169
171
150170
153
15290
15191
121
122
8788
2019
2322
2625
12792
119
29 3015 1632
89 124
86
126
X5R-CERM0402-0.1MM
10UF20%10V
1
2X5R-CERM0402-0.1MM
10UF20%10V
1
2
81
81
81
81
81
79 50
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
P2MM-NSM OMITSM1
100PF16V5%NP0-C0G01005WLAN
1
2
7.5UF20%
0402CERM4V
2.2UH-20%-0.68A-0.25OHM0806
1 2
79 50
79 50
0.01UF
WLAN
10%X5R6.3V
01005
1
2
WLAN
5%16V
01005
27PF
NP0-C0G
1
2
80 79 50
80 79 50
79 50
79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
80 79 50
79 50
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_ITEM
TABLE_ALT_HEAD
COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FORPART NUMBER
IN
IN
IN
OUT
OUT
OUT
IN
BI
OUT
IN
IN
IN
OUT
IN
IN
IN
IN
OUT
SYM 2 OF 2
GND GND
SYM 1 OF 2
ANT_SW_CTRLANT_SW_3P3
5G_ANT_CORE15G_ANT_CORE0
2G_ANT_CORE0
2G_ANT_CORE1
FAST_UART_CTS_IN
WL_DEV_WAKE
FAST_UART_TX
FAST_UART_RTS_OUT
VDDI
O_1
P8V
VBAT
_VCC
VBAT
_RF_
VCC
VBAT
_RF_
VCC
VBAT
_VCC
BT_HOST_WAKE
FAST_UART_RX
BT_REG_ON
JTAG_TRST*
JTAG_SELJTAG_TCKJTAG_TMS
SECI_OUT
WL_REG_ON
SECI_IN
LPO_IN
GP15
CXT_B/TDOCXT_A/TDI
PCIE_REFCLK-PCIE_REFCLK+
SR_VLX
PCIE_PERST*
PCIE_RD-PCIE_RD+
PCIE_TD-PCIE_TD+
WL_HOST_WAKE
PCIE_CLKREQ*
BT_DEV_WAKE
BT_UART_TXDBT_UART_CTS*BT_UART_RTS*
BT_UART_RXD
CBUCK_EXT
WLAN_TIME_SYNC
LHL_GPIO2
OUT
BI
BI
BI
BI
OUT
PP
NC
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
IN
OUT
IN
IN
IN
OUT
IN
OUT
IN
2GHZ LAT2GHZ_C0/BT
2GHZ UAT
WIFI LOWER ANTENNA FEED
2GHZ_C1
WIFI LAT AFTER METROCIRC
WIFI UPPER ANTENNA FEED
81 OF 81
C7701_W
L7701_W
L7700_W
C7709_WC7711_W
L7705_W
R7720_W
C7716_W
W2BPF_W
R7701_W
C7703_W
W25DI_W
C7713_WC7712_W
R7702_W
L7703_W
W5BPF_W
R7711_W
L7704_W
C7708_W
C7700_W
W2XSW_W
R7700_W
C7702_W
50_WLAN_A_0_W
50_WLAN_G_1_BPF_W50_WLAN_2G_SWOUT_BAW_W81
50_WLAN_A_1_W 50_WLAN_A_1_DPLX_W
50_WLAN_G_1_M_W
50_LAT_WLAN_M_W
50_WLAN_A_0_BPF_2_W50_WLAN_A_0_BPF_1_W
50_WLAN_G_1_DPLX_W
ANT_SW_CTRL_W
50_WLAN_2G_SWOUT_EAST_W
50_WLAN_G_0_W
ANT_SW_3P3_W80
50_WLAN_G_1_W
50_WLAN_2G_SWOUT_BAW_W
10.0.0
5 OF 5
051-02159
50_LAT_WLAN_MLC50_LAT_WLAN_SOUTH
50_UAT_WLAN_5G_EAST
50_LAT_WLAN_NORTH
50_UAT_WLAN_2G_EAST
CRITICAL1152S00498 5G CORE0 BPF MATCH R7711_W D211
CRITICAL5G CORE0 BPF MATCH1117S0161 ROWR7711_W
CRITICALR7711_W JPN5G CORE0 BPF MATCH1117S0161
SYNC_DATE=11/28/2016
$PAGE_TITLE=WiFiANTFeeds
01005NP0-C0G
+/-0.1PF16V
4.7PF
1 2
16VCERM01005
0.2PF+/-0.05PF
1
2
2.3NH-+/-0.1NH-0.45A
01005
1 2
22NH-3%-0.12A-3.2OHM01005
NOSTUFF
12
NOSTUFF
22NH-3%-0.12A-3.2OHM01005
12
1/32WMF
01005
0%
0.001 2
80
01005MF1/32W
100K5%
1
2
80
35V5%
01005
100PF
NP0-C0G
1
2
80 79 50
79 50 79 50
79 50
80
LGAAS17
2 3 5 6
1 4
0.00
0%
MF1/32W
01005
1 2
NOSTUFF
0.2PF16V
01005NP0-C0G+/-0.1PF
1
2
0805DPX205850DT-9184A1SJ
2
1 3 5
6
4
NOSTUFF
0.6PF16V+/-0.05PF
01005CERM
1
2
NOSTUFF
NP0-C0G16V+/-0.1PF0.2PF
01005
1
2
0%
01005MF
1/32W
0.001 2
01005NOSTUFF
4.0NH-+/-0.1NH-0.27A
1
2
5GHZLFB185G53CGZE359
2
1 3
1/32W
OMIT_TABLE01005MF
0%
0.001 2
01005
2.0NH-+/-0.1NH-0.70A1 2
16V
01005
0.3PF
C0G-CERM
+/-0.05PF
1
2
80
010056.2NH-3%-0.22A-1.3OHM
12
SBBDCXA4440GC
2 6 97
45
8
3
1
0.4NH-+/-0.1NH-1.0A-0.03OHM
01005
1 2
+/-0.1PF16VNP0-C0G01005
0.2PF1
2
79 50
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCETHE POSESSOR AGREES TO THE FOLLOWING:
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
1
D
C
B
A
DSIZE
PAGE
BRANCH
SHEET
REVISION
DRAWING NUMBER
1
3 245
35 4
678
D
67
C
B
8
APAGE TITLE
2 IV ALL RIGHTS RESERVED
PROPRIETARY PROPERTY OF APPLE INC.THE INFORMATION CONTAINED HEREIN IS THE
Apple Inc.
NOTICE OF PROPRIETARY PROPERTY:
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#TABLE_5_HEAD
BOM OPTIONCRITICAL
BIIN
BI BI
BI BI
BI
BI
INPUT OUTPUT
GND
GND
COM
LO
HI
BI
RF2RF4RF1
VCGND
RF3
VDD
BI
![AT07175: SAM-BA Bootloader for SAM D21 - …ww1.microchip.com/.../Atmel-42366-SAM-BA-Bootloader-for-SAM-D21...AT07175: SAM-BA Bootloader for SAM D21 [APPLICATION NOTE] Atmel-42366A-SAM-BA-Bootloader-for-SAM-D21-ApplicationNote_082014](https://img.pdfslide.us/doc/110x75/5b01bab07f8b9a65618e15c1/at07175-sam-ba-bootloader-for-sam-d21-ww1-sam-ba-bootloader-for-sam-d21-application.jpg)
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