978-1-4673-1184-7/12/$31.00 2012 IEEE 1490

2012 5th International Conference on BioMedical Engineering and Informatics (BMEI 2012)

Phase-Locked Loop of Inverter Based on FPGA

Shuhong Li, Yueqing Zhou School of Electrical Engineering and Automation, Tianjin University

Tianjin, China

AbstractAn induction heating system with a full bridge LLC a kind of load formresonant inverter is described in this paper. Subsequently, the output voltage of inverter and capacitance voltage are chosen as control variables of phase-locked loop (PLL). With regard to LLC resonant inverter, there is a phase error of 90 degrees between the two control variables. First of all, a kind of PLL with XOR Phase Detector (XORPD) is proposed. This PLL is realized by embedded function module 74HCT297 of FPGA. Then a novel PLL with Phase-Frequency Detector (PFD) is designed. Compared with the latter, the former can be more completely implemented by FPGA. However, the latter is able to adapt to more complex input signals, which is good for high frequency and high efficiency of induction heating system.

Keywords-LLC resonant inverter; phase-locked loop (PLL); XOR Phase Detector (XORPD); Phase-Frequency Detector (PFD); FPGA

I. INTRODUCTION Generally, an inverter is the most important constituent part

of an induction heating system. So the design of inverter is crucial for performance of induction heating system. The design of inverter contains two kinds of circuits. They are main circuit and control circuit, respectively. Control circuit consists of phase-locked loop (PLL), overcurrent protective circuit and PWM generating circuit. PLL is used to make the inverter achieve frequency tracking. The output signal of PLL serves as the input signal of PWM generating circuit. And the output signal of PWM generating circuit is used to drive switching devices in the inverter. In addition, overcurrent protective circuit prevents the electron device from suffering burnout.

Because the resonant frequency of load is varied in the process of heating, PLL acts as a very useful control circuit of induction heating system. For induction heating system, frequency tracking can bring about two benefits. One of the benefits is that the biggest inverter output power would be obtained. The other is that zero voltage switch can be realized. So PLL plays an important role for an induction heating system. PLL technique has been studied for a long time, but there is limited research on PLL of LLC resonant inverter. And the rest paper is focused on designing PLL for LLC resonant inverter based on FPGA.

Section II describes a LLC resonant inverter. In Section III, the characteristic of LLC resonant load is talked about, and a

pair of control variables is chosen to design PLL of LLC resonant inverter. Then a popular all digital phase-locked loop (ADPLL) based on FPGA is proposed in Section IV. At last, a novel PLL based on FPGA is designed in Section V.

II. FULL-BRIDGE INVERTER A full bridge inverter with LLC resonant load is proposed

in this section. The designed inverter configuration is shown in Fig. 1. The inverter configuration is an induction heating system. Field effect transistor MOSFET with an antiparallel diode serves as a bridge arm of the full bridge inverter. The part in dash-dotted frame is LLC resonant load.

sL

oi

DU

si

Cu

Figure 1. Full-bridge LLC resonant inverter.

In Fig. 1, DU represents DC voltage source. Current oi flows through load resistance .R si stands for the output current of the inverter. At the same time ou is the output voltage of the inverter, and Cu is the capacitance voltage. At high frequency, field effect transistor MOSFET generally produces parasitic capacitance. However, when designing the control circuit, we usually pay attention to working states of inverter circuit at low frequency and intermediate frequency[1]. So the influence of parasitic capacitance produced by MOSFET is neglected in this study.

When being heated, the resonant frequency 0 of LLC load is varied. And the focus of this study is on designing PLL for the LLC resonant inverter to achieve frequency tracking. In order to design PLL for the LLC resonant load, control variables have to be chosen in advance.

III. CHOOSING CONTROL VARIABLES FOR PHASE-LOCKED LOOP

For LLC resonant load, quality factor Q is expressed as (1)

1491

( )1 s

s

L LQR L L C

=

+ 1

( )Z presents the impedance of LLC resonant load. So the expression of ( )Z is obtained:

1( )1 ( )s

Z j Lj C j L R

= ++ +

(2)

And the series resonant angular frequency o of LLC resonant load is also obtained through (2).

0s

s

L LL L C

+

(3)

The characteristic curve of ( )Z is illustrated in the Fig. 2.

0

20

40

Mag

nitud

e (dB

)

106

-450

4590

Phas

e (de

g)

Frequency (rad/sec)

1 0

z( )

Figure 2. The impedance characteristic curve of LLC resonant load.

For LC series resonant inverterthe output voltage and current of the inverter are usually used as control variables of PLL. Nevertheless, the phase-frequency curve of LLC resonant load shows that the phase angle of ( )Z is not a monotonic function when it changes with frequency . Consequently, for LLC resonant inverter, the output voltage and current of the inverter cannot be used as control variables.

The relation between the output voltage of the inverter ou and capacitor voltage Cu is illustrated by the following

expression:

( )( )

( )C s

uo

u Z j LH

u Z

= = (4)

When LLC load working at the series resonance frequency o , (4) and its phase-frequency characteristic can be expressed

as (5) and (6), respectively.

0 00 2

0

( ) ( 1)( )( )

su

Z j L jQHZ

+= =

(5)

0 2 2

( 1) 1 ( 1)( ) arg( ) arg( )ujQ Q= j + +=

(6)

A variable is assumed as = sL L . If 1 , (6) can be approximated to ( )2 . Equation (7) demonstrates the derivation:

0 2 2

1 ( 1) ( 1)( ) arg( ) arg( )2u

Q Qj j + += =

(7) To verify (7), the characteristic curve of ( )uH is

illustrated in the Fig. 3. In the frequency domain where induction heating power supply generally works, the phase-frequency curve shows that ( ) ( )( )( ) arg tanu C ou u = acts as a monotonic function. Obviously, both ou and Cu could be chosen as control variables of PLL.

-60

-40

-20

0

Mag

nitu

de (d

B)

105 106 107-180-135-90-45

0

Phas

e (de

g)

0

0

Hv( )

(rad/s) Figure 3. The characteristic curve of ( )uH .

With regard to a voltage-fed inverter, inverter output voltage ou and gate drive signal have identical phases and frequencies[2]. At the same time, the phase and frequency of switch drive signal are decided by output signal of PLL. Thereby, the output signal of PLL takes the place of ou for phase detection. So the output signal of PLL is chosen as feedback signal of phase detector. And capacitor voltage Cu is chosen as the reference signal of phase detector.

IV. PHASE-LOCKED LOOP WHITH XOR PHASE DETECTOR Because ou and Cu serve as the control variables of PLL,

when working in locked state, the phase of feedback signal outstrips that of reference signal by 90 degrees. For this reason, XOR Phase Detector (XORPD) fits this pair of control variables. In order to verify the conclusion, an introduction to XORPD is given. The structure of XORPD is illustrated by the module diagram in Fig. 4. The only output of XORPD is du .

refu

fdudu

Figure 4. Module diagram of XOR Phase Detector.

There are two kinds of conditions in which the averaged du is equal to zero.

1) the phase of reference signal outstrips that of feedback signal by 90 degrees.

2) the phase of feedback signal outstrips that of reference signal by 90 degrees.

The above property of XORPD makes itself fit the control variables which are inverter output voltage ou and capacitor voltage .Cu Thus, embedded function module 74HCT297 of FPGA could be chosen as PLL in this study. And the basic

1492

structure of this PLL is shown in Fig. 5. In Fig. 5, K counter serves as low-pass filter. Increment-decrement (ID) counter acts as voltage control oscillator. Whats more, fractional-N counter is necessary for this ADPLL. Hence, before the output signal of ID counter reaches XORPD, its frequency has already been divided by N.

Cu02Nf

OUTXOR

OUTID

0Mf

Figure 5. The basic structure of PLL with XORPD.

With regard to this ADPLL, only three parameters need to be determined. These parameters are K, M and N, which have to be 2 of integer power respectively. For 74HCT297, the minimum K is 8. Generally, M is equal to 2N. According to Ripple Minimum Principle, if K is equal to 4M , the smallest ripple wave is obtained[3]. As for this PLL, M is set to 32, N is set to 16, and K is set to 8. In this condition, the system wave is obtained in Fig. 6.

( )0Mf

1u0

2ui (IDout

DN UP

16 32

)16

8

8

2K

2K

( )02Nf16 32

IDout

IDout 2

IDout 4

IDout 8

0

0

Figure 6. System wave of PLL with XORPD.

V. PHASE-LOCKED LOOP WITH PHASE-FREQUENCY DETECTOR

The above designed ADPLL has been popular and could be realized completely by FPGA. However, this section will propose a novel PLL for LLC resonant inverter. When the control variables of LLC resonant inverter are chosen as inverter output voltage ou and capacitor voltage ,Cu another strategy of PLL can be adopted. In this strategy, Phase-Frequency Detector (PFD) substitutes for XORPD.

D

D

CP

CP

Q

Q

UP

DN"1"

"1"

1u

2u

FF

FF

DC

DC

BU

N

P

dU

Figure 7. Module diagram of Phase-Frequency Detector.

First of all, an introduction to PFD is given. Fig. 7 is the module diagram of PFD. As for this phase detector, there exist only three states whose identifiers are -1, 0 and 1 respectively. Identifier -1 represents the condition that UP is equal to 0 and DN is equal to 1. Identifier 0 represents the condition that both UP and DN are zero. Identifier 1 represents the condition that Up is equal to 1 and DN is equal to 0. 1 stands for the phase of reference signal, and 2 represents the phase of feedback signal. Only the rising edges of the 1 and 2 can change the state of PFD[4]. Fig. 8 illustrates its operation.

1 1

12

2

Figure 8. States of the Phase-Frequency Detector (PFD).

Assume that and dK are the phase error between two input signals and the time averaged output of PFD, respectively. When PFD operates in the region of

( )2 ,2 , the relation between dK and is shown in Fig. 9.

2

2

dKdK

dK

Figure 9. The relation between dK and .

1493

Fig. 9 shows that the phase error range of PFD is 2 . But the phase error range of XORPD is ( )2 . Compared with the PLL with XORPD, the PLL with PFD can adapt to more complex signal environments which have different frequencies and phases. When belongs to ( )2 ,2 , dK acts as a linear function of :

d du K = (8) where dK stands for the gain of PFD. Equation (8) demonstrates that only when both frequency synchronization and phase synchronization are realized, du is equal to zero. And in locked state, the phase of feedback signal is caused to be equal to that of reference signal by PFD.

Consequently, if inverter output voltage ou and capacitor voltage Cu are used as control variables of PLL with PFD, a delay circuit of 90 degrees is necessary. A 90 degrees delay circuit[5] is shown in Fig. 10. The theory waveform diagram of delay circuit is shown in Fig. 11.

1D 1Q

1Q

2D 2Q

2Q

1CP

2CP

Figure 10. 90 degrees delay circuit.

1CP

2CP

1Q

2Q

t

t

t

t

Figure 11. Waveform of 90 degrees delay circuit.

Fig. 12 illustrates the basic structure of this PLL which consisits of PFD, delay circuit of 90 degrees, K counter, ID counter, fractional-N counter and 1/2 frequency divider. For this PLL, both K counter and ID counter will be realized by FPGA. And 2N should be set to 2M . The output of 1/2 frequency divider is used to drive signal Q1 and switching devices of inverter. The output of fractional-N counter is used as the clock signal CP1 and 2CP . According to the principle of PLL, signal Q1 and inverter output voltage ou have identical phases and frequencies. Fig. 11 demonstrates that the frequency of signal Q2 is the same with that of signal Q1. But compared with Q1, the phase of Q2 is delayed for 90 degrees. So when PLL operating in locked state, Q2 and Cu have identical phases and frequencies. Thus, Q2 is used as feedback signal of PDF.

D

D

CP

CP

Q

Q

UP

DN

"1"

"1"

Cu

2u

FF

FF

DC

DC

inc

dec

2f

1D

1Q

2D 2Q

2Q

PFD

2

0Mf 02Nf

1Q

Figure 12. The basic structure of PLL with PFD.

VI. CONCLUSION This paper has proposed two kinds of PLLs for LLC

resonant inverter when control variables are chosen as inverter output voltage and capacitor voltage. The two kinds of PLLs are PLL with XORPD and PLL with PFD, respectively. Compared with the latter, the PLL with XORPD is more popularly used, and there are more perfect theory to analysis its operating principle. Above all, embedded function module 74HCT297 of FPGA makes the former easier to realize frequency tracking than the latter. However, the latter has its own advantages. The PLL with PFD has enhanced the ability to adapt to different phase or frequency errors between two input signals, which is significant to make induction heating power supply realize high frequency and high efficiency. Consequently, an in-depth study of the latter should be undertaken in the area of induction heating system.

REFERENCES

[1] Sun Jinqiu, Research on the controller of induction heating power supply based on FPGA, Master Dissertation, 2005.

[2] S. Chudjuarjeen, A. Sangswang and C. Koompai, An Improved LLC Resonant Inverter for Induction-Heating Applications With Asymmetrical Control, IEEE transactions on industrial electronics, vol. 58, pp. 29152925, July 2011.

[3] Roland E. Best, Phase-Locked Loops: Design, Simulation, and Applications (5th Edition), Tsinghua University Press, 2007.

[4] Dean Banerjee, PLL Performance, Simulation, and Design (4th Edition), 2006.

[5] Wang Ying, Research on LLC Resonant Topology at High Frequency Solid State Induction Heating Power Supplies, Ph. D Dissertation, 2005.