PLL with VCO Band Selection Ko-Chi Kuo

PLL with VCO Band Selection

Ko-Chi Kuo

Auto Band Selection Outline

PART I: Concept Review Auto Band Selection Concept Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

PART II: Circuit Design Review Divide 8 and ECL to CMOS Circuit and Simulation 9 Bit Programmable Counter and Simulation Band Selection Interface Schematic and Simulation Reset DFF Schematic and Simulation VCO Phase Noise Simulation Auto Band Selection Simulation Summary

PART I:Band Selection Concept Review PART I: Concept Review Auto Band Selection Concept Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

Auto Band Selection Concept

The need of Auto Band Selection Multi-Band Solution Using CMOS Binary Digital Varactor Frequency Coverage of RFVCO over 8 Bands Requirements for Band Selection Algorithm to Work How the Band Selection Works Frequency Comparison Concept Frequency Resolution with 8 Band RF VCO Frequency Resolution with 4 Band IF VCO Band Select Circuit Design Band Select Circuit Timing Diagram Summary

The need of Auto Band Selection

VCO frequency variations over temperature(2%) and process(%9)

The minimum RF VCO Frequency Coverage(at RF LO)

2.30GHz

2.xxGHz

60MHz: Minimum required coverage for WCDMA at any temperature

2.yyGHz

2.36GHz

Frequency Tuning is achieved through: CMOS Binary Band-Select Capacitors Small Integrated PIN Diode Varactor

Total Frequency Coverageat given process and temp.

Frequency

Vtune

Multi-band Solution Using CMOS Binary

Digital Varactor

Frequency Coverage of RF VCO over 8 Bands

Band overage is 84%. The band coverage at (000) is 230 MHz for Core VCO, 115MHz after divide-by-2.

* courtesy from Dawn Wang’s RFVCO CDR presentation.

Desired Cover Range 4.6 –4.72 GHz (2.56%)Guard bands for process & temperature 5.4% each

1. Band Selection is performed each time a new channel is selected.

2. There is minimum overlap (f ) between two adjacent bands to cover the maximum expected temperature drift (+/-100 degree C) once a band is chosen.

Frequency(LO)

Vtune

.

.

.

Overlap: f

0.5 2.35

Band Switching Decision Point

Given Minimum Band Overlap (f) : 105MHz

1. 100degree (C) temperature drift: +/- 40MHz

2. BS Algorithm tolerance: +/- 4MHz

3. Vtune Bias Error: +/- 5MHz

4. Band separation Mismatch: This is accounted for in the Minimum Band Overlap (f)

f > 2 x (40M + 4M + 5M) = 98MHz

Requirements for Band Selection Algorithm to Work

Band=0

Band=3

Band=2

Band=1

.

.

....

•Comparison at 2.35Volts reduces algorithm error caused by Vtune voltage variations and Overlap variations.

1. At Power Up:

-- All registers set to zero (as default)

-- Vtune is set to 2.35V

2. Load (fLO (MHz) + 49) / 8 into Band Select Register thru Serial Interface.

-- This loading action triggers Band Select Algorithm

3. Compare Frequencies.

-- (fLO + 49MHz) / 8 > fVCO ?

4. Band selection counter (register) counts up as long as (fLO + 49MHz) / 8 > fVCO .

5. Freeze BS Counter when:

(fLO + 49MHz) / 8 < fVCO

6. Vtune voltage control is released.

* Above procedures are automatic except steps 1 and 2.

How the Band Selection Works

Frequency(LO)

Vtune

.

.

.

Overlap: f

0.5 2.35

Band Switching Decision Point

Band=0

Band=3

Band=2

Band=1

.

.

....

ABS Interconnection Diagram & Operation

• R-register of IF PLL is used to generate 1MHz f_REF for both RF and IF ABS circuits.• BS_Man overrides ABS algorithm and allows manual control of Band_Sel <2:0>• BS_Reset resets all the registers inside ABS circuit blocks.

RF_ABS

fREF

BS_ManBS_Reset

EN( BS Enable)Vtune

RBS<8:0>

VCO_in

fREF _Off

Synthesizer

RF_VCOVtune

BS<2:0>3bits

2.35V

9bits

ABS Operation FlowchartStart / Power Up

As default:

fREF = disabled

Freeze = Low (Disabled)BS_Reset = Low BS_Man = Low Vtune = 2.35 Volts

Load R-Register of IF PLL thru SI to output 1MHz

Load [ fLO(MHz) + 49] / 8 to RBS & IBS thru S.I.

fLO is desired VCO frequency for IF and RF PLL

Loading RBS & IBS tirggers EN high – triggers BS operation

• Reset BS <2:0> to zero• fREF is enabled

Cnt_Start enabled at fREF

From here on operation is synchronized to fREF

Start Down Count

Down Counter reaches ‘0’ before next fREF ?

• Increase BS<2:0> by one• Reload DN_Counter

• Freeze goes High• fREF = Disable • Freeze BS<2:0>• Reset all other Reg’s to ‘0’• Vtune_Release goes High

Vtune (VCO input) is reconnected to loop filter output for normal operation

Ready for normal operation of PLL

END

Load RBS (or IBS) value onto DN_Counter

yes

Vtune

Band

2.35Vfreq (GHz)

8/freq(nS)

297*8/freq

(S)

Band0 2.28 3.51 1.042

Band1 2.31 3.46 1.028

Band2 2.34 3.42 1.015

Band3 2.38 3.37 1.002

Band4 2.40 3.33 0.988

Band5 2.44 3.29 0.976

Band6 2.47 3.25 0.964

Band7 2.49 3.21 0.952

Frequency Resolution with8 Band RF VCO

1. The resolution of band selection counter is set to (fLO + 49MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 3~4 clock cycles.

Vtune

Band

2.35Vfreq (GHz)

8/freq

(nS)

195*8/freq

(S)

Band0 1.50 5.33 1.040

Band1 1.53 5.23 1.020

Band2 1.58 5.06 0.987

Band3 1.65 4.85 0.945

Frequency Resolution with 4 Band IF VCO

1. The resolution of band selection counter is set to (fLO + 34MHz) / 8 so that difference between two band can be larger enough to chose the right band. In this case, each difference is about 4~8 clock cycles.

Given Minimum Band Overlap (f) : 82MHz

1. 100degree (C) temperature drift: +/- 26MHz

2. BS Algorithm tolerance: +/- 4MHz

3. Vtune Bias Error: +/- 4MHz

4. Band separation Mismatch: This is accounted for in the Minimum Band Overlap (f)

f > 2 x (26M + 4M + 4M) = 68MHz

Freeze8 9-bit Down Cntr

9-bitsLoad (fLO (MHz) + 49) / 8 every 1sec

using : RBS register

Cntr = high ?

VCO

2330MHz / 8 = 291MHzVtune

Band_Sel<2:0>

* Using Clk and En inputs of S.I. to manually control Band Selection

* BSR, RBS and RMB are inputs from S.I. Freeze RMB Vtune_Release

TWIF_ClkTWIF_ENB

RMB

BS_Man

3-bitCounter

3-bit

Band_Sel <2:0>

BS_CntD Q

rst

fREF

fVCO / 8

D QQ

Freeze

Band Selection Circuit Design(RF)

Freeze

DN_Cnt

Reload Freeze_b

BS_enable

D QQ

D QQ

EN

BS_enable

FREFRMB

Freeze

EN

D QQ

D QQ

DN_Cnt

Reload

Reload

Freeze

BSR

rst

rstrst

BSR

fREF

CNT_Start

EN

SWITCH

2.35VVtune

LPF_out

* Vtune is determined by vtune release LPF_out is from off-chip LPF

Decode_C ENTWIF_ENB

Vtune_Release

D QfVCO / 8

BSR

Band Selection Circuit Design(IF)

Freeze9-bit Down Cntr

8-bitsLoad (fLO (MHz) + 34) / 8 every 1sec

using : RBS register

Cntr = high ?

1554MHz / 8 =194MHz

* Using Clk and En inputs of S.I. to manually control Band Selection* BSR, RBS and IMB are inputs from S.I. Freeze

IMB Vtune_Release

TWIF_ClkTWIF_ENB

IMB

BS_Man

3-bitCounter

3-bit

Band_Sel <1:0>

BS_Cnt

Freeze

Reload Freeze_b

BS_enable

D QQ

D QQ EN

EN

D QQ

D QQ

DN_Cnt

Reload

rst

rst

BSR

Decode_C

SWITCH

2.35VVtune

LPF_out

* Vtune is determined by vtune release LPF_out is from off-chip LPF

ENEN

TWIF_ENB

8VCO

Vtune

Band_Sel<2:0>

fVCO / 8

Freeze

DN_Cnt

BS_enable

Vtune_Release

D QfVCO / 8

D Q

rst

fREF

D QQ

FREFRMB

FreezeReload

Freeze

BSR

rst

fREF

CNT_Start

BSR

Band Selection Circuit Timing DiagramfREF

EN

Freeze

BS_Enable

Cnt_Start

Reload

Dn_Cnt

BS_Cnt

Band Selection is necessary for the RF and IF VCOs in order to overcome the VCO frequency drift due to the process and temperature variations.

The proposed Band Selection Algorithm takes 2sec per band and less than 20 sec(RF)/12 sec(IF) to accomplish Automatic Band Selection.

Frequency comparison is made through counting the frequency of fRF/8 signal during 1sec (all digital solution.)

Small overhead in silicon area and No Extra Current Consumption.

Summary of Auto Band Selection Algorithm

PART I:Band Selection Concept Review

PART I: Concept Review Auto Band Selection Concept Auto Band Selection Interface with other Blocks(PLLs, VCOs, S.I. )

Auto Band Selection Interface with other Blocks(PLL, VCO, LPF, S.I.)

RF Top Schematic of ABS, PLL, VCO, LPF, and S.I. IF Top Schematic of ABS, PLL, VCO, LPF, and S.I.

Serial InterfaceTWIF_Clk

Data

TWIF_ENRF PLL

RPE RF Low Pass Filter

Iout

RRC<7:0>

RPC<8:0>

RSC<4:0>

RCP

CPS<1:0>

RF VCOVtune

Band_Sel<2:0>

RFAuto Band Selection

LPF_out

OscillatorTCXO

vcop_rf

vcon_rf

RBS<8:0>

BSRRMB

Decode_C

RVE

SWITCH

Vtune_release

2.35V

FREF(From IF PLL)

RF TOP of ABS, PLL, VCO, LPF, S.I.

IF TOP of ABS, PLL, VCO, LPF, S.I.


Data

TWIF_ENIF PLL

IPE IF Low Pass Filter

Iout

IRC<7:0>

IPC<8:0>

ICP

CPS<1:0>

IF VCOVtune

Band_Sel<1:0>

IFAuto Band Selection

LPF_out

OscillatorTCXO

vcop_if

vcon_if

IBS<7:0>

BSRIMB

Decode_C

IVE

SWITCH

Vtune_release

2.35V

FREF(From IF PLL)

PART II: Circuit Design Review Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation 9 Bit Programmable Counter Schematic and Simulation Band Selection Interface Schematic and Simulation Reset DFF Schematic and Simulation VCO Phase Noise Simulation Auto Band Selection Top Level Simulation ABS, PLL, VCO, LPF Top Level Simulation Summary

PART II:Band Selection Circuit Design Review

Auto Band Selection: Divide 8, Biasing, CML to CMOS Circuits

Auto Band Selection: Divide 8, Biasing Corner Simulation Condition Circuit Simulation Result Simulation Summary

Auto Band Selection: Divide 8 and Biasing

Auto Band Interface

LPF_out

Vtune_releaseBand Selection

RBS<8:0> (from S.I.)

Band_Sel<2:0>

FREF(From IF PLL)

8 9-bit Down Cntr

Control LogicBias

circuit

VbiasPWD

VCO_vtune(to VCO vtune)

(from LPF) (to VCO Band select lines)

3-bitCounter

Power on Reset circuit

Control Signal (from S.I.)

Reset

Vtune_release

Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Corner

Process: bipolar fast(3), resistor fast(3), temp =-20C

Process: bipolar fast(3), resistor slow(-3), temp =-20C

Process: bipolar slow(-3), resistor fast(3), temp =-20C

Process: bipolar slow(-3), resistor slow(-3), temp =-20C

Process: bipolar fast(3), resistor fast(3), temp =85C

Process: bipolar fast(3), resistor slow(-3), temp =85C

Process: bipolar slow(-3), resistor fast(3), temp =85C

Process: bipolar slow(-3), resistor slow(-3), temp =85C

Frequency is set at 2.5GHz, Supply Voltage is 2.85V

Auto Band Selection: Divide 8 and CML to CMOS circuit Simulation Result

Freq=2.5G Supply= 2.85V

(1/freq/8) current

Design_bfrf, -20C 3.2n 2.147mA

Design_bfrs, -20C 3.2n 3.296mA

Design_bsrf,-20C 3.2n 2.179mA

Design_bsrs, -20C 3.2n 3.324mA

Design_bfrf, 85C 3.2n 2.122mA

Design_bfrs, 85C 3.2n 3.285mA

Design_bsrf, 85C 3.2n 2.258mA

Design_bsrs, 85C 3.2n 3.488mA

Auto Band Selection Divide 8 and CML to CMOS circuit Simulation Summary

Minimum

Typical

Maximum

Units

Power Supply 2.85 3 3.15 V

[email protected] 2.122 3.488 mA

Operating Frequency

2.36 2.5 GHz


Auto Band Selection: 9 Bit Programmable Counter

Auto Band Selection: 9 Bit Programmable Counter Corner Simulation Condition Circuit Simulation Result Power down/up Simulation Result Corner Simulation Result Simulation Summary

Auto Band Selection: 9 Bit Programmable Counter

Auto Band Interface

LPF_out



Band_Sel<2:0>

FREF(From IF PLL)

8 9-bit Down Cntr

Control LogicBias

circuit

VbiasPWD



3-bitCounter



Reset

Vtune_release

Auto Band Selection Circuit Design9 Bit Programmable Counter

Simulation Corner

Process: nfet fast(3), pfet fast(3), temp =-20C

Process: nfet fast(3), pfet slow(-3), temp =-20C

Process: nfet slow(-3), pfet fast(3), temp =-20C

Process: nfet slow(-3), pfet slow(-3), temp =-20C

Process: nfet fast(3), pfet fast(3), temp =85C

Process: nfet fast(3), pfet slow(-3), temp =85C

Process: nfet slow(-3), pfet fast(3), temp =85C

Process: nfet slow(-3), pfet slow(-3), temp =85CFrequency is set at 2.5GHz, Supply Voltage is 2.85V

Auto Band Selection 9 Bits CounterCorner Simulation Results

Freq=2.5G, Supply=2.85

1/(freq/8)/312) current

Design_nfpf, -20C 998.397nS 1.052mA

Design_nfps, -20C 998.397nS 1.227mA

Design_nspf,-20C 998.397nS 1.389mA

Design_nsps, -20C 998.397nS 1.593mA

Design_nfpf, 85C 998.397nS 1.12mA

Design_nfps, 85C 998.397nS 1.31mA

Design_nspf, 85C 998.397nS 1.478mA

Design_nsps, 85C 998.397nS 1.678mA

Auto Band Selection 9 Bits Counter Simulation Summary

Minimum

Typical Maximum

Units

Power Supply 2.85 3 3.15 V

[email protected] 1.052 1.678 mA

Division 2 298~308

512 Counts

Operating Frequency

2.36 2.5 GHz


Auto Band Selection: Band Selection Interface

Auto Band Selection: Band Selection Interface Auto Band Selection: Band Selection Interface Buffer Circuit worst case

simulation Auto Band Selection: Band Selection Interface Circuit Simulation Result Auto Band Selection: Band Selection Interface with VCO, PLL, LPF

Simulation Result Simulation Summary

Auto Band Selection: Reference Clock Generator

Auto Band Interface

LPF_out



Band_Sel<2:0>

FREF(From IF PLL)

8 9-bit Down Cntr

Control LogicBias

circuit

VbiasPWD



3-bitCounter



Reset

Vtune_release

Auto Band Selection Band Selection Buffer Worst Case Simulation

Simulation case Simulation parameter :Temp, supply voltage, MOS corner model

AC worst case:

Smallest PM (open loop )

85C, 2.85V supply,

PMOS=3, NMOS=-3

Transient case:

largest delay

85C, 2.85V supply,

PMOS=-3, NMOS=-3

Auto Band Selection Interface:Buffer AC Phase Margin Simulation

Phase Margin=60

AC open loop gain=70dB

Auto Band Selection Interface:Buffer Step Input Response Simulation

Settling time=200nsvout

Step input

Auto Band Selection Interface Simulation Result

LPF_in(comes from LPF)

Power_down

Vtune_release

PWD(generated by this interface)

VCO_Vtune(goes to VCO)

This is power on period

ABS find the right band and shut down the ABS

VCO_Vtune=2.35V(settled 300ns after power on)

VCO_Vtune=LPF_in(after ABS find the right

band)

Auto Band Selection Interface with VCO, PLL, LPF Simulation ResultLPF initial condition :0.5V

VCO_Vtune

Vtune_release

Auto Band Selection Interface with VCO, PLL, LPF Simulation ResultLPF initial condition :2.35V

VCO_Vtune

Vtune_release

Auto Band Selection Interface Simulation Summary

The Interface circuit provides the VCO vtune voltage based on ABS status, one is a fixed 2.35V, the other source is from off-chip LPF output.

When ABS select the right band, it generates the power down signal to shut down the current of ABS circuit.

Simulation result shows that after interface circuit shut down ABS, PLL and VCO can still handle LPF initial condition.

PART II: Circuit Design Review Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation 9 Bit Programmable Counter Schematic and Simulation Selection Interface Schematic and Simulation Band Reset DFF Schematic and Simulation VCO Phase Noise Simulation Auto Band Selection Top Level Simulation ABS, PLL, VCO, LPF Top Level Simulation Summary

Auto Band Selection: Band Power On Reset DFF Circuit

Auto Band Selection: Band Power On Reset DFF Circuit Circuit Simulation Result

Auto Band Selection: Band Power On Reset DFF Circuit

Auto Band Interface

LPF_out



Band_Sel<2:0>

FREF(From IF PLL)

8 9-bit Down Cntr

Control LogicBias

circuit

VbiasPWD



3-bitCounter



Reset

Vtune_release

Auto Band Selection Reset DFF Simulation Result

Power OnReset

Power On

PART II: Circuit Design Review Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation 9 Bit Programmable Counter Schematic and Simulation Selection Interface Schematic and Simulation Band Reset DFF Schematic and Simulation VCO Phase Noise Simulation Auto Band Selection Top Level Simulation ABS, PLL, VCO, LPF Top Level Simulation Summary

Auto Band Selection: VCO and Switch Phase Noise Test

Circuit Simulation Result Auto Band Selection: VCO and Switch (with divide 2) Phase Noise Test

Bench Circuit Simulation Result Simulation Summary

Auto Band Selection: VCO and Switch Phase Noise Test

Circuit Simulation Result Circuit Simulation Result Simulation Summary

Auto Band Selection :VCO Simulation

Result VCO with Switch VCO without Switch

-120.252dBc/[email protected]/Hz@1MHz

Auto Band Selection VCO and Switch

Simulation Summary Auto Band Selection: VCO and Switch Phase Noise Test Bench

Simulation result shows no degradation between VCO with switch and VCO without switch.

Auto Band Selection: VCO and Switch(with Divide 2) Phase Noise Test Bench Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch.

Auto Band Selection: VCO and Switch(with Divide 2) PSS Simulation result shows 0.15dBc/Hz@1MHz degradation between VCO with switch and VCO without switch












Data

TWIF_ENRF PLL

RPE RF Low Pass Filter

Iout

RRC<7:0>

RPC<8:0>

RSC<4:0>

RCP

CPS<1:0>

RF VCOVtune

Band_Sel<2:0>

RFAuto Band Selection

LPF_out

OscillatorTCXO

vcop_rf

vcon_rf

RBS<8:0>

BSRRMB

Decode_C

RVE

SWITCH

Vtune_release

2.35V

Auto Band Selection Top Level Simulation

FREF(From IF PLL)

ABS Top Level Simulation Result

BS0

BS1

BS2

CNT_Start

DN_CNT

BS_Cnt

Vtune_Release

Band 7 is selected

ABS Top Level Simulation Result

BS0

BS1

BS2

CNT_Start

DN_CNT

BS_Cnt

Vtune_Release

Band 7 is selected

ABS, PLL, LPF, VCO Top Level Simulation

ABS, PLL, LPF, VCO : Top Level Simulation Circuit Simulation Result ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of

interconnection

ABS, PLL, LPF, VCO Top Level Simulation

ABS, PLL, LPF, VCO : Top Level Simulation Circuit Simulation Result ABS, PLL, LPF, VCO, S.I Top Level Schematic and List of

interconnection

ABS, PLL, LPF, VCO Top Level VerilogA Model Simulation Result

Vtune_release

LPF_in

CP_out

PLL settle

PLL start normal function

PART II: Circuit Design Review Divide 8, Biasing, and CML to CMOS Circuit Schematic and Simulation 9 Bit Programmable Counter Schematic and Simulation Reference Clock Schematic and Simulation Selection Interface Schematic and Simulation Band Reset DFF Schematic and Simulation VCO Phase Noise Simulation Auto Band Selection Top Level Simulation ABS, PLL, VCO, LPF Top Level Simulation Summary

Auto Band Selection Circuit Simulation Summary

Band Selection Circuit start chose band 2S after EN signal enabled and takes additional up to 16S to chose the right band for VCO. The total selection time is 18S(RF), 10S(IF).

The Power Up takes 1S which is smaller than 2S. Whenever channel changed, both RF and IF ABS will be enabled to

select the right band again. Band Selection Circuit will shut down when the right band is selected. The simulation of VerilogA model: PLL,VCO, ABS, LPF shows that

ABS can work properly with other related blocks. The phase noise of VCO has 0.15dBc/Hz @ 1MHz degradation by

adding additional switch on the vtune line.

Documents

PLL with VCO Band Selection Ko-Chi Kuo