PLDS

Programmable Logic Devices

Mohammed Anvar P.KAP/ECE

Al-Ameen Engineering College

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Mohd Anvar Al- Ameen Engg. College

PLDs

– Programmable Logic Devices (PLD)• General purpose chip for implementing circuits• Can be customized using programmable switches

– Main types of PLDs• PLA• PAL• ROM• CPLD• FPGA

– Custom chips: standard cells, sea of gates

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ROM, PAL and PLA Configurations

(a) Programmable read-only memory (PROM)

InputsFixed

AND array(decoder)

ProgrammableOR array

OutputsProgrammable

Connections

(b) Programmable array logic (PAL) device

Inputs ProgrammableAND array

FixedOR array

OutputsProgrammable

Connections

(c) Programmable logic array (PLA) device

Inputs ProgrammableOR array

OutputsProgrammable

Connections

Programmable

ConnectionsProgrammable

AND array

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• Programmable Logic Array (PLA)

– Use to implement circuits in SOP form

– The connections inthe AND plane areprogrammable

– The connections inthe OR plane areprogrammable

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

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• Gate Level Version of PLA

f1

P1

P2

f2

x1 x2 x3

OR plane

Programmable

AND plane

connections

P3

P4

f1 = x1x2+x1x3'+x1'x2'x3

f2 = x1x2+x1'x2'x3+x1x3

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• Customary Schematic of a PLA

f1 = x1x2+x1x3'+x1'x2'x3

f2 = x1x2+x1'x2'x3+x1x3

f 1

P 1

P 2

f 2

x 1 x 2 x 3

OR plane

AND plane

P 3

P 4

x marks the connections left in place after programming

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PLA Logic Implementation

Example:

Equations

Personality Matrix

Key to Success: Shared Product Terms

1 = asserted in term0 = negated in term- = does not participate

1 = term connected to output0 = no connection to output

Input Side:

Output Side:Reuse

of t erms

F 1 1 0 1 0 0

Outputs Inputs Product t erm A

1 -1 -1

B 1 0 -0 -

C -1 0 0 -

F 0 0 0 0 1 1

F 2 1 0 0 1 0

F 3 0 1 0 0 1

A B B C A C B C A

F0 = A + B CF1 = A C + A BF2 = B C + A BF3 = B C + A

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PLA Logic ImplementationExample Continued - Unprogrammed device

All possible connections are availablebefore programming

A B C

F0 F1 F2 F3

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PLA Logic ImplementationExample Continued -Programmed part Unwanted connections are "blown"

Note: some array structureswork by making connectionsrather than breaking them

A B C

F0 F1 F2 F3

AB

BC

AC

BC

A

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PLA Logic ImplementationAlternative representation for high fan-in structures

Short-hand notationso we don't have todraw all the wires!

X at junction indicatesa connection

Notation for implementing

F0 = A B + A B

F1 = C D + C D

A B C D

AB+AB CD+CD

AB

CD

CD

AB

Unprogrammed device

Programmed device

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PLA Logic ImplementationDesign Example

F1 = A B C

F2 = A + B + C

F3 = A B C

F4 = A + B + C

F5 = A ⊕ B ⊕ C

F6 = A ⊕ B ⊕ C

Multiple functions of A, B, CABC

A

B

C

A

B

C

ABC

ABC

ABC

ABC

ABC

ABC

ABC

F1 F2 F3 F4 F5 F6

A B C

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Programmable Array Logic (PAL)

– Also used to implement circuits in SOP form

– The connections inthe AND plane areprogrammable

– The connections inthe OR plane areNOT programmable

f 1

AND plane OR plane

Input buffers

inverters and

P 1

P k

f m

x 1 x 2 x n

x 1 x 1 x n x n

fixed connections

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• Example Schematic of a PAL

f 1

P 1

P 2

f 2

x 1 x 2 x 3

AND plane

P 3

P 4

f1 = x1x2x3'+x1'x2x3

f2 = x1'x2'+x1x2x3

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PAL Logic ImplementationDesign Example: BCD to Gray Code Converter

Truth Table

K-maps

Minimized Functions:

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

W 0 0 0 0 0 1 1 1 1 1 X X X X X X

X 0 0 0 0 1 1 0 0 0 0 X X X X X X

Y 0 0 1 1 1 1 1 1 0 0 X X X X X X

Z 0 1 1 0 0 0 0 1 1 0 X X X X X X

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

0 1 X 1

0 1 X X

0 1 X X

K-map for W

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

0 0 X X

0 0 X X

K-map for X

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 X 0

0 1 X 0

1 1 X X

1 1 X X

K-map for Y

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 X 1

1 0 X 0

0 1 X X

1 0 X X

K-map for Z

W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D

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PAL Logic ImplementationProgrammed PAL:

4 product terms per each OR gate

Minimized Functions:

W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D

A B C D

A B C D

A

BD

BC

0

0

0

0B

C0

0

BC

BCDADBCD

W X Y Z

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PAL Logic ImplementationCode Converter Discrete Gate Implementation

4 SSI Packages vs. 1 PLA/PAL Package!

1: 7404 hex inverters 2,5: 7400 quad 2-input NAND

3: 7410 t ri 3-input NAND 4: 7420 dual 4-input NAND

B

C

C

A

D

D W

X

Y B

B

B

B

C

C

A

D 2

2 Z

1

D

2

4

3

5

3

1 4

2 1

1

1

3

A

C

B

C

B

D

D

A B

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Another Example: Magnitude ComparatorA

K-map for EQ

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

AB CD 00 01 11 10

00

01

11

10

D

B

C

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 1 1 1

0 0 1 1

0 0 0 0

0 0 1 0

K-map for GT

AB CD 00 01 11 10

00

01

11

10

D

B

C

A

0 0 0 0

1 0 0 0

1 1 0 1

1 1 0 0

K-map for L T

0 1 1 1

1 0 1 1

1 1 0 1

1 1 1 0

AB CD 00 01 11 10

00

01

11

10

D

B

C

K-map for NE

A

EQ NE LT GT

ABCD

ABCD

ABCD

ABCD

AC

AC

BD

BD

ABD

BCD

ABC

BCD

A B C D

PLA Logic Implementation

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• Comparing PALs and PLAs

– PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs

– PALs are simpler to manufacture, cheaper, and faster (better performance)

– PALs also often have extra circuitry connected to the output of each OR gate

• The OR gate plus this circuitry is called a macrocell

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• Macrocellf1

back to AND plane

D Q

Clock

SelectEnable

Flip-flop

OR gate from PAL0

1

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Combinational and Sequential PLDS• 16L4 PAL – Combinational Logic

– Up to 16 inputs– 32 bit & bit-bar lines– Up to 4 outputs– Up to 7 product terms per output– 1 product term/output for tri-state

control– Input, Output, Bi-driectional bus (on

per output basis)– Note fuse numbers (early technology)

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• 16R4 PAL – Sequential Logic– 16 inputs (counting feedback into array from DFFs)– Again 32 bit & bit-bar lines– 4 outputs (Q outputs from 8 DFFs)– Up to 64 product terms– The flip-flops are all controlled by a common clock

which is tied directly to pin 1 on the device.– pin 11, which is used as a dedicated input for the

output enable of the flip-flops.

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Simple PLDS• PLD 22V10 – Combinational/Sequential Logic

– PAL devices are most commonly used SPLD– Eg: PAL 22v10– II input pins that feed the AND plane and an additional

input that can serve as Clock input– The OR gates are of variable size, ranges from 8 to 16

inputs– From 8 to 16 product terms per output– Each out put pin has tristate buffer,which allows the pin to

optionally be used as input pin– Introduction of Macro cell-the circuitry between OR gate

and an out put in PAL– Combinational and/or sequential logic in 1 PLD

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Complex Programmable Logic Devices (CPLD)

– SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number

of product terms• Combined number of inputs + outputs < 32 or so

– CPLDs contain multiple circuit blocks on a single chip• Each block is like a PAL: PAL-like block

• Connections are provided between PAL-like blocks via an interconnection network that is programmable

• Each block is connected to an I/O block as well

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• Structure of a CPLD

PAL-likeblock I/O

blo

ck

PAL-likeblock

I/O block

PAL-likeblock I/O

blo

ck

PAL-likeblock

I/O block

Interconnection wires

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• Internal Structure of a PAL-like Block

– Includes macrocells• Usually about 16 each

– Fixed OR planes• OR gates have fan-in

between 5-20

– XOR gates providenegation ability

• XOR has a control input

D Q

D Q

D Q

PAL-like block

PAL-like block

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• More on PAL-like Blocks

– CPLD pins are provided to control XOR, MUX, and tri-state gates

– When tri-state gate is disabled, the corresponding output pin can be used as an input pin

• The associated PAL-like block is then useless

– The AND plane and interconnection network are programmable

– Commercial CPLDs have between 2-100 PAL-like blocks

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• Example CPLD

– Use a CPLD to implement the function• f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

D Q

PAL-like block

(from interconnection wires)x 1 x 2 x 3 x 4 x 5 x 6 x 7 unused

0 0 1

f

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The Xilinx 9500-series CPLD

• The internal PLDs are called Configurable Functional Blocks (FBs or CFBs)

• Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”)

• Each CLPD is packaged in a plastic-leaded chip carrier (PLCC)

• The number of I/O pins are much less than the total number of Macrocells in family of devices

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Xinlinx CPLDs

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Architecture of Xilinx 9500-family CPLD

Global set/reset

Global 3 state control

Global Clock

36 Signal pins

18 outputs

18 Outputenable signals

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XC9500 I/O Block

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FPGA– SPLDs and CPLDs are relatively small and useful for simple

logic devices• Up to about 20000 gates

– Field Programmable Gate Arrays (FPGA) can handle larger circuits

• No AND/OR planes• Provide logic blocks, I/O blocks, and interconnection wires and

switches

• Logic blocks provide functionality• Interconnection switches allow logic blocks to be connected to

each other and to the I/O pins

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FPGA Structure

CLB CLB

CLB CLB

SM SM

SM SM

CLB CLB

CLB CLB

SM

SM

CLB CLB

CLB CLB

SM SM

CLB CLB

CLB CLB

SM

IOB IOB IOB IOB

IOB IOB IOB IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

IOB

Input/Output Block

SwitchMatrix

ConfigurableLogic Block

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FPGA CLB Structure

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• LUTs

– Logic blocks are implemented using a lookup table (LUT)• Small number of inputs, one output• Contains storage cells that can be loaded with the desired values

• A 2 input LUT uses 3 MUXesto implement any desired functionof 2 variables

– Shannon's expansion at work!f

0/1

0/1

0/1

0/1

x 1

x 2

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• Example 2 Input LUT

x1 x2 f0 0 10 1 01 0 01 1 1

f = x1'x2' + x1x2, or using Shannon's expansion:

f = x1'(x2') + x1(x2)= x1'(x2'(1) + x2(0)) + x1(x2'(0) + x2(1))

f

1

0

0

1

x 1

x 2 www.edutalks.org


• 3 Input LUT

– 7 2x1 MUXes and8 storage cells arerequired

– Commercial LUTs have4-5 inputs, and 16-32 storage cells

f

0/1 0/1 0/1 0/1

0/1 0/1 0/1

0/1

x 2

x 3

x 1

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• Programming an FPGA

– LUTs contain volatile storage cells• None of the other PLD technologies are volatile• FPGA storage cells are loaded via a PROM when power is first

applied

– The UP2 Education Board by Altera contains a JTAG port, a MAX 7000 CPLD, and a FLEX 10K FPGA

• The MAX 7000 CPLD chip is EPM7128SLC84-7• EPM7 MAX 7000 family; 128 macrocells; LC84 84 pin PLCC

package; 7 speed grade

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• Example FPGA

– Use an FPGA with 2 input LUTS to implement the function f = x1x2 + x2'x3

• f1 = x1x2

• f2 = x2'x3

• f = f1 + f20 1 0 0

0 1 1 1

0 0 0 1

x 1

x 2

x 2

x 3

f 1

f 2

f 1 f 2

f

x 1

x 2

x 3 f

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• Another Example FPGA

– Use an FPGA with 2 input LUTS to implement the function f = x1x3x6' + x1x4x5x6' + x2x3x7 + x2x4x5x7

• Fan-in of expression is too large for FPGA (this was simple to do in a CPLD)

• Factor f to get sub-expressions with max fan-in = 2– f = x1x6'(x3 + x4x5) + x2x7(x3 + x4x5)

= (x1x6' + x2x7)(x3 + x4x5)

• Could use Shannon's expansion instead– Goal is to build expressions out of 2-input LUTs

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0 0 0 1

0 1 1 1

x 4

x 5

A

B

C

D

x 1

x 6

x 4 f

0 1 1 1

0 0 0 1

x 3

C

D

E

E

f

x 2

x 7

x 5 x 3

0 0 0 1

x 2

x 7 B

0 0 1 0

x 1

x 6 A

• FPGA Implementation

– f = (x1x6' + x2x7)(x3 + x4x5)

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ALTERA FLEX 10K

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FLEX 10K Logic array block

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FLEX 10K Embedded Array block

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Xilinx XC400-CLB

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XC400 -IOB

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Wish you all the best…..

Thank you

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Documents

PLDS