PLACEMENT USING DON’T CARE WIRES

PLACEMENT USINGDON’T CARE WIRES

Fan Mo

Don’t Care Wire Group: P.Chong, Y-J.Jiang, S.Singha and R.K.Brayton

OUTLINE

• Design flow overview

• What is don’t care wire?

• What is our macro-cell placer?

• How to use don’t care wires in placement?

• Experiment, results and conclusion

DESIGN FLOW OVERVIEW

PLA-based Decomposition

SPFD-based Don’t CareWire Generation

Placement based onWire Choices

Resynthesis

Netlist

Layout

Final Placement

pins withwire choices

Cell area andnet connection

determined

wire choicemade

SPFD

• Yamashita and etc., “A new method to express functional permissibility for LUT based FPGAs and its applications”, ICCAD96

• Brayton, “Understanding SPFDs: A new method for specifying flexibility”, IWLS97 • Sinha and Brayton, “Implementation and use of SPFD”, ICCAD98

yy11

yy22

yy55

yy44

YA

yy22

yy33

yy55

yy44

YB

yy11

yy33

yy44

yy55

YC

Y-space

Z-space

Primary Inputs

YA YB YC

SPFD

1

Y-space

0

2

53

7

9 4

6

8

10

need SPFDYA

provide atleast SPFDYA

need SPFDYB

provide atleast SPFDYB

need SPFDYC

provide atleast SPFDYC

Each input pin of a node needs information described by its SPFD, and some other non-TFO nodes provide the required information.

DON’T CARE WIRES

Denition 1 Given a set of sets of nodes R={Rk}, a selection is an

ordered set of nodes {1, … , |R| } such that kRk.

Denition 2 A set of sets R={Rk} is compatible if for each selection,

there exist logic functions at each node such that the implied netlist

for that selection can implement the specications at the primary

outputs.

Theorem Any set of sets of nodes {Rk} satisfying

1. For any selection, the resulting netlist is acyclic, and

2. ’Rk SPFDk SPFD’

is compatible.

DON’T CARE WIRESProcedure (Constructing a compatible set, but still acyclic network)1. Starting from the outputs and proceeding in a backward topological order, for each node in the network, and each of its input pins, , assign SPFDs, SPFD and SPFD so that the required information is supplied. Once

this is done, each SPFD represents the set of minterms which must be distinguished by that node or pin. 2. Initialize for each node ,

ex()={}TFO

and for each input pin, of , let R ={’ }, where ’ is the initial choice of

source for pin . R will eventually represent the set of alternate wires for .3. Starting from the inputs and proceeding in some topological order, at each node , do the following: (a) Let C =~ex()(b) For each fanin wire of : # Find an ’ C such that SPFD SPFD’ .

# Include ’ in R , R = R {’ } .

# Update ex(’ ) = ex() ex(’ ). (to avoid cycles.) # This continues until no more nodes can be added to R .

R ’

exex(())exex((’’ ) )

USE DON’T CARE WIRES IN PLACEMENT

• Based on current placement, determine which wire among the choice set is chosen in terms of wire length reduction.

• Based on current netlist, determine the movement of the cells.

Wire choice interleaves cell placement

AWC PHASE I• For each pin with alternate wires, temporarily disconnect it from the

current net.

• For each net form the bounding boxes of the currently connected pins. These partial bounding boxes form a lower bound on the total wire length.

• For each pin with alternate wires, if its pin position is inside one of the partial bounding boxes for its candidate wires (the original wire plus its alternates), assign it to that net. No increase has been caused by this, and hence the partial assignment seen so far must be part of an optimum assignment.

• For each remaining pin with alternate wires, compute the “delta” costs if it is assigned to each of the candidate nets. There is a net assignment which increase the total net length by the least amount. Choose this assignment and update the chosen net.

• Continue last step until all pins have been assigned.

AWC PHASE I

AWC PHASE II• For each pin which is an extreme of the bounding box of its

currently assigned net, temporarily release it from its assignment, and compute the best net to put it in and its delta decrease cost in doing this. Note that the delta decrease is nonnegative.

• Choose the pin with the maximum delta decrease and reassign the pin to the new net.

• Repeat the above steps until the best delta is 0.

AWC PHASE II

AWC• After PHASE I, there may be pins that can be moved to different

nets to improve the total cost.

• During PHASE II, a pin may be reassigned more than once. To speed up the process, one may want to “lock” a pin once it is reassigned once.

• After PHASE II (with no locking), the solution is locally optimal, in that there is no pin which can be moved to a new net such that the total cost is decreased. However, there might be a set of pins that can be reassigned all at once which decreases the cost.

• Chong and etc., “Don’t care wires in logic/physical design”, IWLS00

FORCE-DIRECTEDMACRO-CELL PLACER

• Iterative so that wire choice can be merged into the placement.

• Incremental so that final placement can start from the layout done after wire choice instead of starting from scratch.

• Need to handle maro-cell, not only standard cell.

Standard cell design Macro-cell design

Iterative and Incremental

• Quinn and Breuer, “A Forced Directed Component Placement Procedure for Printed Circuit Boards”, IE3 Trans.-CAS79

• Eisenmann and Johannes, “Generic global placement and floorplanning”, DAC98

FORCE-DIRECTEDMACRO-CELL PLACER

• Short Total Wire Length Attractive forces applied on connected cells.

• Small AreaCells are dragged by attractive forces.

• Cell Orientation and Aspect Ratio (for soft cell)Gain function describing the relation between force reduction and cell orientation and shape.

• Eliminate OverlappingDensity field method. Make an evenly distributed layout. Also use pads to pull cells apart.

• IterativeIt should be. AWC can be easily merged in the placer.

• Run Time We seek more speed up by using a new wire model.

• Other Interesting FeaturesWire congestion estimation. Pad positioning.

PLACER ATTRACTIVE FORCE

Cell[1]

Star[s]

Chip

Pad[1] Pad[2]

Cell[2]

][

1

][

1

][

1

]][[]][[][]][[

]][[]][[]][[

]][[][

cNT

t

STC

cNT

t

ST

cNT

t

TA

tcSPtcOcPtck

tcSPtcPtck

tcFcF

Using star wire model instead of clique wire model. About 30% saving.

k: net weight; Pc: cell location; OT: terminal offset; Ps: star location

PLACER DENSITY FIELD

.5 .40 .4 0 0

1 .80 .8 0 0

1.2 1.10 1 .2 .1

2 1.80 1.2 1 .7

1.4 1.30 .9 1 .7

1 10 .4 1 .7

.5 .50 .2 .5 .4

0 00 0 0 0

1][

1][

1][

1][

4321

4321

]][[

][][][][

][][][][][

cBRTX

cBLBXbx

cBRTY

cBLBYby

EEEE

CCCCF

bybxf

cfcfcfcf

cfcfcfcfcF

BinNumX

xb

BinNumY

yb ybxbPbybxP

ybxbPbybxPybxbD

BinSizebybxf

1 12

2

]][[]][[

]][[]][[]][[

]][[

]][[

2][]][[

bybxbinveringAllCellsCo

BAL BinSizecADbybxD

CHIP

TOTALBAL area

areaD

MLBX[c]

BLBY[c]

BLBX [c]

BRTX [c]

BRTY[c]

MLBY [c]

MRTX[c]

MRTY [c]

BinSize

PLACER FORCE EQUATIONS

][][][ cFdcFacF FAC

LIMITC

C

C

LIMIT

LIMITCC

CfcF

cF

cFf

fcFcF

cP][

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PLACER CELL ORIENTATION

EW TN

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1

ceSiztcOtcktcFtcF

ceSiztcOtcktcFtcFcg

ceSiztcOtcktcFtcF

ceSiztcOtcktcFtcFcg

cgcgcg

ceSiztcOtcktcFtcF

ceSiztcOtcktcFtcFcg

ceSiztcOtcktcFtcF

ceSiztcOtcktcFtcFcg

cSizetcOtcktcFtcFcg

cSizetcOtcktcFtcFcg

AYAY

cNumTerm

tAXAXR

AYAY

cNumTerm

tAXAXT

VHS

AYAY

cNumTerm

tAXAXE

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cNumTerm

tAXAXW

cNumTerm

tYYAYAYV

cNumTerm

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2][][][

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cSizecSizeceSiz

cSizecSizetceSiz

tcOtcOtcO

tcOtcOtcO

YX

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erCoveredAftoreCoveredBef

F DDcg ][

][][][ cgcgcG FXX Gain of taking an orientation:

PLACER CELL ASPECT RATIO

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1

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1

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cNT

tYY

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cNT

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tcΔOcΔPtcF

tcF

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tcFcgain

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othershw

awha

ahwa

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hwMM

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'/'

'/'/1

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'/',0'/'

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new width/height ratio:

PLACER ORIENTATION vs ASPECT RATION

ORIENTATION ASPECT RATIO

discrete continuous

find a better one find the best

easy to compute more run time

for both hard/soft cell only for soft cell

better in earlier stage better in later stage

PLACER PAD POSITIONING

A

B

C

D

A

B

C

D

1][

1][

][][][

][][

][tBR

tBLbPP

F bfBRfBinSize

tMRLBLf

BinSize

tMBLtF

BMb

bbBMbb

PbPbP

bPbPbDBinSizebf 2

][][

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Attract force

one dimensional density fieldand filling force

PLACER WIRE CONGESTION ESTIMATION 1

LBinSize

wsNd TS

1

2][

Area paid for connections to starin terms of contribution to density field.

w

BinSize

L


]][[)#,max(#]][[ ecKOWWwecKO C

Area paid for the connections to the terminalsin terms of keepout distance of cell edges.

#W-,#W+ : the no. of wires go two opposite directions. w : wire pitche=left,bottom,right,top cell edge; KOC : the constant keepout distance


1/4 1/4 1/41/3 1/3 1/2

1/3 1/4 1/41/2 1/4 1/3

1/2 1/3 1/4 1/4 1/4

1/4 1/4 1/31/4 1/2

T

S

1/4 0 1/41/3 1/3 1/2

1/3 1/4 1/31/2 1/4 1/3

1/2 1/3 1/4 1/3 1/4

1/3 1/4 1/31/4 1/2

T

S

1/4 1/4 1/41/3 1/3 1/2

1/3 1/4 1/41/2 1/4 1/3

1/2 1/3 1/4 1/4 1/4

1/4 1/4 1/31/4 1/2

T

S

LBinSize

wbybxpbybxd RR

1]][[]][[

Rbybxdbybxd RR

1]][[]][[

No obstruction Obstruction, not fully blocked Obstruction, fully blocked

Area paid for the wiring between star and terminalin terms of contribution to density field.

PLACEMENT FLOWInitialize_and_ZeroSize_Cells();SetCellsSizeZero();loop Stage1IterationNumber { ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_and_Move_Cells(); AWC( );AWC( ); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads();}explode();

loop Stage2IterationNumber { IncreaseCellSize(); ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_Cells(); ComputeKeepOutDistance_for_Cells(); ComputeBinDensity(); ComputeFillingForces_Cells(); MoveWithLimit_Cells(); ComputeOrientationGain_and_ChooseOrientation_for_Cells(); AWC( );AWC( ); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads();}

while (exist bin, density > densityThreshold) { ComputeAttractiveForces_and_Move_Stars(); ComputeAttractiveForces_Cells(); ComputeKeepOutDistance_for_Cells(); ComputeBinDensity(); ComputeFillingForces_Cells(); MoveWithLimit_Cells(); ComputeSoftCellAspectRatio(); DetermineChipBoundary(); ComputeAttractiveAndFillingForce_and_Slide_Pads();}CleanUp();

STAGE I STAGE II

CELLAREA RATIO

1

0

CHIPDENSITY

STAGE IIIEXPLODEINITIALIZE CLEAN UP

1

2

3

Resynthesis( );UpdateCellInformation( ); resynthesis

EXPERIMENT

Regular MaximumPLAs In Pins Alt Pins (%) Alts Alt Pins (%) Alts

alu2-5 18 233 32 13.7 28.44 37 15.9 37.43apex6-5 37 553 21 3.8 16.10 27 4.9 81.56apex7-4 12 157 9 5.7 22.22 12 7.6 38.75apex7-5 11 146 5 3.4 14.40 6 4.1 55.83count-4 6 67 4 6.0 12.75 4 6.0 30.25count-5 6 68 3 4.4 21.67 3 4.4 35.00term1-4 15 186 23 12.4 19.61 29 15.6 37.03term1-5 12 170 11 6.5 32.55 15 8.8 44.00ttt2-4 7 73 7 9.6 14.00 7 9.6 15.29ttt2-5 8 85 9 10.6 15.22 10 11.8 18.30x4-5 24 269 19 7.1 34.05 28 10.4 32.64

Characterization of Examples

number of pins with alternatesthe percentage of such pins among all pins

average alternate number of these pins

break the acyclic constrain

EXPERIMENTAL RESULTS

0

2

4

6

8

10

12

14Im

pro

vem

ent

in T

otal

Wir

elen

gth

(%

)

alu2

-5

apex

6-5

apex

7-4

apex

7-5

coun

t-4

coun

t-5

term

1-4

term

1-5

ttt2

-4

ttt2

-5

x4-5

regular re-synthesis max

Average improvement: regular 5.1%, re-synthesis 3.9% max 5.4%

EXPERIMENTAL RESULTS

0

2

4

6

8

10

12

14

16

18Im

pro

vem

ent

in T

otal

Are

a (%

)

alu2

_50

apex

6_50

apex

7_40

apex

7_50

coun

t_40

coun

t_50

term

1_40

term

1_50

ttt2

_40

ttt2

_50

x4_5

0

4i2o1i1o

Average improvement: 4i2o 7.0%, 1i1o 8.2%

CONCLUSION

• Synthesis-interactive placer. AWC.• Improvement in terms of total wire length and

area.• Macro-cell placement algorithm, handling cell

orientation, cell aspect ratio and pin(pad) position. Also with wiring estimation.

Documents

PLACEMENT USING DON’T CARE WIRES