Placement Hand Book

PLACEMENT HAND-BOOK

2012 – 2013

Complied by

Mr.U.Ragavendran

ECE

ACKNOWLEDGEMENT

This is our privilege and pleasant task to express our sincere

gratitude to our respected Director Dr.C.Muthamizhchelvan, Faculty of

Engineering and Technology from whom we had received support and

guidance in the process of this book.

We record our sincere thanks to Dr. S. Malarvizhi, Head of the

Department, Dept. of Electronics and Communication, SRM University,

for providing us the necessary departmental facilities to publish this book.

We also extend our gratitude to Dr.R.Kumar, Professor, Dept. of

Electronics and Communication, SRM University for his useful

instructions and guidance to complete this book.

We deliver our heartfelt gratitude to Mr. P.Vijayakumar

Assistant Professor (Sr.G), Dept. of Electronics and Communication,

SRM University and Placement Team Members for the encouragement

and support they gave in preparation of this book.

We sincerely thank all the Teaching and Non- Teaching Staffs for

their support.

Authors

INDEX

CHAPTER

NUMBER TITLE

PAGE

NUMBER

1 BASIC ELECTRONICS Mr.R.Ramesh

1

2 MICROPROCESSOR & MICRO

CONTROLLER Mrs.R.Vinolee

15

3 DIGITAL ELECTRONICS Mrs.K.Suganthi

52

4 DATA COMMUNICATION &

COMPUTER NETWORK Mrs.V.Nithya & Mr. M. Aravindan

77

5 HARDWARE DESCRIPTION

LANGUAGE Mrs. K. Ferents Koni Jiavana

94

6 COMPUTER ARCHITECTURE Mrs. A. Vinnarasi

159

DEPARTMENT OF ECE

PLACEMENT HAND-BOOK 2012 – 2013 Page 1

CHAPTER 1

BASIC ELECTRONICS

DEPARTMENT OF ECE


1. What is the color code for a 220 5 % resistor?

A.Red, Red, Brown, Gold

B.Orange, Orange, Black, Gold

C.Red, Red, Black, Gold

D.Red, Red, Brown, Silver

2. If 60 J of energy are available for every 15 C of charge, what is the voltage?

A.4 V

B.60 V

C.15 V

D.0.25 V

3. An atom's atomic number is determined by the number of:

A.neutrons minus protons

B.protons

C.electrons

D.neutrons

4. Which resistive component is designed to be temperature sensitive?

A.Thermistor

B.Rheostat

C.Potentiometer

D.Photoconductive cell

5. In practical applications, battery voltage:

A. is restored as soon as disconnect occurs

B. is lowered as the load increases

C. may be stored indefinitely

D. will be reduced to zero as power is drawn

6. A voltmeter is used:

A. to measure current

B. in series with the circuit

C. in parallel with the circuit

D. to measure coulombs

7. If the current in a circuit equals 0 A, it is likely that the

A. voltage is too high

B. resistance is too low

C. circuit has a short

D. circuit is open

8. Which voltage source converts chemical energy to electrical energy?

A. Electrical generator

B. Battery

C. Solar cell

D. Electronic power supply

DEPARTMENT OF ECE


9. In which states may matter may be found?

A. solid, liquid, or mineral

B. solid, gas, or liquid

C. mineral, gas, or liquid

D. plastic, solid, or gas

10. How many valence shell electrons are there in semiconductor atoms?

A. 16 B. 8

C. 4 D. 2

11. When considering conventional current versus electron current flow:

A. electron current flow came first

B. protons move in conventional current flow

C. conventional current flow came first

D. the direction of current is the same in both methods

12. The center frequency of a band-pass filter is always equal to the

A. bandwidth

B. –3 dB frequency

C. bandwidth divided by Q

D. geometric average of the critical frequencies

13. A zero-level detector is a

A. comparator with a sine-wave output

B. comparator with a trip point referenced to zero

C. peak detector

D. limiter

14. A digital-to-analog converter is an application of the

A. scaling adder

B. voltage-to-current converter

C. noninverting amplifier

D.adjustable bandwidth circuit

15. If the input to a comparator is a sine wave, the output is a

A. ramp voltage

B. sine wave

C. rectangular wave

D. sawtooth wave

16. A basic series regulator has

A. an error detector

B. a load

C. a reference voltage

D. both an error detector and a reference voltage

17. A comparator is an example of a(n)

A. active filter

B. current source

DEPARTMENT OF ECE


C. linear circuit

D. nonlinear circuit

18. An ideal operational amplifier has

A. infinite output impedance

B. zero input impedance

C. infinite bandwidth

D. All of the above

19. Another name for a unity gain amplifier is:

A. difference amplifier

B. comparator

C. single ended

D. voltage follower

20. If ground is applied to the (+) terminal of an inverting op-amp, the (–) terminal will:

A. not need an input resistor

B. be virtual ground

C. have high reverse current

D. not invert the signal

21. An astable multivibrator is also known as a:

A. one-shot multivibrator

B. free-running multivibrator

C. bistable multivibrator

D. monostable multivibrator

22. With negative feedback, the returning signal:

A. aids the input signal

B. is proportional to output current

C. opposes the input signal

D. is proportional to differential voltage gain

23. A circuit whose output is proportional to the difference between the input signals is

considered to be which type of amplifier?

A. common-modeB. darlington

C. differentialD. operational

24. The voltage follower has a:

A. closed-loop voltage gain of unity

B. small open-loop voltage gain

C. closed-loop bandwidth of zero

D. large closed-loop output impedance

25. The ratio between differential gain and common-mode gain is called:

A. amplitude

B. differential-mode rejection

C. common-mode rejection

D. phase

26. If the input to a comparator is a sine wave, the output is a:

A. ramp voltage

B. sine wave

DEPARTMENT OF ECE


C. rectangular wave

D. sawtooth wave

27. An instrumentation amplifier has a high

A. output impedance

B. power gain

C. CMRR

D. supply voltage

28. Circuits that shift the dc level of a signal are called

A. limiters

B. clampers

C. peak detectors

D. dc converters

29. The major difference between ground and virtual ground is that virtual ground is only a:

A. voltage reference

B. current reference

C. power reference

D. difference reference

30. The Schmitt trigger is a two-state device that is used for:

A. pulse shaping

B. peak detection

C. input noise rejection

D. filtering

31. When a capacitor is used in place of a resistor in an op-amp network, its placement

determines:

A. open- or closed-loop gain

B. integration or differentiation

C. saturation or cutoff

D. addition or subtraction

32. The common-mode voltage gain is

A. smaller than differential voltage gain

B. equal to voltage gain

C. greater than differential voltage gain

D. None of the above

33. An output that is proportional to the addition of two or more inputs is from which type of

amplifier?

A. differentiator

B. difference

C. summing

D. analog subtractor

34. An ideal amplifier should have:

A. high input current

B. zero offset

C. high output impedance

D. moderate gain

DEPARTMENT OF ECE


35. What is the difference between common-mode and differential-mode input signals?

A. phase relationship

B. voltage

C. current

D. apparent power

36. What is a varistor?

A. a voltage-dependent resistor

B. a voltage-dependent diode

C. a current-dependent resistor

D. a current-dependent diode

37. Which type of transformer is required to create a 180 degree input to a rectifier?

A. center-tapped secondary

B. step-down secondary

C. stepped-up secondary

D. split winding primary

38. Since diodes are destroyed by excessive current, circuits must have:

A. higher voltage sources

B. current limiting resistors

C. more dopants

D. higher current sources

39. A diode for which you can change the reverse bias, and thus vary the capacitance is called

a

A. varactor diode

B. tunnel diode

C. zener diode

D. switching diode

40. When a diode is forward biased, the voltage across it

A. is directly proportional to the current

B. is inversely proportional to the current

C. is directly proportional to the source voltage

D. remains approximately the same

41. Why is heat produced in a diode?

A. due to current passing through the diode

B. due to voltage across the diode

C. due to the power rating of the diode

D. due to the PN junction of the diode

42. The arrow in the schematic symbol of a diode points to

A. the n-type material, which is called the anode

B. the n-type material, which is called the cathode

C. the p-type material, which is called the anode

D. the p-type material, which is called the cathode

43. The diode schematic arrow points to the:

A. trivalent-doped material

B. positive axial lead

DEPARTMENT OF ECE


C. anode lead

D. cathode lead

44. Rectifier output polarity depends upon:

A. cycles of input

B. capacitor polarity

C. half or full wave

D. diode installation

45. The conduction band is closest to the valence band in

A. semiconductors

B. conductors

C. insulators

D. The distance is the same for all of the above.

46. Which of the following circuits would require the least amount of filtering?

A. A half-wave rectifier

B. A full-wave rectifier

C. A bridge rectifier

D. A full-wave rectifier and a bridge rectifier

47. The voltage where current may start to flow in a reverse-biased pn junction is called the

A. breakdown voltage

B. barrier potential

C. forward voltage

D. biasing voltage

48. The area at the junction of p-type and n-type materials that has lost its majority carriers is

called the

A. barrier potential

B. depletion region

C. n region

D. p region

49. At any given time in an intrinsic piece of semiconductor material at room temperature

A. electrons drift randomly

B. recombination occurs

C. holes are created

D. All of the above

50. List three diode packages:

A. clip package, DIP, small current package

B. DIP, small current package, large current package

C. small current package, large current package, and SIP

D. small current package, large current package, clip package

51. When transistors are used in digital circuits they usually operate in the:

A. active region

B. breakdown region

C. saturation and cutoff regions

D. linear region

DEPARTMENT OF ECE


52. To operate properly, a transistor's base-emitter junction must be forward biased with

reverse bias applied to which junction?

A. collector-emitterB. base-collector

C. base-emitterD. collector-base

53. The C-B configuration is used to provide which type of gain?

A. voltageB. current

C. resistanceD. power

54. A transistor may be used as a switching device or as a:

A. fixed resistor

B. tuning device

C. rectifier

D. variable resistor

55. With low-power transistor packages, the base terminal is usually the:

A. tab end

B. middle

C. right end

D. stud mount

56. When a silicon diode is forward biased, what is VBE for a C-E configuration?

A. voltage-divider bias

B. 0.4 V

C. 0.7 V

D. emitter voltage

57. With a PNP circuit, the most positive voltage is probably:

A. groundB. VC

C. VBED. VCC

58. Most of the electrons in the base of an NPN transistor flow:

A. out of the base lead

B. into the collector

C. into the emitter

D. into the base supply

59. In a transistor, collector current is controlled by:

A. collector voltage

B. base current

C. collector resistance

D. all of the above

60. Total emitter current is:

A. IE – IC

B. IC + IE

C. IB + IC

D. IB – IC

DEPARTMENT OF ECE


61. For a C-C configuration to operate properly, the collector-base junction should be reverse

biased, while forward bias should be applied to which junction?

A. collector-emitterB. base-emitter

C. collector-baseD. cathode-anode

JUNCTION FIELD EFFECT TRANSISTORS (JFET)

62. Junction Field Effect Transistors (JFET) contain how many diodes?

A. 4B. 3

C. 2D. 1

63. In the constant-current region, how will the IDS change in an n-channel JFET?

A. As VGS decreases ID decreases.

B. As VGS increases ID increases.

C. As VGS decreases ID remains constant.

D. As VGS increases ID remains constant.

64. A MOSFET has how many terminals?

A. 2 or 3

B. 3

C. 4

D. 3 or 4

65. A very simple bias for a D-MOSFET is called:

A. self biasing

B. gate biasing

C. zero biasing

D. voltage-divider biasing

66. With the E-MOSFET, when gate input voltage is zero, drain current is:

A. at saturation

B. zero

C. IDSS

D. widening the channel

67. How will electrons flow through a p-channel JFET?

A. from source to drain

B. from source to gate

C. from drain to gate

D. from drain to source

68. When VGS = 0 V, a JFET is:

A. saturated

B. an analog device

C. an open switch

D. cut off

69. When the JFET is no longer able to control the current, this point is called the:

DEPARTMENT OF ECE


A. breakdown region

B. depletion region

C. saturation point

D. pinch-off region

70. Which type of JFET bias requires a negative supply voltage?

A. feedback

B. source

C. gate

D. voltage divider

71. In an n-channel JFET, what will happen at the pinch-off voltage?

A. the value of VDS at which further increases in VDS will cause no further increase in ID

B. the value of VGS at which further decreases in VGS will cause no further increases in ID

C. the value of VDG at which further decreases in VDG will cause no further increases in ID

D. the value of VDS at which further increases in VGS will cause no further increases in ID

72. A TRIAC:

A. can trigger only on positive gate voltages

B. can trigger only on negative gate voltages

C. cannot be triggered with gate voltages

D. can be triggered by either a positive or a negative gate voltage

73. What does a hall effect sensor sense?

A. temperature

B. moisture

C. magnetic fields

D. pressure

74. What causes the piezoelectric effect?

A. heat or dissimilar metals

B. pressure on a crystal

C. water running on iron

D. a magnetic field

75. A UJT has:

A. two base leads

B. one emitter lead

C. two emitter leads and one base lead

D. one emitter lead and two base leads

76. The only way to close an SCR is with:

A. a trigger input applied to the gate

B. forward breakover voltage

C. low-current dropout

D. valley voltage

77. What is an SCR?

A. a PNPN thyristor with 3 terminals

B. a PNPN thyristor with 4 terminals

C. a PNP thyristor with 3 terminals

D. an NPN thyristor with 3 terminals

DEPARTMENT OF ECE


78. What type of application would use a photovoltaic cell?

A. an automobile horn

B. a TI 92 calculator

C. a magnetic field detector

D. a remote power source

79. The smallest amount of current that the cathode-anode can have, and still sustain

conduction of an SCR is called the:

A. maximum forward current

B. maximum forward gate current

C. holding current

D. reverse gate leakage current

80. Once a DIAC is conducting, the only way to turn it off is with:

A. a positive gate voltage

B. a negative gate voltage

C. low-current dropout

D. breakover

81. The DIAC is a:

A. transistor

B. unidirectional device

C. three-layer device

D. bidirectional device

82. A transducer's function is to:

A. transmit electrical energy

B. convert energy

C. produce mechanical energy

D. prevent current flow

83. Intrinsic semiconductor material is characterized by a valence shell of how many

electrons?

A. 1B. 2

C. 4D. 6

84. What causes the depletion region?

A. doping

B. diffusion

C. barrier potential

D. ions

85. What is an energy gap?

A. the space between two orbital shells

B. the energy equal to the energy acquired by an electron passing a 1 V electric field

C. the energy band in which electrons can move freely

D. an energy level at which an electron can exist

86. In "n" type material, majority carriers would be:

DEPARTMENT OF ECE


A. holesB. dopants

C. slowerD. electrons

87. Elements with 1, 2, or 3 valence electrons usually make excellent:

A. conductorsB. semiconductors

C. insulatorsD. neutral

88. A commonly used pentavalent material is:

A. arsenicB. boron

C. galliumD. neon

89. Which material may also be considered a semiconductor element?

A. carbonB. ceramic

C. micaD. argon

90. What can a semiconductor sense?

A. magnetism

B. temperature

C. pressure

D. all of the above

91. When an electron jumps from the valence shell to the conduction band, it leaves a gap.

What is this gap called?

A. energy gap

B. hole

C. electron-hole pair

D. recombination

92. Forward bias of a silicon P-N junction will produce a barrier voltage of approximately

how many volts?

A. 0.2B. 0.3

C. 0.7D. 0.8

93. Which semiconductor material is made from coal ash?

A. germaniumB. silicon

C. tinD. carbon

94. When and who discovered that more than one transistor could be constructed on a single

piece of semiconductor material:

A. 1949, William Schockley

B. 1955, Walter Bratten

C. 1959, Robert Noyce

D. 1960, John Bardeen

95. When is a P-N junction formed?

A. in a depletion region

B. in a large reverse biased region

C. the point at which two opposite doped materials come together

D. whenever there is a forward voltage drop

DEPARTMENT OF ECE


96. What is a type of doping material?

A. extrinsic semiconductor material

B. pentavalent material

C. n-type semiconductor

D. majority carriers

97. Minority carriers are many times activated by:

A. heat

B. pressure

C. dopants

D. forward bias

98. Which of the following cannot actually move?

A. majority carriers

B. ions

C. holes

D. free electrons

99. What electrical characteristic of intrinsic semiconductor material is controlled by the

addition of impurities?

A. conductivity

B. resistance

C. power

D. all of the above

100. Base 10 refers to which number system?

A. binary coded decimal

B. decimal

C. octal

D. hexadecimal

DEPARTMENT OF ECE


ANSWER

1 A 26 C 51 C 76 B

2 A 27 C 52 D 77 A

3 B 28 B 53 A 78 D

4 A 29 A 54 D 79 D

5 B 30 A 55 B 80 C

6 C 31 B 56 C 81 D

7 D 32 A 57 A 82 B

8 B 33 C 58 B 83 C

9 B 34 B 59 B 84 D

10 C 35 A 60 C 85 A

11 C 36 A 61 A 86 D

12 D 37 A 62 D 87 A

13 B 38 B 63 A 88 A

14 A 39 A 64 D 89 A

15 C 40 D 65 C 90 D

16 D 41 A 66 B 91 B

17 D 42 C 67 A 92 C

18 C 43 D 68 A 93 A

19 D 44 D 69 A 94 C

20 B 45 B 70 C 95 C

21 B 46 D 71 A 96 B

22 C 47 A 72 D 97 A

23 C 48 B 73 C 98 C

24 A 49 D 74 B 99 A

25 C 50 D 75 D 100 B

DEPARTMENT OF ECE


CHAPTER 2

MICROPROCESSOR

&

MICROCONTROLLER

DEPARTMENT OF ECE


Definition:

Microprocessor is a program-controlled device, which fetches the instructions from memory,

decodes and executes the instructions. . A semiconductor device manufactured by using LSI

technique, including ALU, register arrays & control circuits on a single chip, also known as

MPU (microprocessor unit).

8085 ARCHITECTURE

Fig.1 Architecture of 8085

Control Unit

Generates signals within µP to carry out the instruction, which has been decoded. In reality

causes certain connections between blocks of the µP to be opened or closed, so that data goes

where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‗add‘, ‗subtract‘, ‗AND‘,

‗OR‘, etc. Uses data from memory and Accumulator to perform arithmetic operations.

Always stores result of operation in Accumulator.

Registers

The 8085/8080A-programming model includes six registers, one accumulator, and one flag

register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the

program counter. They are described briefly as follows.

DEPARTMENT OF ECE


The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as

B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE,

and HL - to perform some 16-bit operations. The programmer can use these registers to store

or copy data into the registers by using data copy instructions.

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register

is used to store 8-bit data and to perform arithmetic and logical operations. The result of an

operation is stored in the accumulator. The accumulator is also identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according to data

conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry

(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and

their bit positions in the flag register are shown in the Figure below. The most commonly

used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data

conditions.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a

memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit

register.

The microprocessor uses this register to sequence the execution of the instructions. The

function of the program counter is to point to the memory address from which the next byte is

to be fetched. When a byte (machine code) is being fetched, the program counter is

incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory

location in R/W memory, called the stack. The beginning of the stack is defined by loading

16-bit address in the stack pointer.

Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here from

memory prior to execution. Decoder then takes instruction and ‗decodes‘ or interprets the

instruction. Decoded instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address bus with

addresses of location of the program under execution.

DEPARTMENT OF ECE


8085 Pin description

It is a 8 bit microprocessor.

It is manufactured with N-MOS technology.

It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory

locations through A0-A

15.

The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0

– AD7.

Data bus is a group of 8 lines D0

– D7.

It supports external interrupt request.

A 16 bit program counter (PC)

A 16 bit stack pointer (SP)

Six 8-bit general purpose register arranged in pairs: BC, DE, HL.

It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.

It is enclosed with 40 pins DIP (Dual in line package).

Fig 2 Pin Diagram of 8085

A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0

address,3 stated during Hold and Halt modes.

AD0 - 7 (Input / Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear

on the bus during the first clock cycle of a machine state. It then becomes the data bus during

the second and third clock cycles. 3 stated during Hold and Halt modes.

DEPARTMENT OF ECE


ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and enables

the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set

to guarantee setup and hold times for the address information. ALE can also be used to strobe

the status information. ALE is never 3stated.

SO, S1 (Output)

S1 S0

O O HALT

0 1 WRITE

1 0 READ

1 1 FETCH

S1 can be used as an advanced R/W status.

RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is

available for the data transfer.

WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0

location. Data is set up at the trailing edge of WR. Hold and Halt modes have three states.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is

ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before

completing the read or write cycle.

HOLD (Input)

HOLD indicates that another Master is requesting the use of the Address and Data Buses. The

CPU, upon receiving the Hold request, will relinquish the use of buses as soon as the

completion of the current machine cycle. Internal processing can continue. The processor can

regain the buses only after the Hold is removed. When the Hold is acknowledged, the

Address, Data, RD, WR, and IO/M lines are 3 states.

HLDA (Output)

HOLD ACKNOWLEDGE indicates that the CPU has received the Hold request and that it

will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is

removed. The CPU takes the buses one half clock cycle after HLDA goes low.

DEPARTMENT OF ECE


INTR (Input)

INTERRUPT REQUEST is used as a general purpose interrupt. It is sampled only during the

next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be

inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or

CALL instruction can be inserted to jump to the interrupt service routine. The INTR is

enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is

accepted.

INTA (Output)

INTERRUPT ACKNOWLEDGE is used instead of (and has the same timing as) RD during

the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt

chip or some other interrupt port.

RST 5.5

RST 6.5 - (Inputs)

RST 7.5

RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they

cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5

RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher

priority than the INTR.

TRAP (Input)

Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It

is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.

None of the other flags or registers (except the instruction register) are affected The CPU is

held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to

the processor clock.

DEPARTMENT OF ECE


X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be an

external clock input instead of a crystal. The input frequency is divided by 2 to give the

internal operating frequency.

CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to

the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and

Halt modes.

SID (Input)

Serial input data line the data on this line is loaded into accumulator bit 7 whenever a RIM

instruction is executed.

SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Registers

Accumulator or A register is an 8-bit register used for arithmetic, logic, I/O and load/store

operations.

Flag Register has five 1-bit flags.

Sign - set if the most significant bit of the result is set.

Zero - set if the result is zero.

Auxiliary carry - set if there was a carry out from bit 3 to bit 4 of the result.

Parity - set if the parity (the number of set bits in the result) is even.

Carry - set if there was a carry during addition, or borrow during

subtraction/comparison/rotation.

General Registers

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. When used as a

pair the C register contains low-order byte. Some instructions may use BC register as a data

pointer.

DEPARTMENT OF ECE


8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. When used as a

pair the E register contains low-order byte. Some instructions may use DE register as a data

pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. When used as a

pair the L register contains low-order byte. HL register usually contains a data pointer used to

reference memory addresses.

Stack pointer is a 16 bit register. This register is always decremented/incremented by 2

during push and pop.

Program counter is a 16-bit register.

Instruction Set

8085 instruction set consists of the following instructions:

Data moving instructions.

Arithmetic - add, subtract, increment and decrement.

Logic - AND, OR, XOR and rotate.

Control transfer - conditional, unconditional, call subroutine, return from subroutine and

restarts.

Input/output instructions.

Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Addressing mode

The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination.

In these instructions the source can be a register, an input port, or an 8-bit number (00H to

FFH). Similarly, a destination can be a register or an output port. The sources and destination

are operands. The various formats for specifying operands are called the ADDRESSING

MODES.

For 8085, they are:

Immediate addressing.

Register addressing.

Direct addressing.

Indirect addressing.

DEPARTMENT OF ECE


Immediate addressing

Data is present in the instruction. Load the immediate data to the destination provided.

Example: MVI R , data

Register addressing

Data is provided through the registers. E.g.: MOV Rd, Rs

Direct addressing

Used to accept data from outside devices to store in the accumulator or send the data stored in

the accumulator to the outside device. Accept the data from the port 00H and store them into

the accumulator or Send the data from the accumulator to the port 01H. (E.g) IN 00H or OUT

01H

Indirect Addressing

This means that the Effective Address is calculated by the processor. And the content of the

address (and the one following) is used to form a second address. The second address is

where the data is stored. Note that this requires several memory accesses; two accesses to

retrieve the 16-bit address and a further access (or accesses) to retrieve the data this is to be

loaded into the register.

8086 Microprocessor

It is a 16-bit μp.

8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

It can support up to 64K I/O ports.

It provides 14, 16 -bit registers.

It has multiplexed address and data bus AD0- AD15 and A16 – A19.

It requires single phase clock with 33% duty cycle to provide internal timing.

8086 is designed to operate in two modes, Minimum and Maximum.

It can prefetches up to 6 instruction bytes from memory and queues them in order to speed

up instruction execution.

It requires +5V power supply.

A 40 pin dual in line package

Minimum and Maximum Modes:

The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a

single microprocessor configuration.

The maximum mode is selected by applying logic 0 to the MN / MXinput pin. This is a

multi micro processors configuration.

DEPARTMENT OF ECE


Local Bus Control Signal – Request / Grant Signals: In a maximum mode configuration,

the minimum mode HOLD, HLDA interface is also changed. These two are replaced by

request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus

access mechanism for accessing the local bus.

Internal Registers of 8086

The 8086 has four groups of the user accessible internal registers. They are the instruction

pointer, four data registers, four pointer and index register, four segment registers.

The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status

register, with 9 of bits implemented for status and control flags.

Most of the registers contain data/instruction offsets within 64 KB memory segment.

There are four different 64 KB segments for instructions, stack, data and extra data. To

specify where in 1 MB of processor memory these 4 segments are located the processor uses

four segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with

processor instructions. The processor uses CS segment for all accesses to instructions

referenced by instruction pointer (IP) register. CS register cannot be changed directly. The

CS register is automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program

stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and

base pointer (BP) registers is located in the stack segment. SS register can be changed

directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program

data. By default, the processor assumes that all data referenced by general registers (AX, BX,

DEPARTMENT OF ECE


CX, DX) and index register (SI, DI) is located in the data segment. DS register can be

changed directly using POP and LDS instructions.

Accumulator register consists of two 8-bit registers AL and AH, which can be combined

together and used as a 16-bit register AX. AL in this case contains the low-order byte of the

word, and AH contains the high-order byte. Accumulator can be used for I/O operations and

string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together

and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and

BH contains the high-order byte. BX register usually contains a data pointer used for based,

based indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together

and used as a 16-bit register CX. When combined, CL register contains the low-order byte of

the word, and CH contains the high-order byte. Count register can be used in Loop,

shift/rotate instructions and as a counter in string manipulation,.

Data register consists of two 8-bit registers DL and DH, which can be combined together

and used as a 16-bit register DX. When combined, DL register contains the low-order byte of

the word, and DH contains the high-order byte. Data register can be used as a port number in

I/O operations. In integer 32-bit multiply and divide instruction the DX register contains

high-order word of the initial or resulting number.

The following registers are both general and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is

usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register

indirect addressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and

register indirect addressing, as well as a destination data address in string manipulation

instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.

A flag is a 16-bit register containing 9 one bit flags.

Overflow Flag (OF) - set if the result is too large positive number, or is too small negative

number to fit into destination operand.

DEPARTMENT OF ECE


Direction Flag (DF) - if set then string manipulation instructions will auto-decrement

index registers. If cleared then the index registers will be auto-incremented.

Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.

Single-step Flag (TF) - if set then single-step interrupt will occur after the next

instruction.

Sign Flag (SF) - set if the most significant bit of the result is set.

Zero Flag (ZF) - set if the result is zero.

Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the AL

register.

Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the result

is even.

Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit

during last result calculation.

Addressing Modes

Implied - the data value/data address is implicitly associated with the instruction.

Register - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located

Register indirect - instruction specifies a register containing an address, where data is

located. This addressing mode works with SI, DI, BX and BP registers.

Based:- 8-bit or 16-bit instruction operand is added to the contents of a base register (BX

or BP), the resulting value is a pointer to location where data resides.

Indexed:- 8-bit or 16-bit instruction operand is added to the contents of an index register

(SI or DI), the resulting value is a pointer to location where data resides

Based Indexed:- the contents of a base register (BX or BP) is added to the contents of an

index register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed with displacement:- 8-bit or 16-bit instruction operand is added to the

contents of a base register (BX or BP) and index register (SI or DI), the resulting value is a

pointer to location where data resides.

Memory Program, data and stack memories occupy the same memory space. As the most

of the processor instructions use 16-bit pointers the processor can effectively address only 64

KB of memory.

DEPARTMENT OF ECE


To access memory outside of 64 KB the CPU uses special segment registers to specify

where the code, stack and data 64 KB segments are positioned within 1 MB of memory (see

the "Registers" section below).

16-bit pointers and data are stored as: address: low-order byte address+1: high-order byte

Program memory - program can be located anywhere in memory. Jump and call

instructions can be used for short jumps within currently selected 64 KB code segment, as

well as for far jumps anywhere within 1 MB of memory.

All conditional jump instructions can be used to jump within approximately +127 to -127

bytes from current instruction.

Data memory - the processor can access data in any one out of 4 available segments,

which limits the size of accessible memory to 256 KB (if all four segments point to different

64 KB blocks).

Accessing data from the Data, Code, Stack or Extra segments can be usually done by

prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions by

default may use the ES or SS segments instead of DS segment).

Stack memory can be placed anywhere in memory. The stack can be located at odd

memory addresses, but it is not recommended for performance reasons (see "Data Memory"

above).

Interrupts

The processor has the following interrupts:

INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using

STI/CLI instructions or using more complicated method of updating the FLAGS register with

the help of the POPF instruction.

When an interrupt occurs, the processor stores FLAGS register into stack, disables further

interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt

processing routine address of which is stored in location 4 * <interrupt type>. Interrupt

processing routine should return with the IRET instruction.

NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR

interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is

stored in location 0008h. This interrupt has higher priority then the maskable interrupt.

DEPARTMENT OF ECE


MICROCONTROLLER

4K bytes internal ROM

128 bytes internal RAM

Four 8-bit I/O ports (P0 - P3).

Two 16-bit timers/counters

One serial interface

On-ChipMemory

Internal RAM

SPECIAL FUNCTION REGISTER:

P0 (PORT 0, ADDRESS 80H, BIT-ADDRESSABLE): This is input/output port 0. Each bit

of this SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0

is pin P0.0, bit 7 is pin P0.7. Writing a value of 1 to a bit of this SFR will send a high level on

the corresponding I/O pin whereas a value of 0 will bring it to a low level.

SP (stack pointer, address 81h): This is the stack pointer of the microcontroller. This SFR

indicates where the next value to be taken from the stack will be read from in Internal RAM.

If you push a value onto the stack, the value will be written to the address of SP + 1. That is

to say, if SP holds the value 07h, a PUSH instruction will push the value onto the stack at

address 08h. This SFR is modified by all instructions which modify the stack, such as PUSH,

POP, LCALL, RET, RETI, and whenever interrupts are provoked by the microcontroller

DPL/DPH (DATA POINTER LOW/HIGH, ADDRESSES 82H/83H): The SFRs DPL and

DPH work together to represent a 16-bit value called the Data Pointer. The data pointer is

used in operations regarding external RAM and some instructions involving code memory.

Since it is an unsigned two-byte integer value, it can represent values from 0000h to FFFFh

(0 through 65,535 decimal).

DEPARTMENT OF ECE


PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the

8051's power control modes. Certain operation modes of the 8051 allow the 8051 to go into a

type of "sleep" mode which requires much less power. These modes of operation are

controlled through PCON. Additionally, one of the bits in PCON is used to double the

effective baud rate of the 8051's serial port.

TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used

to configure and modify the way in which the 8051's two timers operate. This SFR controls

whether each of the two timers is running or stopped and contains a flag to indicate that each

timer has overflowed. Additionally, some non-timer related bits are located in the TCON

SFR. These bits are used to configure the way in which the external interrupts are activated

and also contain the external interrupt flags which are set when an external interrupt has

occurred.

TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the mode

of operation of each of the two timers. Using this SFR your program may configure each

timer to be a 16-bit timer, an 8-bit autoreload timer, a 13-bit timer, or two separate timers.

Additionally, you may configure the timers to only count when an external pin is activated or

to count "events" that are indicated on an external pin.

TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch): These two SFRs, taken together,

represent timer 0. Their exact behaviour depends on how the timer is configured in the

TMOD SFR; however, these timers always count up. What is configurable is how and when

they increment in value.

TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh): These two SFRs, taken together,

represent timer 1. Their exact behaviour depends on how the timer is configured in the

TMOD SFR; however, these timers always count up. What is configurable is how and when

they increment in value.

P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR

corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0,

bit 7 is pin P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the

corresponding I/O pin whereas a value of 0 will bring it to a low level.

SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used

to configure the behaviour of the 8051's on-board serial port. This SFR controls the baud rate

of the serial port, whether the serial port is activated to receive data, and also contains flags

that are set when a byte is successfully sent or received.

DEPARTMENT OF ECE


SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive

data via the on-board serial port. Any value written to SBUF will be sent out the serial port's

TXD pin. Likewise, any value which the 8051 receives via the serial port's RXD pin will be

delivered to the user program via SBUF. In other words, SBUF serves as the output port

when written to and as an input port when read from.

P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this

SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 2 is pin

P2.0, bit 7 is pin P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the


IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and

disable specific interrupts. The low 7 bits of the SFR are used to enable/disable the specific

interrupts, where as the highest bit is used to enable or disable ALL interrupts. Thus, if the

high bit of IE is 0 all interrupts are disabled regardless of whether an individual interrupt is

enabled by setting a lower bit.

P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this

SFR corresponds to one of the pins on the microcontroller. For example, bit 0 of port 3 is pin

P3.0, bit 7 is pin P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the


IP (Interrupt Priority, Addresses B8h, Bit-Addressable): The Interrupt Priority SFR is

used to specify the relative priority of each interrupt. On the 8051, an interrupt may either be

of low (0) priority or high (1) priority. An interrupt may only interrupt interrupts of lower

priority. For example, if we configure the 8051 so that all interrupts are of low priority except

the serial interrupt, the serial interrupt will always be able to interrupt the system, even if

another interrupt is currently executing. However, if a serial interrupt is executing no other

interrupt will be able to interrupt the serial interrupt routine since the serial interrupt routine

has the highest priority.

PSW (Program Status Word, Addresses D0h, Bit-Addressable): The Program Status

Word is used to store a number of important bits that are set and cleared by 8051 instructions.

The PSW SFR contains the carry flag, the auxiliary carry flag, the overflow flag, and the

parity flag. Additionally, the PSW register contains the register bank select flags which are

used to select which of the "R" register banks are currently selected.

ACC (Accumulator, Addresses E0h, Bit-Addressable): The Accumulator is one of the

most-used SFRs on the 8051 since it is involved in so many instructions. The Accumulator

resides as an SFR at E0h, which means the instruction MOV A,#20h is really the same as

DEPARTMENT OF ECE


MOV E0h,#20h. However, it is a good idea to use the first method since it only requires two

bytes whereas the second option requires three bytes.

B (B Register, Addresses F0h, Bit-Addressable): The "B" register is used in two

instructions: the multiply and divide operations. The B register is also commonly used by

programmers as an auxiliary register to temporarily store values

DEPARTMENT OF ECE


OBJECTIVE TYPE

QUESTION

DEPARTMENT OF ECE


1. Which interrupt has the highest priority?

a. INTR

b. TRAP

c. RST6.5

d. RST 7.5

2. In 8085 name the 16 bit registers?

a. Stack pointer

b. Program counter

c. Both a & b

d. ACC

3. Which of the following is hardware interrupts?

a. RST5.5, RST6.5, RST7.5

b. INTR, TRAP

c. Both a & b

d. RST 4.5

4. What is the RST for the TRAP?

a. RST5.5

b. RST4.5

c. RST4

d. RST 7.5

5. What are level Triggering interrupts?

a. INTR&TRAP

b. RST6.5&RST5.5

c. RST7.5&RST6.5

d. RST 4.5

6. Which interrupt is not level sensitive in 8085?

a. RST6.5 is a raising edge-trigging interrupt.

b. RST7.5 is a raising edge-trigging interrupt.

c. Both a & b.

d. RST 5.5 is a raising edge-trigging interrupt.

7. What are software interrupts?

a. RST 0 – 7

b. RST 5.5 - 7.5

c. INTR

d. TRAP

8. Which stack is used in 8085?

a. FIFO

b. LIFO

c. FILO

d. LILO

DEPARTMENT OF ECE


9. Why 8085 processor is called an 8 bit processor?

a. Because 8085 processor has 8 bit ALU.

b. Because 8085 processor has 8 bit data bus.

c. Both a & b.

d. 8085 processor has 16 bit ALU

10. What is SIM?

a. Select Interrupt Mask

b. Sorting Interrupt Mask

c. Set Interrupt Mask.

11. RIM is used to check whether, ______

a. The write operation is done or not

b. The interrupt is Masked or not

c. Both a &b

d. The read operation is done

12. What is meant by Maskable interrupts?

a. An interrupt which can never be turned off.

b. An interrupt that can be turned off by the programmer.

c. None

d. RST 5.5

13. In 8086, Example for Non maskable interrupts are

a. Trap

b. RST6.5

c. INTR

d. RST 5.5

14. What does microprocessor speed depends on?

a. Clock

b. Data bus width

c. Address bus width

d. Either data bus nor address bus

15. Can ROM be used as stack?

a. Yes

b. No

16. Which processor structure is pipelined?

a. all x80 processors

b. all x85 processors

c. all x86 processors

d. all x82 processors

DEPARTMENT OF ECE


17. Address line for RST3 is?

a. 0020H

b. 0028H

c. 0018H

d. 0010H

18. In 8086 the overflow flag is set when

a. The sum is more than 16 bits

b. Signed numbers go out of their range after an arithmetic operation

c. Carry and sign flags are set

d. During subtraction

19. The advantage of memory mapped I/O over I/O mapped I/O is,

a. Faster

b. Many instructions supporting memory mapped I/O

c. Require a bigger address decoder

d. All the above

20. BHE of 8086 microprocessor signal is used to interface the

a. Even bank memory

b. Odd bank memory

c. I/O

d. DMA

21. In 8086 microprocessor the following has the highest priority among all type interrupts.

a. NMI

b. DIV 0

c. TYPE 255

d. OVER FLOW

22. In 8086 microprocessor one of the following statements is not true.

a. Coprocessor is interfaced in MAX mode

b. Coprocessor is interfaced in MIN mode

c. I/O can be interfaced in MAX / MIN mode

d. Supports pipelining

23. 8088 microprocessor differs with 8086 microprocessor in

a. Data width on the output

b. Address capability

c. Support of coprocessor

d. Support of MAX / MIN mode

24. Address line for TRAP is?

a. 0023H

b. 0024H

c. 0033H

d. 0034H

DEPARTMENT OF ECE


25. In which T-state does the CPU sends the address to memory or I/O and the ALE signal

for de-multiplexing

a. T1

b. T2

c. T3

d. T4

26. In a DMA write operation the data is transferred

a. from I/O to memory.

b. from memory to I/O.

c. from memory to memory.

d. from I/O to I/O.

27. A certain SRAM has CS = 0 , WE = 0 and OE = 1. In which of the following modes this

SRAM is operating

a. Read

b. Write

c. Stand by

d. None of the above

28. Which of the following is true with respect to EEPROM?

a. contents can be erased byte wise only.

b. contents of full memory can be erased together.

c. contents can be erased using ultra violet rays

d. contents cannot be erased

29. What will be the contents of register AL after the following has been executed

MOV BL, 8C

MOV AL, 7E

ADD AL, BL

a. 0A and carry flag is set

b. 0A and carry flag is reset

c. 6A and carry flag is set

d. 6A and carry flag is reset

29. A Bus cycle is equal to how many clocking periods

a. Two

b. Three

c. Four

d. Six

30. In the instruction FADD, F stands for

a. Far.

b. Floppy.

c. Floating.

d. File.

DEPARTMENT OF ECE


31. The Pentium microprocessor has______execution units.

a. 1

b. 2

c. 3

d. 4

32. Which of the following statement is true?

a. The group of machine cycle is called a state.

b. A machine cycle consists of one or more instruction cycle.

c. An instruction cycle is made up of machine cycles and a machine cycle is

d. made up of number of states.

e. None of the above

33. 8251 is a

a. UART

b. USART

c. Programmable Interrupt controller

d. Programmable interval timer/counter

34. 8088 microprocessor has

a. 16 bit data bus

b. 4 byte pre-fetch queue

c. 6 byte pre-fetch queue

d. 16 bit address bus

35. The memory data bus width in Pentium is

a. 16 bit

b. 32 bit

c. 64 bit

d. None of these

36. Which microprocessor pins are used to request and acknowledge a DMA transfer?

a. reset and ready

b. ready and wait

c. HOLD and HLDA

d. None of these

37. Which of the following statement is false?

a. RTOS performs tasks in predictable amount of time

b. Windows 98 is RTOS

c. Interrupts are used to develop RTOS

d. Kernel is the one of component of any OS

DEPARTMENT OF ECE


38. The flash memory is programmed in the system by 12 V programming pulse.

a. TRUE

b. FALSE

39. The no. of address lines required to address a memory of size 32 K is

a. 15 lines

b. 16 lines

c. 18 lines

d. 14 lines

40. Data rate available for use on USB is

a. 12 Mbits per second

b. 1.5 Mbits per second

c. Both (a) and (b)

d. No restriction

41. In 80186, the timer which connects to the system clock is

a. timer 0

b. timer 1

c. timer 2

d. Any one can be connected

42. The 8051 microcontroller is of ___pin package as a ______ processor.

a. 30, 1byte

b. 20, 1 byte

c. 40, 8 bit

d. 40, 8 byte

43. The SP is of ___ wide register. And this may be defined anywhere in the ______.

a. 8 byte, on-chip 128 byte RAM.

b. 8 bit, on chip 256 byte RAM.

c. 16 bit, on-chip 128 byte ROM

d. 8 bit, on chip 128 byte RAM.

44. After reset, SP register is initialized to address________.

a) 8H

b) 9H

c) 7H

d) 6H

45. What is the address range of SFR Register bank?

a) 00H-77H

b) 40H-80H

c) 80H-7FH

d) 80H-FFH

DEPARTMENT OF ECE


46. Which pin of port 3 is has an alternative function as write control signal for external data

memory?

a) P3.8

b) P3.3

c) P3.6

d) P3.1

47. What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW respectively?

a) 88H, 98H, 99H, 87H, 0D0H.

b) 98H, 99H, 87H, 88H, 0D0H

c) 0D0H, 87H, 88H, 99H, 98H

d) 87H, 88H, 0D0H, 98H, 99H

48. Match the following:

1) TCON i) contains status information

2) SBUF ii) timer / counter control register.

3) TMOD iii) idle bit, power down bit

4) PSW iv) serial data buffer for Tx and Rx.

5) PCON v) timer/ counter modes of operation.

a) 1->ii, 2->iv, 3->v, 4->i, 5->iii.

b) 1->i, 2->v, 3->iv, 4->iii, 5->ii.

c) 1->v, 2->iii, 3->ii, 4->iv, 5->i.

d) 1->iii, 2->ii, 3->i, 4->v, 5->iv.

49. Which of the following is of bit operations?

i) SP ii) P2 iii) TMOD iv) SBUF v) IP

a) ii, v only

b) ii, iv, v only

c) i, v only

d) iii, ii only

50. Serial port interrupt is generated, if ____ bits are set

a) IE

b) RI, IE

c) IP, TI

d) RI, TI

51.Which of the following instruction perform as of indirect RAM to accumulator?

a) MOV A, Rn

b) MOV @Ri, A

c) MOV A, @Ri

d) MOV Rn, A

DEPARTMENT OF ECE


52. ACALL instruction allows specifying ______address in the instruction and calling

subroutine within ______ program memory block.

a) 2byte, 3K

b) 11bit, 2K

c) 9bit, 2K

d) 1byte, 3K

53. Which of the following instruction perform the move accumulator to external RAM of

16bit address?

a) MOV @ DPTR, A

b) MOVX @ Ri, A

c) MOV A, @ Ri

d) MOVX @ DPTR, A

54. Which of the following instruction perform jump indirect relative to DPTR ?

a) JMP A+DPTR

b) JMP DPTR

c) JMP @A+DPTR

d) SJMP A+DPTR

55. Which of the following instruction is wrong?

a) INC DPTR

b) MOV @DPTR, A

c) MOV A, @A+DPTR

d) DEC DPTR

56. Which of the following instruction is of logical instructions?

i) CPL A ii) JC rel iii) DA A iv) ANL A, Rn v) RR A vi) CPL bit

a) i, v

b) v, iii, I

c) iv, ii

d) v, iii, ii

57. What instruction performs Compare immediate to indirect and jump if not equal.

a) CJNE A, #data, rel

b) CJNE Rn, #data, rel

c) CJNE @ Ri, #data, rel

d) CJNE A, data, rel

58. What is the Result of RR A instruction if accumulator contains 1000 0000.

a) 0000 0001

b) 0000 0000

c) 0100 0000

d) 0000 0010

DEPARTMENT OF ECE


59. What is the location value of R0 and the content at that place?

MOV R0, 45H

INC R0

MOV @R0, #30

a) 45H, 4F

b) 50H, 30H

c) 30H, 50H

d) 50H, 45H

60. Which of the following is of type memory initialized Directive?

i) DS ii) SET iii) DW iv) DBIT

a) i, iii

b) ii

c) iii

d) iv, ii

61. Which of the following is not a program linking directive

i) EXTRN ii) SEGMENT iii) NAME iv) PUBLIC

v) USING

a) iv, v

b) ii, iii

c) i, iii

d) ii, v

62. SP of 8051 is of ___ wide and it is loaded with the default value of ___ after reset.

a) 2 byte, 08H

b) 8 bit, 07H

c) 1 byte, 09H

d) 8 bit, 06H

63. Which of the following instruction is used to set bit port directly?

a) SET P1.0

b) MOV P1.0, bit

c) SETB P1.0

d) JB P1.0, bit

64. MOV A, #56H

MOV R1, #50H

MOV 50H, # 45H

XCHD A, @R1

What is the result at A, R1?

a) 56H, 45H

b) 45H, 50H

c) 50H, 56H

d) 45H, 56H

65. The internal RAM memory of the 8051 is;

a) 32 bytes

b) 64 bytes

c) 128 bytes

d) 256 bytes

DEPARTMENT OF ECE


66. Data transfer from I/O to external data memory can only be done with the MOVX

command.

a. TRUE b.False

67. The contents of different registers are given below. Form Effective addresses for

different addressing modes are as follow : Offset = 5000H

[AX]- 1000H, [BX]- 2000H, [SI]- 3000H, [DI]- 4000H, [BP]- 5000H,

[SP]- 6000H, [CS]- 0000H, [DS]- 1000H, [SS]- 2000H, [IP]- 7000H.

I. MOV AX, [5000H]

a) 5000H b) 15000H c) 10500H

68. The conditional branch instruction JNS performs the operations when if __

a) ZF =0 b) SF=0 c) PF=0 d) CF=0

69. Vector address of TRAP

a) 24H b) 36H c) 24 d) 18H

70. SOD pin can drive a D flip-flop?

a) SOD cannot drive any flip-flops.

b) SOD cannot drive D flip-flop, but can drive any other flop-flops.

c) Yes, SOD can drive D flop-flop.

d) No, SOD cannot drive any other flop-flops except D flop-flop.

71. IDIV and DIV instructions perform the same operations for?

a) Unsigned number

b) b) Signed number

c) c) Signed number & Unsigned number

d) d) none of above.

72. What is the output of the following code

AL=88 BCD, CL=49 BCD

ADD AL, CL

DAA

a) D7, CF=1

b) 37, CF=1

c) 73, CF=1

d) 7D, CF=1

DEPARTMENT OF ECE



AL= 49 BCD, BH= 72 BCD

SUB AL, BH

DAS

a) AL=D7, CF=1.

b) AL=7D, CF=1.

c) AL=77, CF=1

d) none of them.

74.What is the output of the following code

AL= -28 decimal, BL=59 decimal

IMUL BL

AX=? , MSB=?

a) AX= F98CH, MSB=1.

b) AX= 1652, MSB=1.

c) BX F9C8H, MSB=1.

d) BX= 1652, MSB=1.


AL= 00110100 BL= 00111000

ADD AL, BL

AAA

a) AL = 6CH

b) 12H

c) 12

d) C6H


AL=00110101 BL= 39H

SUB AL, BL AAS

a) AL= 00000100, CF=1

b) BL=00000100, CF=0

c) AL=11111100 CF=1

d) BL= 00000100, CF=1


CF =0, BH = 179

RCL BH, 1

a) CF=0, OF= 1, BH= 01100101

b) CF=1, OF=1, BH=01100110

c) CF=1, OF =0, BH= 01001101

d) CF=0, OF=0, BH=00101100

DEPARTMENT OF ECE



SI=10010011 10101101, CF=0

SHR SI, 1

a) 37805, CF=1, OF=1

b) 18902, CF=1, OF=1

c) 19820, CF=1, OF=1

d) 53708, CF=1, OF=1


BX=23763 CL=8

ROL BX, CL

a) 0101110011010011, CF=0

b) 1101001101011100, CF=0

c) 0110100010011101, CF=1

d) 1011100110001100, CF=1

80. What is the output of the following code PUSH AL

a) Decrement SP by 2 & push a word to stack

b) Increment SP by 2 & push a word to stack

c) Decrement SP by 2 & push a AL to stack

d) Illegal


AX = 37D7H, BH = 151 decimal

DIV BH

a) AL = 65H, AH= 94 decimal

b) AL= 5EH, AH= 101 decimal

c) AH= E5H, AL= 5EH

d) AL= 56H, AH= 5EH

82. In 8086 microprocessor one of the following instructions is executed before an arithmetic

operation

a) AAM

b) AAD

c) DAS

d) DAA

83.An alternate function of port pin P3.4 in the 8051 is:

a) Timer0

b) Timer 1

c) Interrupt 0

d) Interrupt 1

DEPARTMENT OF ECE


84. The I/O ports that are used as address and data for external memory are:

a) Ports 1 and 2

b) Ports 1and 3

c) Ports 0and 2

d) Ports 0 and 3

85. Which of the following statements will add the accumulator and register 3?

a.ADD @R3, @A

b.ADD@A,R3

c.ADD R3,AADD A,R3

86. The special function registers can be referred to by their hex addresses or by their register names.

a. True b. false

87. Which of the following commands will copy the contents of RAM whose address is in register 0 to port 1?

a. MOV @ P1, R0

b. MOV @ R0, P1

c. MOV P1, @ R0

d. MOV P1, R0

88. Which of the following commands will copy the contents of location 4H to the accumulator?

a. MOV A, 04H

b. MOV A, L4

c. MOV L4, A

d. MOV 04H, A

89. Which of the following instructions will load the value 35H into the high byte of timer 0?

a. MOV TH0, #35H

b. MOV TH0, 35H

c. MOV T0, #35H

d. MOV T0, 35H

90. Bit-addressable memory locations are:

a. 0000 to FFFFH

b. 000 to FFFH

c. 00 to FFH

d. 0 to FH

91.T he I/O port that does not have a dual-purpose role is:

a. port 0

b. port 1

c. port 2

d. port3

92. How many buses are connected as part of the 8085A microprocessor?

a. 2

b. 3

c. 5

d. 8

mailto:b.ADD@A,R3

DEPARTMENT OF ECE


93. The technique of assigning a memory address to each I/O device in the computer system is called:

a. memory-mapped I/O

b. ported I/O

c. dedicated I/O

d. wired I/O

94.PROMs are used to store

a. Bulk information

b. sequential information

c. information to be accessed rarely

d. relatively permanent information

95. In a microprocessor, the register which holds the address of the next instruction to be fetched is.

a. accumulator

b. Program counter

c. stack pointer

d. instructor register

96.the contents of accumulator after the execution of following instruction will be

MVI A,A7H

ORA A

RLC

a. A.CF H

b. B.4F H

c. C.4E H

d. CE H

97.the instruction DAA

a. converts binary to BCD

b. converts BCD to binary

c. decrements accumulator

d. d .add contents of accumulator to accumulator

98.each cell of a station Random access memory contains

a. 6 MOS transistor

b. 4 MOS transistor and 2 capacitors

c. two 2-input NORs and one X-Nor gate

d. XOR gates and shift register

99.In a 8085 microprocessor system with memory mapped I/O

a. I/O devices have 8-bit address

b. I/O devices are accessed using N and out instructions

c. there can be a maximum of 256 inputs devices and 256 output devices

d. Arithmetic and logic operations can be directly performed with the I/O data.

DEPARTMENT OF ECE


100.consider the execution of the following instruction by 8085

MVI H,01FFH

SHLD 2050H

After execution the contents of memory location 2050h,2051h and register H,L will be respectively

a. 01H,FFH,FFH,01H

b. FFH,01H,FFH,01H

c. FFH,01H,01H,FFH

d. 01H,FFH,01H,FFH

DEPARTMENT OF ECE


Answer

1.C 2.C 3.C 4.B 5.B

6.B 7.A 8.B 9.A 10.C

11.B 12.B 13.A 14.C 15.B

16.C 17.C 18.B 19.D 20.B

21.A 22.B 23.A 24.B 25.A

26.A 27.B 28.C 29.C 30.C

31.C 32.B 33.B 34.D 35.C

36.C 37.B 38.A 39.A 40.C

41.C 42.C 43.D 44.C 45.D

46.C 47.A 48.A 49.A 50.D

51.C 52.B 53.D 54.C 55.B

56.A 57.C 58.C 59.B 60.C

61.D 62.B 63.C 64.D 65.C

66.A 67.B 68.B 69.A 70.C

71.B 72.B 73.C 74.A 75.C

76.A 77.B 78.B 79.B 80.D

81.B 82.B 83.A 84.C 85.D

86.C 87.A 88.A 89.A 90.B

91.B 92.B 93.A 94.C 95.B

96.B 97.A 98.A 99.D 100.C

DEPARTMENT OF ECE


INTERVIEW QUESTIONS

DEPARTMENT OF ECE


1.What are the various registers in 8085? - Accumulator register, Temporary register,

Instruction register, Stack Pointer, Program Counter are the various registers in 8085 .

2.In 8085 name the 16 bit registers? - Stack pointer and Program counter all have 16 bits.

3.What are the various flags used in 8085? - Sign flag, Zero flag, Auxillary flag, Parity flag,

Carry flag.

4.What is Stack Pointer? - Stack pointer is a special purpose 16-bit register in the

Microprocessor, which holds the address of the top of the stack.

5.What is Program counter? - Program counter holds the address of either the first byte of the

next instruction to be fetched for execution or the address of the next byte of a multi byte

instruction, which has not been completely fetched. In both the cases it gets incremented

automatically one by one as the instruction bytes get fetched. Also Program register keeps the

address of the next instruction.

6.Which Stack is used in 8085? - LIFO (Last In First Out) stack is used in 8085.In this type

of Stack the last stored information can be retrieved first.

7.What happens when HLT instruction is executed in processor? - The Micro Processor

enters into Halt-State and the buses are tri-stated.

8.What is meant by a bus? - A bus is a group of conducting lines that carriers data, address, &

control signals.

9.What is Tri-state logic? - Three Logic Levels are used and they are High, Low, High

impedance state. The high and low are normal logic levels & high impedance state is

electrical open circuit conditions. Tri-state logic has a third line called enable line.

10. Give an example of one address microprocessor? - 8085 is a one address microprocessor.

11. In what way interrupts are classified in 8085? - In 8085 the interrupts are classified as

Hardware and Software interrupts.

12. What are Hardware interrupts? - TRAP, RST7.5, RST6.5, RST5.5, INTR.

13. What are Software interrupts? - RST0, RST1, RST2, RST3, RST4, RST5, RST6, RST7.

14. Which interrupt has the highest priority? - TRAP has the highest priority.

15. Name 5 different addressing modes? - Immediate, Direct, Register, Register indirect,

Implied addressing modes.

16. How many interrupts are there in 8085? - There are 12 interrupts in 8085.

17. What is clock frequency for 8085? - 3 MHz is the maximum clock frequency for 8085.

18. What is the RST for the TRAP? - RST 4.5 is called as TRAP.

19. In 8085 which is called as High order / Low order Register? - Flag is called as Low order

register & Accumulator is called as High order Register.

DEPARTMENT OF ECE


20. What are input & output devices? - Keyboards, Floppy disk are the examples of input

devices. Printer, LED / LCD display, CRT Monitor are the examples of output devices.

21. Can an RC circuit be used as clock source for 8085? - Yes, it can be used, if an accurate

clock frequency is not required. Also, the component cost is low compared to LC or Crystal.

22. Why crystal is a preferred clock source? - Because of high stability, large Q (Quality

Factor) & the frequency that doesn‘t drift with aging. Crystal is used as a clock source most

of the times.

23. Which interrupt is not level-sensitive in 8085? - RST 7.5 is a raising edge-triggering

interrupt.

24. What does Quality factor mean? - The Quality factor is also defined, as Q. So it is a

number, which reflects the lossness of a circuit. Higher the Q, the lower are the losses.

25. What are level-triggering interrupt? - RST 6.5 & RST 5.5 are level-triggering interrupts.

26. What is a Microprocessor?

Microprocessor is a program-controlled device, which fetches the instructions from memory,

decodes and executes the instructions. Most Micro Processor are single- chip devices.

27. What is SIM and RIM instructions?

SIM is Set Interrupt Mask. Used to mask the hardware interrupts.

RIM is Read Interrupt Mask. Used to check whether the interrupt is Masked or not.

28. Define interrupt?

Interrupt is an signal sent or given to the processor in order to interrupt or to stop the current

process/execution and transfer the control to the specified process in order to perform

particular task.

29. Difference between microprocessor and microcontroller?

30. What are the flags in 8086? - In 8086 Carry flag, Parity flag, Auxiliary carry flag, Zero

flag, Overflow flag, Trace flag, Interrupt flag, Direction flag, and Sign flag.

31. Give examples for Micro controller? - Z80, Intel MSC51 &96, Motorola are the best

examples of Microcontroller.

32. What is the difference between 8086 and 8088? - The BIU in 8088 is 8-bit data bus & 16-

bit in 8086.Instruction queue is 4 byte long in 8088and 6 byte in 8086.

DEPARTMENT OF ECE


CHAPTER 3

DIGITAL

ELECTRONICS

DEPARTMENT OF ECE


Digital electronics represent signals by discrete bands of analog levels, rather than by a

continuous range. All levels within a band represent the same signal state. Relatively small

changes to the analog signal levels due to manufacturing tolerance, signal attenuation or

parasitic noise do not leave the discrete envelope, and as a result are ignored by signal state

sensing circuitry.

In most cases the number of these states is two, and they are represented by two voltage

bands: one near a reference value (typically termed as "ground" or zero volts) and a value

near the supply voltage, corresponding to the "false" ("0") and "true" ("1") values of the

Boolean domain respectively.

Digital techniques are useful because it is easier to get an electronic device to switch into one

of a number of known states than to accurately reproduce a continuous range of values.

Digital electronic circuits are usually made from large assemblies of logic gates, simple

electronic representations of Boolean logic functions.

Advantages:

One advantage of digital circuits when compared to analog circuits is [2]

signals represented

digitally can be transmitted without degradation due to noise. For example, a continuous

audio signal, transmitted as a sequence of 1s and 0s, can be reconstructed without error

provided the noise picked up in transmission is not enough to prevent identification of the 1s

and 0s. An hour of music can be stored on a compact disc using about 6 billion binary digits.

In a digital system, a more precise representation of a signal can be obtained by using more

binary digits to represent it. While this requires more digital circuits to process the signals,

each digit is handled by the same kind of hardware. In an analog system, additional resolution

requires fundamental improvements in the linearity and noise characteristics of each step of

the signal chain.

Computer-controlled digital systems can be controlled by software, allowing new functions to

be added without changing hardware. Often this can be done outside of the factory by

updating the product's software. So, the product's design errors can be corrected after the

product is in a customer's hands.

Information storage can be easier in digital systems than in analog ones. The noise-immunity

of digital systems permits data to be stored and retrieved without degradation. In an analog

system, noise from aging and wear degrade the information stored. In a digital system, as

long as the total noise is below a certain level, the information can be recovered perfectly.

http://en.wikipedia.org/wiki/Signal_(electronics)

http://en.wikipedia.org/wiki/Analog_electronics

http://en.wikipedia.org/wiki/Electrical_potential

http://en.wikipedia.org/wiki/Engineering_tolerance

http://en.wikipedia.org/wiki/Path_loss

http://en.wikipedia.org/wiki/Noise_(electronics)

http://en.wikipedia.org/wiki/Boolean_domain

http://en.wikipedia.org/wiki/Logic_gate

http://en.wikipedia.org/wiki/Boolean_logic#Digital_electronic_circuit_design

http://en.wikipedia.org/wiki/Digital_electronics#cite_note-1

http://en.wikipedia.org/wiki/Noise

http://en.wikipedia.org/wiki/Compact_disc

http://en.wikipedia.org/wiki/Signal_chain_(signal_processing_chain)

DEPARTMENT OF ECE


Disadvantages:

In some cases, digital circuits use more energy than analog circuits to accomplish the same

tasks, thus producing more heat which increases the complexity of the circuits such as the

inclusion of heat sinks. In portable or battery-powered systems this can limit use of digital

systems.

For example, battery-powered cellular telephones often use a low-power analog front-end to

amplify and tune in the radio signals from the base station. However, a base station has grid

power and can use power-hungry, but very flexible software radios. Such base stations can be

easily reprogrammed to process the signals used in new cellular standards.

Digital circuits are sometimes more expensive, especially in small quantities.

Most useful digital systems must translate from continuous analog signals to discrete digital

signals. This causes quantization errors. Quantization error can be reduced if the system

stores enough digital data to represent the signal to the desired degree of fidelity. The

Nyquist-Shannon sampling theorem provides an important guideline as to how much digital

data is needed to accurately portray a given analog signal.

In some systems, if a single piece of digital data is lost or misinterpreted, the meaning of

large blocks of related data can completely change. Because of the cliff effect, it can be

difficult for users to tell if a particular system is right on the edge of failure, or if it can

tolerate much more noise before failing.

Digital fragility can be reduced by designing a digital system for robustness. For example, a

parity bit or other error management method can be inserted into the signal path. These

schemes help the system detect errors, and then either correct the errors, or at least ask for a

new copy of the data. In a state-machine, the state transition logic can be designed to catch

unused states and trigger a reset sequence or other error recovery routine.

Digital memory and transmission systems can use techniques such as error detection and

correction to use additional data to correct any errors in transmission and storage.

On the other hand, some techniques used in digital systems make those systems more

vulnerable to single-bit errors. These techniques are acceptable when the underlying bits are

reliable enough that such errors are highly unlikely. A single-bit error in audio data stored

directly as linear pulse code modulation (such as on a CD-ROM) causes, at worst, a single

click. Instead, many people use audio compression to save storage space and download time,

even though a single-bit error may corrupt the entire song.

http://en.wikipedia.org/wiki/Amplifier

http://en.wikipedia.org/wiki/Tuner_(electronics)

http://en.wikipedia.org/wiki/Radio

http://en.wikipedia.org/wiki/Software_radio

http://en.wikipedia.org/wiki/Quantization_error

http://en.wikipedia.org/wiki/Fidelity

http://en.wikipedia.org/wiki/Nyquist-Shannon_sampling_theorem

http://en.wikipedia.org/wiki/Cliff_effect

http://en.wikipedia.org/wiki/Parity_bit

http://en.wikipedia.org/wiki/Error_correction_and_detection

http://en.wikipedia.org/wiki/Error_detection_and_correction

http://en.wikipedia.org/wiki/Linear_pulse_code_modulation

http://en.wikipedia.org/wiki/CD-ROM

http://en.wikipedia.org/wiki/Audio_compression_(data)

DEPARTMENT OF ECE


Design issues in digital circuits:

Digital circuits are made from analog components. The design must assure that the analog

nature of the components doesn't dominate the desired digital behavior. Digital systems must

manage noise and timing margins, parasitic inductances and capacitances, and filter power

connections.

Bad designs have intermittent problems such as "glitches", vanishingly-fast pulses that may

trigger some logic but not others, "runt pulses" that do not reach valid "threshold" voltages, or

unexpected ("undecoded") combinations of logic states.

Additionally, where clocked digital systems interface to analogue systems or systems that are

driven from a different clock, the digital system can be subject to metastability where a

change to the input violates the set-up time for a digital input latch. This situation will self-

resolve, but will take a random time, and while it persists can result in invalid signals being

propagated within the digital system for a short time.

Since digital circuits are made from analog components, digital circuits calculate more slowly

than low-precision analog circuits that use a similar amount of space and power. However,

the digital circuit will calculate more repeatably, because of its high noise immunity. On the

other hand, in the high-precision domain (for example, where 14 or more bits of precision are

needed), analog circuits require much more power and area than digital equivalents.

Structure of digital systems:

Engineers use many methods to minimize logic functions, in order to reduce the circuit's

complexity. When the complexity is less, the circuit also has fewer errors and less

electronics, and is therefore less expensive.

The most widely used simplification is a minimization algorithm like the Espresso heuristic

logic minimizer within a CAD system, although historically, binary decision diagrams, an

automated Quine–McCluskey algorithm, truth tables, Karnaugh maps, and Boolean algebra

have been used.

Representations are crucial to an engineer's design of digital circuits. Some analysis methods

only work with particular representations.

The classical way to represent a digital circuit is with an equivalent set of logic gates.

Another way, often with the least electronics, is to construct an equivalent system of

electronic switches (usually transistors). One of the easiest ways is to simply have a memory

containing a truth table. The inputs are fed into the address of the memory, and the data

outputs of the memory become the outputs.

http://en.wikipedia.org/wiki/Electronic_filter

http://en.wikipedia.org/wiki/Runt_pulse

http://en.wikipedia.org/wiki/Metastability_in_electronics

http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer

http://en.wikipedia.org/wiki/Espresso_heuristic_logic_minimizer

http://en.wikipedia.org/wiki/Computer-aided_design

http://en.wikipedia.org/wiki/Binary_decision_diagrams

http://en.wikipedia.org/wiki/Quine%E2%80%93McCluskey_algorithm

http://en.wikipedia.org/wiki/Truth_table

http://en.wikipedia.org/wiki/Karnaugh_map

http://en.wikipedia.org/wiki/Boolean_algebra_(logic)

http://en.wikipedia.org/wiki/Logic_gates

http://en.wikipedia.org/wiki/Transistor

DEPARTMENT OF ECE


For automated analysis, these representations have digital file formats that can be processed

by computer programs. Most digital engineers are very careful to select computer programs

("tools") with compatible file formats.

To choose representations, engineers consider types of digital systems. Most digital systems

divide into "combinational systems" and "sequential systems." A combinational system

always presents the same output when given the same inputs. It is basically a representation

of a set of logic functions, as already discussed.

A sequential system is a combinational system with some of the outputs fed back as inputs.

This makes the digital machine perform a "sequence" of operations. The simplest sequential

system is probably a flip flop, a mechanism that represents a binary digit or "bit".

Sequential systems are often designed as state machines. In this way, engineers can design a

system's gross behavior, and even test it in a simulation, without considering all the details of

the logic functions.

Sequential systems divide into two further subcategories. "Synchronous" sequential systems

change state all at once, when a "clock" signal changes state. "Asynchronous" sequential

systems propagate changes whenever inputs change. Synchronous sequential systems are

made of well-characterized asynchronous circuits such as flip-flops, that change only when

the clock changes, and which have carefully designed timing margins.

The usual way to implement a synchronous sequential state machine is to divide it into a

piece of combinational logic and a set of flip flops called a "state register." Each time a clock

signal ticks, the state register captures the feedback generated from the previous state of the

combinational logic, and feeds it back as an unchanging input to the combinational part of the

state machine. The fastest rate of the clock is set by the most time-consuming logic

calculation in the combinational logic.

The state register is just a representation of a binary number. If the states in the state machine

are numbered (easy to arrange), the logic function is some combinational logic that produces

the number of the next state.

In comparison, asynchronous systems are very hard to design because all possible states, in

all possible timings must be considered. The usual method is to construct a table of the

minimum and maximum time that each such state can exist, and then adjust the circuit to

minimize the number of such states, and force the circuit to periodically wait for all of its

parts to enter a compatible state (this is called "self-resynchronization"). Without such careful

design, it is easy to accidentally produce asynchronous logic that is "unstable", that is, real

electronics will have unpredictable results because of the cumulative delays caused by small

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://en.wikipedia.org/wiki/Binary_number_system

http://en.wikipedia.org/wiki/Numerical_digit

http://en.wikipedia.org/wiki/Bit

http://en.wikipedia.org/wiki/State_machine

http://en.wikipedia.org/wiki/Synchronous_system

http://en.wikipedia.org/wiki/Asynchronous_system

http://en.wikipedia.org/wiki/Asynchronous_system

DEPARTMENT OF ECE


variations in the values of the electronic components. Certain circuits (such as the

synchronizer flip-flops, switch debouncers, arbiters, and the like which allow external

unsynchronized signals to enter synchronous logic circuits) are inherently asynchronous in

their design and must be analyzed as such.

As of 2005, almost all digital machines are synchronous designs because it is much easier to

create and verify a synchronous design—the software currently used to simulate digital

machines does not yet handle asynchronous designs. However, asynchronous logic is thought

to be superior, if it can be made to work, because its speed is not constrained by an arbitrary

clock; instead, it runs at the maximum speed of its logic gates. Building an asynchronous

circuit using faster parts makes the circuit faster.

Many digital systems are data flow machines. These are usually designed using synchronous

register transfer logic, using hardware description languages such as VHDL or Verilog.

In register transfer logic, binary numbers are stored in groups of flip flops called registers.

The outputs of each register are a bundle of wires called a "bus" that carries that number to

other calculations. A calculation is simply a piece of combinational logic. Each calculation

also has an output bus, and these may be connected to the inputs of several registers.

Sometimes a register will have a multiplexer on its input, so that it can store a number from

any one of several buses. Alternatively, the outputs of several items may be connected to a

bus through buffers that can turn off the output of all of the devices except one. A sequential

state machine controls when each register accepts new data from its input.

In the 1980s, some researchers discovered that almost all synchronous register-transfer

machines could be converted to asynchronous designs by using first-in-first-out

synchronization logic. In this scheme, the digital machine is characterized as a set of data

flows. In each step of the flow, an asynchronous "synchronization circuit" determines when

the outputs of that step are valid, and presents a signal that says, "grab the data" to the stages

that use that stage's inputs. It turns out that just a few relatively simple synchronization

circuits are needed.

The most general-purpose register-transfer logic machine is a computer. This is basically an

automatic binary abacus. The control unit of a computer is usually designed as a micro

program run by a micro sequencer. A micro program is much like a player-piano roll. Each

table entry or "word" of the micro program commands the state of every bit that controls the

computer. The sequencer then counts, and the count addresses the memory or combinational

logic machine that contains the micro program. The bits from the micro program control the

http://en.wikipedia.org/wiki/Debounce

http://en.wikipedia.org/wiki/Arbiter_(electronics)

http://en.wikipedia.org/wiki/Register_transfer_level

http://en.wikipedia.org/wiki/VHDL

http://en.wikipedia.org/wiki/Verilog

http://en.wikipedia.org/wiki/Number

http://en.wikipedia.org/wiki/Processor_register

http://en.wikipedia.org/wiki/Computer_bus

http://en.wikipedia.org/wiki/Multiplexer

http://en.wikipedia.org/wiki/3-state

http://en.wikipedia.org/wiki/Computer

http://en.wikipedia.org/wiki/Automaton

http://en.wikipedia.org/wiki/Abacus

http://en.wikipedia.org/wiki/Control_unit

http://en.wikipedia.org/wiki/Microprogram

http://en.wikipedia.org/wiki/Microprogram

http://en.wikipedia.org/wiki/Microsequencer

DEPARTMENT OF ECE


arithmetic logic unit, memory and other parts of the computer, including the micro sequencer

itself.

In this way, the complex task of designing the controls of a computer is reduced to a simpler

task of programming a collection of much simpler logic machines.

Computer architecture is a specialized engineering activity that tries to arrange the registers,

calculation logic, buses and other parts of the computer in the best way for some purpose.

Computer architects have applied large amounts of ingenuity to computer design to reduce

the cost and increase the speed and immunity to programming errors of computers. An

increasingly common goal is to reduce the power used in a battery-powered computer system,

such as a cell-phone. Many computer architects serve an extended apprenticeship as micro

programmers.

"Specialized computers" are usually a conventional computer with a special-purpose micro

program.

BOOLEAN ALGEBRA:

Basic operations

After values, the next ingredient of any algebraic system is its operations. Whereas

elementary algebra is based on numeric operations multiplication xy, addition x + y, and

negation −x, Boolean algebra is customarily based on logical counterparts to those

operations, namely conjunction: x∧y or Kxy (AND); disjunction: x∨y or Axy (OR); and

complement or negation: ¬x or Nx (NOT). In electronics, the AND is represented as a

multiplication, the OR is represented as an addition, and the NOT is represented with an over

bar: x ∧ y and x ∨ y, therefore, become xy and x + y.

Conjunction is the closest of these three to its numerical counterpart: consider 0 and 1 = 0,

and 1 and 1 = 1; it is multiplication. As a logical operation the conjunction of two

propositions is true when both propositions are true, and otherwise is false. The first column

of Figure 1 below tabulates the values of x∧y for the four possible valuations for x and y;

such a tabulation is traditionally called a truth table.

Disjunction, in the second column of the figures, works almost like addition, with one

exception: the disjunction of 1 and 1 is neither 2 nor 0 but 1. Thus the disjunction of two

propositions is false when both propositions are false, and otherwise is true. This is just the

definition of conjunction with true and false interchanged everywhere because of this we say

that disjunction is the dual of conjunction.

http://en.wikipedia.org/wiki/Arithmetic_logic_unit

http://en.wikipedia.org/wiki/Memory

http://en.wikipedia.org/wiki/Computer_architecture

http://en.wikipedia.org/wiki/Logical_and

http://en.wikipedia.org/wiki/Logical_or

http://en.wikipedia.org/wiki/Logical_not

http://en.wikipedia.org/wiki/Truth_table

DEPARTMENT OF ECE


Logical negation however does not work like numerical negation at all. Instead it corresponds

to incrementation: ¬x = x+1 mod 2. Yet it shares in common with numerical negation the

property that applying it twice returns the original value: ¬¬x = x, just as − (−x) = x. An

operation with this property is called an involution. The set {0, 1} has two permutations, both

involuntary, namely the identity, no movement, corresponding to numerical negation mod 2

(since +1 = −1 mod 2), and SWAP, corresponding to logical negation. Using negation we can

formalize the notion that conjunction is dual to disjunction via De Morgan's laws, ¬ (x∧y) =

¬x ∨ ¬y and ¬ (x∨y) = ¬x ∧ ¬y. These can also be construed as definitions of conjunction in

terms of disjunction and vice versa: x∧y = ¬ (¬x ∨ ¬y) and x∨y = ¬ (¬x ∧ ¬y).

Various representations of Boolean operations

Figure shows the symbols used in digital electronics for conjunction and disjunction; the

input ports are on the left and the signals flow through to the output port on the right.

Inverters negating the input signals on the way in, or the output signals on the way out, are

represented as circles on the port to be inverted.

FLIP-FLOPS:

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to

store state information. The circuit can be made to change state by signals applied to one or

more control inputs and will have one or two outputs. It is the basic storage element in

http://en.wikipedia.org/wiki/Permutations

http://en.wikipedia.org/wiki/De_Morgan%27s_laws

http://en.wikipedia.org/wiki/Digital_electronics

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/File:Baops.gif




DEPARTMENT OF ECE


sequential logic. Flip-flops and latches are a fundamental building block of digital electronics

systems used in computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data storage can be used for

storage of state, and such a circuit is described as sequential logic. When used in a finite-state

machine, the output and next state depend not only on its current input, but also on its current

state (and hence, previous inputs). It can also be used for counting of pulses, and for

synchronizing variably-timed input signals to some reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-

triggered); the simple ones are commonly called latches.[1]

The word latch is mainly used for

storage elements, while clocked devices are described as flip-flops.[2]

Flip-Flops block diagram and their properties:

Flip-flops are synchronous bistable devices. The term synchronous means the output changes

state only when the clock input is triggered. That is, changes in the output occur in

synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value

and one for the complement value of the stored bit. Since memory elements in sequential

circuits are usually flip-flops, it is worth summarizing the behaviour of various flip-flop types

before proceeding further. All flip-flops can be divided into four basic types: SR, JK, D and

T. They differ in the number of inputs and in the response invoked by different value of input

signals. The four types of flip-flops are defined in the Table 5.1. Each of these flip-flops can

be uniquely described by its graphical symbol, its characteristic table, its characteristic

equation or excitation table. All flip-flops have output signals Q and Q'.

Flip-

Flop

Name

Flip-Flop

Symbol Characteristic Table

Characteristic

Equation Excitation Table

SR

S R Q(next)

0 0 Q

0 1 0

1 0 1

1 1 ?

Q(next) = S + R’Q

SR = 0

Q Q(next) S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

http://en.wikipedia.org/wiki/Sequential_logic

http://en.wikipedia.org/wiki/Digital_electronics

http://en.wikipedia.org/wiki/State_(computer_science)

http://en.wikipedia.org/wiki/Sequential_logic

http://en.wikipedia.org/wiki/Finite-state_machine

http://en.wikipedia.org/wiki/Finite-state_machine

http://en.wikipedia.org/wiki/Clock_signal

http://en.wikipedia.org/wiki/Flip-flop_(electronics)#cite_note-pedroni-0

http://en.wikipedia.org/wiki/Flip-flop_(electronics)#cite_note-ee42-1

DEPARTMENT OF ECE


JK

J K Q(next)

0 0 Q

0 1 0

1 0 1

1 1 Q’

Q(next) = JQ’ +

K’Q

Q Q(next) J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

D

D Q(next)

0 0

1 1

Q(next) = D

Q Q(next) D

0 0 0

0 1 1

1 0 0

1 1 1

T

T Q(next)

0 Q

1 Q’

Q(next) = TQ’ +

T’Q

Q Q(next) T

0 0 0

0 1 1

1 0 1

1 1 0

Table 5.1 Flip-flops and their properties

Logic Diagram

D- Flip Flop

DEPARTMENT OF ECE


JK Flip Flop

T Flip Flop

MULTIPLEXER & DEMULTIPLEXER:

In electronics, a multiplexer (or MUX) is a device that selects one of several analog or

digital input signals and forwards the selected input into a single line.[1]

A multiplexer of 2n

inputs has n select lines, which are used to select which input line to send to the output.[2]

Multiplexers are mainly used to increase the amount of data that can be sent over the network

within a certain amount of time and bandwidth.[1]

A multiplexer is also called a data

selector. They are used in CCTV, and almost every business that has CCTV fitted, will own

one of these.

An electronic multiplexer makes it possible for several signals to share one device or

resource, for example one A/D converter or one communication line, instead of having one

device per input signal.

On the other hand, a demultiplexer (or demux) is a device taking a single input signal and

selecting one of many data-output-lines, which is connected to the single input. A multiplexer

is often used with a complementary demultiplexer on the receiving end.[1]

An electronic multiplexer can be considered as a multiple-input, single-output switch, and a

demultiplexer as a single-input, multiple-output switch.[3]

The schematic symbol for a

multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins

and the short parallel side containing the output pin.[4]

The schematic on the right shows a 2-

to-1 multiplexer on the left and an equivalent switch on the right. The wire connects the

desired input to the output.

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Analog_signal

http://en.wikipedia.org/wiki/Digital_signal

http://en.wikipedia.org/wiki/Multiplexer#cite_note-Network.2B_Guide_to_Networks-0

http://en.wikipedia.org/wiki/Multiplexer#cite_note-1

http://en.wikipedia.org/wiki/Computer_network

http://en.wikipedia.org/wiki/Bandwidth_(signal_processing)


http://en.wikipedia.org/wiki/A/D_converter


http://en.wikipedia.org/wiki/MISO#Characterization_of_systems

http://en.wikipedia.org/wiki/MISO#Characterization_of_systems


http://en.wikipedia.org/wiki/Isosceles_trapezoid


DEPARTMENT OF ECE


PARALLEL VERSUS SERIAL DATA TRANSMISSIONS:

There are two methods of transmitting digital

data.These methods are parallel and serial transmissions. In parallel data transmission,

all bits of the binary data are transmitted simultaneously. For example, to transmit an 8-bit

binary number in parallel from one unit to another, eight transmission lines are

required. Each bit requires its own separate data path. All bits of a word are transmitted at

the same time. This method of transmission can move a significant amount of data in a given

period of time. Its disadvantage is the large number of interconnecting cables between

the two units. For large binary words, cabling becomes complex and expensive. This is

particularly true if the distance between the two units is great. Long multi-wire cables are not

only expensive, but also require special interfacing to minimize noise and distortion

problems. Serial data transmission is the process of transmitting binary words a bit at

a time. Since the bits time-share the transmission medium, only one interconnecting lead is

required. While serial data transmission is much simpler and less expensive because of the

use of a single interconnecting line, it is a very slow method of data transmission. Serial data

transmission is useful in systems where high speed is not a requirement. Serial

data transmission techniques are widely used in

transmitting data between a computer and its peripheral units. While the computer

operates at very high speeds, most peripheral units are slow because of their

electromechanical nature. Slower serial data transmission is more compatible with such

devices. Since the speed of serial transmission is more than adequate in such units, the

advantages of low cost and simplicity of the signal interconnecting obtained.

PARALLEL DATA TRANSMISSION:

In a parallel data transmission system, each bit of the binary word to be transmitted must

have its own data path. There are a variety of ways to implement this data path. The two basic

classifications of transmission line circuits are single-ended and balanced. Single-ended

transmission systems use a single-wire data path for each bit. When combined with a ground

or return reference, the electrical circuit between the sending circuit and the receiving circuit

is complete. In a balanced transmission line system, two conductor cables are used to send

the data. The data on the dual-transmission line is complementary. The dual-transmission

lines also use a ground return reference. While a single-ended transmission line is simpler

and less expensive, it is subject to more noise problems than the balanced or dual-

transmission line system.

DEPARTMENT OF ECE


MULTI-VIBRATOR:

A multivibrator is an electronic circuit used to implement a variety of simple two-state

systems such as oscillators, timers and flip-flops. It is characterized by two amplifying

devices (transistors, electron tubes or other devices) cross-coupled by resistors or capacitors.

The name "multivibrator" was initially applied to the free-running oscillator version of the

circuit because its output waveform was rich in harmonics. [1]

There are three types of

multivibrator circuits depending on the circuit operation:

astable, in which the circuit is not stable in either state —it continually switches from one

state to the other. It does not require an input such as a clock pulse.

monostable, in which one of the states is stable, but the other state is unstable (transient).

A trigger causes the circuit to enter the unstable state. After entering the unstable state, the

circuit will return to the stable state after a set time. Such a circuit is useful for creating a

timing period of fixed duration in response to some external event. This circuit is also known

as a one shot.

bistable, in which the circuit is stable in either state. The circuit can be flipped from one

state to the other by an external event or trigger.

Multivibrators find applications in a variety of systems where square waves or timed intervals

are required. For example, before the advent of low-cost integrated circuits, chains of

multivibrators found use as frequency dividers. A free-running multivibrator with a frequency

of one-half to one-tenth of the reference frequency would accurately lock to the reference

frequency. This technique was used in early electronic organs, to keep notes of different

octaves accurately in tune. Other applications included early television systems, where the

various line and frame frequencies were kept synchronized by pulses included in the video

signal.

http://en.wikipedia.org/wiki/Electronic_circuit

http://en.wikipedia.org/wiki/Oscillators

http://en.wikipedia.org/wiki/Timer

http://en.wikipedia.org/wiki/Flip-flop_(electronics)

http://en.wikipedia.org/wiki/Multivibrator#cite_note-0

http://en.wikipedia.org/wiki/Frequency_divider

http://en.wikipedia.org/wiki/Octave

http://en.wikipedia.org/wiki/Television

DEPARTMENT OF ECE


OBJECTIVE TYPE

QUESTION

DEPARTMENT OF ECE


1.

Any number with an exponent of zero is equal to:

a. zero

b. one

c. that number

d. ten

2. In the decimal numbering system, what is the MSD?

A. The middle digit of a stream of numbers

B. The digit to the right of the decimal point

C. The last digit on the right

D. The digit with the most weight

3. Which of the following statements does NOT describe an advantage of digital technology?

A. The values may vary over a continuous range.

B. The circuits are less affected by noise.

C. The operation can be programmed.

D. Information storage is easy.

4. The generic array logic (GAL) device is ________.

A. one-time programmable

B. reprogrammable

C. a CMOS device

D. reprogrammable and a CMOS device

5. The range of voltages between VL(max) and VH(min) are ________.

A. unknown

B. unnecessary

C. unacceptable

D. between 2 V and 5 V

6. What is a digital-to-analog converter?

A. It takes the digital information from an audio CD and converts it to a usable form.

B. It allows the use of cheaper analog techniques, which are always simpler.

C. It stores digital data on a hard drive.

D. It converts direct current to alternating current.

7. What are the symbols used to represent digits in the binary number system?

A. 0,1

B. 0,1,2

C. 0 through 8

D. 1,2

8. A full subtracter circuit requires ________.

A. two inputs and two outputs

B. two inputs and three outputs

C. three inputs and one output

D. three inputs and two outputs

DEPARTMENT OF ECE


9. The output of an AND gate is LOW ________.

A. all the time

B. when any input is LOW

C. when any input is HIGH

D. when all inputs are HIGH

10. Give the decimal value of binary 10010.

A. 610 B. 910

C. 1810 D. 2010

11. Parallel format means that:

A. each digital signal has its own conductor.

B. several digital signals are sent on each conductor.

C. both binary and hexadecimal can be used.

D. no clock is needed.

E. None

12. A decoder converts ________.

A. noncoded information into coded form

B. coded information into noncoded form

C. HIGHs to LOWs

D. LOWs to HIGHs

13. A DAC changes ________.

A. an analog signal into digital data

B. digital data into an analog signal

C. digital data into an amplified signal

D. none of the above

14. The output of a NOT gate is HIGH when ________.

A. the input is LOW

B. the input is HIGH

C. the input changes from LOW to HIGH

D. voltage is removed from the gate

15. The output of an OR gate is LOW when ________.

A. all inputs are LOW

B. any input is LOW

C. any input is HIGH

D. all inputs are HIGH

16. Which of the following is not an analog device?

A. Thermocouple

B. Current flow in a circuit

C. Light switch

D. Audio microphone

DEPARTMENT OF ECE


17. A demultiplexer has ________.

A. one data input and a number of selection inputs, and they have several outputs

B. one input and one output

C. several inputs and several outputs

D. several inputs and one output

E. None

18. A flip-flop has ________.

A. one stable state

B. no stable states

C. two stable states

D. none of the above

19. Digital signals transmitted on a single conductor (and a ground) must be transmitted in:

A. slow speed.

B. parallel.

C. analog.

D. serial.

20. In a certain digital waveform, the period is four times the pulse width. The duty cycle is

________.

A. 0% B. 25%

C. 50% D. 100%

21. In positive logic, ________.

A. a HIGH = 1, a LOW = 0

B. a LOW = 1, a HIGH = 0

C. only HIGHs are present

D. only LOWs are present

22. Convert the fractional binary number 0000.1010 to decimal.

A. 0.625 B. 0.50

C. 0.55 D. 0.10

23. Digital representations of numerical values of quantities may BEST be described as

having characteristics:

A. that are difficult to interpret because they are continuously changing.

B. that vary constantly over a continuous range of values.

C. that vary in constant and direct proportion to the values they represent.

D. that vary in discrete steps in proportion to the values they represent.

24. A common instrument used in troubleshooting a digital circuit is a(n) ________.

A. logic probe

B. oscilloscope

C. pulser

D. all of the above

DEPARTMENT OF ECE


25. The parallel transmission of digital data:

A. is much slower than the serial transmission of data.

B. requires only one signal line between sender and receiver.

C. requires as many signal lines between sender and receiver as there are data bits.

D. is less expensive than the serial method of data transmission.

26. Convert the fractional decimal number 6.75 to binary.

A. 0111.1100 B. 0110.1010

C. 0110.1100 D. 0110.0110

E. None

27. What is one relative disadvantage of serial transfer?

A. It requires too many conductors.

B. Its interconnect system is complex.

C. It is slow.

D. It can only be used over very short distances.

28. Which format requires fewer conductors?

A. Parallel

B. Serial

C. Both are the same

D. Cannot tell

29. A pulse has a period of 15 ms. Its frequency is ________.

A. 6.66 Hz

B. 66.66 Hz

C. 666.66 Hz

D. 15 Hz

30. Give the decimal value of binary 10000110.

A. 13410 B. 14410

C. 11010 D. 12610

31. The rise time is the time it takes a pulse to go from ________.

A. the base line to the maximum HIGH voltage

B. 10% of the pulse amplitude to the maximum HIGH voltage

C. the base line to 90% of the pulse amplitude

D. 10% of the pulse amplitude to 90% of the pulse amplitude

32. What is an analog-to-digital converter?

A. It makes digital signals.

B. It takes analog signals and puts them in digital format.

C. It allows the use of digital signals in everyday life.

D. It stores information on a CD.

33. A multiplexer has ________.

A. one input and several outputs

B. one input and one output

C. several inputs and several outputs

D. several inputs and one output

DEPARTMENT OF ECE


34. What is the decimal value of 23 ?

A. 2 B. 4

C. 6 D. 8

35. An encoder converts ________.

A. noncoded information into coded form

B. coded information into noncoded form

C. HIGHs to LOWs

D. LOWs to HIGHs

36. What kind of logic device or circuit is used to store information?

A. Counter B. Register

C. Inverter D. Buffer

37. PLCC packages have leads on ________.

A. one side

B. two sides

C. three sides

D. four sides

38. What is the typical invalid voltage for a binary signal?

A. 0.7–2.8 volts

B. 0.8–3 volts

C. 0.8–2 volts

D. 0.7–2.5 volts

E. None


A. 1.40 B. 1.125

C. 1.20 D. 1.80


A. 24.50 B. 18.25

C. 18.40 D. 16.25

E. None

41. How many binary bits are necessary to represent 748 different numbers?

A. 9 B. 7

C. 10 D. 8

42. A periodic digital waveform has a pulse width (tw) of 6 ms and a period (T) of 18 ms. The

duty cycle is ________.

A. 3.3% B. 33.3%

C. 6% D. 18%

43. Any number with an exponent of one is equal to:

A. zero.

B. one.

C. two.

D. that number.

DEPARTMENT OF ECE


44. Serial format means digital signals are:

A. sent over many conductors simultaneously.

B. sent over one conductor sequentially.

C. sent in groups of eight signals.

D. sent in binary coded decimal.

45. What is the decimal value of 2–1

?

A. 0.5 B. 0.25

C. 0.05 D. 0.1

46. Which format can send several bits of information faster?

A. Parallel

B. Serial

C. Both are the same

D. Cannot tell

47. The frequency of a pulse train is 2 kHz. The pulse period is ________.

A. 5 ms

B. 50 ms

C. 500 s

D. 2 s

48. What has happened to the advances in digital technologies over the past three decades?

A. Slowed down considerably

B. Continued to increase, but at a decreasing rate

C. Made excellent progress

D. Nothing short of phenomenal

49. A type of digital circuit technology that uses bipolar junction transistors is ________.

A. TTL B. CMOS

C. LSI D. NMOS

50. How many unique symbols are used in the decimal number system?

A. One B. Nine

C. Ten D. Unlimited

51. A classification of ICs with complexities of 12 to 100 equivalent gates on a chip is known

as ________.

A. SSI B. MSI

C. LSI D. VLSI

52. Which of the following is a semiconductor memory?

A. RAM B. MAR

C. CD-ROM D. CD

DEPARTMENT OF ECE


53. The holes through a PC board are ________.

A. smaller with SMT than with through-hole mounting

B. larger with SMT than with through-hole mounting

C. the same size as with through-hole mounting

D. usually unnecessary

54. A classification of ICs with complexities of 100 to 10,000 equivalent gates per chip is

known as ________.

A. SSI B. MSI

C. LSI D. VLSI

55.

Determine the output frequency for a frequency division circuit that contains 12 flip-

flops with an input clock frequency of 20.48 MHz.

A. 10.24 kHz

B. 5 kHz

C. 30.24 kHz

D 15KHz

56.Which statement BEST describes the operation of a negative-edge-triggered D flip-

flop?

A

.

The logic level at the D input is transferred to Q on NGT of CLK.

B

.

The Q output is ALWAYS identical to the CLK input if the D input is HIGH.

C

.

The Q output is ALWAYS identical to the D input when CLK = PGT.

D

.

The Q output is ALWAYS identical to the D input.

57. Propagation delay time, tPLH, is measured from the ________.

A

.

triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

B

.

triggering edge of the clock pulse to the HIGH-to-LOW transition of the output

C

.

preset input to the LOW-to-HIGH transition of the output

D

.

clear input to the HIGH-to-LOW transition of the output

58. How many flip-flops are in the 7475 IC?

A. 1 B. 2

C. 4 D. 8

59.How many flip-flops are required to produce a divide-by-128 device?

A. 1 B. 4

C. 6 D. 7

DEPARTMENT OF ECE


60.The timing network that sets the output frequency of a 555 astable circuit contains

________.

A. three external resistors are used

B. two external resistors and an external capacitor are used

C. an external resistor and two external capacitors are used

D. no external resistor or capacitor is required

61.The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is

HIGH is called ________.

A. parity error checking

B. ones catching

C. digital discrimination

D. digital filtering

62.What is another name for a one-shot?

A. Monostable B. Multivibrator

C. Bistable D. Astable

63.On a master-slave flip-flop, when is the master enabled?

A. when the gate is LOW

B. when the gate is HIGH

C. both of the above

D. neither of the above

64.One example of the use of an S-R flip-flop is as a(n):

A. racer

B. astable oscillator

C. binary storage register

D. transition pulse generator

65.What is the difference between the 7476 and the 74LS76?

A. the 7476 is master-slave, the 74LS76 is master-slave

B. the 7476 is edge-triggered, the 74LS76 is edge-triggered

C. the 7476 is edge-triggered, the 74LS76 is master-slave

D. the 7476 is master-slave, the 74LS76 is edge-triggered

66.Which of the following is correct for a gated D flip-flop?

A. The output toggles if one of the inputs is held HIGH.

B. Only one of the inputs can be HIGH at a time.

C. The output complement follows the input when enabled.

D. Q output follows the input D when the enable is HIGH.

67.How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?

A. It can't be done.

B. Invert the Q outputs.

C. Invert the S-R inputs.

DEPARTMENT OF ECE


68.A 555 operating as a monostable multivibrator has an R1 of 1 M . Determine C1 for a

pulse width of 2 s.

A. 1.8 F

B. 18 F

C. 18 pF

D. 18 nF

69.Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because

input data is read during the entire time the clock pulse is at a LOW level.

A. True B. False

70.Which of the following is correct for a D latch?

A. The output toggles if one of the inputs is held HIGH.

B. Q output follows the input D when the enable is HIGH.

C. Only one of the inputs can be HIGH at a time.

D. The output complement follows the input when enabled.

71.A J-K flip-flop is in a "no change" condition when ________.

A. J = 1, K = 1

B. J = 1, K = 0

C. J = 0, K = 1

D. J = 0, K = 0

72.A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable

while the:

A. clock is LOW

B. slave is transferring

C. flip-flop is reset

D. clock is HIGH

73. Convert the following SOP expression to an equivalent POS expression.

A.

B.

C.

D.

74. Determine the values of A, B, C, and D that make the sum term equal to

zero.

A. A = 1, B = 0, C = 0, D = 0

B. A = 1, B = 0, C = 1, D = 0

C. A = 0, B = 1, C = 0, D = 0

D. A = 1, B = 0, C = 1, D = 1

DEPARTMENT OF ECE


75. Which of the following expressions is in the sum-of-products (SOP) form?

A. (A + B)(C + D)

B. (A)B(CD)

C. AB(CD)

D. AB + CD

DEPARTMENT OF ECE


ANSWERS

1 2 3 4 5 6 7 8 9 10

A D C A C B D A D B

11 12 13 14 15 16 17 18 19 20

E B B A A D E A A B

21 22 23 24 25 26 27 28 29 30

D D A B B E A E C A

31 32 33 34 35 36 37 38 39 40

B B D D D B C E B B

41 42 43 44 45 46 47 48 49 50

B D C B C B B A D D

51 52 53 54 55 56 57 58 59 60

A A A D B B A C A C

61 62 63 64 65 66 67 68 69 70

D B B A D A A B A D

71 72 73 74 75

B D A A B

DEPARTMENT OF ECE


CHAPTER 4

DATA COMMUNICATION

&

COMPUTER NETWORKS

DEPARTMENT OF ECE


Today computer is available in many offices and homes and therefore there is a need to share

data and programs among various computers with the advancement of data communication

facilities. The communication between computers has increased and it thus it has extended

the power of computer beyond the computer room. Now a user sitting at one place can

communicate computers of any remote sites through communication channel. For

communication of information and messages we use telephone and postal communication

systems. Similarly data and information from one computer system can be transmitted to

other systems across geographical areas. Thus data transmission is the movement of

information using some standard methods. These methods include electrical signals carried

along a conductor, optical signals along an optical fibers and electromagnetic areas. The

following are the basic requirements for working of a communication system.

1. A sender (source) which creates the message to be transmitted.

2. A medium that carries the message.

3. A receiver (sink) which receives the message.

In data communication four basic terms are frequently used. They are

Data: A collection of facts in raw forms that become information after processing.

Signals: Electric or electromagnetic encoding of data.

Signaling: Propagation of signals across a communication medium.

Transmission: Communication of data achieved by the processing of signals.

The data communication software instructs computer systems and devices as to how exactly

data is to be transferred from one place to another. The procedure of data transformation in

the form of software is commonly called protocol. The data transmission software or

protocols perform the following functions for the efficient and error free transmission of data.

1. Data sequencing: A long message to be transmitted is broken into smaller packets of fixed

size for error free data transmission.

2. Data Routing: It is the process of finding the most efficient route between source and

destination before sending the data.

3. Flow control: All machines are not equally efficient in terms of speed. Hence the flow

control regulates the process of sending data between fast sender and slow receiver.

4. Error Control: Error detecting and recovering is the one of the main function of

communication software. It ensures that data are transmitted without any error.

There are three ways for transmitting data from one point to another

DEPARTMENT OF ECE


1. Simplex: In simplex mode the communication can take place in one direction. The

receiver receives the signal from the transmitting device. In this mode the flow of information

is Uni.-directional. Hence it is rarely used for data communication.

2. Half-duplex: In half-duplex mode the communication channel is used in both directions,

but only in one direction at a time. Thus a half-duplex line can alternately send and receive

data.

Full-duplex: In full duplex the communication channel is used in both directions at the same

time. Use of full-duplex line improves the efficiency as the line turn-around time required in

half-duplex arrangement is eliminated. Example of this mode of transmission is the telephone

line. Data is transmitted from one point to another point by means of electrical signals that

may be in digital and analog form. So one should know the fundamental difference between

analog and digital signals. In analog signal the transmission power varies over a continuous

range with respect to sound, light and radio waves. On the other hand a digital signal may

assume only discrete set of values within a given range. Examples are computer and

computer related equipment. Analog signal is measured in Volts and its frequency in Hertz

(Hz). A digital signal is a sequence of voltage represented in binary form. When digital data

are to be sent over an analog form the digital signal must be converted to analog form. So the

technique by which a digital signal is converted to analog form is known as modulation. And

the reverse process, that is the conversion of analog signal to its digital form, is known as

demodulation. The device, which converts digital signal into analog, and the reverse, is

known as modem. Data transmission through a medium can be either asynchronous or

synchronous. In asynchronous transmission data is transmitted character by character as you

go on typing on a keyboard. Hence there is irregular gaps between characters. However, it is

cheaper to implement, as you do not have to save the data before sending. On the other hand,

in the synchronous mode, the saved data is transmitted block by block. Each block can

contain many characters. Synchronous transmission is well suited for remote communication

between a computer and related devices like card reader and printers.

Following are the major communication devices used to day.

1. Wire Pairs: Wire pairs are commonly used in local telephone communication and for

short distance digital data communication. They are usually made up of copper and the pair

of wires is twisted together. Data transmission speed is normally 9600 bits per second in a

distance of 100 meter.

2. Coaxial Cables: Coaxial cable is groups of specially wrapped and insulted wires that are

able to transfer data at higher rate. They consist of a central copper wire surrounded by an

DEPARTMENT OF ECE


insulation over which copper mesh is placed. They are used for long distance telephone lines

and local area network for their noise immunity and faster data transfer.

3. Microwave: Microwave system uses very high frequency radio signals to transmit data

through space. The transmitter and receiver of a microwave system should be in line-of-sight

because the radio signal cannot bend. With microwave very long distance transmission is not

possible. In order to overcome the problem of line of sight and power amplification of weak

signal, repeaters are used at intervals of 25 to 30 kilometers between the transmitting and

receiving end.

4. Communication Satellite: The problem of line-sight and repeaters are overcome by using

satellites which are the most widely used data transmission media in modern days. A

communication satellite is a microwave relay station placed in outer space. INSAT-1B is

such a satellite that can be accessible from anywhere in India. In satellite communication,

microwave signal is transmitted from a transmitter on earth to the satellite at space. The

satellite amplifies the weak signal and transmits it back to the receiver. The main advantage

of satellite communication is that it is a single microwave relay station visible from any point

of a very large area. In microwave the data transmission rate is 16 giga bits per second. They

are mostly used to link big metropolitan cities.

DEPARTMENT OF ECE


OBJECTIVE TYPE

QUESTION

DEPARTMENT OF ECE


1. What is a router?

a) Forwards a packet to the next free outgoing link

b) Determines on which outgoing link a packet is to be forwarded

c) Forwards a packet to all outgoing links.

d) Forwards a packet to all outgoing links, except the link upon which the packet originated

2. A file is downloaded to a home computer using a 56 kbps modem connected to an Internet

Service Provider. If the download completes in 2 minutes, estimate the maximum size of data

downloaded.

a) 6.72 Mbit.

b) 26.88 Mbit

c) 13.44 Mbit

d) 336 Kbit.

3. What is the Principle design of Manchester encoding?

a) ensure that the line remains unbalanced

b) increase the bandwidth of a signal transmitted on the medium

c) have more than one symbol per bit period

d) ensure that a transition occurs in the centre of each bit period

4. What are the most commonly used transmission speeds in BPS used in data

communication?

a) 300

b) 2400 c) 1200

d) 9600

5. What is the default subnet mask for a class C network?

a) 127.0.0.1

b) 255.0.0.0

c) 255.255.0.0

d) 255.255.255.0

6. Your company has a LAN in its downtown office and has now set up a LAN in the

manufacturing plant in the suburbs. To enable everyone to share data and resources between

the two LANs, what type of device(s) are needed to connect them? Choose the most correct

answer.

a) Modem

b) Cable

c) Hub

d) Router

7. Which of the following TCP/IP protocol is used for transferring electronic mail messages

from one machine to another?

a) FTP

b) SNMP

c) SMTP

d) RPC

DEPARTMENT OF ECE


8. Which of the following device is used to connect two systems, especially if the systems use

different protocols?

a) Hub

b) Bridge

c) Gateway

d) Repeater

9. The synchronous modems are more costly than the asynchronous modems because

a) they produce large volume of data

b) they contain clock recovery circuits

c) they transmit the data with stop and start bits.

d) they operate with a larger bandwidth

10. A distributed network configuration in which all data/information pass through a central

computer is

a) Bus

b) Ring

c) Star

d) Point to point

11. What part of 192.168.10.51 is the Network ID, assuming a default subnet mask?

a) 192

b) 192.168.10

c) 0.0.0.51

d) 51

12. What can greatly reduce TCP/IP configuration problems?

a) WINS Server

b) WINS Proxy

c) DHCP Server

d) PDC

13. Usually, it takes 10-bits to represent one character. How many characters can be

transmitted at a speed of 1200 BPS?

a) 10

b) 12

c) 120

d) 1200

14. What device separates a single network into two segments but lets the two segments

appear as one to higher protocols?

a) Switch

b) Bridge

c) Gateway

d) Router

DEPARTMENT OF ECE


15. To make possible the efficient on-line servicing of many teleprocessing system users on

large computer systems, designers are developing

a) Communication systems

b) Multiprogramming systems

c) Virtual storage systems

d) All the above

16. After coding a document into a digital signal, it can be sent by telephone, telex or satellite

to the receiver where the signal is decoded and an exact copy of the original document is

made. What is it called?

a) Telex

b) Word Processor

c) Facsimile

d) Email

17. Which of the following medium access control technique is used for bus/tree?

a) Token ring

b) Token bus

c) CSMA

d) MAC

18. Which of the following is not a transmission medium?

a) Telephone line

b) Coaxial cable

c) modem

d) microwave systems

19. What is the minimum number of wires needed to send data over a serial communication

link layer?

a) 1

b) 2

c) 4

d) 6

20. Typewriter terminals can print computer-generated data at a rate of

a) 10 characters per second

b) 120 characters per second

c) 120 characters per minute

d) 1200 characters per minute

21. Error detection at a data link level is achieved by

a) Bit stuffing

b) CRC

c) Hamming codes

d) Equalization

DEPARTMENT OF ECE


22. This refers to two characteristics: when data to be sent and how fast it can be sent.

a) Semantics

b) Syntax

c) Timing

d) None of the above

23. _________ is an idea or a concept that is precursor to an internet standard

a) RCF

b) RFC

c) ID

d) None of the above.

24. ________ refers to the physical or logical arrangement of the network.

a) Data flow

b) Mode of Operation

c) Topology

d) None of the above

25. The number of point to point links required in a fully connected network for 50 entities is

a) 1225

b) 1250

c) 2500

d) 50

26. A Datagram is_______

a) A self contained network layer packet which is generated by the connectionless protocol.

b) Any packet which is broadcast to more than one destination computer.

c) A packet which is sent by a link layer protocol

d) All the above.

27. A modem is connected in between a telephone line and a

a) Network

b) Computer

c) Communication adapter

d) Serial port

28. Which utility is an all-purpose tool for troubleshooting TCP/IP problems?

a) NBTSTAT

b) Netstat

c) PING

d) Hostname

29. In OSI network architecture, the dialogue control and token management are

responsibilities of

a) Session

b) Network

c) Transport

d) Data Link

DEPARTMENT OF ECE


30. In a synchronous modem, the digital-to-analog converter transmits signal to the

a) Equalizer

b) Modulator

c) Demodulator

d) Terminal.

DEPARTMENT OF ECE


ANSWERS

1 B 11 B 21 B

2 A 12 C 22 C

3 A 13 C 23 B

4 D 14 B 24 C

5 D 15 D 25 C

6 D 16 C 26 A

7 C 17 B 27 C

8 C 18 C 28 C

9 B 19 B 29 A

10 C 20 B 30 A

DEPARTMENT OF ECE


1.Converting data into signals by transforming and encoding the information to produce

electromagnetic signals is the functionality of a ___________.

a. source

b. transmitter

c. receiver

d. destination

2. Which of the following is the simplest error-detection method?

a. Parity

b. Longitudinal redundancy checking

c. Checksum checking

d. Cyclic redundancy checking

3. Which type of error detection uses binary division?

a. Parity

b. Longitudinal redundancy checking

c. Checksum checking

d. Cyclic redundancy checking

4. Which of the following is also called forward error correction?

a. Simplex

b. Retransmission

c. Detection-error coding

d. Error-correction coding

5.___________________ is a technique which transforms an analogue telephone circuit into

a digital signal, and involves three consecutive processes: sampling, quantization and

encoding.

a. Frequency Modulation (FM)

b. Pulse Code Modulation (PCM)

c. Amplitude Modulation (AM)

d. Phase Modulation (PM)

6.The failure density function, f(t) is used to give the probability of failure during an interval

of time. It is known as ______________.

a. Probability density distribution

b. Cumulative probability distribution

c. Cumulative density distribution

d. Failure probability distribution

7.Rather than sending the absolute value of each sample, it is possible to achieve a smaller

transmission bit-rate by sending the difference between consecutive samples. This is

known as _______________.

DEPARTMENT OF ECE


a. delta modulation

b. delta–sigma modulation

c. adaptive delta modulation

d. differential PCM

8.The electron beam in the cathode ray tube (CRT) inside the TV set is made to scan the

whole visible surface of the screen in a zigzag pattern. This is known as ____________.

a. raster

b. picture line

c. frame

d. broadcast

9. The figure below shows an example of a modulation system used in digital

communication. What is that modulation system?

a. PCM Modulation.

b. Delta Modulation.

c. Sigma Modulation.

d. Differential Modulation.

10. One of the compression techniques in communication uses the fact that in most pictures,

there is considerable correlation between neighboring areas that is a high degree of

redundancy in the data to compress. This type of compression is known as

_____________.

a. temporal compression

b. dynamic compression

c. spatial compression

d. random compression

11. Reversible or lossless coding is a type of coding for which the exact data can be

recovered after decoding. This type of coding is used by _________________.

a. PCM encoding

b. Huffman encoding

c. Run-length encoding

d. Both b and c

DEPARTMENT OF ECE


12. The error represented by the difference between the original and quantized signals set a

fundamental limitation to the performance of PCM systems known as

__________________.

a. dynamic range

b. quantization noise

c. detection-error

d. correction-error

13. The most common distance-limiting factor for multi-mode fiber when carrying

high bit-rate traffic is

a. Attenuation loss

b. Chromatic dispersion

c. Fresnel loss

d. Modal dispersion

14. Which of the following modulation schemes provides 4 bits per baud?

a. QPSK

b. 8-PSK

c. 16-QAM

d. 64-QAM

15. The most common distance-limiting factor for multi-mode fiber when carrying

high bit-rate traffic is

a. Attenuation loss

b. Chromatic dispersion

c. Fresnel loss

d. Modal dispersion

16. If the number of bits per sample in a Pulse Coded Modulation (PCM) system is increased

from 5 bits to 6 bits,the improvement in signal to quantization noise ratio will be

(a) 3 dB

(b) 6 dB

(c) 2pi dB

(d) 0 dB

17. A superheterodyne radio receiver with an intermediate frequency of 455 kHz is tuned to a

station operating at 1200 KHz. The associated image frequency is ________ kHz

(a) 1200

(b) 2110

(c) 1100

(d) 455

18. A 10 MHz carrier is frequency modulated with a sinusoidal signal at 500Hz, the

maximum frequency deviation being 50 KHz. The bandwidth required as given by the

Carson‘s rule is

(a) 101kHz (b) 50kHz (c) 105 kHz (d) 100kHz

19. A 1.0 kHz signal is sampled at the rate of 1.8 kHz and the samples are applied to an ideal

rectangular LPF with cut-off frequency of 1.1 kHz, then the output of the filter contains

(a) Only 800 Hz component (b) 800 Hz and 900 Hz components

(c) 800 Hz and 100 Hz components (d) 800Hz, 900 and 100 Hz components

20. In QAM, both ________ of a carrier frequency are varied.

A) frequency and amplitude

B) phase and frequency

C) amplitude and phase

D) none of the above

http://en.wikipedia.org/wiki/Pulse-code_modulation

DEPARTMENT OF ECE


21. In _______, the peak amplitude of one signal level is 0; the other is the same as the

amplitude of the carrier frequency.

A) PSK

B) OOK

C) FSK


22. In _____ transmission, the frequency of the carrier signal is modulated to follow the

changing voltage level (amplitude) of the modulating signal. The peak amplitude and phase

of the carrier signal remain constant, but as the amplitude of the information signal changes,

the frequency of the carrier changes correspondingly.

A) AM

B) PM

C) FM


23. Analog-to-analog conversion is needed if the available bandwidth is _______.

A) low-pass

B) band-pass

C) either (a) or (b)

D) neither (a) nor (b

24 A constellation diagram shows us the __________ of a signal element, particularly

when we are using two carriers (one in-phase and one quadrature).

A) amplitude and phase

B) amplitude and frequency

C) frequency and phase


25. Given an AM radio signal with a bandwidth of 10 KHz and the highest-frequency

component at 705 KHz, what is the frequency of the carrier signal?

A) 700 KHz

B) 705 KHz

C) 710 KHz

D) Cannot be determined from given information

26. If the bit rate for an FSK signal is 1200 bps, the baud rate is ________.

A) 300

B) 400

C) 600

D) 1200

27. If the baud rate is 400 for a QPSK signal, the bit rate is ________ bps.

A) 100

B) 400

C) 800

D) 1600

28. Convert the binary number 1011010 to hexadecimal.

A. 5BB. 5F

C. 5AD. 5C

29. The number of bits used to store a BCD digit is:

A. 8B. 4

C. 1D. 2

DEPARTMENT OF ECE


30. What is the difference between binary coding and binary coded decimal?

A. Binary coding is pure binary.

B. BCD is pure binary.

C. Binary coding has a decimal format.

D. BCD has no decimal format.

DEPARTMENT OF ECE


ANSWER

1 b

2 a

3 d

4 d

5 b

6 a

7 a

8 a

9 b

10 c

11 d

12 b

13 d

14 c

15 d

16 b

17 b

18 a

19 a

20 c

21 b

22 c

23 b

24 a

25 a

26 d

27 c

28 c

29 b

30 a

DEPARTMENT OF ECE


CHAPTER 5

HARDWARE DESCRIPTION

LANGUAGES

(VHDL & VERILOG HDL)

DEPARTMENT OF ECE


VHDL

Introduction

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description

Language. In the mid-1980‘s the U.S. Department of Defense and the IEEE sponsored the

development of this hardware description language with the goal to develop very high-speed

integrated circuit. It has become now one of industry‘s standard languages used to describe

digital systems. The other widely used hardware description language is Verilog. Both are

powerful languages that allow you to describe and simulate complex digital systems. A third

HDL language is ABEL (Advanced Boolean Equation Language) which was specifically

designed for Programmable Logic Devices (PLD). ABEL is less powerful than the other two

languages and is less popular in industry. This tutorial deals with VHDL, as described by the

IEEE standard 1076-1993.

Basic Structure of a VHDL file

A digital system in VHDL consists of a design entity that can contain other entities that are

then considered components of the top-level entity. Each entity is modeled by an entity

declaration and an architecture body. One can consider the entity declaration as the interface

to the outside world that defines the input and output signals, while the architecture body

contains the description of the entity and is composed of interconnected entities, processes

and components, all operating concurrently, as schematically shown in Figure 3 below. In a

typical design there will be many such entities connected together to perform the desired

function.

Figure 3: A VHDL entity consisting of an interface (entity declaration) and a body

(architectural description).

DEPARTMENT OF ECE


VHDL uses reserved keywords that cannot be used as signal names or identifiers. Keywords

and user-defined identifiers are case insensitive. Lines with comments start with two

adjacent hyphens (--) and will be ignored by the compiler. VHDL also ignores line breaks

and extra spaces. VHDL is a strongly typed language which implies that one has always to

declare the type of every object that can have a value, such as signals, constants and

variables.

Entity Declaration

The entity declaration defines the NAME of the entity and lists the input and output ports.

The general form is as follows,

entity NAME_OF_ENTITY is [ generic generic_declarations);]

port (signal_names: mode type;

signal_names: mode type;

:

signal_names: mode type);

end [NAME_OF_ENTITY] ;

An entity always starts with the keyword entity, followed by its name and the keyword is.

Next are the port declarations using the keyword port. An entity declaration always ends

with the keyword end, optionally [] followed by the name of the entity.

The NAME_OF_ENTITY is a user-selected identifier

signal names consists of a comma separated list of one or more user-selected identifiers that

specify external interface signals.

mode: is one of the reserved words to indicate the signal direction:

in – indicates that the signal is an input

out – indicates that the signal is an output of the entity whose value can only be read by other

entities that use it.

buffer – indicates that the signal is an output of the entity whose value can be read inside the

entity‘s architecture

inout – the signal can be an input or an output.

type: a built-in or user-defined signal type. Examples of types are bit, bit_vector, Boolean,

character, std_logic, and std_ulogic.

http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html#DataTypes

DEPARTMENT OF ECE


bit – can have the value 0 and 1

bit_vector – is a vector of bit values (e.g. bit_vector (0 to 7)

std_logic, std_ulogic, std_logic_vector, std_ulogic_vector: can have 9 values to indicate the

value and strength of a signal. Std_ulogic and std_logic are preferred over the bit or

bit_vector types.

boolean – can have the value TRUE and FALSE

integer – can have a range of integer values

real – can have a range of real values

character – any printing character

time – to indicate time

generic: generic declarations are optional and determine the local constants used for timing

and sizing (e.g. bus widths) the entity. A generic can have a default value. The syntax for a

generic follows,

generic (

constant_name: type [:=value] ;

constant_name: type [:=value] ;

:

constant_name: type [:=value] );

Architecture body

The architecture body specifies how the circuit operates and how it is implemented.

As discussed earlier, an entity or circuit can be specified in a variety of ways, such as

behavioral, structural (interconnected components), or a combination of the above.

The architecture body looks as follows,

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations

-- components declarations

-- signal declarations

-- constant declarations

DEPARTMENT OF ECE


-- function declarations

-- procedure declarations

-- type declarations

begin

-- Statements

end architecture_name;

Library and Packages

library and use keywords

A library can be considered as a place where the compiler stores information about a

design project. A VHDL package is a file or module that contains declarations of commonly

used objects, data type, component declarations, signal, procedures and functions that can be

shared among different VHDL models.

We mentioned earlier that std_logic is defined in the package ieee.std_logic_1164 in the ieee

library. In order to use the std_logic one needs to specify the library and package. This is

done at the beginning of the VHDL file using the library and the use keywords as follows:

library ieee;

use ieee.std_logic_1164.all;

The .all extension indicates to use all of the ieee.std_logic_1164 package.

The Xilinx Foundation Express comes with several packages.

ieee Library:

std_logic_1164 package: defines the standard datatypes

std_logic_arith package: provides arithmetic, conversion and comparison functions

for the signed, unsigned, integer, std_ulogic, std_logic and std_logic_vector types

std_logic_unsigned

std_logic_misc package: defines supplemental types, subtypes, constants and

functions for the std_logic_1164 package.

DEPARTMENT OF ECE


To use any of these one must include the library and use clause:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

In addition, the synopsis library has the attributes package:

library SYNOPSYS;

use SYNOPSYS.attributes.all;

One can add other libraries and packages. The syntax to declare a package is as follows:

-- Package declaration

package name_of_package is

package declarations

end package name_of_package;

-- Package body declarations

package body name_of_package is

package body declarations

end package body name_of_package;

Lexical Elements of VHDL

Identifiers

Identifiers are user-defined words used to name objects in VHDL models. We have seen

examples of identifiers for input and output signals as well as the name of a design entity

and architecture body. When choosing an identifier one needs to follow these basic rules:

May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the

underscore (_) character

The first character must be a letter and the last one cannot be an underscore.

An identifier cannot include two consecutive underscores.

DEPARTMENT OF ECE


An identifier is case insensitive (ex. And2 and AND2 or and2 refer to the same

object)

An identifier can be of any length.

Examples of valid identifiers are: X10, x_10, My_gate1.

Some invalid identifiers are: _X10, my_gate@input, gate-input.

The above identifiers are called basic identifiers. The rules for these basic identifiers are often

too restrictive to indicate signals. For example, if one wants to indicate an active low signal

such as an active low RESET, one cannot call it /RESET. In order to overcome these

limitations, there are a set of extended identifier rules which allow identifiers with any

sequence of characters.

An extended identifier is enclosed by the backslash, ―\‖, character.

An extended identifier is case sensitive.

An extended identifier is different from reserved words (keywords) or any

basic identifier (e.g. the identifier \identity\ is allowed)

Inside the two backslashes one can use any character in any order, except that

a backslash as part of an extended identifier must be indicated by an additional

backslash. As an example, to use the identifier BUS:\data, one writes: \BUS:\data\

Extended identifiers are allowed in the VHDL-93 version but not in VHDL-87

Some examples of legal identifiers are:

Input, \Input\, \input#1\, \Rst\\as\

Keywords (Reserved words)

Certain identifiers are used by the system as keywords for special use such as specific

constructs. These keywords cannot be used as identifiers for signals or objects we define. We

have seen several of these reserved words already such as in, out, or, and, port, map, end, etc.

Keywords are often printed in boldface, as is done in this tutorial. For a list of all the

mailto:my_gate@input

DEPARTMENT OF ECE


keywords click on complete keyword list. Extended identifiers can make use of keywords

since these are considered different words (e.g. the extended identifier \end\ is allowed.

Numbers

The default number representation is the decimal system. VHDL allows integer literals and

real literals. Integer literals consist of whole numbers without a decimal point, while real

literals always include a decimal point. Exponential notation is allowed using the letter ―E‖

or ―e‖. For integer literals the exponent must always be positive. Examples are:

Integer literals: 12 10 256E3 12e+6

Real literals: 1.2 256.24 3.14E-2

The number –12 is a combination of a negation operator and an integer literal.

To express a number in a base different from the base ―10‖, one uses the following

convention: base#number#. A few examples follow.

Base 2: 2#10010# (representing the decimal number ―18‖)

Base 16: 16#12#

Base 8: 8#22#

Base 2: 2#11101# (representing the decimal number ―29‖)

Base 16: 16#1D#

Base 8: 8#35#

To make the readability of large numbers easier, one can insert underscores in the

numbers as long as the underscore is not used at the beginning or the end.

2#1001_1101_1100_0010#

215_123

http://www.seas.upenn.edu/~ese171/vhdl/keywordlist.html

DEPARTMENT OF ECE


Characters, Strings and Bit Strings

To use a character literal in a VHDL code, one puts it in a single quotation mark, as

shown in the examples below:

‗a‘, ‗B‘, ‗,‘

On the other hand, a string of characters are placed in double quotation marks as

shown in the following examples:

―This is a string‖,

―To use a double quotation mark inside a string, use two double quotation marks‖

―This is a ―‖String‖‖.‖

Any printing character can be included inside a string.

A bit-string represents a sequence of bit values. In order to indicate that this is a bit string,

one places the ‗B‘ in front of the string: B‖1001‖. One can also use strings in the hexagonal

or octal base by using the X or O specifiers, respectively. Some examples are:

Binary: B‖1100_1001‖, b‖1001011‖

Hexagonal: X‖C9‖, X‖4b‖

Octal: O‖311‖, o‖113‖

Notice that in the hexadecimal system, each digit represents exactly 4 bits. As a result, the

number b‖1001011‖ is not the same as X‖4b‖ since the former has only 7 bits while the latter

represents a sequence 8 bits. For the same reason, O‖113‖ (represents 9 bits) is not the same

sequence as X‖4b‖ (represents 8 bits).

Data Objects: Signals, Variables and Constants

A data object is created by an object declaration and has a value and type associated

with it. An object can be a Constant, Variable, Signal or a File. Up to now we have seen

signals that were used as input or output ports or internal nets. Signals can be considered

wires in a schematic that can have a current value and future values, and that are a function

of the signal assignment statements. On the other hand, Variables and Constants are used to

model the behavior of a circuit and are used in processes, procedures and functions, similarly

as they would be in a programming language. Following is a brief discussion of each class of

objects.

DEPARTMENT OF ECE


Constant

A constant can have a single value of a given type and cannot be changed during the

simulation. A constant is declared as follows,

constant list_of_name_of_constant: type [ := initial value] ;

where the initial value is optional. Constants can be declared at the start of an architecture

and can then be used anywhere within the architecture. Constants declared within a process

can only be used inside that specific process.

constant RISE_FALL_TME: time := 2 ns;

constant DELAY1: time := 4 ns;

constant RISE_TIME, FALL_TIME: time:= 1 ns;

constant DATA_BUS: integer:= 16;

Variable

A variable can have a single value, as with a constant, but a variable can be updated

using a variable assignment statement. The variable is updated without any delay as soon as

the statement is executed. Variables must be declared inside a process (and are local to the

process). The variable declaration is as follows:

variable list_of_variable_names: type [ := initial value] ;

A few examples follow:

variable CNTR_BIT: bit :=0;

variable VAR1: boolean :=FALSE;

variable SUM: integer range 0 to 256 :=16;

variable STS_BIT: bit_vector (7 downto 0);

The variable SUM, in the example above, is an integer that has a range from 0 to 256

with initial value of 16 at the start of the simulation. The fourth example defines a bit vector

or 8 elements: STS_BIT(7), STS_BIT(6),… STS_BIT(0).

http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html#Process

DEPARTMENT OF ECE


A variable can be updated using a variable assignment statement such as

Variable_name := expression;

As soon as the expression is executed, the variable is updated without any delay.

Signal

Signals are declared outside the process using the following statement:

signal list_of_signal_names: type [ := initial value] ;

signal SUM, CARRY: std_logic;

signal CLOCK: bit;

signal TRIGGER: integer :=0;

signal DATA_BUS: bit_vector (0 to 7);

signal VALUE: integer range 0 to 100;

Signals are updated when their signal assignment statement is executed, after a

certain delay, as illustrated below,

SUM <= (A xor B) after 2 ns;

If no delay is specified, the signal will be updated after a delta delay. One can also

specify multiple waveforms using multiple events as illustrated below,

signal wavefrm : std_logic;

wavefrm <= ‗0‘, ‗1‘ after 5ns, ‗0‘ after 10ns, ‗1‘ after 20 ns;

It is important to understand the difference between variables and signals, particularly how it

relates to when their value changes. A variable changes instantaneously when the variable

assignment is executed. On the other hand, a signal changes a delay after the assignment

expression is evaluated. If no delay is specified, the signal will change after a delta delay.

This has important consequences for the updated values of variables and signals. Lets

compare the two files in which a process is used to calculate the signal RESULT [7].

DEPARTMENT OF ECE


Data types

Each data object has a type associated with it. The type defines the set of values that

the object can have and the set of operations that are allowed on it. The notion of type is key

to VHDL since it is a strongly typed language that requires each object to be of a certain type.

In general one is not allowed to assign a value of one type to an object of another data type

(e.g. assigning an integer to a bit type is not allowed). There are four classes of data types:

scalar, composite, access and file types. The scalar types represent a single value and are

ordered so that relational operations can be performed on them. The scalar type includes

integer, real, and enumerated types of Boolean and Character. Examples of these will be

given further on.

Data Types defined in the Standard Package

VHDL has several predefined types in the standard package as shown in the table below. To

use this package one has to include the following clause:

library std, work;

use std.standard.all;

Types defined in the Package Standard of the std Library

Type Range of values Example

bit ‗0‘, ‗1‘ signal A: bit :=1;

bit_vector an array with each element of

type bit

signal INBUS: bit_vector(7

downto 0);

boolean FALSE, TRUE variable TEST: Boolean

:=FALSE‘

character any legal VHDL character (see

package standard); printable

characters must be placed

between single quotes (e.g. ‗#‘)

variable VAL: character :=‘$‘;

file_open_kind* read_mode, write_mode,

append_mode

DEPARTMENT OF ECE


file_open_status* open_ok, status_error,

name_error, mode_error

integer range is implementation

dependent but includes at least –

(231

– 1) to +(231

– 1)

constant CONST1: integer :=129;

natural integer starting with 0 up to the

max specified in the

implementation

variable VAR1: natural :=2;

positive integer starting from 1 up the

max specified in the

implementation

variable VAR2: positive :=2;

real* floating point number in the

range of –1.0 x 1038

to +1.0x

1038

(can be implementation

dependent. Not supported by the

Foundation synthesis program.

variable VAR3: real :=+64.2E12;

severity_level note, warning, error, failure

string array of which each element is of

the type character

variable VAR4: string(1 to 12):=

―@$#ABC*()_%Z‖;

time* an integer number of which the

range is implementation defined;

units can be expressed in sec,

ms, us, ns, ps, fs, min and hr. .

Not supported by the Foundation

synthesis program

variable DELAY: time :=5 ns;

* Not supported by the Foundation synthesis program

User-defined Types

One can introduce new types by using the type declaration, which names the type and

specifies its value range. The syntax is

type identifier is type_definition;

Here are a few examples of type definitions,

DEPARTMENT OF ECE


Integer types

type small_int is range 0 to 1024;

type my_word_length is range 31 downto 0;

subtype data_word is my_word_length range 7 downto 0;

A subtype is a subset of a previously defined type. The last example above illustrates the use

of subtypes. It defines a type called data_word that is a sybtype of my_word_length of which

the range is restricted from 7 to 0. Another example of a subtype is,

subtype int_small is integer range -1024 to +1024;

Floating-point types

type cmos_level is range 0.0 to 3.3;

type pmos_level is range -5.0 to 0.0;

type probability is range 0.0 to 1.0;

subtype cmos_low_V is cmos_level range 0.0 to +1.8;

Note that floating point data types are not supported by the Xilinx Foundation synthesis

program.

Physical types

The physical type definition includes a units identifier as follows,

type conductance is range 0 to 2E-9

units

mho;

mmho = 1E-3 mho;

umho = 1E-6 mho;

nmho = 1E-9 mho;

pmho = 1E-12 mho;

end units conductance;

Here are some object declarations that use the above types,

variable BUS_WIDTH: small_int :=24;

signal DATA_BUS: my_word_length;

variable VAR1: cmos_level range 0.0 to 2.5;

constant LINE_COND: conductance:= 125 umho;

Notice that a space must be left before the unit name.

DEPARTMENT OF ECE


The physical data types are not supported by the Xilinx Foundation Express synthesis

program.

In order to use our own types, we need either to include the type definition inside an

architecture body or to declare the type in a package. The latter can be done as follows for a

package called ―my_types‖.

package my_types is

type small_int is range 0 to 1024;

type my_word_length is range 31 downto 0;

subtype data_word is my_word_length is range 7 downto 0;

type cmos_level is range 0.0 to 3.3;

type conductance is range 0 to 2E-9

units

mho;

mmho = 1E-3 mho;

umho = 1E-6 mho;

nmho = 1E-9 mho;

pmho = 1E-12 mho;


end package my_types;

Enumerated Types

An enumerated type consists of lists of character literals or identifiers. The enumerated type

can be very handy when writing models at an abstract level. The syntax for an enumerated

type is,

type type_name is (identifier list or character literal);

Here are some examples,

type my_3values is (‗0‘, ‗1‘, ‗Z‘);

type PC_OPER is (load, store, add, sub, div, mult, shiftl, shiftr);

type hex_digit is (‗0‘, ‗1‘, ‗2‘, ‗3‘, ‗4‘, ‗5‘, ‗6‘, ‗7‘, 8‘, ‗9‘, ‗A‘, ‗B‘, ‗C‘, ‗D‘, ‗E‘, ‗F‘);

type state_type is (S0, S1, S2, S3);

DEPARTMENT OF ECE


Examples of objects that use the above types:

signal SIG1: my_3values;

variable ALU_OP: pc_oper;

variable first_digit: hex_digit :=‘0‘;

signal STATE: state_type :=S2;

If one does not initialize the signal, the default initialization is the leftmost element of the list.

Enumerated types have to be defined in the architecture body or inside a package as shown

in the section above.

An example of an enumerated type that has been defined in the std_logic_1164 package is

the std_ulogic type, defined as follows

type STD_ULOGIC is (

‗U‘,-- uninitialized

‗X‘,-- forcing unknown

‗0‘,-- forcing 0

‗1‘,-- forcing 1

‗Z‘,-- high impedance

‗W‘,-- weak unknown

‗L‘,-- weak 0

‗H‘.-- weak 1

‗-‗);-- don‘t care

In order to use this type one has to include the clause before each entity declaration.

library ieee; use ieee.std_logic_1164.all;

Composite Types: Array and Record

Composite data objects consist of a collection of related data elements in the form of an

array or record. Before we can use such objects one has to declare the composite type first.

Array Type

An array type is declared as follows:

type array_name is array (indexing scheme) of element_type;

type MY_WORD is array (15 downto 0) of std_logic;

type YOUR_WORD is array (0 to 15) of std_logic;

type VAR is array (0 to 7) of integer;

type STD_LOGIC_1D is array (std_ulogic) of std_logic;

DEPARTMENT OF ECE


In the first two examples above we have defined a one-dimensional array of elements of the

type std_logic indexed from 15 down to 0, and 0 up to 15, respectively. The last example

defines a one-dimensional array of the type std_logic elements that uses the type std_ulogic

to define the index constraint. Thus this array looks as follows:

Index: ‗U‘ ‗X‘ ‗0‘ ‗1‘ ‗Z‘ ‗W‘ ‗L‘ ‗H‘ ‗-‗

Element:

We can now declare objects of these data types. Some examples are given

signal MEM_ADDR: MY_WORD;

signal DATA_WORD: YOUR_WORD := B―1101100101010110‖;

constant SETTING: VAR := (2,4,6,8,10,12,14,16);

In the first example, the signal MEM_ADDR is an array of 16 bits, initialized to all ‗0‘s. To

access individual elements of an array we specify the index. For example, MEM_ACCR(15)

accesses the left most bit of the array, while DATA_WORD(15) accesses the right most bit of

the array with value ‗0‘. To access a subrange, one specifies the index range,

MEM_ADDR(15 downto 8) or DATA_WORD(0 to 7).

Multidimensional arrays can be declared as well by using a similar syntax as above,

type MY_MATRIX3X2 is array (1 to 3, 1 to 2) of natural;

type YOUR_MATRIX4X2 is array (1 to 4, 1 to 2) of integer;

type STD_LOGIC_2D is array (std_ulogic, std_ulogic) of std_logic;

variable DATA_ARR: MY_MATRIX :=((0,2), (1,3), (4,6), (5,7));

The variable array DATA_ARR will then be initialized to,

0 2

1 3

4 6

5 7

To access an element one specifies the index, e.g. DATA_ARR(3,1) returns the value 4.

The last example defines a 9x9 array or table with an index the elements of the std_ulogic

type.

DEPARTMENT OF ECE


Sometimes it is more convenient not to specify the dimension of the array when the array

type is declared. This is called an unconstrained array type. The syntax for the array

declaration is,

type array_name is array (type range <>) of element_type;

Some examples are

type MATRIX is array (integer range <>) of integer;

type VECTOR_INT is array (natural range <>) of integer;

type VECTOR2 is array (natural range <>, natural range <>) of std_logic;

The range is now specified when one declares the array object,

variable MATRIX8: MATRIX (2 downto -8) := (3, 5, 1, 4, 7, 9, 12, 14, 20, 18);

variable ARRAY3x2: VECTOR2 (1 to 4, 1 to 3)) := ((‗1‘,‘0‘), (‗0‘,‘-‗), (1, ‗Z‘));

Record Type

A second composite type is the records type. A record consists of multiple elements that may

be of different types. The syntax for a record type is the following:

type name is

record

identifier :subtype_indication;

:

identifier :subtype_indication;

end record;

As an example,

type MY_MODULE is

record

RISE_TIME :time;

FALL_TIME: time;

SIZE: integer range 0 to 200;

DATA: bit_vector (15 downto 0);

end record;

signal A, B: MY_MODULE;

DEPARTMENT OF ECE


To access values or assign values to records, one can use one of the following methods:

A.RISE_TIME <= 5ns;

A.SIZE <= 120;

B <= A;

Type Conversions

Since VHDL is a strongly typed language one cannot assign a value of one data type to a

signal of a different data type. In general, it is preferred to the same data types for the signals

in a design, such as std_logic (instead of a mix of std_logic and bit types). Sometimes one

cannot avoid using different types. To allow assigning data between objects of different

types, one needs to convert one type to the other. Fortunately there are functions available in

several packages in the ieee library, such as the std_logic_1164 and the std_logic_arith

packages. As an example, the std_logic_1164 package allows the following conversions:

Conversions supported by std_logic_1164 package

Conversion Function

std_ulogic to bit to_bit(expression)

std_logic_vector to bit_vector to_bitvector(expression)

std_ulogic_vector to bit_vector to_bitvector(expression)

bit to std_ulogic To_StdULogic(expression)

bit_vector to std_logic_vector To_StdLogicVector(expression)

bit_vector to std_ulogic_vector To_StdUlogicVector(expression)

std_ulogic to std_logic_vector To_StdLogicVector(expression)

std_logic to std_ulogic_vector To_StdUlogicVector(expression)

The IEEE std_logic_unsigned and the IEEE std_logic_arith packages allow additional

conversions such as from an integer to std_logic_vector and vice versa.

The syntax of a type conversion is as follows:

type_name (expression);

DEPARTMENT OF ECE


In order for the conversion to be legal, the expression must return a type that can be

converted into the type type_name. Here are the conditions that must be fulfilled for the

conversion to be possible.

Type conversions between integer types or between similar array types are

possible

Conversion between array types is possible if they have the same length

and if they have identical element types or convertible element types.

Enumerated types cannot be converted.

Attributes

VHDL supports 5 types of attributes. Predefined attributes are always applied to a prefix such

as a signal name, variable name or a type. Attributes are used to return various types of

information about a signal, variable or type. Attributes consist of a quote mark (‗) followed

by the name of the attribute.

Signal attributes

The following table gives several signal attributes.

Attribute Function

signal_name’event returns the Boolean value True if an event on the

signal occurred, otherwise gives a False

signal_name’active returns the Boolean value True there has been a

transaction (assignment) on the signal, otherwise

gives a False

signal_name’transaction returns a signal of the type ―bit‖ that toggles (0 to 1

or 1 to 0) every time there is a transaction on the

signal.

signal_name’last_event returns the time interval since the last event on the

signal

signal_name’last_active returns the time interval since the last transaction

on the signal

DEPARTMENT OF ECE


signal_name’last_value gives the value of the signal before the last event

occurred on the signal

signal_name’delayed(T) gives a signal that is the delayed version (by time

T) of the original one. [T is optional, default T=0]

signal_name’stable(T) returns a Boolean value, True, if no event has

occurred on the signal during the interval T,

otherwise returns a False. [T is optional, default

T=0]

signal_name’quiet(T) returns a Boolean value, True, if no transaction has

occurred on the signal during the interval T,

otherwise returns a False. [T is optional, default

T=0]

An example of an attribute is

if (CLOCK’event and CLOCK=‘1‘) then …

This expression checks for the arrival of a positive clock edge. To find out how much time

has passed since the last clock edge, one can use the following attribute:

CLOCK‘last_event

Scalar attributes

Several attributes of a scalar type, scalar-type, are supported. The following table shows

some of these attributes.

Attribute Value

scalar_type’left returns the first or leftmost value of scalar-

type in its defined range

scalar_type’right returns the last or rightmost value of scalar-

type in its defined range

scalar_type’low returns the lowest value of scalar-type in its

defined range

scalar_type’high returns the greatest value of scalar-type in

its defined range

DEPARTMENT OF ECE


scalar_type’ascending True if T is an ascending range, otherwise

False

scalar_type‘value(s) returns the value in T that is represented by

s (s stands for string value).

Here are a few examples.

type conductance is range 1E-6 to 1E3

units mho;


type my_index is range 3 to 15;

type my_levels is (low, high, dontcare, highZ);

conductance‘right returns:1E3

conductance‘high1E3

conductance‘low1E-6

my_index‘left3

my_index‘value(5)―5‖

my_levels‘leftlow

my_levels‘lowlow

my_levels‘highhighZ

my_levels‘value(dontcare)―dontcare‖

Array attributes

By using array attributes one can return an index value corresponding to the array range.

The following attributes are supported.

Attribute Returns

MATRIX‗left(N)

MATRIX‘right(N)

MATRIX‘high(N)

left-most element index

right-most index

upper bound

DEPARTMENT OF ECE


MATRIX‘low(N)

MATRIX‘length(N)

MATRIX‘range(N)

MATRIX‘reverse_range(N)

MATRIX‘ascending(N)

lower bound

the number of elements

range

reverse range

a Boolean value TRUE if index is an

ascending range, otherwise FALSE

The number N between parentheses refers to the dimension. For a one-dimensional array, one

can omit the number N as shown in the examples below. Lets assume the following arrays,

declared as follows:

type MYARR8x4 is array (8 downto 1, 0 to 3) of boolean;

type MYARR1 is array (-2 to 4) of integer;

MYARR1‘leftreturns: -2

MYARR1‘right4

MYARR1‘high4

MYARR1‘reverse_range4 downto to -2

MYARR8x4‘left(1)8

MYARR8x4‘left(2)0

MYARR8x4‘right(2)3

MYARR8x4‘high(1)8

MYARR8x4‘low(1)1

MYARR8x4‘ascending(1) False

Operators

VHDL supports different classes of operators that operate on signals, variables and

constants. The different classes of operators are summarized below.

Class

1. Logical operators and or nand nor xor xnor

2. Relational = /= < <= > >=

DEPARTMENT OF ECE


operators

3. Shift operators sll srl sla sra rol ror

4.Addition operators + = &

5. Unary operators + -

6. Multiplying op. * / mod rem

7. Miscellaneous op. ** abs not

The order of precedence is the highest for the operators of class 7, followed by class 6 with

the lowest precedence for class 1. Unless parentheses are used, the operators with the highest

precedence are applied first. Operators of the same class have the same precedence and are

applied from left to right in an expression. As an example, consider the following

std_ulogic_vectors, X (=‘010‘), Y(=‘10‘), and Z (‗10101‘). The expression

not X & Y xor Z rol 1

is equivalent to ((not X) & Y) xor (Z rol 1) = ((101) & 10) xor (01011) =(10110) xor

(01011) = 11101. The xor is executed on a bit-per-bit basis.

Behavioral Modeling: Sequential Statements

As discussed earlier, VHDL provides means to represent digital circuits at different levels of

representation of abstraction, such as the behavioral and structural modeling. In this section

we will discuss different constructs for describing the behavior of components and circuits in

terms of sequential statements. The basis for sequential modeling is the process construct. As

you will see, the process construct allows us to model complex digital systems, in particular

sequential circuits.

Process

A process statement is the main construct in behavioral modeling that allows you to use

sequential statements to describe the behavior of a system over time. The syntax for a process

statement is

DEPARTMENT OF ECE


[process_label:] process [ (sensitivity_list) ] [is]

[ process_declarations]

begin

list of sequential statements such as:

signal assignments

variable assignments

case statement

exit statement

if statement

loop statement

next statement

null statement

procedure call

wait statement

end process [process_label];

A process is declared within an architecture and is a concurrent statement. However, the

statements inside a process are executed sequentially. Like other concurrent statements, a

process reads and writes signals and values of the interface (input and output) ports to

communicate with the rest of the architecture. One can thus make assignments to signals that

are defined externally (e.g. interface ports) to the process, such as the Q output of the flip-

flop in the above example. The expression CLK‘event and CLK = ‗1‘ checks for a positive

clock edge (clock event AND clock high).

The sensitivity list is a set of signals to which the process is sensitive. Any change in the

value of the signals in the sensitivity list will cause immediate execution of the process. If the

sensitivity list is not specified, one has to include a wait statement to make sure that the

process will halt. Notice that one cannot include both a sensitivity list and a wait statement.

Variables and constants that are used inside a process have to be defined in the

process_declarations part before the keyword begin. The keyword begin signals the start of

the computational part of the process. The statements are sequentially executed, similarly as

a conventional software program. It should be noted that variable assignments inside a

process are executed immediately and denoted by the ―:=‖ operator. This is in contrast to

signal assignments denoted by ―<=‖ and which changes occur after a delay. As a result,

changes made to variables will be available immediately to all subsequent statements within

DEPARTMENT OF ECE


the same process. For an example that illustrates the difference between signal and variable

assignments see the section on Data Types (difference between signals and variables).

If Statements

The if statement executes a sequence of statements whose sequence depends on one or more

conditions. The syntax is as follows:

if condition then

sequential statements

[elsif condition then

sequential statements ]

[else

sequential statements ]

end if;

Each condition is a Boolean expression. The if statement is performed by checking each

condition in the order they are presented until a ―true‖ is found. Nesting of if statements is

allowed.

Case statements

The case statement executes one of several sequences of statements, based on the value of a

single expression. The syntax is as follows,

case expression is

when choices =>


when choices =>


-- branches are allowed

[ when others => sequential statements ]

end case;

The expression must evaluate to an integer, an enumerated type of a one-dimensional array,

such as a bit_vector. The case statement evaluates the expression and compares the value to

each of the choices. The when clause corresponding to the matching choice will have its

statements executed. The following rules must be adhered to:

DEPARTMENT OF ECE


no two choices can overlap (i.e. each choice can be covered only once)

if the ―when others" choice is not present, all possible values of the expression must

be covered by the set of choices.

Loop statements

A loop statement is used to repeatedly execute a sequence of sequential statements. The

syntax for a loop is as follows:

[ loop_label :]iteration_scheme loop


[next [label] [when condition];

[exit [label] [when condition];

end loop [loop_label];

Labels are optional but are useful when writing nested loops. The next and exit statement are

sequential statements that can only be used inside a loop.

The next statement terminates the rest of the current loop iteration and execution will

proceed to the next loop iteration.

The exit statement skips the rest of the statements, terminating the loop entirely, and

continues with the next statement after the exited loop.

There are three types of iteration schemes:

basic loop

while … loop

for … loop

Basic Loop statement

This loop has no iteration scheme. It will be executed continuously until it encounters an exit

or next statement.

[ loop_label :] loop




end loop [ loop_label];

DEPARTMENT OF ECE


The basic loop (as well as the while-loop) must have at least one wait statement.

While-Loop statement

The while … loop evaluates a Boolean iteration condition. When the condition is TRUE, the

loop repeats, otherwise the loop is skipped and the execution will halt. The syntax for the

while…loop is as follows,

[ loop_label :] while condition loop




end loop[ loop_label ];

The condition of the loop is tested before each iteration, including the first iteration. If it is

false, the loop is terminated.

For-Loop statement

The for-loop uses an integer iteration scheme that determines the number of iterations. The

syntax is as follows,

[ loop_label :] for identifier in range loop




end loop[ loop_label ];

The identifier (index) is automatically declared by the loop itself, so one does not

need to declare it separately. The value of the identifier can only be read inside the

loop and is not available outside its loop. One cannot assign or change the value of the

index. This is in contrast to the while-loop whose condition can involve variables that

are modified inside the loop.

DEPARTMENT OF ECE


The range must be a computable integer range in one of the following forms, in which

integer_expression must evaluate to an integer:

o integer_expression to integer_expression

o integer_expression downto integer_expression

Next and Exit Statement

The next statement skips execution to the next iteration of a loop statement and proceeds with

the next iteration. The syntax is

next [label] [when condition];

The when keyword is optional and will execute the next statement when its condition

evaluates to the Boolean value TRUE.

The exit statement skips the rest of the statements, terminating the loop entirely, and

continues with the next statement after the exited loop. The syntax is as follows:

exit [label] [when condition];

The when keyword is optional and will execute the next statement when its condition

evaluates to the Boolean value TRUE.

Notice that the difference between the next and exit statement, is that the exit statement

terminates the loop.

Wait statement

The wait statement will halt a process until an event occurs. There are several forms of the

wait statement,

wait until condition;

wait for time expression;

wait on signal;

wait;

DEPARTMENT OF ECE


The Xilinx Foundation Express has implemented only the first form of the wait statement.

The syntax is as follows,

wait until signal = value;

wait until signal’event and signal = value;

wait until not signal’stable and signal = value;

The condition in the ―wait until‖ statement must be TRUE for the process to resume. A few

examples follow.

wait until CLK=‘1‘;

wait until CLK=‘0‘;

wait until CLK‘event and CLK=‘1‘;

wait until not CLK‘stable and CLK=‘1‘;

For the first example the process will wait until a positive-going clock edge occurs, while for

the second example, the process will wait until a negative-going clock edge arrives. The last

two examples are equivalent to the first one (positive-edge or 0-1 transitions). The hardware

implementation for these three statements will be identical.

It should be noted that a process that contains a wait statement can not have a sensitivity list.

If a process uses one or more wait statements, the Foundation Express synthesizer will use

sequential logic. The results of the computations are stored in flip-flops.

Null statement

The null statement states that no action will occur. The syntax is as follows,

null;

It can be useful in a case statement where all choices must be covered, even if some of them

can be ignored.

DEPARTMENT OF ECE


Dataflow Modeling – Concurrent Statements

Behavioral modeling can be done with sequential statements using the process construct or

with concurrent statements. The first method was described in the previous section and is

useful to describe complex digital systems. In this section, we will use concurrent statements

to describe behavior. This method is usually called dataflow modeling. The dataflow

modeling describes a circuit in terms of its function and the flow of data through the circuit.

This is different from the structural modeling that describes a circuit in terms of the

interconnection of components.

Concurrent signal assignments are event triggered and executed as soon as an event on one of

the signals occurs. In the remainder of the section we will describe several concurrent

constructs for use in dataflow modeling.

Simple Concurrent signal assignments.

We have discussed several concurrent examples earlier in the tutorial. In this section we will

review the different types of concurrent signal assignments.

A simple concurrent signal assignment is given in the following examples,

Sum <= (A xor B) xor Cin;

Carry <= (A and B);

Z <= (not X) or Y after 2 ns;

The syntax is as follows:

Target_signal <= expression;

in which the value of the expression transferred to the target_signal. As soon as an event

occurs on one of the signals, the expression will be evaluated. The type of the target_signal

has to be the same as the type of the value of the expression.

DEPARTMENT OF ECE


Conditional Signal assignments

The syntax for the conditional signal assignment is as follows:

Target_signal <= expression when Boolean_condition else

expression when Boolean_condition else

:

expression;

The target signal will receive the value of the first expression whose Boolean condition is

TRUE. If no condition is found to be TRUE, the target signal will receive the value of the

final expression. If more than one condition is true, the value of the first condition that is

TRUE will be assigned.

Selected Signal assignments

The selected signal assignment is similar to the conditional one described above. The syntax

is as follows,

with choice_expression select

target_name <= expression when choices,

target_name <= expression when choices,

:

target_name <= expression when choices;

The target is a signal that will receive the value of an expression whose choice includes the

value of the choice_expression. The expression selected is the first with a matching choice.

The choice can be a static expression (e.g. 5) or a range expression (e.g. 4 to 9). The

following rules must be followed for the choices:

No two choices can overlap

All possible values of choice_expression must be covered by the set of choices, unless

an others choice is present.

DEPARTMENT OF ECE


Structural Modeling

Structural modeling was described briefly in the section Structural Modeling in ―Basic

Structure of a VHDL file‖. A structural way of modeling describes a circuit in terms of

components and its interconnection. Each component is supposed to be defined earlier (e.g. in

package) and can be described as structural, a behavioral or dataflow model. At the lowest

hierarchy each component is described as a behavioral model, using the basic logic operators

defined in VHDL. In general structural modeling is very good to describe complex digital

systems, though a set of components in a hierarchical fashion.

A structural description can best be compared to a schematic block diagram that can be

described by the components and the interconnections. VHDL provides a formal way to do

this by

Declare a list of components being used

Declare signals which define the nets that interconnect components

Label multiple instances of the same component so that each instance is

uniquely defined.

The components and signals are declared within the architecture body,

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations

component declarations

signal declarations

begin

-- Statements

component instantiation and connections

:

end architecture_name;

DEPARTMENT OF ECE


Component declaration

Before components can be instantiated they need to be declared in the architecture

declaration section or in the package declaration. The component declaration consists of the

component name and the interface (ports). The syntax is as follows:

component component_name [is]

[port (port_signal_names: mode type;

port_signal_names: mode type;

:

port_signal_names: mode type);]

end component [component_name];

The component name refers to either the name of an entity defined in a library or an entity

explicitly defined in the VHDL file (see example of the four bit adder).

The list of interface ports gives the name, mode and type of each port, similarly as is done in

the entity declaration.

A few examples of component declaration follow:

component OR2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;

component PROC

port (CLK, RST, RW, STP: in std_logic;

ADDRBUS: out std_logic_vector (31 downto 0);

DATA: inout integer range 0 to 1024);

component FULLADDER

port(a, b, c: in std_logic;

sum, carry: out std_logic);

http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html#EntityDeclaration

DEPARTMENT OF ECE


end component;

As mentioned earlier, the component declaration has to be done either in the architecture

body or in the package declaration. If the component is declared in a package, one does not

have to declare it again in the architecture body as long as one uses the library and use

clause.

Component Instantiation and interconnections

The component instantiation statement references a component that can be

Previously defined at the current level of the hierarchy or

Defined in a technology library (vendor‘s library).

The syntax for the components instantiation is as follows,

instance_name : component name

port map (port1=>signal1, port2=> signal2,… port3=>signaln);

The instance name or label can be any legal identifier and is the name of this particular

instance. The component name is the name of the component declared earlier using the

component declaration statement. The port name is the name of the port and signal is the

name of the signal to which the specific port is connected. The above port map associates the

ports to the signals through named association. An alternative method is the positional

association shown below,

port map (signal1, signal2,…signaln);

in which the first port in the component declaration corresponds to the first signal, the second

port to the second signal, etc. The signal position must be in the same order as the declared

component‘s ports. One can mix named and positional associations as long as one puts all

positional associations before the named ones. The following examples illustrates this,

DEPARTMENT OF ECE


component NAND2

port (in1, in2: in std_logic;

out1: out std_logic);

end component;

signal int1, int2, int3: std_logic;

architecture struct of EXAMPLE is

U1: NAND2 port map (A,B,int1);

U2: NAND2 port map (in2=>C, in2=>D, out1=>int2);

U3: NAND3 port map (in1=>int1, int2, Z);

…..

DEPARTMENT OF ECE


Verilog HDL

Verilog differs from regular programming languages in 3 main aspects: (1) simulation

time concept, (2) multiple threads, and (3) some basic circuit concepts like network

connections and primitive gates.

Modules

In Verilog, circuit components are designed inside a module. Modules can contain both

structural and behavioral statements. Structural statements represent circuit components like

logic gates, counters, and microprocessors. Behavioral level statements are programming

statements that have no direct mapping to circuit components like loops, if-then statements,

and stimulus vectors which are used to exercise a circuit.

A module starts with the keyword module followed by an optional module name and an

optional port list. The key word endmodule ends a module.

`timescale 1ns / 1ps

//create a NAND gate out of an AND and an Invertor

module some_logic_component (c, a, b);

// declare port signals

output c;

input a, b;

// declare internal wire

wire d;

//instantiate structural logic gates

and a1(d, a, b); //d is output, a and b are inputs

not n1(c, d); //c is output, d is input

endmodule

//test the NAND gate

module test_bench; //module with no ports

reg A, B;

wire C;

//instantiate your circuit

some_logic_component S1(C, A, B);

DEPARTMENT OF ECE


//Behavioral code block generates stimulus to test circuit

initial

begin

A = 1'b0; B = 1'b0;

#50 $display("A = %b, B = %b, Nand output C = %b \n", A, B, C);

A = 1'b0; B = 1'b1;


A = 1'b1; B = 1'b0;


A = 1'b1; B = 1'b1;


end

endmodule

Structural Design with Gate Primitives and the Delay operator

Verilog defines some basic logic gates as part of the language. For example:

nand a1(out1, in1, in2); //2-input NAND gate

nand a2(out1, in1, in2, in3, in4, in5); //5-input NAND gate

By default the timing delay for the gate primitives is zero time. You can define the rising

delay, falling delay using the #(rise, fall) delay operator. And for tri-state gates you can also

define the turn-off delay (transition to high impedance state Z) by using the #(rise, fall, off)

delay operator. For example

notif0 #(10,11,27) inv2(c,d,control) //rise=10, fall=11, off=27(not if control=0)

nor #(10,11) nor1(c,a,b); //rise=10, fall=11 (nor gate)

xnor #(10) xnor1(i,g,h); //rise=10, fall=10 (xnor gate)

Also each of the 3 delays can be defined to have minimum, typical, and a maximum value

using the a colon to separate the values like 8:10:12 instead of 10 in the above examples. At

run time, the Verilog simulator looks for to see if the +mindelay, +typdelay, or +maxdelay

option has been defined so that it will know which of the 3 time values to use. If none of the

options are specified then the typical value is used.

// min:typ:max values defined for the (rise, fall) delays

or #(8:10:12, 10:11:13) or1(c,a,b);

The delay operator has one subtle side effect: it swallows narrow input pulses. Normally, the

delay operator causes the output response of a gate to be delayed a certain amount of time.

DEPARTMENT OF ECE


However if the input pulse width is shorter then the overall delay of the gate then the change

will not be shown on the output.

Here is a list of logic primitives defined for Verilog:

Gate Parameter List Examples

nand nor and

or xor xnor

scalable, requires at

least 2 inputs(output,

input1, input2, � ,

inputx)

and a1(C,A,B);nand na1(out1,in1,in2,in3,in4);nor

#(5) n1(D,A,B);//delay = 5 time unitsxor #(3,4,5)

x1(E,A,B);//rise,fall,off delaysnor #(3:4:5)

n2(F,A,B);//min:typ:max of delays

not buf (output, input) not inv1(c,a);

notif0bufif0

control signal active

low(output, input,

control)

notif0 inv2(c,a, control);

notif1bufif1

control signal active

high(output, input,

control)

not inv1(c,a, control);

Structural Design with Assignment Statements

If you have a lot of random logic, the gate primitives of the previous section are tedious to

use because all the internal wires must be declared and hooked up correctly. Sometimes it is

easier to just describe a circuit using a single Boolean equation. In Verilog, Boolean

equations which have similar timing properties as the gate primitives are defined using a

continuous assignment statement.

For example,:

wire d;

and a1(d, a, b);

not n1(c, d);

can be replaced with one statement:

assign c = !(a && b); //notice that wire d was not used here

Assignments can also be made during the declaration of a wire. In this case the assign

keyword is implicitly assumed to be there for example:

wire d;

assign d = a || b; //continuous assignment

DEPARTMENT OF ECE


wire d = a || b; //implicit continuous assignment

By default the timing delay for assignment statements is zero time. You can define a

propagation delay using the #delay operator just like we did for the gate primitives. The

following examples have the exact same timing.

wire c;

assign #5 c = a && b; //delay in the continuous assignment

wire #5 c = a && b; //delay in the implicit assignment

wire #5 c; //delay in the wire declaration

assign c = a && b;

To demonstrate the pulse swallowing effect of the delays operator, consider the following

senario. In the above examples, if input a changed value at time 10 (and held its value for at

least 5 time units), then the output c would change values at time 15. If input a had a value

pulse that was shorter then the propagation delay of the assignment then the value on a

would not be passed to the output.

The delay operator can also use the full rise, fall, and off delays and each delay can have a

minimum:typical: maximum value. The following is a valid line of code.

and #(8:10:12, 10:11:13, 26:27:29) a1(c,a,b); //min:typ:max of (rise,fall,off)

Appendix A defines all of the operators that can be used in an assignment statement.

Structural Design with using Modules

Verilog supports hierarchical design by allowing modules to instantiate other modules. For

example

module test_bench;

...

some_logic_component S1(C, A, B); //instantiate a some_logic_component module

...

endmodule

By default the timing inside a module is controlled by the module itself. However, modules

can be defined to have parameterized delays similar to the #(4,5) delay operator used with

gate primitives. In the module definition, use the parameter keyword to create delay

variables. Parameters can also be used to change other scalar values in the module. When

the module is instantiated then you can choose to override the delay values using the

DEPARTMENT OF ECE


#(parameter) notation. For example:

module some_logic_component (c, a, b);

... //some code

parameter andDelay = 2; //default delays

parameter invDelay = 2;

and #andDelay a1(d, a, b); //using parameter delays

not #invDelay n1(c, d);

endmodule

module test_bench; //module with no ports

...

some_logic_component #(5,4) S3(E, A, B); //override andDelay=5, invDelay=4

some_logic_component #(5) S2(D, A, B); //override andDelay=5, invDelay=2

some_logic_component S1(C, A, B); //uses default delays

....

endmodule

Modules also support a special kind of timing called specify blocks which can be used in

conjunction with SDF analyzers. Specify blocks also support continuous setup and hold

checking.

Behavioral Design with Initial and Always blocks

Behavioral code is used to describe circuits at a more abstract level then the structural level

statements we have studied. All Behavioral code occurs within either an initial block or in an

always block. A module can contain several initial and always blocks. These behavioral

blocks contain statements that control simulation time, data flow statements (like if-then and

case statements), and blocking and non-blocking statements.

An initial block executes once during a simulation. Initial blocks are usually used to

initialize variables and to describe stimulus waveforms which exercise which drive the

simulation.

An always block continuously repeats its execution during a simulation. Always blocks

usually contain behavioral code that models the actual circuit operation.

During a simulation each always and each initial block begin to execute at time zero. Each

block executes concurrently with each structural statement and all the other behavioral

DEPARTMENT OF ECE


blocks. The following example shows a behavioral SRAM model. The initial block sets the

memory cells to zero at startup. The always block executes each time there is a change on

the write control line, the chip select line, or the address bus. As an exercise, copy and paste

this code into a verilog file and write a test bench to exercise the model. If you are using

VeriLogger Pro then you can draw a test bench.

//SRAM Model

module sram(CSB,WRB,ABUS,DATABUS);

input CSB; // active low chip select

input WRB; // active low write control

input [11:0] ABUS; // 12-bit address bus

inout [7:0] DATABUS; // 8-bit data bus

//** internal signals

reg [7:0] DATABUS_driver;

wire [7:0] DATABUS = DATABUS_driver;

reg [7:0] ram[0:4095]; // memory cells

integer i;

initial //initialize all RAM cells to 0 at startup

begin

DATABUS_driver = 8'bzzzzzzzz;

for (i=0; i < 4095; i = i + 1)

ram[i] = 0;

end

always @(CSB or WRB or ABUS)

begin

if (CSB == 1'b0)

begin

if (WRB == 1'b0) //Start: latch Data on rising edge of CSB or WRB

begin

DATABUS_driver <= #10 8'bzzzzzzzz;

@(posedge CSB or posedge WRB);

$display($time," Writing %m ABUS=%b DATA=%b",ABUS,DATABUS);

DEPARTMENT OF ECE


ram[ABUS] = DATABUS;

end

if (WRB == 1'b1) //Reading from sram (data becomes valid after 10ns)

begin

#10 DATABUS_driver = ram[ABUS];

$display($time," Reading %m ABUS=%b DATA=%b",ABUS,DATABUS_driver);

end

end

else //sram unselected, stop driving bus after 10ns

begin

DATABUS_driver <= #10 8'bzzzzzzzz;

end

end

endmodule

Structural Data Types: wire and reg

Verilog supports structural data types called nets which model hardware connections

between circuit components. The two most common structural data types are wire and reg.

The wire nets act like real wires in circuits. The reg type hold their values until another

value is put on them, just like a register hardware component. The declarations for wire

and reg signals are inside a module but outside any initial or always block. The initial state

of a reg is x unknown, and the initial state of a wire is z.

Ports:Modules communicate with each other through ports, the signals listed in the

parameter list at the top of the module. Ports can be of type in, out, and inout.

Here are 3 simplistic rules for matching the structural data type to the type of port:

1. Use reg as the outputs of Behavioral blocks. If you us a wire then the value will

never be seen by other blocks.

2. Use wire for all inputs, inouts, and most outputs of Structural elements.

3. If you need a special strength type operation use special net keyword wand, wor,

tir, triand, trior, trireg.

Behavioral Data Types: integer, real, and time

The types in integer and real are convenient data types to use for counting in behavioral

code blocks. These data types act like their counter parts in other programming languages.

DEPARTMENT OF ECE


If you eventually plan to synthesize your behavioral code then you would probably want to

avoid using these data types because they often synthesize large circuits.

The data type time can hold a special simulator value called simulation time which is

extracted from the system function $time. The time information can be used to help you

debug your simulations.

..... //code fragment from inside a module

integer i, y;

real a;

real b = 3.5;

real c = 4;

time simulationTime;

initial

begin

y = 4;

i = 5 + y;

c = c + 3.5;

a = 5.3e4;

simulationTime = $time;

$display("integer y = %d, i = %f \n", y, i);

$display("reals c = %f, a = %e, b= %g \n", c, a, b);

$display("time simulationTime = %t \n", simulationTime);

End

Number Syntax

Numbers in verilog are in the following format

'

The size is always specified as a decimal number. If no is specified then the default size is

at least 32bits and may be larger depending on the machine. Valid base formats are 'b , 'B

, 'h , 'H 'd , 'D , 'o , 'O for binary, hexadecimal, decimal, and octal. Numbers consist of

strings of digits (0-9, A-F, a-f, x, X, z, Z). The X's mean unknown, and the Z's mean high

impedance If no base format is specified the number is assumed to be a decimal number.

Some examples of valid numbers are:

2'b10 // 2 bit binary number

'b10 // at least a 32-bit binary number

DEPARTMENT OF ECE


3 // at least a 32-bit decimal number

8'hAf // 8-bit hexadecimal

-16'd47 // negative decimal number

Behavioral Design with blocking and non-blocking statements

There are 2 kinds of assignment statements: blocking using the = operator, and non-

blocking using the <= operator. Blocking assignments act like sequential code statements

and execute when they are called. Non-blocking schedule events to happen at some time in

the future. This can be confusing because lines that appear after a non-blocking statement

execute at the same time as the non-blocking statement. Here are some examples:

#5 x = 1'b0; // blocks for 5 time units, applies value to x, then next line goes

y = 1'b1; // blocks, sets y to 1 now, then next statement goes

y <= #3 1'b0; // evaluates now, schedules apply y=0 in 3 time units, and next line goes

#5 x <= y; // waits for 5 time units, evaluates,

// schedules apply at end of current time, and next line goes

The following two code blocks are not equivalent:

// Section 1: Blocking statements execute sequentially

#5 a = b; // waits 5 time units, evaluates and applies value to a

c = d; // evaluates and applies value to c

// Section 2: Non-Blocking statements execute concurrently

#5 a <= b; // waits 5 time units, evaluates, schedules apply for end of current time

c <= d; // evaluate, schedules apply for end of current time

// At end of current time both a and c receive their values

Arrays, Vectors, and Memories

Verilog supports three similar data structures called Arrays, Vectors, and Memories.

Arrays are used to hold several objects of the same type. Vectors are used to represent

multi-bit busses. And Memories are arrays of vectors which are accessed similar to

hardware memories. Read the following examples to determine how to reference and use

the different data structures.

//*** Arrays for integer, time, reg, and vectors of reg ***************

integer i[3:0]; //integer array with a length of 4

time x[20:1]; //time array with length of 19

reg r[7:0]; //scalar reg array with length of 8

DEPARTMENT OF ECE


c = r[3]; //the 3rd reg value in array r is assigned to c

//*** Vectors are multi-bit words of type reg or net (wire)************

reg [7:0] MultiBitWord1; // 8-bit reg vector with MSB=7 LSB=0

wire [0:7] MultiBitWord2; // 8-bit wire vector with MSB=0 LSB=7

reg [3:0] bitslice;

reg a; // single bit vector often referred to as a scalar

.... //referencing vectors

a = MultiBitWord1[3]; //applies the 3rd bit of MultiBitWord1 to a

bitslice = MultiBitWord1[3:0]; //applies the 3-0 bits of MultiBitWord1 to bitslice

//*** Memories are arrays of vector reg ********************************

reg [7:0] ram[0:4095]; // 4096 memory cells that are 8 bits wide

//code excerpt from Chapter 2 SRAM model

input [11:0] ABUS; // 12-bit address bus to access all 4096 memory cells

inout [7:0] DATABUS; // 8-bit data bus to wite into and out of a memory cell

reg [7:0] DATABUS_driver;

wire [7:0] DATABUS = DATABUS_driver; //inout must be driven by a wire

....

for (i=0; i < 4095; i = i + 1) // Setting individual memory cells to 0

ram[i] = 0;

end

....

ram[ABUS] = DATABUS; //writing to a memory cell

....

DATABUS_driver = ram[ABUS]; //reading from a memory cell

Operators

Here is a small selection of the Verilog Operators which look similar but have different

effects. Logical Operators evaluate to TRUE or FALSE. Bitwise operators act on each bit

of the operands to produce a multi-bit result. Unary Reduction operators perform the

DEPARTMENT OF ECE


operation on all bits of the operand to produce a single bit result.

Operator Name Examples

! logical negation

~ bitwise negation

&& logical and

& bitwise and abus =

bbus&cbus;

& reduction and abit = &bbus;

~& reduction nand

|| logical or

| bitwise or

| reduction or

~| reduction nor

^ bitwise xor

^ reduction xor

~^ ^~ bitwise xnor

~^ ^~ reduction xnor

== logical equality, result may be unknown if x or z in the input if (a == b)

=== logical equality including x and z

!= logical inequality, result may be unknown if x or z in the input

!== logical inequality including x and z

> relational greater than

>> shift right by a number of positions a = shiftvalue

>> 2;

>= relational greater than or equal

< relational less than

<< shift left by a number of positions

DEPARTMENT OF ECE


<= relational less than or equal if (a <= b)

<= non blocking assignment statement, schedules assignment for

future and allows next statement to execute #5 b <= b + 2;

= blocking assignment statement, waits until assignment time

before allowing next statement to execute #5 a = a + 2;

Verilog also supports arithmetic, replication, and concatenation operators

DEPARTMENT OF ECE


INTERVIEW QUESTIONS

DEPARTMENT OF ECE


1. What is VHDL?

2. List out all IEEE standard libraries available in VHDL?

3. What is Gate-level simulation?

4. Why we go for Gate-level simulation?

5. Which is the tool responsible for mapping the net lists to physical devices?

6. How the ―timing verification‖ will be done?

7. List out all strengths of signals in std_logic_1164

8. Is that object of type Real is supported in VHDL?

9. What is a configuration?

10. List out the objects of VHDL?

11. Which are the major data types in VHDL?

12. Which are the two composite types?

13. What is the difference between array and record?

14. What is an alias and write its syntax?

15. What is the use of subtype in VHDL?

16. Write an syntax for subtype?

17. What are signals?

18. When the computed values will get assign to signal?

19. What are the properties of signal?

20. Which is the signal assignment operator?

21. How the signal acts within a process and outside the process?

22. Mention the two delays in VHDL?

23. How will you specify the delay in VHDL?

24. What is inertial delay?

25. What is propagation delay?

26. Which is the default delay in VHDL?

27. What is the main functionality of block statements?

28. How the processes in program executes and how statements within process executes?

29. How much time simulator takes to execute all statements in process?

30. Mention two types of process?

31. Explain variables, constants?

32. List out the differences between signal and variable?

33. List some the sequential statements?

34. List out the different options available for wait statement?

35. Is ―Real‖ data type is synthesizable?

36. How we can include package in our program?

37. What do we need to generate hardware from VHDL model?

DEPARTMENT OF ECE


38. How we come to know that the particular model reflects intended behavior?

39. What is the main difference between software language and HDL?

40. How will you test the design?

41. How will you justify that it is strongly typed language?List out the levels of abstractions in

VHDL?

43. Which type of assignment statements will be used in data flow level and behavioral level?

44. What is the difference between sequential circuit and combinational circuit?

45. Why is configuration used?

46. What is generate? What the types are of generate?

47. What is access type?

48. What is generic?

49. While accessing an array, can we give the array index as a variable?

50. What is record?

51. What is the difference between a latch and flip flop?

52. Define setup time and hold time?

53. What is metastability?

54. How can we overcome metastability?

55. What are attributes?

56. What is a test bench?

57. What is the difference between inout and buffer ports?

58. What is signal array?

59. How the signal array is declared?

60. How multi dimensional array is declared?

61. Will synthesizer accept multi dimensional array? if not how we can declare that?

62. List out the four modes for port in VHDL?

63. Which is the concatenation operator?

64. What is combinational process?

65. What are constants?

66. What is assertion?

67. What is the syntax of assertion?

68. Which are the severity levels in assertion?

69. Which is the default severity level?

70. Is that assert is sequential statement or concurrent statement?

71. Find the value of A, B, C in the following circuit ,after 3 clock cycles.

DEPARTMENT OF ECE


72. If A=10 and B=20, without using temporary register how can you interchange the two things

73. What is the expression for output 'y' in the following circuit?

74. What is the difference between Moore and Mealy state machines?

75. Differences between Signals and Variables in VHDL?

76. Write a verilog code to swap contents of two registers with and without a temporary register?

77. Difference between blocking and non-blocking ststement.

78. Tell me how blocking and non blocking statements get executed?

79. Difference between task and function?

80. Difference between inter statement and intra statement delay?

81. Difference between $monitor,$display & $strobe?

82. What is difference between Verilog full case and parallel case?

83. What is meant by inferring latches, how to avoid it?

84. Variable and signal which will be Updated first?

85. What is sensitivity list?

86. In a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk? if

yes, why?

87. Can you tell me some of system tasks and their purpose?

88. Can you list out some of enhancements in Verilog 2001?

89. Write a Verilog code for synchronous and asynchronous reset?

90. What is pli?why is it used?

91. How to write FSM is verilog?

92. What is difference between freeze deposit and force?

http://4.bp.blogspot.com/_c99lLjgQ8ho/S8Vo4FmMKII/AAAAAAAAAlo/jiUauU2GRGg/s1600/stm+ing.JPG

http://3.bp.blogspot.com/_c99lLjgQ8ho/S8VqF8FMhrI/AAAAAAAAAl4/8214t-3cxjE/s1600/educe.JPG

http://4.bp.blogspot.com/_c99lLjgQ8ho/S8Vo4FmMKII/AAAAAAAAAlo/jiUauU2GRGg/s1600/stm+ing.JPG

http://3.bp.blogspot.com/_c99lLjgQ8ho/S8VqF8FMhrI/AAAAAAAAAl4/8214t-3cxjE/s1600/educe.JPG

DEPARTMENT OF ECE


93. Will case infer priority register if yes how give an example?

94. Case X, Case Z differentiate which is preferable, why?

95. What is the difference between the following two lines of Verilog code?

#5 a = b;

a = #5 b;

96. What is the difference between:

c = foo ? a : b;

andif (foo) c = a;

else c = b;

97. What does `timescale 1 ns/ 1 ps signify in a verilog code?

98. What is the difference between === and == ?

99. What is the difference between wire and reg?

100. Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case?

101. What are Different types of Verilog Simulators ?

102. What happens if there is connecting wires width mismatch?

103. What is the difference between transport delay and inertial delay?

104. What is the difference between ( = = , ! = ) and ( = = = , ! = = )?

DEPARTMENT OF ECE


ANSWER

1. VHDL stands for VHSIC Hardware description language. Where VHSIC stands for Very

High Speed Integrated Circuit.

2. std_logic_1164., numeric_std., numeric_bit ., std_logic_arith., std_logic_unsigned

3. Simulating synthesized net list is called Gate-level simulation.

4. The main advantage is that the test bench can be re-used with synthesized circuit that

means we can apply similar test patterns to gate level model to verify that it has response

similar to original model.

5. Implementation tool.

6. This can be done by creating timing model by implementation tool. Where the timing

model consists of gate-level primitives augmented with detailed delay information and can be

used to verify the timing behavior.

7. ‘U‘ --Uninitialized ‘X‘ --Forcing Unknown ‘0‘ --Forcing 0 ‘1‘ --Forcing 1 ‘Z‘ --High

Impedance ‘W‘ --Weak Unknown ‘L‘ -- Weak 0 ‘H‘ -- Weak 1 ‘-‘ -- don‘t care

8. No, because floating point numbers cannot be mapped to hardware.

9. It is that block of code which will bind the particular architecture body to its entity and a

component with an entity.

10. Signal, Variable, Constant.

11. Scalar Types and Composite Types

12. Array and Record

13. Array contains many elements of the same type. But Record contains many elements of

different types.

14. Alias is an alternative name assigned to part of an object. alias alias_name : subtype is

name;

15. Subtype is mainly used for range checking and for imposing additional constraints on

types.

16. subtype name is base type range constraint;

17. Signals are like wires which connect design entities together and communicate changes

in values within a design.

18. After delta delay

19. Type and Type attributes, value, time.

DEPARTMENT OF ECE


20. ― < = ―

21. Signal assignment is concurrent outside the process and sequential within a process.

22. Inertial delay and Transport delay

23. Using after clause.

24. This is the delay often found in switching circuits where spikes will not propagate

further in circuit.

25. Transport delay models the behaviour of a wire, in which all pulses are propagated

irrespective there width

26. Delta delay.

27. Block statements don't have special functionality as such it separates part of the code

without adding any functionality.

28. Processes will be executed concurrently but statements within process will be executed

sequentially.

29. Zero simulation time.

30. Combinational and Clocked processes.

31. Variables are key words used to declare and can be used inside a process or

subprograms. Variable assignment occurs immediately. Variable retain their variables

throughout the entire simulation. Require less memory Constant is identifiers with a fixed

value. They should not be assigned any values by the simulation process.

32. Signals Connects design entities together. Signals can be declared both inside and

outside of the process. It has three properties like type & type attributes, Value, Time. Signals

assign its value after delta delay. Signals require more memory.

Variables are the identifiers within process or subprograms. This can only be declared within

process can't be used outside a process. It has only two properties like Type, Value. Variable

assigned its value immediately. Variable require less memory.

33. If, else, else, case, loops, wait statement.

34. wait on signal, wait until boolean_expr, wait for time_expr

35. Real is not synthesizable.

36. library work;

use work.pkg_name.all;

Add these lines in code just after the standard library declaration.

37. We need following tools

1. Simulation tool. 2. Synthesis tool. 3. Implementation tool.

DEPARTMENT OF ECE


38. We use a tool called simulator to simulate the model to verify that the description is

working as intended.

39. Concurrency.

40. By sending different input to design by test bench.

41. VHDL allows LHS & RHS operators of same type.

42. Different types in LHS & RHS is illegal in VHDL

43. Data flow level, Structural Level, Behavioural Level

44. Concurrent statements will be used in data flow level and Sequential statements will be

used in behavioural level.

45. To select one of the many architecture bodies that an entity may have.

46. Concurrent statements can be conditionally selected or replicated during the elaboration

phase. This is called generate .there are two forms of generate. -for generate -if generate

47. These provide access to object that contains a sequence of values of a given type. Values

belonging to access type are pointers to a dynamically allocated object of some other type.

48. Generics are used to pass certain type of information into o design description from its

environment.

49. Yes, we can. But the range of variable should be limited such that it doesn‘t access

outside the array limits.

50. It is a collection of values that may belong to different types.

51. Latches are level sensitive and flip flops are edge sensitive. Latch allows time borrowing

whereas flip-flop does not allow time borrowing. Latches hold the last logic at output if we

put it off. Flip-flops transfer data only at that instant of time and can be changed until next

signal change.

52. Setup time is the time required for the synchronous inputs of a flip-flop to be stable

before a clock pulse is applied. Hold time is the time that the synchronous inputs of a flip-

flop remain stable after the active clock transaction is finished.

53. Metastability is an unknown state. It is neither 0 or nor 1. If the setup time and hold time

are violated, the flip-flop goes into metastability state.

54. Using proper synchronizers. 2. Using faster flip-flops.

55. An attribute is a value, function, range, signal, type or constant that can be associated

with certain names within VHDL description. These names could be among others, entity

name, architecture name.

56. It is a code that generates the stimuli to test out design correctness. It automatically

verifies the code accuracy. It also verifies whether the code meets the circuit requirements.

DEPARTMENT OF ECE


57. A buffer is an OUT port with read capability. A buffer port may have at most one driver

within the architecture whereas inout port is just bidirectional port.

58. A set of signals may also be declared as a signal array which is a concatenated set of

signals.

59. < type> (< range>)

60. type array_name is array (index_range, index_range) of element_type; .

61. No we can declare the multi dimentional array as two uni dimentional array as shown in

below example type byte is array (7 downto 0 ) of std_logic; type mem is array (3 downto 0)

of byte;

62. in,out,inout,buffer.

63. ―&‖

64. Process having all inputs in sensitivity list..

65. Are identifiers with a fixed value.

66. it is the statement used to report an error when a condition i false.

67. assert < condition> report < message> severity< level>

68. Warning , Error , Failure.

69. Error.

70. Both

71. This is a simple Ring counter. An n-bit ring counter has n states. The 3-bit counter

shown above has 3 states and they are : 100 , 010 , and 001, 100 and so on. So after 3

clock cycles A,B,C = 100.

72. Perform the following operations sequentially:

A = A xor B;

B = A xor B;

A = A xor B;

Now A=20 and B=10.

73. Ans : (In the notation I have used,A' means not(A), and AB means (A and B).

y = ( A'B'C + AB'C' + A'BC + ABC' )

= ( A'C (B+B') + AC' (B+B') )

= A'C + AC'

= A xor C.

74. Moore and Mealy state machines are two ways of designing a state machine. Moore state

machines are controlled in such a way that the outputs are a function of the previous state and

DEPARTMENT OF ECE


the inputs. However, Mealy state machines are controlled in a way such that the Outputs may

change with a change of state OR with a change of inputs. A Moore state machine may

require more states(but less complexity) than a Mealy state machine to accomplish the same

task.

75. Signals update a value after some "delta" time or at the end of the process. But variable

updates a value immediately.

76. With temp reg ;

always @ (posedge clock)begin

temp=b;

b=a;

a=temp;

end

Without temp reg;

always @ (posedge clock)

begin

a <= b;

b <= a;

end

77. The Verilog language has two forms of the procedural assignment statement: blocking

and non-blocking. The two are distinguished by the = and <= assignment operators. The

blocking assignment statement (= operator) acts much like in traditional programming

languages. The whole statement is done before control passes on to the next statement. The

non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and

assigns the left-hand sides at the end of the time unit. For example, the following Verilog

program

78. // testing blocking and non-blocking assignment

module blocking;

reg [0:7] A, B;

initial begin: init1

A = 3;

#1 A = A + 1; // blocking procedural assignment

DEPARTMENT OF ECE


B = A + 1;

$display("Blocking: A= %b B= %b", A, B ); A = 3;

#1 A <= A + 1; // non-blocking procedural assignment

B <= A + 1;

#1 $display("Non-blocking: A= %b B= %b", A, B );

end

endmodule

produces the following output:

Blocking: A= 00000100 B= 00000101

Non-blocking: A= 00000100 B= 00000100

79. Function:

A function is unable to enable a task however functions can enable other functions.

A function will carry out its required duty in zero simulation time. ( The program time will

not be incremented during the function routine)

Within a function, no event, delay or timing control statements are permitted

In the invocation of a function there must be at least one argument to be passed.

Functions will only return a single value and cannot use either output or inout statements.

Tasks:

Tasks are capable of enabling a function as well as enabling other versions of a Task

Tasks also run with a zero simulation however they can if required be executed in a non zero

simulation time.

Tasks are allowed to contain any of these statements.

A task is allowed to use zero or more arguments which are of type output, input or inout.

A Task is unable to return a value but has the facility to pass multiple values via the output

and inout statements .

80. //define register variables

reg a, b, c;

//intra assignment delays

initial

DEPARTMENT OF ECE


begin

a = 0; c = 0;

b = #5 a + c; //Take value of a and c at the time=0, evaluate

//a + c and then wait 5 time units to assign value

//to b.

end

//Equivalent method with temporary variables and regular delay control

initial

begin

a = 0; c = 0;

temp_ac = a + c;

#5 b = temp_ac; //Take value of a + c at the current time and

//store it in a temporary variable. Even though a and c

//might change between 0 and 5,

//the value assigned to b at time 5 is unaffected.

end

81. These commands have the same syntax, and display text on the screen during simulation.

They are much less convenient than waveform display tools like cwaves?. $display and

$strobe display once every time they are executed, whereas $monitor displays every time one

of its parameters changes.

The difference between $display and $strobe is that $strobe displays the parameters at the

very end of the current simulation time unit rather than exactly where it is executed. The

format string is like that in C/C++, and may contain format characters. Format characters

include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t

(time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number

instead of the space needed. Append b, h, o to the task name to change default format to

binary, octal or hexadecimal.

Syntax:

$display (�format_string�, par_1, par_2, ... );

$strobe (�format_string�, par_1, par_2, ... );

DEPARTMENT OF ECE


$monitor (�format_string�, par_1, par_2, ... );

82. A "full" case statement is a case statement in which all possible case-expression binary

patterns can be matched to a case item or to a case default. If a case statement does not

include a case default and if it is possible to find a binary case expression that does not match

any of the defined case items, the case statement is not "full."

A "parallel" case statement is a case statement in which it is only possible to match a case

expression to one and only one case item. If it is possible to find a case expression that would

match more than one case item, the matching case items are called "overlapping" case items

and the case statement is not "parallel."

83. To avoid inferring latches make sure that all the cases are mentioned if not default

condition is provided.

84. Signals

85. The sensitivity list indicates that when a change occurs to any one of elements in the list

change, statement inside that begin�end always block will get executed.

86. Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity

disk otherwise it will result in pre and post synthesis mismatch.

87. $display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $display.This can be used for displaying strings, expression or

values of variables.

Here are some examples of usage.

$display("Hello oni");

--- output: Hello oni

$display($time) // current simulation time.

--- output: 460

counter = 4'b10;

$display(" The count is %b", counter);

--- output: The count is 0010

$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive

mode where the

user can enter commands; $finish exits the simulator back to the operating system

DEPARTMENT OF ECE


88. In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity

list . In Verilog 2001, we can use comma as shown in the example below.

// Verilog 2k example for usage of comma

always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS

of combo logics . This removes typo mistakes and thus avoids simulation and synthesis

mismatches,

Verilog 2001 allows port direction and data type in the port list of modules as shown in the

example below

module memory (

input r,

input wr,

input [7:0] data_in,

input [3:0] addr,

output [7:0] data_out

);

89. Synchronous reset, synchronous means clock dependent so reset must not be present in

sensitivity disk eg:

always @ (posedge clk )

begin if (reset)

. . . end

Asynchronous means clock independent so reset must be present in sensitivity list.

Eg

Always @(posedge clock or posedge reset)

begin

if (reset)

. . . end

90. Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface

Verilog programs with programs written in C language. It also provides mechanism to access

internal databases of the simulator from the C program.

PLI is used for implementing system calls which would have been hard to do otherwise (or

impossible) using Verilog syntax. Or, in other words, you can take advantage of both the

DEPARTMENT OF ECE


paradigms - parallel and hardware related features of Verilog and sequential flow of C - using

PLI.

91. There r mainly 4 ways 2 write fsm code

1) using 1 process where all input decoder, present state, and output decoder r combine in one

process.

2) using 2 process where all comb ckt and sequential ckt separated in different process

3) using 2 process where input decoder and persent state r combine and output decoder

seperated in other process

4) using 3 process where all three, input decoder, present state and output decoder r separated

in 3 process.

92. $deposit(variable, value);

This system task sets a Verilog register or net to the specified value. variable is the

register or net to be changed; value is the new value for the register or net. The value

remains until there is a subsequent driver transaction or another $deposit task for the

same register or net. This system task operates identically to the ModelSim

force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is

specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved

signals. This is designed to provide compatibility with force files. But if you prefer -freeze

as the default for both resolved and unresolved signals.

93. Yes Case can infer priority register depending on coding style

reg r;

// Priority encoded mux,

always @ (a or b or c or select2)

begin

r = c;

case (select2)

2'b00: r = a;

2'b01: r = b;

endcase

end

94. CASEZ :

Special version of the case statement which uses a Z logic value to represent don't-care bits.

DEPARTMENT OF ECE


CASEX :

Special version of the case statement which uses Z or X logic values to represent don't-care

bits.

CASEZ should be used for case statements with wildcard dont cares, otherwise use of CASE

is required; CASEX should never be used. This is because: Dont cares are not allowed in the

"case" statement. Therefore casex or casez are required. Casex will automatically match any

x or z with anything in the case statement. Casez will only match zs -- xs require an absolute

match.

95. #5 a = b; Wait five time units before doing the action for "a = b;".

a = #5 b; The value of b is calculated and stored in an internal temp register,After five time

units, assign this stored value to a.

96. The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10, and b

= 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so you'd always

get c = b.

97. 'timescale directive is a compiler directive.It is used to measure simulation time or delay

time. Usage : `timescale / reference_time_unit : Specifies the unit of measurement for times

and delays. time_precision: specifies the precision to which the delays are rounded off.

98. output of "==" can be 1, 0 or X.

output of "===" can only be 0 or 1.

When you are comparing 2 nos using "==" and if one/both the numbers have one or more bits

as "x" then the output would be "X" . But if use "===" outpout would be 0 or 1.

e.g A = 3'b1x0

B = 3'b10x

A == B will give X as output.

A === B will give 0 as output.

"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the input is

X output will be X

"===" is used for comparison of X also.

99. Net types: (wire,tri)Physical connection between structural elements. Value assigned by

a continuous assignment or a gate output. Register type: (reg, integer, time, real, real time)

represents abstract data storage element. Assigned values only within an always statement or

an initial statement. The main difference between wire and reg is wire cannot hold (store) the

value when there no connection between a and b like a->b, if there is no connection in a and

DEPARTMENT OF ECE


b, wire lose value. But reg can hold the value even if there in no connection. Default

values:wire is Z,reg is x.

100. This is a popular coding error. You used the bit wise AND operator (&) where you

meant to use the logical AND operator (&&).

101. There are mainly two types of simulators available.

Event Driven

Cycle Based

102. For example there are two signals rhs[7:0], and lhs[15:0]. If we do rhs = lhs. Then it is

equivalent to rhs = lhs[7:0]. Assignment starts from LSBs of the signals, and ends at the MSB

of smaller width signal.

103. Transport delay is the delay caused by the wires connecting the gates. Wire do delay the

signal they carry, this is due to the wire resistance, capacitance, and inductance. Simply

transport delay is propagation delay on a wire. In verilog transport delay is modeled as

follows:

a <= #10 b; Inertial delay is the time taken by a gate to change its output. It is the gate delay.

In verilog inertial delay is modeled as follows: assign #10 a = b;

104. The equality operators ( = = , ! = ) will yield an x if either operand has x or z in its bits.

Where as the case equality operators ( = = = , ! = = ) compare both operands bit by bit and

compare all bits, including x and z.

DEPARTMENT OF ECE


CHAPTER 6

COMPUTER

ARCHITECTURE

DEPARTMENT OF ECE


FUNCTIONAL UNITS OF A COMPUTER SYSTEM

Digital computer systems consist of three distinct units. These units are as follows: Input unit

Central Processing unit Output unit these units are interconnected by electrical cables to

permit communication between them. This allows the computer to function as a system. Input

Unit A computer must receive both data and program statements to function properly and be

able to solve problems. The method of feeding data and programs to a computer is

accomplished by an input device. Computer input devices read data from a source, such as

magnetic disks, and translate that data into electronic impulses for transfer into the CPU.

Some typical input devices are a keyboard, a mouse,or a scanner. Central Processing Unit

The brain of a computer system is the central processing unit (CPU). The CPU processes data

transferred to it from one of the various input devices. It then transfers either an intermediate

or final result of the CPU to one or more output devices. A central control section and work

areas are required to perform calculations or manipulate data. The CPU is the computing

center of the system. It consists of a control section, an arithmetic-logic section, and an

internal storage section (main memory). Each section within the CPU serves a specific

function and has a particular relationship with the other sections within the CPU.

Some practitioners of computer architecture at companies such as Intel and AMD use more

fine distinctions:

Macroarchitecture - architectural layers that are more abstract than microarchitecture, e.g.

ISA

ISA (Instruction Set Architecture) - as defined above

Assembly ISA - a smart assembler may convert an abstract assembly language common to a

group of machines into slightly different machine language for different

implementations - higher level language tools such as

compilers may define a consistent interface or contract to programmers using them,

abstracting differences between underlying ISA, UISA, and microarchitectures. E.g. the C,

C++, or Java standards define different Programmer Visible Macroarchitecture - although in

practice the C microarchitecture for a particular computer includes

tecture) - a family of machines with different

hardware level microarchitectures may share a common microcode architecture, and hence a

DEPARTMENT OF ECE


UISA. - the set of functions that a microprocessor is expected to provide,

from the point of view of a hardware platform. E.g. the x86 A20M, FERR/IGNNE or FLUSH

pins, and the messages that the processor is expected to emit after completing a cache

invalidation so that external caches can be invalidated. Pin architecture functions are more

flexible than ISA functions - external hardware can adapt to changing encodings, or changing

from a pin to a message - but the functions are expected to be provided in successive

implementations even if the manner of encoding them changes.

Design goals

The exact form of a computer system depends on the constraints and goals for which it was

optimized. Computer architectures usually trade off standards, cost, memory capacity, latency

and throughput. Sometimes other considerations, such as features, size,w eight, reliability,

expandability and power consumption are factors as well. The most common scheme

carefully chooses the bottleneck that most reduces the computer's speed. Ideally, the cost is

allocated proportionally to assure that the data rate is nearly the same for all parts of the

computer, with the most costly part being the slowest. This is how skillful commercial

integrators optimize personal computers.

Central processing unit (CPU) —

The part of the computer that executes program instructions is known as the processor or

central processing unit (CPU). In a microcomputer, the CPU is on a single electronic

component, the microprocessor chip, within the system unit or system cabinet. The system

unit also includes circuit boards, memory chips, ports and other components. A

microcomputer system cabinet will also house disk drives, hard disks, etc., but these are

considered separate from the CPU. This is principal part of any digital computer

system,generally composed of control unit, and arithmetic-logic unit the ‗heart‖ of the

computer.It constitutes the physical heart of the entire computer system; to it is linked various

peripheral equipment, including input/output devices and auxiliary storage units.

Control Unit is the part of a CPU or other device that directs its operation. The control unit

tells the rest of the computer system how to carry out a program‘s instructions. It directs the

movement of electronic signals between memory—which temporarily holds data, instructions

and processed information—and the ALU. It also directs these control signals between the

DEPARTMENT OF ECE


CPU and input/output devices. The control unit is the circuitry that controls the flow of

information through the processor, and coordinates the activities of the other units within it.

In a way, it is the "brain", as it controls what happens inside the processor, which in turn

controls the rest of the PC.

Arithmetic-Logic Unit usually called the ALU is a digital circuit that performs two types of

operations— arithmetic and logical. Arithmetic operations are the fundamental mathematical

operations consisting of addition, subtraction, multiplication and division. Logical operations

consist of comparisons. That is, two pieces of data are compared to see whether one is equal

to, less than, or greater than the other. The ALU is a fundamental building block of the

central processing unit of a computer. Memory — Memory enables a computer to store, at

programs. Memory—also known as the primary storage or main

memory—is a part of the microcomputer that holds data for processing, instructions for

processing the data (the program) and information (processed data). Part of the contents of

the memory is held only temporarily, that is, it is stored only as long as the microcomputer is

turned on. When you turn the machine off, the contents are lost. The capacity of the memory

to hold data and program instructions varies in different computers. The original IBM PC

could hold approximately 6,40,000 characters of data or instructions only. But modern

microcomputers can hold millions, even billions of characters in their memory.

Input device :

An input device is usually a keyboard or mouse, the input device is the conduit through

which data and instructions enter a computer. A personal computer would be useless if you

could not interact with it because the machine could not receive instructions or deliver the

results of its work. Input devices accept data and instructions from the user or from another

computer system (such as a computer on the Internet). Output devices return processed data

to the user or to another computer system. The most common input device is the keyboard,

which accepts letters, numbers, and commands from the user. Another important type of

input device is the mouse, which lets you select options from on-screen menus. You use a

mouse by moving it across a flat surface and pressing its buttons. A variety of other input

devices work with personal computers, too: The trackball and touchpad are variations of the

mouse and enable you to draw or point on the screen. The joystick is a swiveling lever

mounted on a stationary base that is well suited for

playing video games.

DEPARTMENT OF ECE


Basic Operational Concepts of a Computer

• Most computer operations are executed in the ALU (arithmetic and logic unit) of a

processor.

• Example: to add two numbers that are both located in memory.

– Each number is brought into the processor, and the actual addition is carried out by the

ALU.

– The sum then may be stored in memory or retained in the processor for immediate use.

Registers

• When operands are brought into the processor, they are stored in high-speed storage

elements (registers).

• A register can store one piece of data (8-bit registers, 16-bit registers, 32-bit registers, 64-bit

registers, etc…)

• Access times to registers are faster than access times to the fastest cache unit in the memory

hierarchy.

How are instructions sent between memory and the processor

• The program counter (PC) or instruction pointer (IP) contains the memory address of the

next instruction to be fetched and executed.

• Send the address of the memory location to be accessed to the memory unit and issue the

appropriate control signals (memory read).

• The instruction register (IR) holds the instruction that is currently being executed.

• Timing is crucial and is handled by the control unit within the processor.

Single BUS STRUCTURES :

Bus structure and multiple bus structures are types of bus or computing. A bus is basically a

subsystem which transfers data between the components of a Computer components either

within a computer or between two computers. It connects peripheral devices at the same time.

- A multiple Bus Structure has multiple inter connected service integration buses and for each

bus the other buses are its foreign buses. A Single bus structure is very simple and consists of

a single server. - A bus can not span multiple cells. And each cell can have more than one

buses. Published messages are printed on it. There is no messaging engine on Single bus

structure I)In single bus structure all units are connected in the same bus than connecting

DEPARTMENT OF ECE


different buses as multiple bus structure. Ii)multiple bus structure's performance is better than

single bus structure.

Iii)single bus structure's cost is cheap than multiple bus structure.

Computer software, or just software is a general term used to describe the role that

computer programs, procedures and documentation play in a computer system. The term

includes:

users.

memory

devices on board mainboards or other types of integrated hardware carriers. dleware,

which controls and co-ordinates distributed systems.

systems, which interface with hardware to provide the necessary services for application

software. rogramming.

Software testing consists of various methods to test and declare a software product fit before

it can be launched for use by either an individual or a group. ware, which is an umbrella

term or container term for all utilities and application software that serve in combination for

testing a software package but not necessarily may optionally contribute to operational

purposes. As such, testware is not a standing configuration but merely a working

environment for application software or subsets thereof.

Software Characteristics

-out".

Assembler

Typically a modern assembler creates object code by translating assembly instruction

mnemonics into opcodes, and by resolving symbolic names for memory locations and other

entities. The use of symbolic references is a key feature of assemblers, saving tedious

calculations and manual address updates after program modifications. Most assemblers also

include macro facilities for performing textual substitution—e.g., to generate common short

sequences of instructions to run inline, instead of in a subroutine.

DEPARTMENT OF ECE


Assembly language

A program written in assembly language consists of a series of instructions—mnemonics that

correspond to a stream of executable instructions, when translated by an assembler, that can

be loaded into memory and executed.

Basic elements

Any Assembly language consists of 3 types of instruction statements which are used to

define the program operations:

Types of Addressing Modes

Each instruction of a computer specifies an operation on certain data. The are various ways of

specifying address of the data to be operated on. These different ways of specifying data are

called the addressing modes. The most common addressing modes are:

splacement addressing mode

To specify the addressing mode of an instruction several methods are used. Most often used

are:

a) Different operands will use different addressing modes.

b) One or more bits in the instruction format can be used as mode field. The value of the

mode field determines which addressing mode is to be used.

The effective address will be either main memory address of a register.

DEPARTMENT OF ECE


The Instruction Set Architecture

•superscalar processor --can execute more than one instructions per cycle.

•cycle--smallest unit of time in a processor.

•parallelism--the ability to do more than one thingat once.

•pipelining--overlapping parts of a large task to increase throughput without

decreasing latency.

Instruction Length

•Variable-length instructions (Intel 80x86, VAX) require multi-step fetch

and decode, but allow for a much more flexible and compact instruction set.

•Fixed-length instructions allow easy fetch and decode, and simplify

pipelining and parallelism.

All MIPS instructions are 32 bits long.

–this decision impacts every other ISA decision we make because it makes

instruction bits scarce.

Four principles of IS architecture

–simplicity favors regularity

–smaller is faster

–good design demands compromise

–make the common case fast

Instruction Set Architecture (ISA)

The Instruction Set Architecture (ISA) is the part of the processor that is visible to the

programmer or compiler writer. The ISA serves as the boundary between software and

hardware. We will briefly describe the instruction sets found in many of the microprocessors

used today. The ISA of a processor can be described using 5 catagories:

Operand Storage in the CPU

Where are the operands kept other than in memory?

Number of explicit named operands

How many operands are named in a typical instruction.

DEPARTMENT OF ECE


Operand location

Can any ALU instruction operand be located in memory? Or must all operands be

kept internaly in the CPU?

Operations

What operations are provided in the ISA.

Type and size of operands

What is the type and size of each operand and how is it specified?

Of all the above the most distinguishing factor is the first.

The 3 most common types of ISAs are:

1. Stack - The operands are implicitly on top of the stack.

2. Accumulator - One operand is implicitly the accumulator.

3. General Purpose Register (GPR).

Reduced Instruction Set Computer (RISC)

As we mentioned before most modern CPUs are of the GPR (General Purpose Register) type.

A few examples of such CPUs are the IBM 360, DEC VAX, Intel 80x86 and Motorola

68xxx. But while these CPUS were clearly better than previous stack and

accumulator based CPUs they were still lacking in several areas:

1. Instructions were of varying length from 1 byte to 6-8 bytes. This causes problems with the

pre-fetching and pipelining of instructions.

2. ALU (Arithmetic Logical Unit) instructions could have operands that were memory

locations. Because the number of cycles it takes to access memory varies so does the whole

instruction. This isn't good for compiler writers, pipelining and multiple issue.

3. Most ALU instruction had only 2 operands where one of the operands is also the

destination. This means this operand is destroyed during the operation or it must be saved

before somewhere.

DEPARTMENT OF ECE


OBJECTIVE TYPE

QUESTION

DEPARTMENT OF ECE


Q.1 In a virtual memory system, the addresses used by the programmer belongs to

(A) memory space. (B) physical addresses.

(C) address space. (D) main memory address.

Q.2 The method for updating the main memory as soon as a word is removed from the

Cache is called

(A) Write-through (B) write-back

(C) protected write (D) cache-write

Q.3 A control character is sent at the beginning as well as at the end of each block in

thesynchronous-transmission in order to

(A) Synchronize the clock of transmitter and receiver.

(B) Supply information needed to separate the incoming bits into individual

character.

(C) Detect the error in transmission and received system.

(D) Both (A) and (C).

Q.4 In a non-vectored interrupt, the address of interrupt service routine is

(A) Obtained from interrupt address table.

(B) Supplied by the interrupting I/O device.

(C) Obtained through Vector address generator device.

(D) Assigned to a fixed memory location.

Q.5 Divide overflow is generated when

(A) Sign of the dividend is different from that of divisor.

(B) Sign of the dividend is same as that of divisor.

(C) The first part of the dividend is smaller than the divisor.

(D) The first part of the dividend is greater than the divisor.

Q.6 Which method is used for resolving data dependency conflict by the compiler

itself?

(A) Delayed load. (B) operand forwarding.

(C) Pre fetch target instruction. (D) loop buffer.

Q.7 Stack overflow causes

(A) Hardware interrupt.

(B) External interrupt.

(C) Internal interrupt.

(D) Software interrupt.

Q.8 Arithmetic shift left operation

(A) Produces the same result as obtained with logical shift left operation.

(B) Causes the sign bit to remain always unchanged.

(C) Needs additional hardware to preserve the sign bit.

(D) Is not applicable for signed 2's complement representation.

DEPARTMENT OF ECE


Q.9 Zero address instruction format is used for

(A) RISC architecture.

(B) CISC architecture.

(C) Von-Neuman architecture.

(D) Stack-organized architecture.

Q.10 Address symbol table is generated by the

(A) memory management software.

(B) assembler.

(C) match logic of associative memory.

(D) generated by operating system

Q.11 The ASCII code for letter A is

(A) 1100011 (B) 1000001

(C) 1111111 (D) 0010011

Q.12 The simplified expression of (A+B) + C is

(A) (A + B)C (B) A(B + C)

(C) (C+A + B) (D) None of these

Q.13 The negative numbers in the binary system can be represented by

(A) Sign magnitude (B) I's complement

(C) 2's complement (D) All of the above

Q.14 ABCD - seven segment decoder / driver in connected to an LED display.

Which segments are illuminated for the input code DCBA = 0001.

(A)b, c (B) c, b

(C)a, b, c (D) a, b, c, d

Q.15 How many flip-flops are required to produce a divide-by-32 device?

(A)4 (B) 6

(C)5 (D) 7

Q.16 The content of a 4-bit register is initially 1101. The register is shifted 2 times to the

right with the serial input being 1011101.

What is the content of the register after each shift?

(A)1110, 0111 (B) 0001, 1000

(C)1101, 1011 (D) 1001, 1001

Q.17 How many different addresses are required by the memory that contain 16K

words?

(A)16,380 (B) 16,382

(C)16,384 (D) 16,386

Q.18 What is the bit storage capacity of a ROM with a 512' 4-organization?

(A) 2049 (B) 2048

(C) 2047 (D) 2046

DEPARTMENT OF ECE


Q.19 DMA interface unit eliminates the need to use CPU registers to transfer data

from

(A) MAR to MBR (B) MBR to MAR

(C) I/O units to memory (D) Memory to I/O units

Q.20 How many 128 x 8 RAM chips are needed to provide a memory capacity of

2048 bytes?

(A) 8 (B) 16

(C) 24 (D) 32

Q.21 Which of the following is a self complementing code?

(A) 8421 code (B) 5211

(C) Gray code (D) Binary code

Q.22 Which gate can be used as anti-coincidence detector?

(A) X-NOR (B) NAND

(C) X-OR (D) NOR

Q.23 Which of the following technology can give high speed RAM?

(A) TTL (B) CMOS

(C) ECL (D) NMOS

Q.24 In 8085 microprocessor how many I/O devices can be interfaced in I/O mapped

I/O technique?

(A) Either 256 input devices or 256 output devices.

(B) 256 I/O devices.

(C) 256 input devices & 256 output devices.

(D) 512 input-output devices.

Q.25 After reset, CPU begins execution of instruction from memory address

(A) 0101H (B) 8000H

(C) 0000H (D) FFFFH

Q.26 Which is true for a typical RISC architecture?

(A) Micro programmed control unit.

(B) Instruction takes multiple clock cycles.

(C) Have few registers in CPU. (D) Emphasis on optimizing instruction pipelines.

Q.27 When an instruction is read from the memory, it is called

(A) Memory Read cycle (B) Fetch cycle

(C) Instruction cycle (D) Memory write cycle

Q.28 Which activity does not take place during execution cycle?

(A) ALU performs the arithmetic & logical operation.

(B) Effective address is calculated.

(C) Next instruction is fetched.

(D) Branch address is calculated & Branching conditions are

checked.

DEPARTMENT OF ECE


Q.29 A circuit in which connections to both AND and OR arrays can be

programmed is called

(A) RAM (B) ROM

(C) PAL (D) PLA

Q.30 If a register containing data (11001100)2 is subjected to arithmetic shift left

operation, then the content of the register after 'ashl' shall be

(A) (11001100)2 (B) (1101100)2

(C) (10011001)2 (D) (10011000)2

Q.31 Which logic is known as universal logic?

(A) PAL logic. (B) NAND logic.

(C) MUX logic. (D) Decoder logic.

Q.32 The time for which the D-input of a D-FF must not change after the clock is

applied is known as

(A) Hold time. (B) Set-up time.

(C) Transition time. (D) Delay-time.

Q.33 How many memory chips of (128 x 8) are needed to provide a memory

capacity of 4096 x 16?

(A)64 (B) A B

(C)32 (D) None

Q.34 In addition of two signed numbers, represented in 2' s complement form

generates an overflow if

(A) A. B = 0 (B) A = 0

(C) 1 B A = Å (D) A + B = 1

Q.35 Addition of (1111)2 to a 4 bit binary number 'a' results

(A) Incrementing A (B) Addition of (F)H

(C) No change (D) Decrementing A

Q.36 In a microprocessor system, suppose. TRAP, HOLD, RESET Pin

got activated at the same time, while the processor was executing some

instructions, then it will first respond to

(A) TRAP (B) HOLD

(C) RESET (D) None

Q.37 Pseudo instructions are

(A) Machine instructions (B) Logical instructions

(C) Micro instructions (D) instructions to assembler.

Q.38 An attempt to access a location not owned by a Program is called

(A) Bus conflict (B) Address fault

(C) Page fault (D) Operating system fault

DEPARTMENT OF ECE


Q. 39 Dynamic RAM consumes ________ Power and ________ then the Static RAM.

(A) more, faster (B) more, slower

(C) less, slower (D) less, faster

Q.40 The flag register content after execution of following program by 8085

microprocessor shall be

Program

SUB A

MVI B, (01)H

DCR B

HLT

(A) (54)H (B) (44)H

(C) (45)H (D) (55)H

Q.41 Which flag of the 8085's flag register is not accessible to programmer

directly?

(A)Zero flag

(B)Carry flag

(C)Auxiliary carry flag

(D)Parity flag

Q.42 Cache memory works on the principle of

(A) Locality of data.

(B) Locality of reference

(C) Locality of memory

(D) Locality of reference & memory

Q.43 Which of the following is a Pseudo instruction?

(A) SPHL (B) LXI

(C) NOP (D) END

Q.44 A demultiplexer can be used as

(A)Encoder (B)Decoder

(C)Multiplexer (D)None of the above

Q.45 Excess-3 equivalent representation of (1234)H is

(A) (1237)Ex-3 (B) (4567)Ex-3

(C) (7993)Ex-3 (D) (4663)Ex-3

Q.46 Which of the memory holds the information when the Power Supply is switched

off?

(A) Static RAM (B) Dynamic RAM

(C) EEROM (D) None of the above

Q.47 Minimum no. of NAND gate required to implement a Ex-OR function is

(A)2 (B)3

(C)4 (D)5

DEPARTMENT OF ECE


Q.48 Which of the following interrupt is maskable?

(A)INTR (B)RST 7.5

(C)TRAP (D)Both (A) and (B)

Q.49 Which of the following expression is not equivalent to x?

(A) x NAND x (B) x NOR x

(C) x NAND 1 (D) x NOR 1

Q.50 Word 20 contains 40 Word 30 contains 50 Word 40 contains 60 Word 50 contains

70 Which of the following instructions does not, load 60 into the Accumulator

(A) Load immediate 60

(B) Load direct 30

(C) Load indirect 20

(D) both (A) & (C)

Q.51 An interrupt for which hardware automatically transfers the program to a specific

memory location is known as

(A) Software interrupt

(B) Hardware interrupt

(C) Maskable interrupt

(D) Vector interrupt

Q.52 Synchronous means _______

(A) At irregular intervals

(B) At same time

(C) At variable time

(D) None of these

Q.53 'n' Flip flops will divide the clock frequency by a factor of

(A)n2 (B) n

(C)2n (D) log (n)

Q.54 In DMA the data transfer is controlled by

(A)Microprocessor (B) RAM

(C)Memory (D) I/O devices

Q.55 The number of instructions needed to add a numbers an store the result in

memory using only one address instruction is

(A)n (B) n - 1

(C)n +1 (D) Independent of n

Q.56 Negative numbers cannot be represented in

(A)Signed magnitude form

(B)I's complement form

(C)2's complement form

(D)8-4-2-1 code

Q.57 Which of the following architecture is/are not suitable for realizing SIMD

(A)Vector Processor (B) Array Processor

DEPARTMENT OF ECE


(C)Von Neumann (D) All of the above

Q.58 In Boolean expression A+BC equals

(A)(A+B)(A+C) (B) (A'+B)(A'+C)

(C)(A+B)(A'+C) (D) (A+B)C

Q.59 A JK flip-flop can be implemented using D flip-flop connected such that

(A)D=JQ+KQ (B) D=JQ+KQ

(C)D=JQ+KQ (D) D=JQ+KQ

Q.60 An effective solution to the power consumption problem lies in using _______

transistors to implement ICs.

(A) NMOS (B) TTL shottky

(C) PMOS (D) both NMOS & PMOS

Q.61 Memory interleaving technique is used to address the memory modules in order to

have

(A) higher average utilization

(B) faster access to a block of data

(C) reduced complexity in mapping hardware

(D) both (A) & (B)

Q.62 In a multiprogramming system, which of the following is used

(A) Data parallelism (B) Paging concept

(C) L1 cache (D) None of the above

Q.63 Cycle stealing technique is used in

(A) Interrupt based data transfer

(B) Polled mode data transfer

(C) DMA based data transfer

(D) None of these

Q.64 Manipulation of individual bits of a word is often referred to as

(A) Bit twidding (B) Bit swapping

(C) Micro-operation (D) None of these

Ans. (A)

Q.65 Which of the following is not a characteristic of a RISC architecture.

(A) Large instruction set (B) One instruction per cycle

(C) Simple addressing modes (D) Register-to-register operation

Q.66 When CPU is not fully loaded, which of the following method of data transfer is

preferred

(A) DMA (B) Interrupt

(C) Polling (D) None of these

Q.67 Associative memory is some times called as

(A) Virtual memory (B) Cache memory

(C) Main memory (D) Content addressable memory

Q.68 BCD equivalent of Two's complement is

(A) nine's complement (B) ten's complement

DEPARTMENT OF ECE


(C) one's complement+1 (D) none of these

Q.69 PAL circuit consists of

(A) Fixed OR & programmable AND logic

(B) Programmable OR & Fixed AND Logic

(C) Fixed OR & fixed AND logic

(D) Programmable OR & programmable AND logic

Q.70 8085 microprocessor carryout the subtraction by

(A) BCD subtraction method

(B) Hexadecimal subtraction method

(C) 2‘s complement method

(D) Floating Point subtraction method

Q.71 CPU checks for an interrupt signal during

(A) Starting of last Machine cycle

(B) Last T-State of instruction cycle

(C) First T-State of interrupt cycle

(D) Fetch cycle

Q.72 During DMA acknowledgement cycle, CPU relinquishes

(A) Address bus only (B) Address bus & control bus

(C) Control bus & data bus (D) Data bus & address bus

Q.73 If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than

the output of the cascaded arrangement shall be of

(A) 4.8 KHz (B) 12 KHz

(C) 2 KHz (D) 8 KHz

Q.74 If the stack pointer is initialised with (4FEB)H, then after execution of Push

operation in 8085 microprocessor, the Stack Pointer shall be

(A) 4FEA (B) 4FEC

(C) 4FE9 (D) 4FED

Q.75 A more efficient way to organise a Page Table is by means of an associative

memory having

(A) Number of words equal to number of pages

(B) Number of words more than the number of pages

(C) Number of words less than the number of pages

(D) Any of the above

Q.76 If there are four ROM ICs of 8K and two RAM ICs of 4K words, than the address

range of Ist RAM is (Assume initial addresses correspond to ROMs)

(A) (8000)H to (9FFF)H (B) (6000)H to (7FFF)H

(C) (8000)H to (8FFF)H (D) (9000)H to (9FFF)H

Q.77 C B A Å Å is equal to A B C for

(A) A=0, B=1, C=0 (B) A=1, B=0, C=1

(C) A=1, B=1, C=1 (D) All of the above

DEPARTMENT OF ECE


Q.78 Gray code equivalent of (1000)2 is

(A) (1111)G (B) (1100)G

(C) (1000)G (D) None of these

DEPARTMENT OF ECE


ANSWER

1 2 3 4 5 6 7 8 9 10

C B B D B A C A D B

11 12 13 14 15 16 17 18 19 20

B A C A C A C B D B

21 22 23 24 25 26 27 28 29 30

A C C C C A B D A D

31 32 33 34 35 36 37 38 39 40

B A A C C D A B C A

41 42 43 44 45 46 47 48 49 50

C B D B B C C B D B

51 52 53 54 55 56 57 58 59 60

B B B D D C C A A D

61 62 63 64 65 66 67 68 69 70

C B C A A D D C A C

71 72 73 74 75 76 77 78

B D C D A C D A

DEPARTMENT OF ECE


INTERVIEW QUESTIONS

DEPARTMENT OF ECE


DEPARTMENT OF ECE


1.What is big endian and little endian format?

The name big endian is used when lower byte addresses are used for the more

significiant of the word. The name little endian is used for the less significiant bytes of

the word.

2.What is a branch instruction?

Branch instruction is a type of instruction which loads a new value into the program

counter.

3.What is branch target?

As a result of branch instructions , the processor fetches and executes the instruction

at a new address called branch target, instead of the instruction at the location that

follows the branch instruction in sequential address order.

4.What is a pointer?

The register or memory location that contains the address of an operand is called a

pointer.

5.Define Response time and Throughput.

Response time is the time between the start and the completion of the event. Also

referred to as execution time or latency.Throughput is the total amount of work done

in a given amount of time

6.Define device interface.

The buffer registers DATAIN and DATAOUT and the status flags SIN and SOUT are

part of circuitry commonly known as a device interface.

7.What is byte addressable memory?

The assignment of successive addresses to successive byte locations in the memory is

called byte addressable memory.

8.What is pipelining?

The overlapping of execution of successive instructions is called pipelining.

9.What is multiprogrraming or multitasking?

The operating system manages the concurrent execution of several application

programs to make the best possible uses of computer resources.this pattern of

concurrent execution is called multiprogrraming or multitasking.

DEPARTMENT OF ECE


10.What is text editor?

It is used for entering and editing application programs. The user of this program

interactively executes command that allow statements of a source program entered at a

keyboard to be accumulated in a file.

11.What is a compiler?

A system software program called a compiler translates the high-level language

program into a suitable machine language program containing instructions such as the

Add and Load instructions.

12.Define Bus?

A group of lines that serves as a connecting path for several devices is called a bus.

13.Define interrupt and ISR?

An interrupt is a request from an I/O device for service by the processor. The

processor provides the requested service by executing the interrupt service routine.

14.What are the steps in executing a program?

1.Fetch

2.Decode

3.Execute

4.Store

15.What are the registers generally contained in the processor?

MAR-Memory Address Register MDR-Memory Data Register

IR-Instruction Register,R0-Rn-General purpose Registers,PC-Program Counter

16.What is cache memory?

The small and fast RAM units are called as caches. When the execution of an

instruction calls for data located in the main memory, the data are fetched and a copy

is placed in the cache. Later if the same data is required it is read directly from the

cache.

17.What is guard bits?

DEPARTMENT OF ECE


Guard bits are extra bits which are produced during the intermediate steps to yield

maximum accuracy in the final results.

18.What is the advantage of non restoring over restoring division?

Non restoring division avoids the need for restoring the contents of register after

an successful subtraction.

19.How CSA speeds up multiplication?

It reduces the time needed to add the summands. Instead of letting the carries ripple

along the rows, they can be saved and introduced into the next row, at the correct

waited position.

20.What are the two techniques for speeding up the multiplication operation?

Bit Pair recoding

CSA

21.What are the two attractive features of Booth algorithm

It handles both positive and negative multipliers uniformly

It achieves some efficiency in the number of additions required when

the multiplier has a few large blocks of ones

22.What are the two approaches to reduce delay in adders

Fastest electronic technology in implementing the ripple carry logic design

Augmented logic gate network

23.What is the delay encountered for all the sum bits in n-bit binary

addition/subtraction logic unit?

The gate delays with and without overflow logic are 2n+2 and 2n respectively

Compare vertical organization and horizontal organization.

24.ertical organization Horizontal organization

1. Highly encoded schemes

2. Specify only a small number of control signals.

DEPARTMENT OF ECE


3. Operating speed is high. Minimally encoded schemes

Many resources can be controlled.

25.Name some register output control signals.

Pcout, MDRout, Zout, Offsetout, R0out, R1out, R2out, R3out, and TEMPout

26.What is control store?

The microroutines for all instructions in the instruction set of a computer are stored in

a special memory called the control store.

27.Define microroutine and microinstruction.

A sequence of control words corresponding to the control sequence of a machine

instruction constitutes the microroutine for that instruction, and the individual control

words in this microroutine are referred to as microinstructions.

28.What is microprogrammed control?

Microprogrammed control is a scheme in which control signals are generated by a

program similar to machine language programs.

29.What is mean by branch instruction.

A branch instruction is an instruction which replaces the contents of the PC with the

branch target address. This address is usually obtained by adding an offset X, which is

given in the branch instruction, to the updated value of the PC. The location following

a branch instruction is called a branch delay slot.

30.What is a deadlock

A deadlock is a situation that can arise when two units, A and B, use a shared

resource. Suppose that unit B cannot complete its task until unit A completes its task.

At the same time, unit B has been assigned a resource that unit A needs. If this

happens, neither unit can complete its task. Unit A is waiting for the resource it needs,

which is being held by unit b. at the same time, unit B is waiting for unit A to finish

before it can release that resource.

31.What are superscalar processors?

Several instructions start execution in the same clock cycle, and the processor

is said to use multiple issue. Such processors are capable of achieving an instruction

execution throughput of more than one instruction per cycle. They are known as

superscalar processors.

DEPARTMENT OF ECE


32.What is delayed branching?

A technique called delayed branching can minimize the penalty incurred as a

result of conditional branch instructions. The idea is simple. The instructions in the

delay slots are always fetched. Therefore, we would like to arrange for them to be

fully executed whether or not the branch is taken. The objective is to be able to place

useful instructions in these slots. If no useful instructions can be placed in the delay

slots, these slots must be filled with NOP instructions.

33.What is branch folding

The instruction fetch unit has executed the branch instruction concurrently

with the execution of other instructions. This technique is referred to as branch

folding.

34.What is structural hazard?

Structural hazard is the situation when two instructions require the use of a

given hardware resource at the same time. The most common case in which this

hazard may arise is in access to memory.

35.What are called stalls?

An alternative representation of the operation of a pipeline in the case of a

cache miss gives the function performed by each pipeline stage in each clock cycle.

The periods in which the decode unit, execute unit, and the write unit are idle are

called stalls. They are also referred to as bubbles in the pipeline.

36.What are instruction hazards?

The pipeline may also be stalled because of a delay in the availability of an

instruction. For example, this may be a result of a miss in the cache, requiring the

instruction to e fetched from the main memory. Such hazards are often called control

hazards or instruction hazards.

37.What is data hazard?

Any condition that causes the pipeline to stall is called a hazard. A data hazard

is any condition in which either the source or the destination operands of an

instruction are not available at the time expected in the pipeline. As a result some

operation has to be delayed, and the pipeline stalls.

38.What is lockup-free?

A cache that can support multiple outstanding misses is called lockup-free.

DEPARTMENT OF ECE


39.What is booting?

When the power is turned on the OS has to be loaded into the main

memory which takes place as part of a process called booting.To initiate booting a

tiny part of main memory is implemented as a nonvolatile ROM.

40.What is page frame?

An area in the main memory that can hold one page is called as page frame.

41. What is virtual memory?

Techniques that automatically move program and datablocks into the physical

main memory when they are required for execution are called as virtual memory.

42.What is virtual address?

The binary address that the processor used for either instruction or data called

as virtual address.

43.What is write miss?

During the write operation if the addressed word is not in cache then said to be

write miss.

44.Define miss rate?

It is the number of misses stated as a fraction of attempted accesses.

45. Define miss penalty?

The extra time needed to bring the desired information into the cache.

46. Define hit rate?

The number of hits stated as a fraction of all attempted access .

47. What is write-back or copy back protocol?

For a write operation using this protocol during write hit: the technique is to

update only the cache location and to mark it as updated with an associated flag bit,

often called the dirty or modified bit. The main memory location of the word is

updated later, when the block containing this marked word is to be removed from the

cache to make room for a new block. For a write miss: the block containing the

addressed word is first brought into the cache, and then the desired word in the cache

is overwritten with the new information.

DEPARTMENT OF ECE


48. Define cache line.

Cache block is used to refer to a set of contiguous address locations of some

size. Cache block is also referred to as cache line.

49. Define flash memory?

It is an approach similar to EEPROM technology. A flash cell is based on a

single transistor controlled by trapped charge just like an EEPROM cell.

50. What is cache memory?

It is a small, fast memory that is inserted between the larger, slower main

memory and the processor. It reduces the memory access time.

51. What are RIMMs?

RDRAM chips can be assembled in to larger modules called RIMMs. It can

hold upto 16 RDRAMs.

52. Differentiate static RAM and dynamic RAM?

Static RAM Dynamic RAM

They are fast They are slow

They are very expensive They are less expensive

They retain their state indefinitely They do not retain their state indefinitely

They require several transistors They require less no transistors.

Low density High density

53. What are SIMMs and DIMMs?

SIMMs are Single In-line Memory Modules. DIMMs are Dual In-line Memory

Modules. Such modules are an assembly of several memory chips on a separate small

board that plugs vertically into a single socket on the motherboard.

54. Define Memory Latency?

It is used to refer to the amount of time it takes to transfer a word of data to or

from the memory.

55. What is a word line?

In a memory cell, all the cells of a row are connected to a common line called

as word line.

DEPARTMENT OF ECE


56. What is MMU?

MMU is the Memory Management Unit. It is a special memory control circuit

used for implementing the mapping of the virtual address space onto the physical

memory.

57. What is meant by handshake?

Handshake is used between the master and the slave for controlling data

transfers on the bus.

58. What is known as cycle stealing?

The processor originates most memory access cycles, the DMA controller can

be said to ―steal‖ memory cycles from the processor. Hence ,this interweaving

technique is usually called cycle stealing.

59. What is known as multitasking?

Multitasking is a mode of operation in which a processor executes several user

programs at the same time.

60. What is known as a debugger?

System software usually includes a program called a debugger, which helps

the programmer find errors in a program.

Documents

Placement Hand Book