EXTERNAL USE

NAS/SSSC Spring Meeting April 2, 2009

NANOMANUFACTURING TECHNOLOGY

2EXTERNAL USE

Moore's Law and Transistor Scaling

§ Decrease transistor dimensions by k, drop voltage by k§ Circuit area reduced by 1/k2, speed increased by k§ Power per circuit reduced by 1/k2, power per area constant

1T

1975 1985 1995 2005 2015

Bit

s/C

hip

1K

1M

1G

0.2 0.4 0.6 0.8

Technology (um)

DS

P A

A B

atte

ry H

ou

rs

100

50

0

Video

Speech

0

Year

0.25um

90nm

45nm

1um

3EXTERNAL USE

Moore's Law and Transistor Cost

1B

1M

1K

1

1968 1973 1978 1983 1988 1993 1998 2003 2008

(Source: G. Moore, ISSCC 2003)

Number ofTransistors(x Billions)

Cost perTransistor(Nano $)

4EXTERNAL USE

A Recent Product Enabled by Nanoelectronics

2006 ~ $200 2020 = 5¢*

† Memory cost only

* Extrapolating memory cost reduction factor over last 30 years and display cost/area over last 10 years

1975 = $1B†

x ~ 1000

IBM 370/195

5EXTERNAL USE

Cost Per Function

Cost

Function

Cost

Function

Process Cost

Area

Process Cost

Area

(Good) Function

Area

(Good) Function

Area

6EXTERNAL USE

Cost Per Function: VLSI Technology

Cost

Function

Cost

Function

Process Cost

Area

Process Cost

Area

(Good) Function

Area

(Good) Function

AreaScaling has been the primary cost driver for ICs – but not at an overcompensating increase in process cost/area

193nm SADP193nm SADP

7EXTERNAL USE

PREPARATION PATTERNTRANSFER

PROCESS CONTROL/DFM

PRODUCTIVITY

Etch§ High Aspect Ratio Etch§ Critical Etch§ Damascene Etch§ Trimming

Patterning Films§ CVD Hardmask§ CVD ARC/Spin-on ARC§ PVD HardmaskPlanarity Enhancement§ Ecmp§ Real-Time Profile Ctrl§ Fixed-Abrasive CMP

Patterning Is More Than Printing

§ Automation§ eDiagnostics

§ Material Handling§ Reticle Management

§ CD SEM§ OPC Qualification§ APC

§ Defect Inspectionand Review§ Overlay

§ Scanner§ Track§ Mask/Mask Etch§ Photoresist§ K1 reduction

PRINTING

8EXTERNAL USE

Self Aligned Double Patterning

LER = 3.1nm (3σ)

LER = 1.5nm (3σ)

9EXTERNAL USE

Progress Through Materials Innovation

Source: Intel – ISTAC Meeting 2-2004

10EXTERNAL USE

Integrated Hi-k/Metal Gate CMOS

Metal Gates for nMOS and pMOS

Hi-K layer for low leakage

High mobility interface layerGraded

transition layer

11EXTERNAL USE

Require Nanoscale Resolution and Throughput

35nm void30nm defect

80nm 120nm 160nm 220nm 270nm

New ToolExisting Tool

Throughput (300mm WPH)

Pixel = 80nm 120nm 160nm 220nm 270nm

New ToolExisting Tool

Throughput (300mm WPH)

Pixel =0

2000

4000

6000

8000

10000

12000

14000

16000

18000

1996 1998 2000 2002 2004

Defects Reviewed Per Day at a Leading Fab

12EXTERNAL USE

Two Key Semiconductor Market Trends

§ Accelerated consolidation of wafer manufacturers– Foundries vs. IDMs– Memory oversupply– Process R&D costs

§ Fewer product families aggressively follow Moore's law– Application drivers– Developing economies– Performance compromises– Design costs

FeatureSize

Year

Analog

Consumer Logic

NAND, DSPs, µProcessors, GPUs

DRAM

Industry: Scaling Trends

Semiconductor content in electronics, units and transistors all continue to increase but:

13EXTERNAL USE

European Commission, Nanotechnology Innovation for Tomorrow’s World, Research DG, 2004.

Promise of Nanotechnology

14EXTERNAL USE

Nanomanufacturing TechnologySmall features on a large production scale

Scale Up?

Placing a nanotube?

AdditionalInnovation

More Than Nanofabrication – Repeatable, Robust, Reliable, Controllable and Cost Effective

15EXTERNAL USE

Flat Panel Display (LCD) Manufacturing

> 20% Bigger (HD)TV Every Year for the Same Price

0

20

40

60

80

100

120

1992

1993

1994

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

LCD Industry Revenue ($B) Production Cost per Area (k$/m2)

0.1

1

10

100

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

200420042020””~$1000~$1000

200420042020””~$1000~$1000

200820084242”” ~$1000~$1000

200820084242”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

0.1

1

10

100

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

200420042020””~$1000~$1000

200420042020””~$1000~$1000

200820084242”” ~$1000~$1000

200820084242”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

0.1

1

10

100

1995

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005

2006

2007

2008

2009

2010

200420042020””~$1000~$1000

200420042020””~$1000~$1000

200820084242”” ~$1000~$1000

200820084242”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

2011 2011 6060”” ~$1000~$1000

16EXTERNAL USE

Courtesy Sharp

Cost

Function

Cost

Function

Process Cost

Area

Process Cost

Area

(Good) Function

Area

(Good) Function

Area

Cost Per Function: Flat Panel Displays

Cost per area tends to be an equivalent or predominant factor in applications other than VLSI

Applied PECVD 5.7

AKT-PIVOT™ 55KV PVD

17EXTERNAL USE

1600370x470400x500

3500 / 4300 / 4300A550x650600x720620x750

5500/5500A680x880730x920

10K1000x1200

15K / 15KA1100x12501200x1300

40K / 40KA1870x22001950x2250

41,140 cm2(1.52 from 25 K)

ModelSubstrate Size (mm)

Gen 2 Gen 3 / 3.5 Gen 4 Gen 5 Gen 5 Gen 7 / 7.5

System Layout

Substrate Area

2,000 cm2(1.00)

4,650 cm2(2.33 from 1600)

6,716 cm2(1.44 from 4300)

12,000 cm2(1.79 from 5500)

15,600 cm2(1.30 from 10K)

ACLS ACLS

2/ '93~ 4/ '95~ 1/ '00~ 8/ '01~ 6/ '02~ 7/ '04~1st Release

Gen 8

ACLS

50K 2160x2460

53,136 cm2(1.21 from 40 KA)

2006

Gen 5.5

19,500 cm2(1.25 from 15 K)

20K 1300x1500

ACLS

8/ '04~

ACLS

25K / 25KA1500x1800 1500x1850

27,750 cm2(1.78 from 15 K)

5/ '03~

Gen 6

Flat Panel Display Equipment – PECVD

Gen 10 = 60nm uniformity over ~ 10Gen 10 = 60nm uniformity over ~ 101919 nmnm22 area at 50spharea at 50sph

Gen 10 AKT-90K PECVD

18EXTERNAL USE

Nanotechnology Opportunities In Energy

EnergyConversion

EnergyStorage

EnergyConservation

Technology to improve performance, form and cost

19EXTERNAL USE

Architectural Coated Glass

Cost Reductions Achieved with Low-e Coatings

Low-e Coatings

Phoenix

San Antonio

700 An

nu

al En

ergy E

xpen

ditu

res ($)300

500

400

600

Cost Reductions Achieved with Low-e Coatings

Low-e Coatings

Phoenix

San Antonio

700 An

nu

al En

ergy E

xpen

ditu

res ($)300

500

400

600

700 An

nu

al En

ergy E

xpen

ditu

res ($)300

500

400

600

2000 ft2 house with 300 ft2 of windows

20EXTERNAL USE

Increasing Adoption of Coated Glass

Savings from 2007 Global Output ~ 36,000 Bbl/day†

† Equivalent to 12 oil wells or 18Mt CO2

Bird’s Nest Stadium (Beijing)Shanghai SYP Engineering Glass Co.

10,000m2 of high performance Low-E glass

House of Sweden (Washington DC)AGC Flat Glass

5500m2 Stopray® Elite and Stopray® Carat glass

Main Triangle Building (Frankfurt)Guardian Industries

15,000m2 SunGuard® Solar Control and Low-E coated glass

Burj Dubai (UAE)Guardian Industries100,000m2 SunGuard® Solar Control and Low-E coated glass

21EXTERNAL USE

Large Area Glass Coating Systems

§ Glass Substrate is ~ 2.6 m x 3.6 m– Uniformity Spec of +/- 1% on 275 nm film (10 layer Triple Low e stack)

§ 18 Chamber System ~ 90m: one panel every 20 sec – Output per month ~ 7Mft2

22EXTERNAL USE

Electrochromic "Smart Glass"

Key Requirements for Market Adoption:§ Performance: Energy efficiency, lifetime§ Form: Color selection, match non-EC panes, pane-to-pane

consistency, large size panes, on-off§ Cost: At least comparable to Low-e glass + shadesTypical Structure§ ~ 10 metal/dielectric layers, most < 100nm thick (up to ~ 500nm)

Images courtesy of Sage Electrochromics

23EXTERNAL USE

Primary Commercial Solar PV Markets

Today’s Installed Base 5.4 GW

Residential Commercial Rooftop Utility Scale

Market Drivers§High utility bills§Availability of incentives§Green choice

Today’s Installed Base 4.2 GW

Market Drivers§High utility bills§Unpredictable cost §Under-utilized urban space

Today’s Installed Base 5.4 GW

Market Drivers§Solar economics§Favorable tax policy§Unpredictable fuel and carbon costs

Source: Navigant 2007, 2008, Marketbuzz 2008

Total new PV installations in 2008 ~4.1 GW

24EXTERNAL USE

Crystalline SiliconPreferred for residential applications

Thin FilmPreferred for large scale applications

Mainstream PV Technologies

Common focus to drive down cost per watt

25EXTERNAL USE

Solar Learning Curve: Module Cost/Watt

$1

$10

$100

1 10 100 1,000 10,000 100,000 1,000,000

Cumulative Production (MWp)

Mo

du

le P

rice

(20

06 $

/Wp

)

Historical Prices (cSi dominated)

1980

2007

$1.00/W @ >100 GW

c-Si

Source: Adapted from NREL

Polysiliconshortage

Production line size (Megawatts per Year)

Lines Per Factory

0.5(1980)

2

5(2000)

3

50(2005)

4

100(2010)

10

$1.00/W @ <20 GW

Thin Film 2007

> $1 per kWh equivalent PV electricity cost=

Cost

Watt

Cost / m2

Watt / m2=

Cost

Watt

Cost / m2

Watt / m2=

Cost

Watt

Cost / m2

Watt / m2

26EXTERNAL USE

Crystalline Silicon PV Value Chain

Poly-SiFeedstock

Poly-SiFeedstock

IngotProduction

CellProduction

ModuleAssembly

Distribution,Integration &Installation

MC

Cz

Wafer orSheet

Production

27EXTERNAL USE

Improve Material Efficiency: Thin Wafers

Cost / m2

Watt / m2

* Cost assumes fixed silicon costs at $55/kg and constant efficiency

Kerf Loss

Wafer Thickness

$0.52 / Wp*$0.46 / Wp*

$0.42 / Wp*

$0.34 / Wp*

28EXTERNAL USE

High Productivity ARC/Passivation

0

1000

2000

3000

4000

Nitride CompositeStack

Lif

etim

e (µ

Sec

)Applied ATON™ PVD

Cost / m2

Watt / m2

§ Yield§ Thruput§ Uptime§ Thin

wafers§ COC

§ Efficiency§ Uniformity

§ Low Interface State Density

§ Optically Transparent

§ Stable After Contact Firing

29EXTERNAL USE

Thin Wafer Processing

30EXTERNAL USE

Thin Film PV Value Chain

CellProduction

(Si, CdTe, CIS)

ModuleAssembly

Distribution,Integration &Installation

Wafer orSheet

Production

10.000 keV

139 flexi-solar 11/29/2007

FOV: 200.0 µm 50.0 µm