PICe-FRM26 B Manual - DAQ SYSTEM

PCIe-FRM26_B Users Manual (Rev 1.1)

-1- http://www.daqsystem.com

PCIe-FRM26_B User’s Manual

Windows, Windows2000, Windows NT and Windows XP are trademarks of Microsoft. We acknowledge that the

trademarks or service names of all other organizations mentioned in this document as their own property.

Information furnished by DAQ system is believed to be accurate and reliable. However, no responsibility is assumed by DAQ

system for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or copyrights of DAQ system.

The information in this document is subject to change without notice and no part of this document may be copied or

reproduced without the prior written consent.

Copyrights 2005 DAQ system, All rights reserved.



-- CONTENTS –

1. Introduction

2. PCIe-FRM26_B

2.1 FPGA Block Diagram

2.2 Camera Link

2.3 Camera Link and PCIe-FRM24

3. PCIe-FRM26_B Board Description

3.1 PCIe-FRM26_B Device Layout

3.2 Device Functions

3.3 Connector Pin-out

3.3.1 J5(SDR26) Connector



3.3.4 J1 Connector

3.3.5 J2 Connector

3.3.6 J7 Connector

4. Installation

4.1 Hardware Installation

4.1.1 Product Contents

4.1.2 Installation Process

4.2 Drive Installation

5. Sample Program

5.1 Functions related to Image Frame

5.2 Functions related to UART

5.3 Functions related to CC

Appendix

A.1 General Specification

A.2 Dimensions

Reference



1. Introduction The PCIe-FRM26_B is an image acquisition device that supports cameras compatible with thre

e Base configuration camera links. The PCIe-FRM26_B acquires the image in real time and tran

smits it to the host PC. Easy installation and fast image transfer are the right equipment to meet

the needs of low cost and high efficiency industries.

The sample program provided by the DAQ System is provided in a source form so that the A

PI provided for using the board can be briefly tested, so that it can be modified and used by th

e user. Please refer to Chapter 5 Sample Program for a detailed explanation.

The SDR 26-pin connector can be connected to a Camera Link compatible camera and consist

s of channels 0-2 from the bottom connector (J8). In addition, each SDR connector provides four

pairs of RS-422 signal lines and four CC (camerc Control) signals. Please refer to 3.3 Connector

Pin-Out for a detailed explanation.

It is a board that transmits image frames taken with standard Camera-link camera to PC by PCI

Express 4x interface method. The operation of the board is controlled by the API, and the following

figure shows the interlocking operation of the board.

[Figure 1-1 PCIe-FRM26_B Board usage example]

In [Figure 1-1], PCIe-FRM26_B is installed in PCI Express slot in PC and receives image frame from

camera through Camera-Link standard interface. The transmitted data is transferred to the application

program through the PCI Express 4x interface.



[Features of PCIe-FRM26_B]

Supports 3 Base Configuration Camera Link

Supports Area Scan Camera

Supports CC1/CC2 Trigger

PCI Express 4x Interface

Supports 2.5GT/s Per lane

Acquisit ion pixel clock rates up to 85MHz

UART(Data Bit 8, 1 start, 1 stop, No parity, 600 /19200/38400/57600/115200bps)

Windows XP/7/8/10 (32/64bit)

Windows Application Programming Interface(DLL)

[Application]

Image Acquisit ion(Pattern, Particles etc.)

Inspection equipment (Sensor, Semiconductor, Device etc.)

Surveil lance security Solution

Black and White, Color Image Display

Medical Image Capture (X-ray, Supersonic etc.)



2. PCIe-FRM26_B

2.1 FPGA Block Diagram

As shown in the figure below, the overall control of the PCIe-FRM26_B is handled by the FPGA

Core Logic. Main functions include Frame Data reception, Camera Control signal and UART

function.

These functions are performed using the API on the PC through the PCI Express 4x interface.

PCI Target

/ Master

PCI Express

4x BUSLocal Bus

Address

Data(Mem,I/O)

Reserved

(0x00 ? 0x5F)

Reserved

(0x70 ? 0xAF)

UART

(0x60)

Camera Link(LVDS)

(0xC0)

Interrupt controller

DIO

(0xD0)

Ext. Address, Data, Control

Local BUS

Interrupt

Controller

(0xb0)

INT sources in Chip

IO Decoder

MEM Decoder

To each IO

Module

PCIe-FRM26_B INTERNAL BLOCK - FPGA

From Ext.

CLOCK syn.

MEM Decoder

BUS Mux

Reserved

(0xE0 ? 0xFF)

[Figure 2-1. PCIe-FRM26_B Function Block Diagram]

FPGA core logic is programmed using JTAG, and the logic program is stored in FPGA Program

Logic and loaded when power is turned on.



2.2 Camera Link

Camera Link is a communication interface for use in a vision application development. In the

past, the camera manufacturer and Frame Grabber manufacturers use their own standard

connectors and cables. This has caused a lot of confusion and increased costs to users. In order

to eliminate this confusion and increase the data rate and data transmission trouble, the

specifications of Camera Link interface have been made to the regulations of cable or connector

assembly specifications, transfer speed, transfer method at the meeting of camera makers and

Frame grabber manufacturers.

Currently, many digital video solution use the LVDS (Low Voltage Differential Signal)

communication as defined RS-644. LVDS is a way to improve the existing RS-422 that had

intractable cable and transmission speed limit. RS-644 LVDS was the Camera Link standard. The

LVDS can be transferred the data at high speed using low voltage swing differential signal

Differential Signal. This is compared with the existing single-ended signal (Single-ended Signal)

using one of the lines, the differential signal transmits the signal using two complementary lines.

Such a transfer is characterized by excellent noise immunity, low power consumption, large in-

phase voltage transmission to refer only to the data transfer on the ground, however Single-ended

system is impossible.

Camera Link has multiple configuration with depending on the amount of data to be transferred.

Base Configuration consists of 28 bits, including a 24-bit pixel data and 3-bit video sync signal

lines of the Data Valid, Frame Line Valid, Line Valid, one reserved signal line, and can transmit

2.04Gbit / s (256MB / s). Medium Configuration can be transmitted the 48bit video signal to

4.08Gbit/s(510Mb/s), Full Configuration can be transmitted the 64bit video signal to

5.44Gbit/s(680MB/s). Camera Link requires two cables to transfer more than Medium

Specifications.

Transmitter part is converted to LVDS data stem’s 4/8/12 from 28/48/64 bit CMOS / TTL data

only. Converted signal is transmitted to MDR Cable in accordance with the Transmit Clock signal,

the opposite Receiver will be converted into parallel LVDS data of 28/48/64 bits of CMOS / TTL

according to the Receive Clock signal from 4/8/12 LVDS data. This Channel Link technology can

immediately take advantage of the low cost chip-set because easy to learn and easy to transplant.

Camera Link Interface includes Base Configuration, Medium Configuration, Full Configuration.

Base Configuration is used 4 RS-644 LVDS pairs for controlling the Transmitter/Receiver and

Camera like Figure 2-2, is used for communication between the camera and the frame grabber.

Transferred the data from serial 26-Pin MDR Cable, is used to change 28-bit parallel image data at



the Receiver part of Frame Grabber.

[Figure 2-2. Base Camera Link Block Diagram]



2.3 Camera Link and PCIe-FRM26_B

PCIe-FRM26_B supports Camera Link Base Configuration. Base Configuration consists of 4

LVDS signal lines that serialize 28 bit parallel signals including 24 data bits and 4 enable signals

Frame Valid, Line Valid, Data Valid, and a spare, and one LVDS signal line to synchronize with

camera, Asynchronous serial communication for communicating with the camera, including four

CC (Camera Control) signals. A total of eleven LVDS signal lines, including two LVDS lines, are

transmitted over one SDR cable.

The transmitted signal is deserialized the 12 video LVDS serial signals into 64-bit parallel video

signals and control signals (Frame Valid, Line Valid, Data Valid, and a spare) for each specification

through the Channel Link chip in PCIe-FRM26_B. In addition, a clock signal is generated by one

LVDS for synchronizing the signal between the camera and the PCIe-FRM26_B, and the

remaining camera control signals and communication signals are converted into a general TTL

signal level.

CCx+

CCx-

Camera Control

Above picture is a Camera Control output circuit from PCIe-FRM24_B board to Camera for the

specific control of the Camera-link Cable.

The PCIe-FRM24_B board has four differential digital outputs. Each output is mapped by Digital

output. Below picture[Figure 2-3] display that each bit position set.



CC1+

CC1-

CC_D0

CC2+

CC2-

CC_D1

CC3+

CC3-

CC_D2

CC4+

CC4-

CC_D3

[Figure 2-3. Camera Control LVDS Digital Output Circuit]

The figure below shows a circuit that uses the serial input signal input through the camera-link

cable as a general input on the PCIe-FRM26_B board.

[Figure 2-4. Serial Communication LVDS Digital Output Circuit]



3. PCIe-FRM26_B Board Description

Each important board function will be briefly explained. Please refer to the parts specification for

detailed function..

3.1 PCIe-FRM26_B Device Layout

PCI Express 4x Interface

FPGA

U16U23

U8

U19

U10

J7

J4

D11D12D13D14

J1U2

U3

U11

U22

U15

U18

D1

DAQ systemwww.daqsystem.com

PCIe-FRM26_BRev. A

D2D3D4D5

U20

ON

1 2

J2J5

J8

J6

U9

U12U13

U4

U6U7

J3

U1

U14

U6

10

0

J9

[Figure 3-1. PCIe-FRM26_B Device Layout]

The board has eight LEDs, each of which is described below..

D1 : When the board finishes the configuration and is ready for operation, it is turned on.

D2 ~ D5 : For Test

D11 ~D14 : Lights up when Lane (0 ~ 3) is normal with PCI Express 4 Lane Status Indicator..



3.2 Main device functions

(1) SDR-26 Connecter : J5, J6, J8

Camera Link Base Connector

(2) LVDS Link : U4, U6, U7, U9, U12, U13, U16, U19, U20

Receive an image frame.

(3) FPGA : U8

All functions of the board are controlled through this FPGA Logic.

(4) PCI Express Chipset : U23

PCI Express Bridge.

(5) Regulator : U1, U2, U14

It supplies the power used by the board..



3.3 Connector Pin-out

The connectors and jumpers used in PCIe-FRM26_B are described. The main connectors are

SDR 26pin connectors J5(Channel 2) and J6(Channel 1), J8(Channel 0) connectors for Camera

Link connection.

[Figure 3-2] shows the board, external bracket, and connection connector.

3

109876

12

54

191817161514

13121124

23222120

2625

3

109876

12

54

191817161514

13121124

23222120

2625

3

109876

12

54

191817161514

13121124

23222120

2625

[Figure 3-2. PCIe-FRM26_B Front View]

J5

J6

J8




The figure below shows the pin map of the J5 connector of the board to be used when

using Base Configuration Camera Link. All pin specifications are input / output based on the

Camera link standard. For details, refer to the Camera Link standard document.

3

10

9

8

7

6

1

2

5

4

19

18

17

16

15

14

13

12

1124

23

22

21

20

Inner shield Inner shield

26

25

ZDRRX-

ZDRTX+

ZCLK-

Z3-

Z2-

Z1-

Z0-

Inner shield

Frame Grabber

ZDRRX+

ZDRTX-

ZCLK+

Z3+

Z2+

Z1+

Z0+

Inner shield

ZCC4-

ZCC3+

ZCC2-

ZCC1+

ZCC4+

ZCC3-

ZCC2+

ZCC1-

[Figure 3-3. PCIe-FRM26_B J5 Connector Pin-out]



[Table 1. J5 Connector Description]

Pin Signal Name Description Remark

1 Inner Shield Cable shield

2 ZCC4- Camera Control output 4-

3 ZCC3+ Camera Control output 3+

4 ZCC2-- Camera Control output 2-


6 ZDRRX+ Serial to Frame grabber +

7 ZDRTX- Serial to Camera-

8 Z3+ Camera link LVDS receive data3 +

9 ZCLK+ Camera link LVDS receive clock +




13 Inner Shield

14 Inner Shield





19 ZDRRX- Serial to Frame grabber-

20 ZDRTX+ Serial to Camera+

21 Z3- Camera link LVDS receive data3-

22 ZCLK- Camera link LVDS receive clock-




26 Inner Shield

(Note) For more information, refer to Camera Link Standard Specification.







3

10

9

8

7

6

1

2

5

4

19

18

17

16

15

14

13

12

1124

23

22

21

20


26

25

YDRRX-

YDRTX+

YCLK-

Y3-

Y2-

Y1-

Y0-

Inner shield

Frame Grabber

YDRRX+

YDRTX-

YCLK+

Y3+

Y2+

Y1+

Y0+

Inner shield

YCC4-

YCC3+

YCC2-

YCC1+

YCC4+

YCC3-

YCC2+

YCC1-







2 YCC4- Camera Control output 4-

3 YCC3+ Camera Control output 3+

4 YCC2-- Camera Control output 2-


6 YDRRX+ Serial to Frame grabber +

7 YDRTX- Serial to Camera-

8 Y3+ Camera link LVDS receive data3 +

9 YCLK+ Camera link LVDS receive clock +




13 Inner Shield

14 Inner Shield





19 YDRRX- Serial to Frame grabber-

20 YDRTX+ Serial to Camera+

21 Y3- Camera link LVDS receive data3-

22 YCLK- Camera link LVDS receive clock-




26 Inner Shield




3.3.3 J8(MDR26) Connector




3

10

9

8

7

6

1

2

5

4

19

18

17

16

15

14

13

12

1124

23

22

21

20


26

25

DRRX-

DRTX+

RxCLKIN-

RxIN3-

RxIN2-

RxIN1-

RxIN0-

Inner shield

Frame Grabber

DRRX+

DRTX-

RxCLKIN+

RxIN3+

RxIN2+

RxIN1+

RxIN0+

Inner shield

CC4-

CC3+

CC2-

CC1+

CC4+

CC3-

CC2+

CC1-







2 CC4- Camera Control output 4-

3 CC3+ Camera Control output 3+

4 CC2-- Camera Control output 2-


6 DRRX+ Serial to Frame grabber +

7 DRTX- Serial to Camera-

8 RxIN3+ Camera link LVDS receive data3 +

9 RxCLKIN+ Camera link LVDS receive clock +




13 Inner Shield

14 Inner Shield





19 DRRX- Serial to Frame grabber-

20 DRTX+ Serial to Camera+

21 RxIN3- Camera link LVDS receive data3-

22 RxCLKIN- Camera link LVDS receive clock-




26 Inner Shield




3.3.4 J1 Connector

J1 is a Joint Test Action Group (JTAG) connector used to update the board's FPGA program.

Do not use it when operating the board normally.

3.3.5 J2 Connector

The PCIe-FRM26_B board is designed to use up to four PCIe-FRM26_B boards

simultaneously in a single system (PC). Each board can be set via the 4-pin DIP switch

(SW1) in the board.

1

ON

OFF

2

[Figure 3-6. J2 Switch]

[Table 4. J2 Description]

1 2 Description

OFF OFF Board Number 0

ON OFF Board Number 1

OFF ON Board Number 2

ON ON Board Number 3

3.3.6 J7 Connector (2Pin Header, 2.54mm)

3.3V external DC power connector. It is a power source for FPGA installation and is not

normally used.



4. Installation

Before installing the board, make sure that the package contents are correct.

4.1 Hardware Installation

4.1.1 Product Contents

① PCIe-FRM26_B Board

② CD (Driver/Manual/API/Sample Source etc.)

4.1.2 Installation Process

① Turn off the PC power.

② Remove the computer cover using the instructions from the computer manual.

③ Insert the board empty PCI Express slot as soon as possible to close the CPU.

④ Remove the blank metal plate located at the back of the selected slot. Keep the remo

ved screw to fasten the board after installation.

⑤ You should try number 3 in case of multi-board.



4.2 Driver Installation

The board should be used in Windows 2000 SP4 or later, or Windows XP SP1 or later. First,

turn off the PC, insert the PCIe-FRM24_B board into the PCI Express slot, and turn on the PC.

When the "Start New Hardware Wizard" window opens as shown below, select the following and

click the Next button.

PCIe-FRM26_B recognizes each Base Configuration port as a driver. That is, as shown in the

figure below, it is recognized as 3 devices and the installation process is performed 3 times.



1. Select the Driver folder from the enclosed CD and click the Next button.



2. Click the Next button.

It indicates that the installation processor is proceeding as shown below.



3. When the installation is complete, check that the driver is installed normally as follows.

4. Confirm that DAQ System -> "PCIe-FRM26" is installed in My Computer -> Properties ->

Hardware -> Device Manager

The above picture shows a screen where the PCIe-FRM26_B board is normally installed in the

PC.

Important Notice : After installation, you should re-boot the system for the proper operation.



5. sample Program

The TestApp folder on the CDROM supplied with the board provides a sample program "FrmTest"

for easy use of the board. First, "FrmTest.exe", which is one of the executable files, displays frame

data in hexadecimal value and stores it in memory or hard disk to utilize the frame data required by

the developers. It is an executable file that shows the screen easily.

In order to test the sample program, the driver of the board must first be installed. The sample

program is provided in source form so that the API provided for using the board can be briefly tested,

so it can be modified and used by the user.

5.1 Functions related to Image Frame

[Figure 5-1. Run sample program "FrmTest.exe"]

To use the above sample program, you need an API (Application Programming Interface). The API

is provided in the form of a "DLL", and an import library and a header file are required for

compilation. All the files listed above are included in the CDROM you provide. To run the sample



program normally, the API DLL (PCI_FRM26B.dll) must be in the executable file folder, the Windows

system folder, or the folder specified by the Path environment variable.

In case of multi-board, two execution programs must be opened at the same time. When the

program is closed, the remaining program operation is stopped. You must run Device init and Start

again.

Sample program execution sequence is as follows.

1. Get B'd # to determine the number of the board installed on the board

2. Select the board number for Board #.

3. Open Device Init Set the frame size to the specified resolution. (1024x768 setting)

4. Video0 ~ Video2: Start Start by selecting the number that matches the Base port you want to

use.

5. Get Resolution Get2Set View (Still) or Auto View (Movie)

6. DE Use Depending on the sensor, the Data Valid signal may not be required.

The description of each menu bar is as follows. The menu bar, which is not described here, is

an unused function.

(1) “Board #” selection

Four boards can be selected. Three devices are allocated per port on one board.

A total of 12 devices can be connected.

(2) “Open” button

Start the device of the selected board.

(3) “Close” button

Close the device of the selected board.

(4) “Device Init” button

Initialize the image frame function. It is performed only once when the power is first applied..



(5) “Init ” button

It initializes a LVDS and UART.

(6) “Video 0 F/R”

It displays the frame rate per second.

(7) “Start” button

It starts transmission of images with "Start" and "stop" Toggle buttons.

(8) “View” button

The image frame stored on the board is read to the PC. If the image frame is not stored on

the board, you have to wait until the save is completed.

"Auto View": Show the video as checked.

(9) “Save” button

Clicking on the box will save the image data as a binary file in frame units.

(10) “Get Res.” button

It displays the resolution of the input image.

(11) “Get2Set.” button

It shows in the top column to set the input image resolution by “Get Res”.

(12) “RGB/YUV” selection

It selects RGB or YUV image signal.

(13) “DE Use” selection

It selects the Data Valid signal.

(14) “cc Out”

It displays the CC value of the corresponding bit. Only the upper bits are valid with a



32 bit value.

Ex) When f000 is written, it becomes CC alternate output. If it is 0, it becomes Digital Out.

bit0 (CC1 configure) = "0": digital out1 / "1": alternate (Trigger1 output)

bit1 (CC2 configure) = "0": digital out2 / "1": alternate (Trigger2 output)

bit2 (CC3 configure) = "0": digital out3 / "1": Reserved

bit3 (CC4 configure) = "0": digital out4 / "1": Reserved

5.2 Functions related to UART

(1) “Open” selection

Normally UART Get is blocked and then clicked to open UART Get (For test)

(2) “UART” selection

It selects 9600, 19200, 38400, 57600, 115200 Baud Rate.

(3) “UART Send” button

It sends UART data in the above column..

(4) “UART Get” button

It gets data from the UART buffer.

(5) “Buffer Clear” button

It clears the UART Receiver buffer.



5.3 Functions related to CC

(1) “Video Select” selection

First, select the video channel to use the Trigger.

(2) „CC Configure‟ selection

The camera control signal line can be selected from CC1 ~ CC4 with Camera Option.

(CC3 and CC4 are not used at present.)

(3) „CC_Out‟ button

CC Output the CC value of the selected bit in Configure.

1 ": output" 1 ": output" 0 "

1 ": output" 1 ": output" 0 "

bit2 (CC3 out) = reserved

bit3 (CC4 out) = reserved

(4) „Configure Trigger‟ button

Set Trigger Delay, Width, and Blank for Trigger # 1 (CC1) and Trigger # 2 (CC2).

Delay & Width: 0 ~ 65535 Blank: 0 ~ 16777215

The total settable frequency is f = 1 / T

1 / ((65535 + 65535 + 16777215) * 10 ns) = 0.17 Hz.

Ex.)When the default setting Delay / Width / Blank is set to 0/0/0, it is output as 20Mhz

because it is 50ns (10 + 40) in total. When the setting value increases by 1 as shown in the



figure below, The value is increased by 10 ns.

Trigger Clock Delay Width Blank

0 0 0

40

10

20

40

0 1 0

0 2 0

30

40

Trigger Clock Delay Width Blank

0 0 0

40

10

10

50

1 0 0

0 0 1

50

10

Increasing the Width increases the width of the pulse and increases the Delay, Blank.

For example, if you want to use the trigger clock for CC1 or CC2 at 5000hz, select CC from

the "CC Cfg" button and set Delay / Width / Blank as shown below.

Trigger Clock

155us

45us

Pulse Width = 4500 x 10ns = 45us

Pulse Delay + Blank = (5000 + 10000) x 10ns = 155us



(4) „Inv. CC„ button

It inverts the pulse of the selected CC1 or CC2 Trigger.

Invert

Normal



Appendix

A.1 General Specification

Specification

General

PCI Express 4x interface (2.5GT/s per Lane)

Camera Link interface specification 1.0 and 1.1

Support Three Base Camera Link Interface

Three 26-pin (SDR-26) Connectors with support of the Base

Camera Link Specification

Three ports can be used for CC1 / CC2 Trigger

H/W and SDK is controlled by a programmable FPGA

Transfer image frame data to PC

Software

Supported OS Windows XP/7/8/10 (32/64bit)

API Interface with Application through client DLL

Sample Software Test Sample software for evaluation



A.2 Dimensions

The dimensions of board are as follows. (159.5 x 112.5 mm)



References

1. Specification of Camera Link Interface Standard for Digital Cameras and Frame Grabbers

-- Camera Link committee

2. PCI Local Bus Specification Revision2.1

-- PCI Special Interest Group

3. How to install PCI DAQ Board

-- DAQ system

4. AN201 How to build application using API

-- DAQ system

5. AN312 PCIe-FRM26_B API Programming

-- DAQ system

6. Camera Link

-- DAQ system

Documents

PICe-FRM26 B Manual - DAQ SYSTEM