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MTO HEALICs Program July 9, 2010 Cogno: A Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios. PI: Behzad Razavi Co-PIs: Danijela Cabric, Dejan Markovic, Ali Sayed, and Jason Woo Electrical Engineering Dept. University of California, Los Angeles COTRs: Jay Rockway, SPAWAR - PowerPoint PPT Presentation
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MTO HEALICs ProgramJuly 9, 2010
Cogno: A Self-Healing Mixed-Signal Baseband Processor for Cognitive Radios
PI: Behzad Razavi
Co-PIs: Danijela Cabric, Dejan Markovic,
Ali Sayed, and Jason Woo
Electrical Engineering Dept.
University of California, Los Angeles
COTRs: Jay Rockway, SPAWAR
Cynthia Hanson, SPAWAR
HEALICs PI Review, p. 2
Outline
• System and Schedule Review• MTO Questions• Technical Description - Measured ADC Slice Results - ADC Design and Layout - Jitter Reduction - RF Spectrum Sensing• Backup Slides - Teaming and Personnel - Financials
HEALICs PI Review, p. 3
System and Schedule Review
Razavi: ADC DesignMarkovic: Logic Synthesis Mismatch ModelingSayed: Self-Healing AlgorithmsWoo: Mismatch Modeling
Razavi: PLL DesignMarkovic: Logic Synthesis Spectrum Sensing ImplementationSayed: Jitter Healing AlgorithmsCabric: Spectrum Sensing Algorithms
Team Member Resource Allocation
Behzad Razavi
42%
Danijela Cabric
12.6%
Dejan Markovic
29%
A. H. Sayed 12.6%
Jason Woo 4%
HEALICs PI Review, p. 4
MTO Questions
• When presenting the metrics chart, please provide updates to table with measured and /or
simulated values. Updated.
• Please provide an update on testing of the single ADC comparator “slice”. To be presented
• There is still concern from the government team that a design of the full self-healing ADC should be finalized and prototyped as soon as possible to mitigate risk going into the latter half of Phase I. July tapeout to mitigate risks
• Provide an update regarding the expected performance from both the interleaved and single slice ADC architectures. Are you on track to tape-out the different design variants (for risk mitigation) in July? To be discussed on slide 6.
• Document co-PI contributions to the ADC design process. To be presented.
• Please present the justification of the effectiveness of your proposed jitter reduction technique. To be presented.
HEALICs PI Review, p. 5
Summary of Accomplishments
• ADC:
- Finalized and froze ADC architecture.
- Successfully measured one ADC slice.
- Incorporated comparator noise averaging during self-healing.
- Laid out, extracted, and verified coarse stage and one slice of fine stage (including self-healing machinery).
• 8-dB reduction in ADC clock jitter by self-healing with 6 mW of power
• Taped out spectrum sensing chip
HEALICs PI Review, p. 6
Present Challenges
• ADC:
- Higher power consumption than expected because of rush
to tape out. (High risk)
- Complex self-healing due to comparator noise averaging. (Moderate risk) tape out coarse ADC and one slice of fine
ADC in July.
- Difficult to interleave two ADCs on one chip because of the large number of high-speed digital outputs (~40)
Interleave two ADCs on PC board.
HEALICs PI Review, p. 7
Phase I Program Metrics
ADC Program Metrics
Metric Unit Phase I GNG
Performer Status to date(Provide
Measured/Simulated Values)
Program GNG Metrics
Performance Yield(1) % ≥ 95 Simulated
Power Consumption Overhead - -600XSimulated; baseline
design very power hungry
Area Overhead - -7X Based on layout
Performer Defined Metrics
Resolution (ENOB) bits 10 (9.5) Simulated
Power mW 10 18 Simulated
Sampling Rate GHz 1 Simulated
Area mm2 2.5 Simulated
Energy/bit fJ/bit 18 Simulated
HEALICs PI Review, p. 8
Tapeout Schedule
Design Iteration ID
Foundry Technology
CDR DateTape-Out
DateParts
DeliveredControl (on or
off chip)
Block Block Block
Lead Team Member
Lead Team Member
DARPA/MTO
DSP 1a TSMC 65nm 10/08/2009 10/23/2009 12/19/2009 N/AFFT
D.MarkovicRadio DSP D.Markovic
Multi-Vdd Design
DSP 1b TSMC 65nm 10/08/2009 10/23/2009 12/19/2009 N/ADecimation D.Markovic
Interp. Filter D.Markovic
Multi-GHz Design
SliceTest TSMC 65nm 11/20/2009 1/12/2009 4/10/2010Heal and Measure(on chip)
Comparator(Hashemi)
Self-healing Matrix
(Hashemi)
Control Logic(Hashemi)
RF DSP TSMC 65nm 05/24/2010 06/07/2010 08/09/2010 On chipFFT
D. MarkovicPower
detector DMRF DSP
ADCCog TSMC 65nm 7/1/2010 7/29/2010 10/29/2010Coarse Stage, Fine Healing
Slice
Coarse Stage(Sahoo)
Fine Slice(Hashemi)
SHA(Chiang)
HEALICs PI Review, p. 9
Coarse Healing Slice
• To test coarse healing cancellation scheme:– One coarse comparator
– A chain of FFs
– Ladder
– Healing scheme (sense/correct OS)
– Begin/end of the chain
– Timing
Q
QSET
CLR
S
R
FFQ
QSET
CLR
S
R
FFQ
QSET
CLR
S
R
FFQ
QSET
CLR
S
R
FFQ
QSET
CLR
S
R
FF
. . . . . .
Reference Ladder
Comp
V rj V r(j+1)V r(j-1)
. . . . . .
Use the negative output of the comp to clock the chain
HEALICs PI Review, p. 10
Test Assembly
Die photograph
Chip is bonded to a copper board
HEALICs PI Review, p. 11
Measurement Modes
There are two operation modes:1. ADC Operation mode2. Calibration mode
Vin
Vip
Vrefn_nom
Vrefp_nom
Vop
Von
Clock
Vrefp_slide
Vrefp_mid
Control Logic
Switching network
HEALICs PI Review, p. 12
Measurement Results
Step1: test comp in ADC operation mode
Low decision Metastable
HEALICs PI Review, p. 13
Measurement Results
Step 2: reset self-healing register; start reference sliding
ocomp output during healing Ccomp out after healing
HEALICs PI Review, p. 14
Measurement Summary
VDD (V) 0.8 0.9 1 1.1 1.2
Vslide-reset (mV) 533 600 666 733 800
Vslide-settled
(mV)681 756 850 932 1070
Offset before healing (mV)
74 82 90 97 97
Offset after healing (mV)
<6 < 7 <8 <9 <10
• VDD : supply voltage• Vsilde-reset : ref voltage at the beginning of chain• Vslide-settled: ref voltage after calibration is done
Slice operates as expected, demonstrating the self-healing operation.
HEALICs PI Review, p. 15
Architecture IX
• Coarse decision slides one input of preamp to a close estimate of the analog input voltage.
• Maximum output voltage generated by preamp is half of the value in Arch. VIII linearity is improved.
• But timing budget is still tight.
HEALICs PI Review, p. 16
Coarse ADC Comparators
• Coarse ADC comparators incorporate:– Digital healing of comparator offset by sliding the
reference input of the comparator along the ladder.
– Distributed sample-and-hold
– Avoids corruption of comparator decision by kick-back from other comparators.
– Self resetting of the sampling capacitors
– Preventing memory effects.
– Kick-back cancellation circuit
– Resulting in a maximum of 3 mV systematic offset of a comparator as opposed to 15 mV in the absence of the circuit.
HEALICs PI Review, p. 17
Coarse Comparator
Self Resetting Switches
Kick-back Cancellation
Circuit
HEALICs PI Review, p. 18
Coarse ADC Layout
Self-Healing Logic
Resistor Ladder & Bypass Capacitors
127 Comparators
Total height 1.60 mmTotal length 0.36 mm
1.6
mm
0.36 mm
HEALICs PI Review, p. 19
Fine ADC
• 16 Fine blocks (FB) each consists of
• one preamp• 25 comps with built-in offsets
• Every two FBs share one preamp
• Fine healing corrects offset of preamp and offset of comparator
HEALICs PI Review, p. 20
Fine ADC
• To remove kick-back noise of the fine comps:
• Distributed sampling to isolate the sampling nodes of comparators
• Pipelining: to improve speed
• Share one cap between two comps to reduce loading on preamp
HEALICs PI Review, p. 21
Fine ADC
• Each preamp slides over 8 sub-ranges• The amplified sub-range is finely digitized by fine comps• An overlap of 14-LSB is chosen to correct:
• Coarse comp uncorrected offset (4-LSB)• Coarse comp thermal noise (4-LSB)• Timing mismatch between Fine stage and Coarse stage (±3-LSB)
HEALICs PI Review, p. 22
ADC Timing and Clock Phases
• Two clock phases• PhS: sample input signal• PHH: hold, clock of the coarse ADC
• Self_timed operation: coarse ADC generates clock for the fine• En_Fine: is the output of the coarse to enable the fine • PHS,early: early sampling phase to clock the fine comps
HEALICs PI Review, p. 23
Fine ADC: Offset Healing
• Fine comparator:• VDD = 1.2 V• I_avg = 80 uA• σn,in = 630 uV-rms
• Offset tuning:• Tune gate voltage of a transistor that is in parallel with input transistors, i.e. Vcal
HEALICs PI Review, p. 24
Fine Healing Logic (I)
• Fine healing logic heals the offset of the fine comparators by sliding one of the inputs of the fine comparator along a ladder.
• The key blocks in the fine healing logic are:1. Shift Register with a moving “1” that tells which
comparator is being healed.2. Input scan chain to load the control signals for the
switches that tap on to the resistor ladder.3. Self-healing logic slice incorporating:
1. Registers storing comparator state and which comparator is being healed
2. Tri-states to enable reading out of each state3. Decoders that control the switches
4. Output scan chain to read out the state of each comparator.
5. Each comparator is healed many times and the results are compiled to determine the “favorable” tap voltage.
HEALICs PI Review, p. 25
Fine Healing Logic (II)
Shift Register with a shifting “1” that tells which comparator is being healed. Input scan chain. Output scan chain.
HEALICs PI Review, p. 26
Fine Calibration Logic (III)
• The healing sequence is as follows:1. Toggle “RESETB” from “0” to “1”. This resets all the registers
in the shift-register along the slice to “0” and the bottom most register to “1”.
2. Toggle “ShiftClk” shifting “1” to the register of “Slice 0”.3. Scan data into the input scan-chain using “DinScan” and
“ScanClk”.4. Toggle “LoadClk”. This loads data in the input scan chain to
the corresponding registers of the slice that is enabled by the “1” in the shift register.
5. Clock the comparator a few times and average the comparator output.
6. The value of the register which corresponds to 50% “1s” and “0s” is the value that has removed the offset of the comparator.
7. The register value can be read out using the output scan chain.8. Toggle “ShiftClk” again to shift the “1” and move on to the next
comparator.
HEALICs PI Review, p. 27
Fine ADC Layout
• Fine ladder: poly resistors with bypass caps
• Preamp layout:
• Requires:
• 1023 resistors• 128 bypass caps at sliding ref taps
32 um
11 u
m• Fine comp & SR Latch layout:
15 um
3.9
um
HEALICs PI Review, p. 28
Fine ADC Layout
• Fine slice: 2 x (comp and its calibration logic)
Fine CompFine
Decoder 5-1 MUX Switches Bypass caps
133 um
7.8
um
7.8
um
250 um
• One half of slice: (comp and its calibration logic)
• Fine slice: 2 x (comp and its calibration logic)
HEALICs PI Review, p. 29
Jitter Redcution & Spectrum Sensing
Metric Unit Phase I GNGPerformer Status to Date
Simulated Value Measured Value
Program GNG Metrics
ADC Jitter Reduction – Performer Defined Metrics
Reduction in ADC Clock Jitter% of
Sampling period
0.1% 0.3% -
SNR Gain dB 10 dB 8.1 dB -
Power Consumption mW < 10 mW 6 mW -
Area mm2 < 0.1 mm2 0.067 mm2 -
RF Spectrum Sensing Processor – Performer Defined Metrics
RF bandwidth MHz 250 500 (250) 64 (FPGA)
Signal detection dB −5 dB −5 dB −5 dB (FPGA)
Power consumption mW < 20 mW 19.06 mW (9.53 mW)
Area mm2 < 2 mm2 1.64 mm2
• Jitter reduction – major updates
– Quantization noise is factored into simulation
– Fixed-point implementation of the recovery algorithm
– Hardware performance metrics are computed (Area/Power)
• RF spectrum sensing – major updates
– RF sensing with (PD, PFA) = (0.9, 0.1) detection performance
– Experimentally verified signal detection with SNR = −5dB
– Taped out spectrum sensing chip (9.53 mW, 250 MHz band)
HEALICs PI Review, p. 30
Jitter Reduction Summary
DesignFPGA
LUT CountEstimatedChip Area
GOPSEstimated
Chip PowerSNR Gain
Arch. #1 9610 0.481 mm2 175 GOPS 35 mW 9 dB
Arch. #2 2942 0.147 mm2 35 GOPS 7 mW 8.1 dB
Arch. #3 1339 0.067 mm2 30 GOPS 6 mW 8.1 dB
Assumptions:• The SNR is computed by inputting a tone at 250 MHz and
computing the SNR at the output of the system.• The area is computed assuming a direct ratio of:
10,000 LUTs = 0.5mm2
• The power is computed assuming 5 GOPS/mW efficiency
HEALICs PI Review, p. 31
• A high frequency tone is modulated with a low frequency tone and injected into the incoming signal. These tones will serve as training for the estimation method.
Jitter Reduction:Proposed Architecture
Jitter Reduction:Proposed Architecture
• The training tones are scaled by the coefficient α and the quantization noise q(n) is incorporated:
HEALICs PI Review, p. 32
Jitter Estimation and Compensation
• The block diagram is illustrated below where the jitter estimation and jitter compensation is based on Q5 report.
• Analysis on jitter estimation performance indicates that the estimates will be:
• Where the variance of the error is:
• Where α is a scale factor to scale the power of the training tones compared to the incoming signal.
HEALICs PI Review, p. 34
Matlab/Simulink Hardware Model
• The fixed point design was implemented in Simulink using the Synplify DSP fixed-point blockset:
Linear interpolationbased on the derivative of the incoming signal
HEALICs PI Review, p. 35
Architecture Design
Architecture #1:• 128-tap low-pass filter• 11-tap derivative filter
• Area: 9610 LUTs (meets 100 MHz timing)
Architecture #2:• accumulator low-pass filter• Direct-form 9-tap derivative filter
• Area: 2942 LUTs (meets 89 MHz timing)
Architecture #3:• Accumulator low-pass filter• Anti-symmetric 9-tap derivative filter
• Area: 1339 LUTs (meets 89 MHz timing)
10-16 bit wordlengths
HEALICs PI Review, p. 36
Wideband Spectrum Sensing: Issues and Specifications
• Interfering power issues
– Introduced by strong adjacent-band signals
– Makes weak signals difficult to detect
Radio BW Freq. Res. Sensitivity Max Tsensing PFA PD Power Area
500 MHz 500 kHz −5 dB 50 ms 0.1 0.9 20 mW 2 mm2
PSD
f0 Fs/2
Large Power Signal
BOI Signal
Large Power SignalWindow
Shape
Leakage Power
InterfererIn-Band Power
Leakage Power
• Specifications
HEALICs PI Review, p. 37
Design Challenges in Sensing Algorithms
• Interfering power increases estimation error
– Design goal can’t be met even with max sensing time• Ignoring interfering power leads to underestimated thr.
– False-alarm rate increases
Simulation Settings
K (Signal BW) 1
SNR −5 dB
INR 30 dB
Freq. Spacing 1-bin
FFT Size 1024-point
0 0.2 0.4 0.6 0.8 1PFA
0
0.2
0.4
0.6
0.8
1
PD
T = 0.2 ms
T = 50 ms
Desired operating region Opt. Thr.Sub-Opt. Thr.
PFA
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
P D
Desired op. region
Increased
sensing time
HEALICs PI Review, p. 38
Proposed Wideband Spectrum Sensing Processor
• Multitap windowed power detector
– Reduce Tsensing by interfering power suppression
• Number of averages and threshold adaptation schemes
– Meet PD and PFA by adapting to interfering power
| |2PowerMeas.
Prog.Acc.
Int. PowerMeas.
Noise PowerMeas.
Avg. #Cal.
ThesholdCal.
PowerDetect
FromADC
H0 / H1
Multitap Windowed Power Detector
# of Accumulation Adaptation
Threshold Adaptation
MultitapWindow
1024ptFFT
HEALICs PI Review, p. 39
• Adapts decision thresholds to in-band interfering power
Threshold Adaptation
0
1
( ) : ( ) ( )
( ) : ( ) ( ) ( )
H c X c V c
H c X c S c V c
0
1
( ) : ( ) ( ) ( )
( ) : ( ) ( ) ( ) ( )
H c X c V c I c
H c X c S c V c I c
Noise Power ( svf2
)
Band of Interest
Adjacent-Band Signal
Interfering Power ( sif2
)
Desired OperatingRegionPD
PFA
Adapt # of Avg. to sif2
0 0.1 0.20.8
0.9
1
Adapt threshold to sif2
• Includes in-band interferer into the binary hypothesis test
HEALICs PI Review, p. 40
Threshold Adaptation Analysis
• Tmw(c) as a function of noise power and interfering power
– Allows dynamical threshold adaptation
• The number of averages and decision threshold depend on SNR, PD, PFA, noise power, and interfering power
1 2 2FA vf ifc Q P M c M c c c s s
2
2 2 1 1
11 if vf FA D
D
c c Q P Q PM c Q P
SNR
s s
2 20
22 20
( ) | ( ) ( ) ( )
( ) | ( ) ( ) ( )
mw vf if
mw vf if
E T c H c M c c
Var T c H c M c c
s s
s s
: fitting factor
HEALICs PI Review, p. 41
Sensing Performance Analysis
• Multitap windowed FPD
1
0
( )
(
( ) 1
0 )
1 M cH
mwm
H c
H c
T c cK
Hm c M c M mx S FW S FW x ¤
Modeled by M-dependent sequence
0
0
( ) ( ) | ( )( )
( ) | ( )
mwFA
c E T c H cP c Q
Var T c H c
1
1
( ) ( ) | ( )( )
( ) | ( )
mwD
c E T c H cP c Q
Var T c H c
As M is large enough, Tmw(c) can be modeled by Gaussian distribution
1
0
( ) 12
( )
0 ( )
1[ ]
cu
cl
kM c
mw mm
H c
ck k H
T c X k cK
¤ Hc M m c M mS FW x S FW x
Used to derive # of averages and decision threshold
HEALICs PI Review, p. 42
Improvement in Detection Rate
• Only multitap windowed FPD meets the detection rate constraint within 100 FFT averages
Simulation Settings
M (# of Avg.) 100
K (Signal BW) 1
SNR −5 dB
INR 20 dB
Freq. Spacing 2-bin
FFT Size 1024-point
More than 1.3x increase in detection rate
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
PFA
PD
Multitap Windowed FPDMultitap Windowed FPD (sim.)Windowed FPD Windowed FPD (sim.) Conventional FFT FPDConventional FFT FPD (sim.)
PFA
0 0.2 0.4 0.6 0.8 10
0.2
0.4
0.6
0.8
1
P D
HEALICs PI Review, p. 43
Improvement in False-Alarm Rate
More than 2x decrease in false-alarm rate @ INR > 10 dB
Simulation Settings
K (Signal BW) 1
SNR −5 dB
INR 0-20 dB
Freq. Spacing 1-bin
FFT Size 1024-point
0 5 10 15 20
Interferer to Noise Ratio (dB)
PF
A
0
0.2
0.4
0.6
0.8
1
Conv.=ConventionalAdap.=Adaptive
Adap. ThresholdPFA
Conv. ThresholdPFA
HEALICs PI Review, p. 44
Improvement in Sensing Time
• Only multitap windowed FPD meets sensing time constraint for a 1-bin adjacent-band interferer
1 2 3 4 5 6 7 810 -1
10 1
10 3
10 5
Conventional FFT FPDMultitap Windowed FPD
Windowed FPD
50 ms
Interfer to Signal Spacing (Bin)
Sen
sing
Tim
e (m
s)
102
104
106
103
105
107
Accum
ulation Num
ber (M)
104
102
100
More than an order of magnitude reduction in sensing time
Simulation Settings
K (Signal BW) 1
PD 0.9
PFA 0.1
SNR −5 dB
INR 30 dB
Freq. Spacing 1-8 bins
FFT Size 1024-point
HEALICs PI Review, p. 45
Hardware Emulation Setup
• Cognitive radio test bed
– BEE2 platform: 5 high performance Xilinx FPGAs with Power PC processors, Gigabit serial channels, Ethernet, support for up to 20GB of RAM
– Mixed signal Front End Baseband processor (2 12-bit ADCs at 64MS/s and 2 14-bit DACs at 128 MS/s)
– Analog front-end radio
HEALICs PI Review, p. 46
Experimental Settings
• Wideband radio BW is limited by the analog front-end
– Scales the target 500 MHz spectrum to 64 MHz
– Scales the frequency resolution to 64.5 kHz (to keep the FFT size)
Wideband Spectrum Settings
Wideband Bandwidth 64 MHz
Frequency Resolution 64.5 kHz
Band of Interest Signal Settings Adjacent-Band Signal Settings
Modulation FM Modulation FM
Signal Bandwidth 50 kHz Signal Bandwidth 50 kHz
Carrier Frequency 2483.05 MHz Carrier Frequency 2482.975 MHz
SNR −5 dB INR 0 − 40 dB
HEALICs PI Review, p. 47
Experimental Results
• Proposed threshold adaptation algorithm
– Meets PFA constraints
• Proposed number of accumulation adaptation scheme
– Meets PD constraints
– Meets sensing time constraints (M < 104)
0 10 20 30 400
0.2
0.4
0.6
0.8
1
Interferer to Noise Ratio (dB)
PF
A
Norm
alized Threshold
PFA w/ Thr. Adap.PFA w/o Thr. Adap.Thr.
Thr.=ThresholdAdap.=Adaptation
100
101
102
0 10 20 30 40
Interferer to Noise Ratio (dB)
PD
101
102
103
104
Accum
ulation Num
ber (M)
Acc. # (M)
PD w/ Acc. # Adap.PD w/o Acc. # Adap.
Acc.=AccumulationAdap.=Adaptation
0
0.2
0.4
0.6
0.8
1
HEALICs PI Review, p. 48
Design Challenges in Processor Architecture
• Low power design
– FFT consumes more than 50% of the total power
– Parallelism and voltage scaling for power reduction
– Factorize optimal FFT PU combination to minimize power-area product
• Small area (low cost) design
– Large dynamic range of the spectrum leads the data path after FFT processor requires large WL
– Memory for storing FFT power, noise power, and interfering power occupies > 50% of the total area
– Changing data format to reduce WL for area saving
HEALICs PI Review, p. 49
Parallel-Pipelined FFT for Power Reduction
• Parallel architecture allows VDD scaling to reduce power
– 8x parallelism achieves minimum power-area product• FFT factorization determines optimal PU combination
– 128-pt FFT with radix-4/radix-4/radix-8 architecture achieves 4x power-area-product reduction
N1=64N2=16
0
0.2
0.4
0.6
0.8
1
0 2 4 6 8 10Normalized Area
Nor
mal
ized
Pow
er
N1=512N2=2
N1=256N2=4 N1=128
N2=8
N1=1024N2=1
Ref. Design
Opt. Design
0.4 0.6 0.8 1
0.6
0.8
1 Ref. Design
Opt. Design
A1
A13
128 PointPipeline FFT
8 Point Parallel
FFT
Radix-8 PE
D4 D2 D1TW
21
8
Radix-4 PE
D16 D8TW
Radix-4 PE
D64 D32
HEALICs PI Review, p. 50
8
( )2
( )2
20 40
55
55
12
8
Multitap WindowedPipelined FFT
12
MemoryBank
Noise PowerEstimation
&Int. PowerEstimation
MemoryBank
MemoryBank
55
55
Changing Data Format for Area Reduction
8
Power Meas.&
Accumulation
30
30
12
8
Multitap WindowedPipelined FFT
12
MemoryBank
MemoryBank
MemoryBank
Noise PowerEstimation
&Int. PowerEstimation
pow_cal
Flt. syn.
pow_cal
r
i
PowerMeas.
Flt. syn.
1
0
ControllerM
FFT_out
20
15
15
5
25
Complex Signal
Real SignalMantissaExponent
• Reduces memory size by changing the data format
– 60% area reduction is achieved by changing 2’s complement to floating-point representation
UnsignedTo
Flt. Pt.
20
10
5Magnitude
Mantissa
Exponent
HEALICs PI Review, p. 51
Power-Area Summary
• Synthesis estimates
Logic Area (mm2) Power (mW)
MW 0.06 0.52
FFT 0.3 7.06
ACC 0.06 0.82
ANC 0.03 0.16
DTC 0.03 0.14
Other 0.01 0.12
Total 0.49 8.82
• Total chip power: 19.06 mW (500 MHz band) (9.53 mW for 250 MHz band)
Memory Area (mm2) Power (mW)
MW 0.107 2.82
FFT 0.072 2.42
ACC 0.1 2.92
Noise Power 0.035 0.24
Int. Power 0.035 0.24
# of Acc. 0.035 0.26
Other 0.004 1.34
Total 0.39 10.24
HEALICs PI Review, p. 52
Technology
Process TSMC 65 1P9M
Clock Freq. 500 MHz
Supply Voltage 0.8 V (Memory)0.5 V (Logic)
Area
Gate Count 1.45M
Core Area 1.64 mm2
Chip Area 2.76 mm2
Power
Total 19.06 mW
Memory 10.24 mW @ 0.8 V
Logic 8.82 mW @ 0.5 V
MemoryCore
LogicCore
1820 um
15
20
um
Chip Summary
HEALICs PI Review, p. 53
Backup Slides
HEALICs PI Review, p. 54
II. Teaming Personnel
UCLA Team• Dr. Ali. H. Sayed, Co-PI
• Zaid Towfic, Graduate Student• Shang-Kee Ting, Graduate Student
• Dr. Danijela Cabric, Co-PI• Oussama Sekkat, Graduate Student• Santiago Rodriguez-Parera, Graduate Student
• Dr. Dejan Markovic, Co-PI• Tsung-Han Yu, Graduate Student• Victoria Wang, Graduate Student• Chia-Hsiang Yang, Graduate Student
• Dr. Behzad Razavi, PI• Sedigheh Hashemi, Graduate Students• Wood Chiang, Graduate Student• Bibhu Sahoo, PostDoc• Marco Zanuso, PostDoc
• Dr. Jason Woo, Co-PI
HEALICs PI Review, p. 55
III. Publications
Conference Publications• Shang-Kee Ting, Ali H. Sayed. Reduction of the Effects of
Spurious PLL Tones on A/D Converters. ISCAS 2010 Conference.
• Zaid Towfic, Shang-Kee Ting, Ali H. Sayed. Sampling Clock Jitter Estimation and Compensation in ADC Circuits. ISCAS 2010 Conference.
• T.-H. Yu, S. Rodriguez-Parera, D. Markovic, D. Cabric. Cognitive Radio Wideband Spectrum Sensing Using Multitap Windowing and Power Detection with Threshold Adaptation. ICC 2010 Conference.
Manuscripts in Submission
• T.-H. Yu, O. Sekkat, S. Rodriquez-Parera, D. Markovic, D. Cabric. A Performance-Power-Area Efficient Processor Architecture for Wideband Spectrum Sensing. IEEE TCAS-I (in submission)
HEALICs PI Review, p. 56
Teaming and Personnel
Team Member Responsibilities Allocated Fund Percentage of Time
Behzad Razavi Self-Healing ADC $1M 42%
Danijela Cabric Baseband Spectrum Sensing
$300K 12.6%
Dejan Markovic Baseband Implementation
$692K 29%
A. H. Sayed ADC clock jitter reduction and self-healing PLL algorithms.
$300K for this task
(total $600K)
12.6%
Jason Woo Variability Modeling $100K 4%
HEALICs PI Review, p. 57
Financials
University of California Los AngelesN66001-09-1-2029
$-$10,000
$20,000$30,000$40,000
$50,000$60,000
$70,000$80,000$90,000
$100,000$110,000$120,000
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$160,000$170,000
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$210,000$220,000
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11
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$ m
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Spending Plan, monthly Billed, monthly
Ceiling Spending Plan, cumulative
Government Increments Billed, cumulative