Published by MB/SC 1270 Quality Printed in the Netherlands Subject to modification EN 3122 785 19391

2012-Oct-12

2012 © TP Vision Netherlands B.V.All rights reserved. Specifications are subject to change without notice. Trademarks are theproperty of Koninklijke Philips Electronics N.V. or their respective owners. TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjustearlier supplies accordingly.PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.

Colour Television Chassis

VES1.1ELA

See table of contents on page 3

Revision ListEN 2 VES1.1E LA1.

2012-Oct-12 back to div. table

1. Revision ListManual xxxx xxx xxxx.0• First release.

Manual xxxx xxx xxxx.1• Added the CSM menu on page 49

2. Technical Specifications and Connections

Index of this chapter:Technical specificationsDirections for Use

Notes:• Figures can deviate due to the different set executions.• Specifications are indicative (subject to change).

Technical Specifications

For on-line product support please use the links in Table 2-1. Here is product information available, as well as getting started, user manuals, frequently asked questions and software & drivers.

Table 2-1 Described Model numbers

Directions for Use

You can download this information from the following websites:http://www.philips.com/supporthttp://www.p4c.philips.com

CTN Styling Published in:

22PFL2807H/12 2800 3122 785 19390

32PFL2807H/12

Contents 1 Introduction .............................................................................................................................................. 6

1.1 General Block Diagram ................................................................................................................... 6

1.2 MB62 Placement of Blocks............................................................................................................... 7

2 Tuner (TU3) ............................................................................................................................................... 8

2.1 General description of the Sony RE216 tuner .................................................................................. 8

2.2 Pinning ............................................................................................................................................ 9

3 Audio amplifier stage with AZAD2102 (U163, U164) ............................................................................. 10

3.1 General description ........................................................................................................................ 10

3.2 Features .......................................................................................................................................... 10

3.3 Absolute Ratings ........................................................................................................................... 11

3.3.1 Electrical Characteristics ....................................................................................................... 11

3.3.2 Operating specifications ....................................................................................................... 12

3.4 Pinning ............................................................................................................................................ 13

4 Audio amplifier stage with TPA3113 (U168) .......................................................................................... 13

4.1 General Description ........................................................................................................................ 13

4.2 Absolute Ratings ............................................................................................................................. 14

4.2.1 Electrical Characteristics ......................................................................................................... 14

4.2.2 Operating Specifications ....................................................................................................... 15

4.3 Pinning ........................................................................................................................................... 15

5 Power stage............................................................................................................................................. 16

5.1 Power management ....................................................................................................................... 19

6 Microcontroller – MSTAR (U5) ............................................................................................................... 21

6.1 Description ..................................................................................................................................... 21

6.2 MSTAR block diagram ..................................................................................................................... 25

6.3 Reset circuit .................................................................................................................................... 26

7 CI interface .............................................................................................................................................. 26

8 USB interface .......................................................................................................................................... 27

9 DDR2 SDRAM K4T1G164QF (U155) ........................................................................................................ 28

9.1 Description ..................................................................................................................................... 28

9.2 Features .......................................................................................................................................... 28

Pinning ........................................................................................................................................................ 29

10 Scaler and LVDS sockets ...................................................................................................................... 30

10.1 LVDS sockets block diagram ........................................................................................................... 30

10.2 Panel supply switch circuit ............................................................................................................. 30

11 SPI flash memory - MX25L1005 (U158) .............................................................................................. 31

11.1 General Description........................................................................................................................ 31

11.2 Features .......................................................................................................................................... 31

11.3 Absolute maximum ratings ............................................................................................................ 32

11.4 Pinning ............................................................................................................................................ 32

12 NAND Flash memory – NAND512XXA2C (U162) ................................................................................ 33

12.1 General Description........................................................................................................................ 33

12.2 Features .......................................................................................................................................... 33

12.3 Pinning ............................................................................................................................................ 34

13 LNBH23L (U6) ..................................................................................................................................... 35

13.1 Description ..................................................................................................................................... 35

13.2 Features .......................................................................................................................................... 35

13.3 Block diagram ................................................................................................................................. 36

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3) ....................................................................... 36

14.1 Description ..................................................................................................................................... 36

14.2 Features .......................................................................................................................................... 36

14.3 Pin Assignment ............................................................................................................................... 38

15 LM1117 (U175, U180, U181) .............................................................................................................. 39

15.1 General description ........................................................................................................................ 39

15.2 Features .......................................................................................................................................... 39

15.3 Applications .................................................................................................................................... 39

15.4 Absolute maximum ratings............................................................................................................. 39

15.5 Pinning ............................................................................................................................................ 40

16 MP2012 (U176) ................................................................................................................................... 40

17 General description ............................................................................................................................ 40

17.1 Features .......................................................................................................................................... 40

17.2 Pinning ............................................................................................................................................ 41

18 RTA8283A (U23, U173) ....................................................................................................................... 41

18.1 General description ........................................................................................................................ 41

18.2 Features .......................................................................................................................................... 41

18.3 Pinning ............................................................................................................................................ 43

19 MP1583 (U174) ................................................................................................................................... 44

19.1 General description ........................................................................................................................ 44

19.2 Features .......................................................................................................................................... 44

19.3 Pinning ............................................................................................................................................ 44

20 FDC642 ................................................................................................................................................ 45

20.1 General description ........................................................................................................................ 45

20.2 Features .......................................................................................................................................... 45

20.3 Pinning ............................................................................................................................................ 45

21 FDC604P .............................................................................................................................................. 46

21.1 General description ........................................................................................................................ 46

21.2 Features .......................................................................................................................................... 46

21.3 Pinning ............................................................................................................................................ 46

22 Connectors .......................................................................................................................................... 47

22.1 SCART (SC1) .................................................................................................................................... 47

22.2 HDMI (CN707, CN708) .................................................................................................................... 47

22.3 VGA (CN711) ................................................................................................................................. 48

23 Customer service mode (CSM) ........................................................................................................... 49

24 Service menu mode ............................................................................................................................ 49

24.1 Main service menu ......................................................................................................................... 49

24.2 Video Settings ................................................................................................................................. 50

24.3 Audio Settings ................................................................................................................................. 50

24.4 Options 1 ........................................................................................................................................ 51

24.5 Options 2 ........................................................................................................................................ 51

24.6 Tuning Settings ............................................................................................................................... 52

24.7 Source Settings ............................................................................................................................... 52

24.8 Diagnostic ....................................................................................................................................... 52

24.9 USB operations ............................................................................................................................... 52

24.10 Profile Operations ........................................................................................................................... 55

24.10.1 Upload profile Data from USB ............................................................................................ 55

24.10.2 PQ Files Operations ............................................................................................................ 55

24.10.3 Upload PQ files from USB ................................................................................................... 55

24.10.4 Ci+ credentials key update ................................................................................................. 55

24.10.5 HDCP keys update............................................................................................................... 55

24.10.6 Edid update ........................................................................................................................ 56

24.10.7 DDR settings update ........................................................................................................... 56

24.10.8 MAC address update .......................................................................................................... 56

25 Software update .................................................................................................................................. 56

26 Troubleshooting ................................................................................................................................. 56

26.1 No backlight problem ..................................................................................................................... 56

26.2 CI module problem ......................................................................................................................... 58

26.3 LED blinking problem ...................................................................................................................... 60

26.4 IR problem ...................................................................................................................................... 60

26.5 Keypad touchpad problems ........................................................................................................... 61

26.6 USB problems ................................................................................................................................. 62

26.7 No sound problem .......................................................................................................................... 62

26.8 No sound problem at headphone .................................................................................................. 63

26.9 Standby On/Off problem ................................................................................................................ 63

26.10 DVD problems ................................................................................................................................. 64

26.11 No signal problem .......................................................................................................................... 64

27 Styling sheet ....................................................................................................................................... 66

28 Schematics SSB ................................................................................................................................... 67

1 Introduction The 17MB62 mainboard is driven by a MStar SOC. This IC is capable of handling Video and audio processing, Scaling-Display processing, 3D comb filter, OSD and text processing, LVDS transmitting, channel and MPEG2/4 decoding, integrated DVB-T/C demodulator and media center functionality.

The TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo. Also DVB T, DVB-C are supported internal demodulators of Mstar IC and DVB-S/S2 is supported with external demodulator.

Sound system output is supplying max. 2 × 2.5 W (less 10% THD at maximum output) with 4 Ω speakers or 2 × 6 W for stereo 8 Ω speakers.

Supported peripherals are:

1 RF input VHF I, VHF III, UHF @ 75 Ω (Common) 1 Side AV (CVBS, R/L_Audio) 1 SCART socket (Common) 1 YPbPr (Optional) 1 PC input (Common) 2 HDMI 1.3 input (1 HDMI input is common, 1 input is optional) 1 S/PDIF output (Optional) 1 Headphone (Optional) 1 Common interface (Common) 1 USB (Common) 1 DVD (Optional) 1 On-board Keypad (Optional) 1 External Keypad (Optional) 1 External TouchPad (Optional)

1.1 General Block Diagram

1.2 MB62 Placement of Blocks

2 Tuner (TU3) A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3 Bands (From 48 MHz to 862 MHz for COFDM, from 45.25 MHz to 863.25 MHz for CCIR channels). The tuning is available through the digitally controlled I2C bus (PLL).

In the active antenna option, the following circuits are used. ANT_CTRL pin is controlled by microcontroller. If ANT_CTRL is low, ANT_PWR will be low. If ANT_CTRL is high, ANT_PWR wilbe high.

OVER_CUR_DETECT pin is a monitor for short circuit in antenna. OVER_CUR_DETECT is lowANT_CTRL will be low, so ANT_PWR will be low. Finally, short circuit protection is done by circuits and microcontroller.

2.1 General description of the Sony RE216 tuner The SUT-RE216 is designed for terrestrial TV (digital & analog) and digital cable reception. It includes a full band tuner and a channel filtering for digital signals. It provides a low IF output aftechannel filtering to drive a channel demodulator. Tuning, band switching and initialization are made via an I2C bus interface. The module is built on a low-loss printed circuit board carrying all the components in a metal housing frame with top and rear covers. The single aerial connector is mounted on one frame side and all other connections are made via pins at the bottom.

Features:

Full frequency range from 47 to 870 Mhz Digital Platform (DVB-T/T2, DVB-C, ISDB-T & ATSC) Analog platforms (PAL B/G/I/D/K, NTSC M & SECAM L/L’) Low IF tuner concept Programmable channel Filter bandwidth Fully I2C bus controlled For Hybrid TV applications

2.2 Pinning

3 Audio amplifier stage with AZAD2102 (U163, U164)

3.1 General description 17MB62 uses two 2,5 W Class D Mono Audio Amplifers for from 16" to 24" TVs. AZAD2102B is a 2.9 Watts (max. can offer 3.0 Watts @ Load = 3 Ω,THD = 10%, AVdd = DVdd = 5.5 Volt) with high efficiency filter-free class-D audio power amplifier in a 1613 mm x 1613 mm wafer chip scale package (WCSP). AZAD2102B uses Current- switch technology to achieve high performance class-d amplifier that features 0.03% THD, 85% efficiency, –70 dB PSRR, to improve RF-rectification immunity. AZAD2102B provide a Vibration-Spectrum modulation clock for PWM Output. This vibration frequency is around 10 kHz shift (+/- 5 kHz of Fpwm). The advantage of the small size package (WCSP) makes AZAD2102B very suitable for mobile phone and PDA device application. And the Class-D amplifier structure let AZAD2102B to have highly efficiency power consumption than Class-AB amplifier. AZAD2102B can shrink the application board, reduce system cost, and external components. ESD level protection I/O embedded in AZAD2102B. For general applications, there is no need to add extra ESD protection devices (like Varistors) in application systems for AZAD2102B’s I/O

3.2 Features CMOS Technology High Efficiency 85% High PSRR 70 dB at 217 Hz Differential OP-amp Input AZAD2102B provides Vibration-Spectrum Modulation clock for reduce EMI Provide Mute function (set Mute_B to GND will go into Mute status) For the input stage AZAD2102B built-in a 10Kohm resistors (Gain

setting = 29.5 dB) Maximum Battery Life and Minimum Heat Efficiency With an 8 Ω Speaker: 3.5 mA Quiescent Current Output Power at 10% THD 2.85 Watts at AVdd = DVdd = 5.0 Volt, Rload = 4 Ω 1.45 Watts at AVdd = DVdd = 3.6 Volt, Rload = 4Ω 0.30 Watts at AVdd = DVdd = 3.0 Volt, Rload = 4Ω 1.75 Watts at AVdd = DVdd = 5.5 Volt, Rload = 8Ω 0.87 Watts at AVdd = DVdd = 3.6 Volt, Rload = 8Ω 0.41 Watts at AVdd = DVdd = 3.0 Volt, Rload = 8Ω Eliminate Power on and Power-off “Pop” noise A fewer external components Optimized PWM output stage eliminates LC output filter Internally generate 290 kHz switching frequency to eliminate capacitor and resistor Improve PSRR (–70 dB) and wide supply voltage (3.0 V to 5.5 V) Fully differential design reduces RF rectification This chip has been built-in a very strong ESD protection. System level ESD 4 KV (IEC 61000-4-2 ESD Contact Level) Wafer chip scale package (WCSP) TSSOP package with exposed pad

3.3 Absolute Ratings

3.3.1 Electrical Characteristics VDD = AVdd = DVdd, VSS = AVss = DVss = Ground

TA = 25C, Filter Bandwidth = 20 Hz -20 kHz

PARAMETER Symbol TEST COND TIONS MNI TYP MAX UNIT

Operating Votlage Vop AVdd-DVdd to AVss-DVss 3.0 5 5.5 v Output offset voltage

vos

VDD = 5.5 V,VI= 0 V,AV = 6 V/V 4.5 6.5

mV VDD = 3.6 V,VI= 0 V,AV = 6 V/V 2.1 4.0

VDD = 3.0 V,VI= 0 V,AV = 6 V/V 1.2 3.0 Power supply rejection ratio

PSRR

VDD = 3.0 V to 5.5 V, AV = 2 V/V input ac grounded with

Ci=2.2uF,Vripple=200mVpp, RL=80 f=217Hz

-68

dB

Common mode rejection ratio Cf':lRR VDD = 3.0 V to 5.5 V,Vic = VDD/2 to

0.5 V,Vi c = VDD/2 to 0.5 VDD -0.8 V,-65

dB

High level nput current

IIIHII

VDD= 5.5V,Vi=5.8V 25

uA

Low level Input current

IIlLI VDD= 5.5V,Vi=-0.3V 1

uA

Operation current

lop

VDD = 5.5 V,no load 3.6 5.0

mA VDD = 3.6 V,no load 3.0 4.2

VDD = 3.0 V,no load 2.5 3.5 Output switching frequency

Fpwm

VDD = 5.5 V,no load 290

KHz VDD = 3.6 V,no load 300

VDD = 3.0 V,no load 315 Vibration-Spectrum Modulation clock Ranqe Fvs

VDD = 5.0 V,no load +/-5 +/-10

KHz

Under Voltage Protection

UVP

Vin+ and Vin- connect to GND,no load 2.0 2.5 v

Mute_B pin Impedance RMuB Mute_B to Ground 270 KQ Gain Gain VDD=5.0V,Ri=5K0+10K

O (Av=20V/V) 18 I 20 I 22

V/V

3.3.2 Operating specifications TA = 25°C,Gain = 20 V/V,

PARAMETER TEST COND TIONS MIN TYP MAX UNIT

Pw

Output power

THO+ N = 10%, f = 1kHz,RL = 4Q

VDD = 5.0V 2.85

w VDD = 3.6 V 1.45

VDD = 3.0 V 0.77 THO + N = 1%, f = 1 kHz, RL = 4 Q

VDD = 5.0 V 2.25

w VDD = 3.6 V 1.15

VDD = 3.0 V 0.60 THO+ N = 10%, f = 1kHz,RL = 8Q

VDD = 5.0 V 1.75

w VDD = 3.6 V 0.87

VDD = 3.0 V 0.47 THO + N = 1%, f = 1 kHz, RL = 8 Q

VDD = 5.0 V 1.39

w VDD = 3.6 V 0.70

VDD = 3.0 V 0.36

THD+N

Total harmonic distortion plus noise

VDD = 5.0 V,PO = 1W,RL = 8 Q,f = 1kHz 0.15

% VDD = 3.6 V,PO = 0.5 W,RL = 8 Q, f = 1 kHz 0.12

VDD = 3.0 V,PO = 200 mW, RL = 8 Q, f = 1kHz 0,09

PSRR

Supply ripple rejection ratio

VDD = 3.6 V, Av=20V/V,Inputs connect to grounded with Ci = l.OJ,JF

F = 217 H.z, VRipple = 200 mVpp

-67

dB

SNR Signal-to-noise ratio VDD = 5 V,PO = 1W,RL = 8 Q 95 dB

Vnoise

Output noise level

VDD = 3.6 V,f = 20 Hz to 20 kHz, nputs ac-grounded with Ci = l.OJJF

No weighting 45 J,JVRMS

A weighting 40 CMRR Common mode

rejecti on ratio

VDD = 3.6 V,Vin = 100mVpp f = 217Hz -72

dB

ZI Input impedance 8 10 12 kQ

ZF Feedback resistor 120 150 180 kQ

3.4 Pinning

4 Audio amplifier stage with TPA3113 (U168)

4.1 General Description 17MB62 uses a 6W Class D Mono Audio Amplifers for from 26” to 32” TVs. The TPA3113D2 is a 6-W (per channel) efficient, Class-D audio power amplifier for driving bridged-tied stereo speakers. Advanced EMI Suppression Technology enables the use of inexpensive ferrite bead filters at the outputs while meeting EMC requirements. SpeakerGuard™ speaker protection circuitry includes an adjustable power limiter and a DC detection circuit. The adjustable power limiter allows the user to set a "virtual" voltage rail lower than the chip supply to limit the amount of current through the speaker. The DC detect circuit measures the frequency and amplitude of the PWM signal and shuts off the output stage if the input capacitors are damaged or shorts exist on the inputs.

The TPA3113D2 can drive stereo speakers as low as 4 Ω. The high efficiency of the TPA3113D2, 87%, eliminates the need for an external heat sink when playing music.

The outputs are also fully protected against shorts to GND, VCC, and output-to-output. The short-circuit protection and thermal protection includes an auto-recovery feature.

3.2. Features 6-W/ch into an 8-Ω Loads at 10% THD+N From a 10-V Supply 12-W into a 4-Ω Mono Load at 10% THD+N From a 10-V Supply 87% Efficient Class-D Operation Eliminates Need for Heat Sinks Wide Supply Voltage Range Allows Operation from 8 V to 26 V Filter-Free Operation SpeakerGuard™ Speaker Protection Includes Adjustable Power Limiter plus DC

Protection Flow Through Pin Out Facilitates Easy Board Layout Robust Pin-to-Pin Short Circuit Protection and Thermal Protection with Auto

Recovery Option Excellent THD+N / Pop-Free Performance Four Selectable, Fixed Gain Settings Differential inputs

4.2 Absolute Ratings

4.2.1 Electrical Characteristics

4.2.2 Operating Specifications AC CHARACTERISTICS TA = 25•c, Vee = 12 V, RL = 8 0 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

KsvR Supply ripple rejection 200 mVpp ripple from 20 Hz-1kHz, Gain = 20 dB,Inputs ac-coupled to AGNO -70

dB

THO+N Total harmonic distortion +noise RL = 8 0, f = 1kHz, Po = 3 W (half-power) 0.06 % Vn Output integrated noise

20 Hz to 22 kHz,A-weighted filter, Gani = 20 dB

65 IJV

-80 dBV

Crosstalk P0 = 1 W,Gain = 20 dB, f = 1 kHz -100 dB SNR Signa-l to-noise ratoi Maximum output at THO+N < 1%, f = 1 kHz,

Gain = 20 dB, A-weighted 102

dB

fosc Oscillator frequency 250 310 350 kHz

Thermal trip point 150 ·cThermal hysteresis 15 ·c

4.3 Pinning

PIN 110/P

DESCRIPTION

NAME Pin Number

so

1

I Shutdown logic input for audio amp (LOW = outputs Hi-Z,HIGH = outputs enabled).TTL logic levels with compliance to AVCC.

FAULT

2

0

Open drain output used to display short circuit or de detect fault status.Votlage compilant to AVCC.Short circuit faults can be set to auto-recovery by connecting FAULT pin to SO pin. Otherwise, both short circuit faults and de detect faults must be reset by cycling PVCC.

LINP 3 I Postiive audio input for left channeL Biased at 3V.

LINN 4 I Negative audio input for left channeL Biased at 3V.

GAlNO 5 I Gani select least significant bit. TTL logic levels with compliance to AVCC.

GAIN1 6 I Gani seel ct most significant bit TTL logic levels with compliance to AVCC.

AVCC 7 p Analog supply

AGNO 8 Analog signalground. Connect to the thermal pad. GVOO

9

0 High-side FET gate drive supply.Nominalvoltage is 7V. Also should be used

as supply for PLIMIT function PLIMIT

10

I Power limti leveladjust Connect a resistor divider from GVOO to GND to set

powerlimit. Connect directly to GVOO for no power limit.

RINN 11 I Negative audio input for right channe.l Biased at 3V.

RINP 12 I Positive audio input for right channeL Biased at 3V. NC 13 Not connected

PBTL 14 I ParallelBTL mode switch PVCCR

15 p Power supply for right channel H-bridge. Right channeland left channelpower

supply inputs are connect internally. PVCCR

16 p Power supply for right channel H-bridge. Right channelandleft

channelpower supply inputs are connect internally. BSPR 17 I Bootstrap 110 for right channel, positive high-side FET.

OUTPR 18 0 Class-0 H-bridge positive output for right channel.

PGNO 19 Power ground for the H-bridges. OUTNR 20 0 Class-0 H-bridge negative output for right channel.

BSNR 21 I Bootstrap 1/0 for right channel, negative high-side FET.

BSNL 22 I Bootstrap 1/0 for left channe,l negative high-side FET.

OUTNL 23 0 Class-0 H-bridge negative output for left channel.

PGNO 24 Power ground for the H-bridges. OUTPL 25 0 Class-0 H-bridge positive output for left channeL

BSPL 26 I Bootstrap 1/0 for left channe,l positive high-side FET. PVCCL

27 p Power supply for left channelH-bridge. Right channel and left channel power

supply inputs are connect internally. PVCCL

28 p Power supply for left channelH-bridge. Right channel and left channel power

supply inputs are connect internally.

5 Power stage The DC voltages required at various parts of the chassis and panel are provided by a main power supply unit. MB62 chassis can operate with IPS60, IPS16, IPS17, PW26, PW27 as main power supply and also with 12V adaptor.

CN706 is used for IPS60, IPS16 and IPS17 and CN1 is used for PW26 and PW27.

JK9 is used for the adapter option and also CN705 inverter socket or DB32 chassis with CN706 is used to supply backlight.

The power supplies generate 18V, 12V, 5V, 3,3V and 12V, 5V, stand by mode DC voltages. Power stage which is on-chassis generates 5V, 3V3 stand by voltage and 12V, 8V, 5V, 3V3, 2.5V, 1,8V and 1,2V supplies for other different parts of the chassis. Chassis block diagram is indicated below.

The blocks on power block diagram is using dependent to main supply. For PW26 and PW27 just common blocks are enough for proper operation.

For IPS16, IPS17, IPS60 below blocks must work properly.

For adopter case also below blocks are necessary.

Short CCT Protection Circuit

Short circuit protection is necessary for protecting chassis and main IC against damages when any Vcc supply shorts to ground. Protect pin should be logic high while normal operation. When there is a short circuit protect pin shold be logic low. After any short detection, SW forces LEDs on LED card to blink.

5.1 Power management

---MB62 Power Management with Adaptor---

---MB62 Power Management with PW25/ PW26---

---MB62 Power Management with IPS16/IPS17/IPS60/PW05---

---MB62 Power Management with PW03/PW04/PW07---

6 Microcontroller – MSTAR (U5)

6.1 Description MSD9WB9PT-2 (Main IC) (U5)

The MSD9WB9PT-2 is MStar’s most up-to-date system-on-chip solution for flat panel integrated digital television products. Building on the success of MStar’s preceding SOC series, the MSD9WB9PT-2 provides most cost-effective solution for DTV application with creative and attractive features exclusively presented by MStar. The MSD9WB9PT-2 integrates DTV/multi-media all-purpose AV decoder, DVB-T demodulator, VIF demodulator, and Sound/Video processor into a single device. This allows the overall BOM to be reduced significantly making the MSD9WB9PT-2 a very competitive multi-media DTV solution. For ATV users, the MSD9WB9PT-2 provides multi- standard analog TV support with adaptive 3D video decoding and VBI data extraction. The build-in audio decoder is capable of decoding FM, AM, NICAM, A2, BTSC and EIA-J sound standards. The MSD9WB9PT-2 supplies all the necessary A/V inputs and outputs to complete a receiver design including a multi-port HDMI receiver and component video ADC. All input selection multiplexed for video and audio are integrated, including full SCART support with CVBS output. The equipped MStar MACE-5 color engine is the latest masterpiece from MStar famous color engine series providing excellent video and picture quality in Full-HD and large-scale displaying system. To meet the increasingly popular energy legislative requirements without the use of additional hardware, the MSD9WB9PT-2 has an ultra low power standby mode during which an embedded MCU can act upon standby events and wake up the system as required.

The MSD9WB9PT-2 is composed of several modules:

High Performance Micro-processor

o Ultra high speed/performance 32-bit RISC CPU o One full duplex UARTs o Supports USB and ISP programming o DMA Engine

Transport Stream De-multiplexer o Supports parallel and serial TS interface, with or without sync signal o Supports TS input and output for external CI module o Maximum TS data rate is 104 Mb/sec for serial or 16 MB/sec for parallel o 32 general purpose PID filters and section filters for each transport stream

de-multiplexer o Supports additional audio/video/PCR filters o Supports TS DMA channel for time-shift o Supports 3DES/DES and AES encryption/decryption

MPEG-2 Video Decoder o ISO/IEC 13818-2 MPEG-2 video MP@HL o Automatic frame rate conversion o Supports resolution up to HDTV (1080i, 720p) and SDTV

MPEG-4 Video Decoder

o ISO/IEC 14496-2 MPEG-4 ASP video decoding o Supports resolutions up to HDTV (1080p@30fps) o Supports DivX1 Home Theater & HD profilesOptional o Supports VC-1Optional, FLV video format decoding

Hardware JPEG o Supports sequential mode, single scan o Supports both color and grayscale pictures o Following the file header scan the hardware decoder fully handles the

decode process o Supports programmable Region of Interest (ROI) o Supports formats: 422/411/420/444/422T o Supports scaling down ratios: 1/2, 1/4, 1/8 o Supports picture rotation

NTSC/PAL/SECAM Video Decoder o Supports NTSC-M, NTSC-J, NTSC-4.43, PAL (B,D, G, H, M, N, I, Nc),

and SECAM standards o Automatic standard detection o Motion adaptive 3D comb filter o Five configurable CVBS & Y/C S-video inputs o Supports Teletext, Closed Caption (analog CC 608/ analog CC 708/digital

CC 608/digital CC708), V-chip and SCTE Multi-Standard TV Sound Processor

o SIF audio decoding o Supports BTSC/A2/EIA-J demodulation o Supports NICAM/FM/AM demodulation o Supports MTS Mode Mono/Stereo/SAP in BTSC/ EIA-J mode o Supports Mono/Stereo/Dual in A2/NICAM mode o Built-in audio sampling rate conversion (SRC) o Audio processing for loudspeaker channel, including volume, balance,

mute, tone, EQ,virtual stereo/surround and treble/bass controls o Advanced sound processing options available,for example: SRS1, BBE2,

QSound3, Audyssey4 o Supports digital audio format decoding:

MPEG-1, MPEG-2 (Layer I/II), MP3, Dolby Digital (AC-3), AAC-LC Supports Optional Dolby Digital Plus, Dolby mPulse, and MS10

multistream decoder, including Dolby Digital Encoder for transcoding streams to Dolby Digital 5.1 (DDCO)

Supports MPEG Audio, Dolby Digital, Dolby Digital Plus format AD (Audio Description)

o Supports PVR and time-shifting Audio Interface

o One SIF audio input interface with minimal external saw filters o Four L/R audio line-inputs o Two L/R outputs for main speakers and additional line-outputs o Supports stereo headphone driver o I2S digital audio input & output o S/PDIF digital audio output o HDMI audio channel processing o Programmable delay for audio/video synchronization

o Analog RGB Compliant Input Port o Three analog ports support up to 1080P o Supports PC RGB input up to SXGA@75Hz o Supports HDTV RGB/YPbPr/YCbCr o Supports Composite Sync and SOG Sync-on-Green o Automatic color calibration o AV-link support o Analogue RGB Auto-Configuration & Detection o Auto input signal format and mode detection o Auto-tuning function including phasing, positioning, offset, gain, and jitter

detection o Sync Detection for H/V Sync

DVI/HDCP/HDMI Compliant Input Port o Two HDMI/DVI Input ports o HDMI 1.3 Compliant o HDCP 1.1 Compliant o 225 MHz @ 1080P 60 Hz input with 12-bit Deep-color support o CEC support o Single link DVI 1.0 compliant o Robust receiver with excellent long-cable support

MStar Advanced Color Engine (MStarACE-5) 10/12-bit internal data processing Fully programmable multi-function scaling engine

o Nonlinear video scaling supports various modes including Panorama o Supports dynamic scaling for VC-1

High-Quality DTV video processor o 3D motion video deinterlacer with motion object stabilizer o Edge-oriented deinterlacer with edge and artifact smoother o Automatic 3:2/2:2/M:N pull-down detection and recovery o 3D multi-purpose noise reduction for DTV or lousy air/cable input o MPEG artifact removal including de-blocking and mosquito noise

reduction o Arbitrary frame rate conversion

MStar Professional Picture Enhancement: o Dynamic brilliant and fresh color o Dynamic Blue Stretch o Intensified contrast and details o Dynamic Vivid Skin o Dynamic sharpened Luma/Chroma edges o Global and local dynamic depth of field perception o Accurate and independent color control o Supports sRGB and xvYCC color processing o Supports HDMI 1.3 deep color format

Programmable 12-bit RGB gamma CLUT Output Interface

o Single/dual link 8/10-bit LVDS output o Supports panel resolution up to Full-HD (1920x1080) @ 60Hz o Supports TH/TI format o Supports dithering options to 6/8-bit output o Spread spectrum output for EMI suppression

CVBS Video Encoder o Supports all NTSC/PAL TV Standard o Stand-alone scaling engine o Programmable Hue, Contract, Brightness o Supports TTX/CC/WSS output

o CVBS Video Output

o Allows CVBS output of all source inputs 2D Graphics Engine

o Hardware Graphics Engine for responsive o Interactive applications o Supports point draw, line draw, rectangle draw/fill, text draw and trapezoid

draw o BitBlt, stretch BitBlt, trapezoid BitBlt, mirror BitBlt and rotate BitBlt o Raster Operation (ROP) o Support Porter-Duff

VIF Demodulator o Compliant with NTSC M/N, PAL B, G/H, I, D/K, SECAM L/L' standards o Audio/Video dual-path processor o Stepped-gain PGA with 25 dB tuning range and 1 dB tuning resolution o Maximum IF gain of 37 dB o Programmable TOP to accommodate different tuner gain and SAW filter

insertion loss to optimize noise and linearity performance o Multi-standard processing with single SAW o Supports silicon tuner low IF output architecture

DVB-T Demodulator o Digital carrier frequency offset correction: ±500KHz o Optimised for SFN channels with pre/post-cursive echoes inside/outside

the guard o Acquisition range ±857kHz includes up to 3x ±1/6 MHz transmitter offset o Meets Nordig Unified 1.0.3, D-Book 5.0, EICTA E-Book/C-Book test

requirement o ±400kHz internal carrier offset recovery range o 6.8 usecs echo cancellation at 7 Msym/s o Supports IF, low-IF, zero-IF inputs o Ultra-fast automatic blind UHF/VHF channel scan (constellations and

symbol rate) Connectivity

o Two USB 2.0 host ports o USB architecture designed for efficient support of external storage

devices in conjunction with off air broadcasting Miscellaneous

o DRAM interface supporting one 16-bit DDR2 @1066MHz o Supports PVR o Supports Common Interface for conditional access support o Bootable SPI interface with serial flash support o Parallel interface for external NAND flash support o Power control module with ultra low power MCU available in standby

mode o 380-ball LFBGA package o Operating Voltages: 1.26V (core), 1.8V (DDR2), 2.5V and 3.3V (I/O and

analog)

6.2 MSTAR block diagram

6.3 Reset circuit Reset circuit using for initiliazing main Mstar IC. Reset condition is high and nomal working condition is low for RESET pin.

7 CI interface CI Interface Power Switch: It is used for CI module supply, when Module is inserted (it means CI detect is low) This circuit is opened or closed by CI_POWER_CTRL port of main uController

8 USB interface Main Concept IC has integrated 2 USB 2.0 interface. One of them is used for ethernet function, the other one is used for USB connectivity for last user. Last user can play video, picture and audio files. Also digital channels can be record to external storage device by this interface. All SW files can be updated with interface.

USB circuit has 3 main parts Integrated USB 2.0 Host interface of D3K (U5) Protection IC (U145) Over current protection IC (U8)

9 DDR2 SDRAM K4T1G164QF (U155)

9.1 Description The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed to comply with the following key DDR2 SDRAM features such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver (OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the crosspoint of differential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 1Gb (x8) device receive 14/10/3 addressing. The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1 Gb DDR2 device is available in 60 ball FBGA(x8) and 84ball FBGA(x16).

9.2 Features

JEDEC standard VDD = 1.8V ± 0.1V Power Supply VDDQ = 1.8V ± 0.1V 533MHz fCK for 1066Mb/sec/pin 8 Banks Posted CAS Programmable CAS Latency: 4, 5, 6, 7 Programmable Additive Latency: 3, 4, 5. 6 Write Latency(WL) = Read Latency(RL) -1 Burst Length: 4 , 8(Interleave/nibble sequential) Programmable Sequential / Interleave Burst Mode Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional

feature) Off-Chip Driver(OCD) Impedance Adjustment On Die Termination Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High Temperature Self-Refresh rate enable Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE <

95°C All of products are Lead-free, Halogen-free, and RoHS compliant

OQ14 UOM

OQ9 VooQ

OQ12

VooQ

OQ3

UOQS

UOQS DQ15

VoDQ

OQ13

LDQS

OQ7

VoDQ DQO

OQ2 OQ5

Voo

OOT

Voo

•••

Pinning

1 2 3 7 8 9

Ball Locations (x16) 1 2 3 4 s 6 8 9

AB ••••••++++++•·••••• cD •••+++•· ••

• Populated ball + Ball not populated

Top view (See the balls throughpackage)

E•••++++•• •• H •••+++•· ••

KJ +••+++•·• • ML +•••••++++•· •+• N •••+++•· •+ pR +•••••+++•· •+•

10 Scaler and LVDS sockets

10.1 LVDS sockets block diagram

10.2 Panel supply switch circuit This switch is used to open and close panel supply of TCON. It is controlled by port of main ucontroller. Also with this circit panel sequency could be adjusted correctly. 3 panel supplys are connected to this circuit. All of them are optional according to panels.

11 SPI flash memory - MX25L1005 (U158)

11.1 General Description MX25L1005 is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The MX25L1005 feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). SPI access to the device is enabled by CS# input. The MX25L1005 provide sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector(4K-bytes) or block(64K-bytes). To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC current. The MX25L1005 utilize MXIC's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

11.2 Features Serial Peripheral Interface (SPI) compatible -- Mode 0 and Mode 3 1,048,576 x 1 bit structure 32 Equal Sectors with 4K byte each, Any Sector can be erased individually 2 Equal Blocks with 64K byte each, Any Block can be erased individually Single Power Supply Operation

2.7 to 3.6 volt for read, erase, and program operations Latch-up protected to 100mA from -1V to Vcc +1V Low Vcc write inhibit is from 1.5V to 2.5V

11.3 Absolute maximum ratings

RATING VALUE Ambient Operating Temperature

0°C to 70°C

Storage Temperature -55°C to 125°C Applied Input Voltage -0.5v to 4.6v Applied Output Voltage -0.5v to 4.6v

VCC to Ground Potential -0.5v to 4.6v

11.4 Pinning 8-PIN SOP (150mil)

SYMBOL DESCRIPTION CS# Chip select SI Serial Data Input SO Serial Data Output SCLK Clock Input HOLD# Hold, to pause the device without

deselecting the device VCC +3.3v Power Supply

GND Ground

12 NAND Flash memory – NAND512XXA2C (U162)

12.1 General Description The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that uses the single level cell (SLC) NAND technology. It is referred to as the small page family.

The NAND512R3A2C, NAND512R4A2C, and NAND512W3A2C have a density of 512 Mbits and operate with either a 1.8 V or 3 V voltage supply. The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.

To extend the lifetime of NAND flash devices it is strongly recommended to implement an error correction code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A write protect pin is available to give a hardware protection against program and erase operations.

12.2 Features High density NAND flash memories

o 512-Mbit memory array o Cost effective solutions for mass storage applications

NAND interface

o x8 or x16 bus width o Multiplexed address/ data

Supply voltage: 1.8 V, 3 V Page size

o x8 device: (512 + 16 spare) bytes o x16 device: (256 + 8 spare) words

Block size

o x8 device: (16K + 512 spare) bytes o x16 device: (8K + 256 spare) words

Page read/program

o Random access: 12 μs (3 V)/15 μs (1.8 V) (max) o Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min) o Page program time: 200 μs (typ)

Copy back program mode Fast block erase: 2 ms (typ)

Status register Electronic signature Chip Enable ‘don’t care’ Security features

o OTP area

Serial number (unique ID) option Hardware data protection

o Program/erase locked during power transitions

Data integrity o 100,000 program/erase cycles (with ECC) o 10 years data retention

RoHS compliant packages Development tools

o Error correction code models o Bad blocks management and wear leveling algorithms

12.3 Pinning

13 LNBH23L (U6)

13.1 Description Intended for analog and digital satellite receivers,the LNBH23L is a monolithic voltage regulator and interface IC, assembled in QFN32 5 x 5 specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dish or to the multi-switch box. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing.

13.2 Features

Complete interface between LNB and I²C bus

Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A)

Selectable output current limit by external resistor

Compliant with main satellite receivers output voltage specification

Auxiliary modulation input (EXTM pin) facilitates DiSEqC™ 1.X encoding

Accurate built-in 22 kHz tone generator suits widely accepted standards

Low-drop post regulator and high efficiency step-up PWM with integrated power

NMOS allow low power losses

Overload and over-temperature internal protections with I²C diagnostic bits

LNB short circuit dynamic protection

+/- 4 kV ESD tolerant on output power pins

13.3 Block diagram

14 Advanced DVB-S/S2 demodulator M88DS3002 (U3)

14.1 Description The M88DS3002 is an advanced single-chip demodulator for digital satellite television broadcasting. It is fully compliant with the DVB-S/S2 standard and can support QPSK, 8PSK, 16APSK and 32APSK demodulation schemes. The chip provides a fast, easy-to- apply and cost-effective front-end solution for digital satellite receiver. The M88DS3002 accepts baseband differential or single ended I and Q signals from a tuner, then digitizes, demodulates and decodes the signals, and finally outputs an MPEG transport stream. The M88DS3002 supports symbol rate from 1 Msps up to 45 Msps, and code rate from 1/4 to 9/10. Its features cover blind scan, fade detection, timing and carrier recovery, performance monitoring, co-channel interference cancellation, command interface, and DiSEqC™ 2.X interface, etc. The device is controlled via a 2-wire serial bus. The M88DS3002 works properly with 1.25 V and 3.3 V voltage supplies. Typically, the power consumption is around 390 mW. The chip is available in a 64-pin QFN package and is RoHS compliant.

14.2 Features

Multi-standard demodulation Compliant with DVB-S/S2 specification QPSK, 8PSK, 16APSK and 32APSK demodulation schemes Maximum channel bit rate is 130 Mbps Maximum symbol rates are: 45 Msps for QPSK and 8PSK; 36 Msps for 16APSK

and 28 Msps for 32APSK

• DSP features

Symbol rate sweeping I/Q impairment cancellation Automatic spectrum inversion Adaptive equalizer for RF reflection removal Roll-off factor automatic identification Blind scan for programming search High performance on-chip micro-controller Multi-error monitor Accurate SNR estimation Multi-lock indicators Clipping rate reporter DC removal Automatic frequency correction (AFC) Fast timing loop acquisition Robust frame synchronization scheme Phase noise indicator Fast system recovery from fading or other abnormal conditions Co-channel interference cancellation Constellation monitor

Interface

DVB-S/S2 common, parallel and serial MPEG output interface compliant 2-wire serial bus to configure the device 2-wire bus repeater for tuner configuration DiSEqC™ 2.X compliant interface General purpose output (GPO) Dedicated reference clocks (13.5MHz / 27MHz) generation

System o On-chip 8-bit ADC o On-chip PLL for master clock from a 27 MHz external clock or quartz

crystal o Sleep mode supported

---Block Diagram of M88DS3002---

14.3 Pin Assignment

15 LM1117 (U175, U180, U181)

15.1 General description The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V. The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT- 223, TO-220, and TO-252 D-PAK packages. A minimum of 10μF tantalum capacitor is required at the output to improve the transient response and stability.

15.2 Features Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions Space Saving SOT-223 Package Current Limiting and Thermal Protection Output Current 800mA Line Regulation 0.2% (Max) Load Regulation 0.4% (Max) Temperature Range LM1117 0°C to 125°C LM1117I -40°C to 125°C

15.3 Applications 2.85V Model for SCSI-2 Active Termination Post Regulator for Switching DC/DC Converter High Efficiency Linear Regulators 15 32” TFT TV Service Manual 10/01/2005 Battery Charger Battery Powered Instrumentation

15.4 Absolute maximum ratings

15.5 Pinning

16 MP2012 (U176)

17 General description The MP2012 is a fully integrated, internally compensated 1.2MHz fixed frequency PWM step-down converter. It is ideal for powering portable equipment that runs from a single cell Lithium-Ion (Li+) Battery, with an input range from 2.7V to 6V. The MP2012 can provide up to 1.5A of load current with output voltage as low as 0.8V. It can also operate at 100% duty cycle for low dropout applications. With peak current mode control and internal compensation, the MP2012 is stable with ceramic capacitors and small inductors. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown.

17.1 Features 2.7-6V Input Operation Range Output Adjustable from 0.8V to VIN 1 μA Max Shutdown Current. Up to 95% Efficiency 100% Duty Cycle for Low Dropout Applications 1.2MHz Fixed Switching Frequency Stable with Low ESR Output Ceramic Capacitors Thermal Shutdown Cycle-by-Cycle Over Current Protection Short Circuit Protection Available in 6-pin 3x3mm QFN

17.2 Pinning

Pin #

Name Description

1 FB Feedback input. An external resistor divider from the output to GND, tapped to the FB pin sets the output voltage.

2 GND, Exposed

Pad

Ground pin. Connect exposed pad to ground plane for proper thermal performance.

3 SW Switch node to the inductor. 4 PVIN Input supply pin for power FET. 5 VIN Input Supply pin for controller. Put small

decoupling ceramic near this pin. 6 EN Enable input, “High” enables MP2012. EN is

pulled to GND with 1Meg internal resistor.

18 RTA8283A (U23, U173)

18.1 General description The RT8283A is a high-efficiency, monolithic synchronous step-down DC/DC converter that can deliver up to 3A output current from a 4.5V to 23V input supply. The RT8283A's current mode architecture and external compensation allow the transient response to be optimized over a wide range of loads and output capacitors. Cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. The RT8283A also provides output under voltage protection and thermal shutdown protection. The low current (<3μA) shutdown mode provides output disconnect, enabling easy power management in batterypowered systems. The RT8283A is available in a SOP-8 package.

18.2 Features ±1.5% High Accuracy Feedback Voltage Integrated N-MOSFET Switches Current Mode Control Fixed Frequency Operation : 340kHz Output Adjustable from 0.8V to 20V Up to 95% Efficiency Thermal Shutdown Protection

18.3 Pinning

Pin No. Pin

Name Description

1 BOOT Bootstrap for high-side gate driver. Connect a 0.1μF or greater ceramic capacitor from BOOT to SW pins.

2 VIN Input Supply 4.5V to 23V. Must bypass with a suitably large ceramic capacitor.

3 SW Phase Node--Connect to external L-C filter.. 4, 9 (Exposed

Pad) GND Ground.

5 FB Feedback Input pin is connected to the converter output. It is used to set the output of the converter to regulate to the desired value via an internal res divider. For an adjustable output, an external res divider is connected to this pin.

6 COMP Compensation Node. COMP is used to compensate the regulation Control loop. Connect a series RC network from COMP to GND. In some cases, an additional capacitor from COMP to GND is required.

7 EN Enable Input Pin. Logic high enables the converter; a logic low forces the RT8253A into shutdown mode. Attach this pin to VIN with a 100kΩ pull up resistor for automatic startup.

8 SS Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 13.5ms.

19 MP1583 (U174)

19.1 General description The MP1583 is a step-down regulator with a built-in internal Power MOSFET. It achieves 3A of continuous output current over a wide input supply range with excellent load and line regulation. Current mode operation provides fast transient response and eases loop stabilization. Fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. An adjustable soft-start reduces the stress on the input source at start-up. The MP1583 requires a minimum number of external components, providing a compact solution.

19.2 Features 3A Output Current Programmable Soft-Start 100mΩ Internal Power MOSFET Switch Stable with Low ESR Output Ceramic Capacitors Up to 95% Efficiency 20μA Shutdown Mode Fixed 385KHz Frequency Thermal Shutdown Cycle-by-Cycle Over Current Protection Wide 4.75V to 23V Operating Input Range Output Adjustable from 1.22V to 21V Under-Voltage Lockout

19.3 Pinning

Pin No.

Pin Name

Description

1 BOOT High-Side Gate Drive Bootstrap Input. BS supplies the drive for the high-side N-Channel MOSFET switch.

2 IN Power Input. Drive IN with a 4.75V to 23V power source. 3 SW Power Switching Out is the switching node that supplies power to the

output 4 GND Ground. 5 FB Feedback Input. FB senses the output voltage and regulates it. Drive

FB with a resistive voltage divider from the output voltage. FB threshold is 1.222V.

6 COMP Compensation Node is used to compensate the regulation control loop.

7 EN Enable/UVLO. A voltage greater than 2.71V enables operation. For complete low current shutdown the EN pin voltage needs to be at less than 900mV. When the voltage on EN exceeds 1.2V, the internal regulator will be enabled and the soft-start capacitor will begin to charge. The MP1583 will start switching after the EN pin voltage reaches 2.71V.

8 SS Soft-Start Control Input. SS controls the soft-start period.

20 FDC642

20.1 General description This P-Channel 2.5V specified MOSFET is produced using Fairchild’s advanced PowerTrench® process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance.

These devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the larger packages are impractical.

20.2 Features Max rDS(on) = 65 mΩ at VGS = -4.5 V, ID = -4.0 A Max rDS(on) = 100 mΩ at VGS = -2.5 V, ID = -3.2 A Fast switching speed Low gate charge (11nC typical) High performance trench technology for extremely low rDS(on) SuperSOTTM-6 package: small footprint (72% smaller than standard

SO-8); low profile (1 mm thick) Termination is Lead-free and RoHS Compliant

20.3 Pinning

21 FDC604P

21.1 General description This P-Channel 1.8V specified MOSFET uses Fairchild’s low voltage PowerTrench process. It has been optimized for battery power management applications.

21.2 Features –5.5 A, –20 V. RDS(ON) = 33 mΩ @ VGS = –4.5 V RDS(ON) = 43 mΩ @ VGS = –2.5 V RDS(ON) = 60 mΩ @ VGS = –1.8 V Fast switching speed. High performance trench technology for extremely low RDS(ON)(S)

21.3 Pinning

22 Connectors

22.1 SCART (SC1)

22.2 HDMI (CN707, CN708)

22.3 VGA (CN711)

23 Customer service mode (CSM) To enter the Customer Service Mode, press “MENU-1-2-3-6-5-4” keys consecutively, on the remote control. The read-only top-level service menu will appear. Pressing theRETURN or MENU key will exit service menu.

24 Service menu mode

To enter the service menu, press “MENU-4-7-2-5” keys consecutively, on the remote control. The top-level service menu will appear. All submenus can be selected via Up/Down keys and displayed by pressing OK key. When a submenu is displayed, top-level service menu disappears. Pressing RETURN key, returns to the one level higher menu. Pressing the MENU key will exit service menu.

Some items are changeable at service menu, the values of which are stored in the NVM when the menu is closed. Some items are read-only, which can only be changed by Profile Manager and displayed in service menu for convenience.

24.1 Main service menu Service menu or a sub-menu is displayed on the screen when the TV is in one of the TV/AV/PC modes. It shows what the items are set in Profile Manager. It is a read-only screen, not writable.

It shows the following items:

• TV Life Time: The number of minutes the set is in the “On” mode.

• Standby SW Version: The version number of the Stand-by software.

• Mboot Version: The version number of the Mboot software.

• PANEL: The LCD panel identification including the software version information.

• PQ: Picture quality tool version information.

• PROFILE: TV specific option profile

• PIX FILES: Not applicable

• HW Profile Version: The version number of the hardware profile.

• SW Profile Version: The version number of the software profile.

• Lan Profile Version: The version number of the Lan profile.

• Customer: Philips

Items exist in the main screen of service menu. Also, software version number and DCF id are written in the header of service menu.

The main items in Service Menu:

24.2 Video Settings RF AGC adjustments for neighbour and image channels exist or don't. Also, ADC Calibration gain

and offset values for RGB separately due to selected sources

24.3 Audio Settings Surround type and surround mode text items are displayed.

24.4 Options 1 Profile options such as AUTO TV off time, Power up mode, EPG type, etc. are displayed in options 1.

24.5 Options 2 Profile options such as APS sorting, Dynamic Menu, Auto zoom mode etc. are displayed in Options 2.

24.6 Tuning Settings Tuner type is displayed.

24.7 Source Settings Enable and disabled sources are displayed.

When TV is disabled, Items which are connected to Tuner are picked off from menu. (Install and Retune Menu, Channel List Menu...).

24.8 Diagnostic The result of various diagnostic tests are displayed here.

24.9 USB operations USB operations are performed by pressing that button.

See Service Menu Design Idea for Menu structure, look and feel, position, etc…

Video Settings RF AGC SECAM

RF AGC NEIGHBOUR NO IMAGE NO

RF AGC NEIGHBOUR NO IMAGE YES

RF AGC NEIGHBOUR YES IMAGE NO

RF AGC NEIGHBOUR YES IMAGE YES

RF AGC

ADC Calibration Source

ADC Calibration R Gain

ADC Calibration G Gain

ADC Calibration B Gain

ADC Calibration R Offset

ADC Calibration G Offset

ADC Calibration B Offset

Audio Settings Surround Type

Surround Mode Text

Options 1 Auto TV OFF

Power Up mode

Backlight Trick Mode

Cable Support

EPG Type

Hotel Mode

LCN

PC Standby

Stby Search

Test Tool

Local Key

Volume Level

Options 2 Aps Sorting

Dynamic Menu

EPG Menus

Transparent Text

HDMI Number

Remote control type

DCF ID

Tuning Settings Tuner Type

Source Settings TV

EXT1

EXT2

EXT2-S

FAV

S-VIDEO

HDMI 1

HDMI 2

HDMI 3

HDMI 4

YPBPR

VGA/PC

Blu-ray

Diagnostic Remote control test

UHF test

VHF test

Factory reset

Tuner I2C

IF I2C

HDMI I2C

Ethernet

EDID Status

HDCP Status

DDR Settings

CI+ Credentials

MAC Address

USB Operations Press this button to perform USB operations.

USB stick should be connected before this operation.

24.10 Profile Operations VES1.1E LA profile data are kept in the flash file system as separate files. So they can be downloaded to USB memory stick or uploaded to TV from a memory stick individually.

24.10.1 Upload profile Data from USB 1. Create a folder named profile in the USB stick. 2. Copy mb62_swprofile.bin and mb62_hwprofile.bin into the USB profile folder. 3. Plug the USB stick into the TV. 4. Open service menu and select “USB Operations”.

The files will be automatically copied to the TV flash file system.

After a reboot, App/Mw will start to use new profiles. It is possible to upload hardware or software profiles separately.

24.10.2 PQ Files Operations It is also possible to download/upload PQ files from/into MB62 when USB Operations button in service

menu is pressed.

Whenever a USB stick is connected to TV set and USB Operations button in service menu is pressed, /pq folder is checked.

If it exists and if they include some files, necessary copy/delete operations are performed.

24.10.3 Upload PQ files from USB

1. Create a folder named “pq” in the USB stick. 2. Copy VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin and Titania2_Main_Text.bin into USB “pq”

folder. 3. Connect USB stick to TV. 4. Open service menu, select “USB Operations”.

The files named VESTEL_D1_Plus_PNL.bin, Titania2_Main.bin, Titania2_Main_Ex.bin and Titania2_Main_Text.bin will be copied from USB to TV.

24.10.4 Ci+ credentials key update 1. Create a “spi” folder in root of the memory stick 2. Copy mb62_credentials.bin to “spi” folder 3. Connect the USB stick to the TV.

4. Perform USB Operations in the service menu.

24.10.5 HDCP keys update 1. Create a “spi” folder in roof of the memory stick. 2. Copy “mb62_hdcp.bin” to “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

24.10.6 Edid update 1. Create a “spi” folder in root of the memory stick. 2. Copy “edid.edid” to the “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

24.10.7 DDR settings update 1. Create a “spi” folder in root of the memory stick. 2. Rename the ddr binary file to be used which resides in the config_mb62 folder as mb62_ddr.bin. 3. Copy the file “mb62_ddr.bin” to the “spi” folder. 4. Connect the USB stick to the TV. 5. Perform USB operations in the service menu.

24.10.8 MAC address update 1. Create “spi” folder in root of the memory stick. 2. Copy the file “mb62_mac.bin” to the “spi” folder. 3. Connect the USB stick to the TV. 4. Perform USB operations in the service menu.

25 Software update In the VES1.1E LA there is only one software package. From following steps software update procedure can be seen:

1. MB62_en.bin, mboot.bin and usb_auto_update_T4.txt documents should copy directly

inside of a flash memory(not in a folder). 2. Put flash memory to the tv when tv is powered off. 3. Power on the and wait when the tv is opened. 4. If first time installation screen is displayed, it means software update procedure is

successful.

26 Troubleshooting

26.1 No backlight problem Problem: If TV is working, led is normal and there is no picture and backlight on the panel.

Possible couses: Backlight pin, dimming pin, backlight supply, stby on/off pin

Backlight pin should be high in open position. If it is low, please check Q181 and panel cables.

Dimming pin should be high or square wave in open position. If it is low, please check S16 for Mstar side and panel or power cables, connectors.

Backlight power supply should be in panel specs. Please check CN705 for MB62, related connectors for power supply cards.

STBY_ON/OFF should be low for standby on condition, please check R1677.

26.2 CI module problem Problem: CI is not working when CI module inserted.

Possible couses: Supply, suply control pin, detect pins, mechanical positions of pins CI supply shoul be 5V when CI module inserted. If it is not 5V please check CI_POWER_CTRL, this pin should be low.

PCM

".

Please check mechanical positions ofCI module.

Detect ports should be low. If it is not low please check Cl connector pins, Cl module pins and 3V3_VCC on MB62.

R1632

PCM D3 PCM D4

4 PCM DS

Cl Detect PCM D6

7 PCM CB N 8 PCM AlO

PCM OB_N 10 PCM All 11 PCM A9 12 PCM AS 13 PCM A13 14 PCM A14 3V3_VCC

21 22 23 12p 24 sov 25

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Cl Detect 30

'A 31

26.3 LED blinking problem Problem: LED blinking, no other operation

This problem indicates a short on Vcc voltages. Protect pin should be logic high while normal operation. When there is a short circuit protect pin will be logic low. If you detect logic low on protect pin, unplug the TV set and control voltage points with a multimeter to find the shorted voltage to ground.

26.4 IR problem Problem: LED or IR not working Check LED card supply on MB62 chasis.

LED SOCKET Ql70

L--<J SV STBY F259

+----·2-- - -·[>IR IN C949 600R

· H

N

Ql7l

26.5 Keypad touchpad problems Problem Keypad or Touchpad is not working.

@ .-< BC949B

Check keypad supply and keyboard pin on the SSB.

26.6 USB problems Problem: USB is not working or no USB Detection.

Check USB Supply, It should be nearly 5V.

26.7 No sound problem Problem: No audio at main TV speaker outputs.

Check supply voltages of VDD_AUDIO, 5V_VCC and 3V3_VCC with a voltage-meter. There may be a problem in headphone connector or headphone detect circuit (when headphone is connected, speakers are automatically muted). Measure voltage at HP_DETECT pin, it should be 3.3v.

26.8 No sound problem at headphone Problem: No audio at headphone output.

Check HP detect pin, when headphone is. Check 5V_VCC and 3V3_VCC with a voltage- meter.

26.9 Standby On/Off problem Problem: Device cannot boot, TV hangs in standby mode.

There may be a problem about power supply. Check 12V_VCC, 5V_VCC and 3V3_VCC with a voltage-meter. Also there may be a problem about SW. Try to update TV with latest SW. Additionally it is goood to check SW printouts via hyper-terminal (or Teraterm). These printouts may give a clue about the problem.

26.10 DVD problems Problem: DVD is not working.

Check that DVD source is selected in Service menu. Check supply voltage of DVD namely 12V_VCC.

26.11 No signal problem Problem: No signal in TV mode. Check tuner supply voltage; 3V3_TUN. Check tuner options are correctly set in Service menu. Check AGC voltage at IF_AGC pin of tuner.

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MPL

IFIE

R

SAV

Slim

INPU

T

SAV

RCA

INPU

T

PC IN

PUT

1UF

62R

62R

62R

SC S

VHS

opt

62R

3006

4869

NC30

0624

23

3006

2840

Ula

s D

erel

i

17m

b62-

18

RAM

&N

AN

D&C

I

87

65

43

21

A B C D E F

AX

M

12

34

56

78

A B C D E F

OF:

A3

PRO

JECT

NA

ME

:

SCH

NAM

E :

DRA

WN

BY

:

SHEE

T:

14-0

3-20

11_1

7:06

R195

0 10k

4k7R8

R94k7

3V3_

VCC

4k7

R197

1

R16634k71 2

R16184k7 12

TUN

_SCL

_MST

TUN

_SD

A_M

ST

1V8_

VCC

DD

R18V

R10

4k7

16V100n

C913

330R F8

12

3V3_

TUN

ER

IF_A

GC_

MST

R124k7

22R

R131

3

22R

R198

6

R198

722

R

22R

R198

4

R198

522

R

22R

R160

3

F181

60R

R161

3

22R

1 2 3 45678

R1 R2 R3 R4O

VER_

CU

R_D

ETEC

T

R161

0

22R

1 2 3 45678

R1 R2 R3 R4

50V

4p7C9

67

3V3_

VCC

R117

24k

7

33R

R142

5

R142

733

R

100R R5

C905

10V

100n

R33

33R

C71

2

10V

100n

12C

709

10V

100n

12C7

1010

0n10

V12

R6 100R

VCC

_PC

MC

IA

10V

220n

C121

4

DD

R18V

AVD

D_D

DR

R13561k

22R

R136

71 2 3 4

5678R1 R2 R3 R4

1kR1

365

DD

R18V

1kR1355

220n 10

V

C683

1kR1

364

C715

220n 10

V22

0n 10V

C714

10V

220n

C716

C711

220n 10

V

C713 10

V22

0n

DD

R18V

C5V6

D205

22R

R198

2

R138

0

22R

1 2 3 45678

R1 R2 R3 R4

R137

0

22R

1 2 3 45678

R1 R2 R3 R4R136

6

22R

1 2 3 45678

R1 R2 R3 R4

R160

9

22R

1 2 3 45678

R1 R2 R3 R422R

R136

91 2 3 4

5678R1 R2 R3 R4

U155HY5PS121621C

J1

R1

M9

J9

E1

A1

G9

G7

G3

G1

E9

C9

C7

C3

C1

A9

J2

J7

H8

H2

F8

F2

E7

D8

D2

B8

B2

A7

P9N1

J3E3A3

K9K8J8K2L8K3L7K7L3L2R2P7M2

P3P8P2N7

N3

N8

N2

M7

M3

M8

R8R7R3L1E2A2

B3A8

B7B9B1D9

D1

D3

D7

C2C8F9F3E8F7F1H9

H1

H3

H7

G2

G8

DQ

0

DQ

1

DQ

2

DQ

3

DQ

4

DQ

5

DQ

6

LQD

S

LQD

S_P

LDM

DQ

7

DQ

8

DQ

9

DQ

10

DQ

11

DQ

12

DQ

13

DQ

14

DQ

15

UD

QS

UD

QS_

P

UD

M

NC

1

NC

2

NC

3

NC

4

NC

5

NC

6

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

BA0

BA1

RAS_

P

CA

S_P

WE_

P

CS_P CK

E CK

CK_P OD

T

VSS1

VSS2

VSS3

VSS4

VSS5

VSSQ1

VSSQ2

VSSQ3

VSSQ4

VSSQ5

VSSQ6

VSSQ7

VSSQ8

VSSQ9

VSSQ10

VSSDL

VREF

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDD1

VDD2

VDD3

VDD4

VDD5

VDDL

3V3_

VCC

R151

333

R

C906

10V

100n

U5

MSD

9WB9

PT-2

C10

D21 A9

E20

B9 E19

C9 F20

B8 F19

D20 C8 F21

C13

A19

A12

B19

A20

B12

C19

A13

B14

C18

C14

A18

B18

B13

B17

C15

A16

C16

A15

B15

B16

C17

C12

B11

C20

B20

B10

A10

C21

B21

D19

C11

F18

MVR

EF

A_O

DT

A_B

AD

R[2]

A_B

AD

R[1]

A_B

AD

R[0]

A_C

ASZ

A_R

ASZ

A_W

EZ

A_M

CLK

EA

_MC

LKZ

A_M

CLK

A_D

QM

[1]

A_D

QM

[0]

A_D

QSB

[1]

A_D

QS[

1]A

_DQ

SB[0

]A

_DQ

S[0]

A_M

DA

TA[1

5]A

_MD

ATA

[14]

A_M

DA

TA[1

3]A

_MD

ATA

[12]

A_M

DA

TA[1

1]A

_MD

ATA

[10]

A_M

DA

TA[9

]A

_MD

ATA

[8]

A_M

DA

TA[7

]A

_MD

ATA

[6]

A_M

DA

TA[5

]A

_MD

ATA

[4]

A_M

DA

TA[3

]A

_MD

ATA

[2]

A_M

DA

TA[1

]A

_MD

ATA

[0]

A_M

AD

R[12

]A

_MA

DR[

11]

A_M

AD

R[10

]A

_MA

DR[

9]A

_MA

DR[

8]A

_MA

DR[

7]A

_MA

DR[

6]A

_MA

DR[

5]A

_MA

DR[

4]A

_MA

DR[

3]A

_MA

DR[

2]A

_MA

DR[

1]A

_MA

DR[

0]1

BSH103Q209

R138

533

R1234

5 6 7 8R1R2R3R4

R117

14k

7

R151

433

R

33R

R140

2

R198

322

R

U5

MSD

9WB9

PT-2

K21

L19

M19

T12

U13

V14

V12

V18

R19

P19

N21

N19

V20

U20

T20

T19

P17

N18

U17

V16

R20

R17

T16

V19

W21

U16

V17

T17

V21

T14

M21

P16

N20

G21

G20

G19

U10 T9 V11

U11 U9

T10

V9

P18

R18

T18

W19

Y21

Y19

R21

T21

Y20

W20

R16

K20

L20

M20

T13

U14

U12

T11

U18

U19

P20

K19

W1

Y1 AA

2Y2 Y3 AA

3

W5

W4

AA

4Y4 W

6Y5

GPI

O69

GPI

O68

GPI

O67

GPI

O66

RF_A

GC

IF_A

GC

SIFM

SIFP

VIFM

VIFPIMIP

TS0S

YNC

TS0V

ALI

DTS

0CLK

TS0D

ATA

[7]

TS0D

ATA

[6]

TS0D

ATA

[5]

TS0D

ATA

[4]

TS0D

ATA

[3]

TS0D

ATA

[2]

TS0D

ATA

[1]

TS0D

ATA

[0]

TS1S

YNC

TS1V

ALI

DTS

1CLK

TS1D

ATA

[7]

TS1D

ATA

[6]

TS1D

ATA

[5]

TS1D

ATA

[4]

TS1D

ATA

[3]

TS1D

ATA

[2]

TS1D

ATA

[1]

TS1D

ATA

[0]

F_RB

Z/G

PIO

136

PF_W

EZ/G

PIO

134

PF_O

EZ/G

PIO

133

PF_C

E1Z/

GPI

O13

2PF

_CE0

Z/G

PIO

131

PF_A

D[1

5]/G

PIO

130

PF_A

LE/G

PIO

135

GPI

O12

7G

PIO

128

GPI

O12

5

PCM

REG

/CI_

CLK

PCM

IOW

/CI_

WR

PCM

WA

IT/C

I_W

ACK

CI_C

DPC

MW

ENPC

MCE

N/C

I_CS

PCM

IOR/

CI_

RDPC

MO

ENPC

M_I

RQ/C

I_IN

T

CI_R

STPC

MA

DR[

14]/

CI_

A[1

4]PC

MA

DR[

13]/

CI_

A[1

3]PC

MA

DR[

12]/

CI_

A[1

2]PC

MA

DR[

11]/

CI_

A[1

1]PC

MA

DR[

10]/

CI_

A[1

0]PC

MA

DR[

9]/C

I_A

[9]

PCM

AD

R[8]

/CI_

A[8

]PC

MA

DR[

7]/C

I_A

[7]

PCM

AD

R[6]

/CI_

A[6

]PC

MA

DR[

5]/C

I_A

[5]

PCM

AD

R[4]

/CI_

A[4

]PC

MA

DR[

3]/C

I_A

[3]

PCM

AD

R[2]

/CI_

A[2

]PC

MA

DR[

1]/C

I_A

[1]

PCM

AD

R[0]

/CI_

A[0

]

PCM

DA

TA[7

]/CI

_DA

TA[7

]PC

MD

ATA

[6]/

CI_D

ATA

[6]

PCM

DA

TA[5

]/CI

_DA

TA[5

]PC

MD

ATA

[4]/

CI_D

ATA

[4]

PCM

DA

TA[3

]/CI

_DA

TA[3

]PC

MD

ATA

[2]/

CI_D

ATA

[2]

PCM

DA

TA[1

]/CI

_DA

TA[1

]PC

MD

ATA

[0]/

CI_D

ATA

[0] 2

DIG

ITA

L_IF

_N

180RR1977

VCC_

PCM

CIA

DIG

ITA

L_IF

_P

12V_

VCC

33R

R139

5

12345 6 7 8

R1R2R3R4

VCC_

PCM

CIA

R117

74k

7

R195

14k

7

CN14

1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

BC84

8BQ

208

1

2

3

VCC_

PCM

CIA

C966

50V

12p

33R

R139

8

12345 6 7 8

R4 R1R3 R2

R164

210

k3V

3_VC

C

3V3_

VCC

10k

R163

2

PCM

_CD

1_N

C968

12p

50V

33R

R139

4

12345 6 7 8

R1R2R3R4

33R

R139

9

12345 6 7 8

R1R2R3R4

R139

633

R1234

5 6 7 8R1R2R3R4

R139

733

R1234

5 6 7 8R1R2R3R4

33R

R139

2

12345 6 7 8

R1R2R3R4

R140

133

R

5V_V

CC

33R

R142

4

R139

333

R

12345 6 7 8

R1R2R3R433

RR1

384

12345 6 7 8

R1R2R3R4

R139

033

R1234

5 6 7 8R1R2R3R4

R151

233

R

10V

C653

100n

12

10V

C654

100n

12

R195

34k

7

3V3_

VCC

CI_

POW

ER_C

TRL

50V

C969

12p

C68

7

10V

220n

R14964k7

3V3_

VCC

R16604k7

12

33R

R194

2

6V3

22u

C970

BACK

LIG

HT_

ON

/OFF

R344

1k2

33kR1605

R160433k

R160

718

k18

kR1

606

HD

MI1

_5V

HD

MI0

_5V

BC84

8BQ

181

1

2

3

R166

14k

71

2

R16621k23V3_VCC

S81

U16

2

NA

ND

512-

A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24252627282930313233343536373839404142434445464748

NC2

9

NC2

8

NC2

7

NC2

6

I/O7

I/O6

I/O5

I/O4

NC2

5

NC2

4

NC2

3

VDD

2

VSS2

NC2

2

NC2

1

NC2

0

I/O3

I/O2

I/O1

I/O0

NC1

9

NC1

8

NC1

7

NC1

6N

C15

NC1

4

NC1

3

NC1

2

NC1

1

WP

WAL

CL

NC1

0

NC9

VSS1

VDD

1

NC8

NC7

ERRBNC6

NC5

NC4

NC3

NC2

NC1

PAN

EL_V

CC_O

N/O

FF

100nC1220

10V1

2

FLH

_3.3

V

F_RB

Z

FLH

_3.3

V

R149

53k

9

3V3_

VCC

60R

F187

100n

10V

C656

12

100n

10V

C657

12

6V3

C868

22u

FLH

_3.3

V FLH

_3.3

V

FLH

_3.3

V

R138

833

R1 2 3 4

5678R1 R2 R3 R4

R138

233

R1234

5 6 7 8R1R2R3R433

RR1

383

12345 6 7 8

R1R2R3R4

R138

933

R1234

5 6 7 8

R4 R1R3 R2

R34

33R

4k7

R47

4k7

R48

R49

4k7

22u

C782

6V3

22R

R133

2

220n

C71

8

10V

R136

8

22R

1 2 3 45678

R1 R2 R3 R4

R50 4k

7

FLH

_3.3

V

AA_D

DR2

_DQ

SB0

AA

_DD

R2_D

QSB

0

AA

_BA

DR_

BA2

AA_B

AD

R_BA

2

AA_M

CLK

AA_M

CLK

AA_M

CLKZ

AA_M

CLKZ

AA_D

DR2

_DQ

SB1

AA

_DD

R2_D

QSB

1

AA_D

DR2

_DQ

S1

AA

_DD

R2_D

QS1

AA_D

DR2

_DQ

S0

AA

_DD

R2_D

QS0

AA

_DD

R2_D

QM

0

AA_D

DR2

_DQ

M0

AA

_DD

R2_D

QM

1

AA_D

DR2

_DQ

M1

AA_

BAD

R_BA

0

AA_B

AD

R_BA

0

AA_

BAD

R_BA

1

AA_B

AD

R_BA

1

AA

_OD

T

AA_O

DT

AA_

WEZ

AA_W

EZ

AA_

RASZ

AA

_RA

SZ

AA_

CASZ

AA

_CA

SZ

AA

_MD

ATA

15

AA_M

DA

TA15

AA

_MD

ATA

14

AA_M

DA

TA14

AA

_MD

ATA

13

AA_M

DA

TA13

AA

_MD

ATA

12

AA_M

DA

TA12

AA

_MD

ATA

11

AA_M

DA

TA11

AA

_MD

ATA

10

AA_M

DA

TA10

AA

_MD

ATA

9

AA_M

DA

TA9

AA

_MD

ATA

8

AA_M

DA

TA8

AA

_MD

ATA

5

AA_M

DA

TA5

AA

_MD

ATA

2

AA_M

DA

TA2

AA

_MD

ATA

0

AA_M

DA

TA0

AA

_MA

DR1

2

AA_

MA

DR1

2

AA

_MA

DR1

1

AA_

MA

DR1

1

AA

_MA

DR1

0

AA_

MA

DR1

0

AA

_MA

DR9

AA_

MA

DR9

AA

_MA

DR8

AA_

MA

DR8

AA

_MA

DR7

AA_

MA

DR7

AA

_MA

DR6

AA_

MA

DR6

AA

_MA

DR5

AA_

MA

DR5

AA

_MA

DR4

AA_

MA

DR4

AA

_MA

DR3

AA_

MA

DR3

AA_

MA

DR2

AA

_MA

DR2

AA

_MA

DR1

AA_

MA

DR1

AA_

MA

DR0

AA

_MA

DR0

A_M

ADR1

2

A_M

AD

R12

A_M

AD

R11

A_M

AD

R11

A_M

ADR1

0

A_M

AD

R10

A_M

ADR9

A_M

ADR9

A_M

AD

R8

A_M

ADR8

A_M

ADR7

A_M

ADR7

A_M

AD

R6

A_M

ADR6

A_M

ADR5

A_M

ADR5

A_M

AD

R4

A_M

ADR4

A_M

ADR3

A_M

ADR3

A_M

ADR2

A_M

ADR2

A_M

ADR1

A_M

ADR1

A_M

ADR0

A_M

ADR0

A_M

DA

TA0

A_M

DA

TA0

MVR

EF

MVR

EF

A_B

AD

R_BA

2

A_B

AD

R_BA

2

A_D

DR2

_DQ

SB1

A_D

DR2

_DQ

SB1

A_D

DR2

_DQ

S1

A_D

DR2

_DQ

S1

A_D

DR2

_DQ

SB0

A_D

DR2

_DQ

SB0

A_D

DR2

_DQ

S0

A_D

DR2

_DQ

S0

A_D

DR2

_DQ

M0

A_D

DR2

_DQ

M0

A_D

DR2

_DQ

M1

A_D

DR2

_DQ

M1

A_BA

DR_

BA0

A_B

AD

R_BA

0

A_BA

DR_

BA1

A_B

AD

R_BA

1

A_O

DT

A_O

DT

A_M

CLKE

A_M

CLKE

A_W

EZ

A_W

EZ

A_RA

SZ

A_RA

SZ

A_CA

SZ

A_CA

SZ

TS_M

DI1

TS_M

DI1

TS_M

DI2

TS_M

DI2

TS_M

DI3

TS_M

DI3

TS_M

DI4

TS_M

DI4

TS_M

DI5

TS_M

DI5

TSM

ICLK

TSM

ICLK

TSM

IVAL

ID

TSM

IVA

LID

TS_M

DI0

TS_M

DI0

A_M

DA

TA9

A_M

DA

TA9

A_M

DA

TA2

A_M

DA

TA2

A_M

DA

TA5

A_M

DA

TA5

A_M

DA

TA7

A_M

DA

TA7

A_M

DA

TA8

A_M

DA

TA8

A_M

DA

TA10

A_M

DA

TA10

A_M

DA

TA11

A_M

DA

TA11

A_M

DA

TA12

A_M

DA

TA12

A_M

DA

TA13

A_M

DA

TA13

A_M

DA

TA14

A_M

DA

TA14

A_M

DA

TA15

A_M

DA

TA15

A_M

CLKZ

A_M

CLKZ

A_M

CLK

A_M

CLK

PCM

_CD

2_N

PCM

_CD

2_N

TSM

OST

ART

TSM

OST

ART

TSM

OCL

K

TSM

OCL

K

TSM

OVA

LID

TSM

OVA

LID

TS_M

DO

7

TS_M

DO

7

TS_M

DO

6

TS_M

DO

6

TS_M

DO

5

TS_M

DO

5

TS_M

DO

4

TS_M

DO

4

TS_M

DO

3

TS_M

DO

3

TS_M

DO

0

TS_M

DO

0

PCM

_WE_

N

PCM

_WE_

N

PCM

_IO

RD_N

PCM

_IO

RD_N

PCM

_IO

WR_

N

PCM

_IO

WR_

N

PCM

_IRQ

A_N

PCM

_IRQ

A_N

PCM

_OE_

N

PCM

_OE_

N

PCM

_CE_

N

PCM

_CE_

N

PCM

_WA

IT_N

PCM

_WAI

T_N

PCM

_RST

PCM

_RST

PCM

_D0

PCM

_D0

PCM

_D1

PCM

_D1

PCM

_D2

PCM

_D2

PCM

_D3

PCM

_D3

PCM

_D6

PCM

_D6

PCM

_D7

PCM

_D7

PCM

_D5

PCM

_D5

PCM

_A8

PCM

_A8

PCM

_A9

PCM

_A9

PCM

_A11

PCM

_A11

PCM

_A12

PCM

_A12

PCM

_A10

PCM

_A10

PCM

_A14

PCM

_A14

PCM

_A13

PCM

_A13

PCM

_A7

PCM

_A7

PCM

_A7

PCM

_A6

PCM

_A6

PCM

_A6

PCM

_A5

PCM

_A5

PCM

_A5

PCM

_A4

PCM

_A4

PCM

_A4

PCM

_A3

PCM

_A3

PCM

_A3

PCM

_A2

PCM

_A2

PCM

_A2

PCM

_A1

PCM

_A1

PCM

_A1

PCM

_A0

PCM

_A0

PCM

_A0

TS0_

CLK

TS0_

CLK

TS0_

SYN

C

TS0_

SYN

C

TS0_

VALI

D

TS0_

VALI

D

TS0_

D7

TS0_

D7

TS0_

D6

TS0_

D6

TS0_

D5

TS0_

D5

TS0_

D4

TS0_

D4

TS0_

D3

TS0_

D3

TS0_

D2

TS0_

D2

P_D

0

P_D

0

P_D

1

P_D

1

P_D

2

P_D

2

P_D

3

P_D

3

P_D

5

P_D

5

P_D

6

P_D

6

P_D

7

P_D

7

P_A

0

P_A0

P_A

3

P_A

3

P_A

4

P_A

4

P_A

5

P_A

5

P_A

6

P_A6

P_A

7

P_A

7

P_A

8

P_A

8

P_A

9

P_A

9

P_A

10

P_A1

0

P_A

11

P_A1

1

P_A

12

P_A1

2

P_A

13

P_A1

3

P_A

14

P_A1

4

P_W

AIT

_N

P_W

AIT

_N

P_IO

WR_

N

P_IO

WR_

N

P_RE

SET

P_RE

SET

P_IR

QA

_N

P_IR

QA

_N

P_O

E_N

P_O

E_N

P_IO

RD_N

P_IO

RD_N

P_CE

_N

P_CE

_N

P_W

E_N

P_W

E_N

F_RB

Z

PF_A

D15

PF_A

D15

PF_C

E1Z

PF_C

E1Z

PF_C

E0Z

PF_C

E0Z

PF_A

LE

PF_A

LE

PF_O

EZ

PF_O

EZ

PF_W

EZ

PF_W

EZ

TS1_

D0

TS1_

D0

TS1_

D1

TS1_

D1

TS1_

D2

TS1_

D2

TS1_

D3

TS1_

D3

TS1_

D4

TS1_

D4

TS1_

D5

TS1_

D5

TS1_

D6

TS1_

D6

TS1_

D7

TS1_

D7

TS1_

CLK

TS1_

CLK

TS1_

VALI

D

TS1_

VALI

D

TS1_

SYN

C

TS1_

SYN

CTS

MIS

YNC

TSM

ISYN

C

TS_M

DI6

TS_M

DI6

TS_M

DI7

TS_M

DI7

AA_M

CLKE

AA_M

CLKE

A_M

DA

TA6

A_M

DA

TA6

AA_M

DA

TA6

AA

_MD

ATA

6A_

MD

ATA

1

A_M

DA

TA1

AA_M

DA

TA1

AA

_MD

ATA

1A_

MD

ATA

3

A_M

DA

TA3

AA_M

DA

TA3

AA

_MD

ATA

3A_

MD

ATA

4

A_M

DA

TA4

AA_M

DA

TA4

AA

_MD

ATA

4

AA

_MD

ATA

7

AA_M

DA

TA7

P_RE

G_N

P_RE

G_N

PCM

_REG

_N

PCM

_REG

_N

P_A

1

P_A

1

P_A

2

P_A

2

TS_M

DO

2

TS_M

DO

2

TS0_

D0

TS0_

D0

TS_M

DO

1

TS_M

DO

1

TS0_

D1

TS0_

D1

PCM

_D4

PCM

_D4

P_D

4

P_D

4

NA

ND

_ALE

NA

ND

_ALE

NA

ND

_CEz

NA

ND

_CEz

NA

ND

_CLE

NA

ND

_CLE

NA

ND

_WPz

NA

ND

_WPz

NA

ND

_WPz

9k1

NC

NC

3002

2165

KU

LLA

NIL

DI

CI IN

TERF

ACE

NC

1k

0R

NA

ND

FLA

SH

128 MEGABYTE

TS IN

& O

UT

3V3_STBY4k71 2

R1614

PRO

TECT

R1915220k

C117

7

100n 16

V

L120

4u7

SPD

IF_O

UT

AM

P_M

UTE

DVD

_IR_

ON

/OFF

4u7

L119

3V3_STBY

10u

10V

C119

610

VC1

195

10u

C1185

100p50V

SAV_

AU

DIO

_IN

_LSA

V_A

UD

IO_I

N_R

C119

8 10V

10u

SCA

RT_A

UD

IO_I

N_L

R183810k

Ula

s D

erel

iAU

DIO

_IO

&H

DM

I_IN

PUTs

8

17m

b62-

1

87

65

43

21

A B C D E F

AX

M

12

34

56

78

A B C D E F

OF:

A3

PRO

JECT

NA

ME

:

SCH

NA

ME

:

DRA

WN

BY

:

SHEE

T:

14-0

3-20

11_1

7:06

R16014k7

12

C15

16V100n

600RF5

12

220RR1858

100u

C116

9

16V

1216

V10

0u

C116

8 12

CN70

7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 192021

HD

MI_

1_CL

KP

HD

MI_

1_CL

KN

HD

MI_

1_RX

0P

HD

MI_

1_RX

0N

HD

MI_

1_RX

1P

HD

MI_

1_RX

1N

HD

MI_

1_RX

2P

HD

MI_

1_RX

2N

HD

MI_

0_SC

LH

DM

I_0_

SDA

CEC

HD

MI_

1_SC

LH

DM

I_1_

SDA

HD

MI1

_5V

HD

MI1

_HPD

10R

R188

11

2

R188

310

R1

2

R187

110

R1

2

10R

R187

01

2

R187

210

R2

10R

R188

41 R1

882

10R

12

10R

R187

61

CEC

R187

310

R1

2

R187

510

R1

2

47kR1862

12

47kR1863

12

R187

410

R1

R187

710

R1

2

47kR1864

12

R186547k 12

10R

R188

51

2

R188

810

R1

2

10R

R187

91

2

R188

610

R1

2

R186

810

R1

2

10R

R186

71

2

10R

R186

91

2

R188

710

R1

2

10R

R188

01

2

R187

810

R1

2H

DM

I0_H

PDH

DM

I0_5

V

HD

MI_

0_RX

2P

HD

MI_

0_CL

KP

HD

MI_

0_CL

KN

HD

MI_

0_RX

0N

HD

MI_

0_RX

0PH

DM

I_0_

RX1N

HD

MI_

0_RX

1PH

DM

I_0_

RX2N

MSD

9WB9

PT-2

U5

E2 F3 F2 G3

G2

G1

E3 E1 H5

H6

J6 B2 B1 C2

C1

D2

D1

A2

C3

J5 K4 K5 H4

N5

L4 R5 T6 P6 P5 T4 T5 N6

R6 W9

AA

9Y7 AA

7

U5

U6

U4

D4

D6

F4 F5 E4 C4 D3

P4SP

DIF

O

I2S_

IN_W

SI2

S_IN

_SD

I2S_

IN_B

CK

I2S_

OU

T_BC

KI2

S_O

UT_

WS

I2S_

OU

T_SD

I2S_

OU

T_M

CK

AU

VRM

AU

VAG

AU

VRP

EAR_

OU

TREA

R_O

UTL

AU

OU

TR1

AU

OU

TL1

AU

OU

TR0

AU

OU

TL0

AU

R3A

UL3

AU

R2A

UL2

AU

R1A

UL1

AU

R0A

UL0

CEC

HO

TPLU

GB

DD

CDB_

DA

DD

CDB_

CKRX

BCKP

RXBC

KNRX

B2P

RXB2

NRX

B1P

RXB1

NRX

B0P

RXB0

N

HO

TPLU

GA

DD

CDA

_DA

DD

CDA

_CK

RXA

CKP

RXA

CKN

RXA

2PRX

A2N

RXA

1PRX

A1N

RXA

0PRX

A0N

3

CN70

8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 192021

50V

C1183

4n7

R189

710

0R

R1899220k

R190

010

0R

C1184

50V4n7

220kR1898

DSP

_MA

IN_R

DSP

_MA

IN_L

MA

IN_L

MA

IN_R

R190

410

k

R191912k

470p

C1190

50V

10k

R190

3

R191812k

SC_A

UD

_L_I

N10

kR1

901

12kR1920

470p

C1188

50V

SAV_

L_IN

C1189

50V470p

SC_A

UD

_R_I

N

470p50V

C1187

SAV_

R_IN

R192112k

10k

R190

2SC

ART

_AU

DIO

_IN

_R

SCA

RT_A

UD

IO_I

N_L

SAV_

AU

DIO

_IN

_L

SAV_

AU

DIO

_IN

_R

22kR1925

12

R192422k

12

SC_R

_OU

T

SC_L

_OU

T

50V100p

C1186

DSP

_SCA

RT_L

DSP

_SCA

RT_R

R222

100R

12

100R

R223

12

3V3_STBY

SCA

RT_A

UD

IO_I

N_R

10V

10uC1

197

DSP

_MA

IN_R

HD

MI1

_HPD

HDMI0_5V R18954k7 12

4k7R1896

12

R190

91k

12

Q20

4BC

848B

1

2

3

1kR1

910

12

BC84

8BQ

203

1

2

3

R191

21k

12

10V4u

7C

1200

HDMI1_5V

1kR1

911

12

HD

MI0

_HPD

CEC

4k7R1892

12

10R

R191

71

2ST

BY_I

NFO

10u

C118

2

10V

10V

10u

C117

0

600R

F301

12

12V_

VCC

TL06

2

U17

81 2 3 4

5678VD

D

OU

T2

IN2-

IN2+

VSS

IN1+

IN1-

OU

T182

kR1

927

12

4k7R17

123V3_VCC

DSP

_MA

IN_L

4k7R1656

12DSP

_SC

ART

_L

PL4

PL3

PL2

PL1

R191

433

k1

2

47p

50V

C120

6

R192

682

k1

2

47p

C120

5

50VR1

913

33k

12

V+

V+

C118

1

10V

10u

SC_L

_OU

T20

kR1

928

12

SC_A

UD

_L_O

UT

SC_A

UD

_R_O

UT

1u

C120

3

6V3

R192

920

k1

2

SC_R

_OU

T

12V_

VCC

V+R1

916

220k

S92

12

Q20

2BC

848B

1

2

3

50V220p

C1178

1 2

C120

2

6V3

1u

SPD

IF_O

UT

R190

710

0R1

2

4k7R1889

12

4k7R1890

12

5V_V

CC

C11

75

100n 10

V

12

C117

6

100n 10

V

12

C5V6

D19912

220p50

V

C117

9

12

R19081k

12

JK10

12 3

DSP

_SC

ART

_RD

SP_H

P_L

DSP

_HP_

R

10kR1840

100n16

VC1

174

C120

16V

3

1u10

VC1

199

10u

3V3_VCC

HD

MI_

1_RX

2P

AN

T_CT

RL

HD

MI_

1_RX

2N

HD

MI_

1_RX

1NH

DM

I_1_

RX1P

HD

MI_

1_RX

0NH

DM

I_1_

RX0P

HD

MI_

1_CL

KNH

DM

I_1_

CLKP

HD

MI_

1_SC

LH

DM

I_1_

SDA

HD

MI_

0_SD

A

HD

MI_

0_CL

KNH

DM

I_0_

CLKP

HD

MI_

0_RX

0NH

DM

I_0_

RX0P

HD

MI_

0_RX

1NH

DM

I_0_

RX1P

HD

MI_

0_RX

2NH

DM

I_0_

RX2P

HD

MI_

0_SC

L

TP251 1

RESE

T_TU

NER

R183610k

3V3_STBY

10u

10V

C117

1

R1859220R

HP_

R

HP_

LD

SP_H

P_L

DSP

_HP_

R

10u

C118

0

10V

R183910k

RESE

T_S2

NC

HD

MI2

HD

MI1

AU

DIO

OU

TPU

Ts

MO

DE

SELE

CTIO

N

AU

DIO

INPU

Ts

PRE-

AM

P fo

r SCA

RT A

UD

IO

COA

X SP

DIF

OU

T

MO

DE

SELE

CTIO

N

NC

NC

COMMONOPTIONAL

MO

DE

SELE

CTIO

N

NC

60R

F281

60R

F297

12V_

VCC

R168

410

k1

2

VDD

_AU

DIO

F285

60R

24V_

VCC

5V_V

CC

220u C8

7010V

220u10

V

C61

5

3k9R1711

12

R171215k

12

C112

3

1u 50V

12V_

VCC

VDD_AUDIO

S87

12

R1718100k

12

220n

C104

5 25V

5V_V

CC

1N4148

D1911 2

Q18

6BC

848B

1

2

3

50V

C945

1n

C944

1n50V

F298

60R

F299

60R

C943

1n50V

C942

50V1n

R_A

UD

IO_P

_OU

T

R_A

UD

IO_P

L_A

UD

IO_N

L_A

UD

IO_P

R_A

UD

IO_N

1u 25V

C107

3

R168

710

k10

kR1

696

S85

6V3

C10

771u

1uC1

075

6V3

HP_

L

R185410k

12

MA

IN_R

L_A

UD

IO_P

_OU

T

L_A

UD

IO_N

_OU

T

R_A

UD

IO_N

_OU

T

R_A

UD

IO_P

_OU

T

U16

8

TPA

3110

D2

1516171819202122232425262728

1413121110987654321SD FA

ULT

LIN

P

LIN

N

GA

IN0

GA

IN1

AVC

C

AG

ND

GVD

D

PLIM

IT

RIN

N

RIN

P

NC

PBTL

PVCC

L2

PVCC

L1

BSPL

OU

TPL

PGN

D1

OU

TNL

BSN

L

BSN

R

OU

TNR

PGN

D2

OU

TPR

BSPR

PVCC

R1

PVCC

R2

R170

210

k1

2

VDD

_AU

DIO

R171

610k

R171

410

0kR1

715

100k

VDD

_AU

DIO

VDD

_AU

DIO

CN71

0

1 2 3 4 5 6

HP_

MU

TE

1u

6V3

C107

6

100u

C120

8

35V

TP51

1

TP52

1

100u

C120

9

35V

TP23

01

TP22

91

Ula

s D

erel

iA

UD

IO_A

MP&

HP_

AM

P8

17m

b62-

1

87

65

43

21

A B C D E F

AX

M

12

34

56

78

A B C D E F

OF:

A3PR

OJE

CT N

AM

E :

SCH

NAM

E :

DRA

WN

BY

:

SHEE

T:

14-0

3-20

11_1

7:07

F294

60R

R1701100k

R170

468

0R

10n50V

C1219

R1980100R

1

2

3

4 5

6

7

8

R4

R1

R3

R2

100RR1981

1

2

3

4 5

6

7

8

R4

R1

R3

R2

Q19

22N

7002

SK24

D19

2

1kR1941

10u

C103

2

16V

HP_

R

D203

C5V6

Q21

02N

7002

1u 25V

C107

4

6V3

C107

81u

AM

P_EN

C117

2

16V

10n

F296

60R

R623

4k7

VDD_AUDIO

R185510k

12

R817100R

BC84

8BQ

133

1

2

3

100RR818

VDD_AUDIO

10V

220n

C602

L_A

UD

IO_P

_OU

T

L_A

UD

IO_N

_OU

T

MA

IN_L

4k7R624

C665

100n 10

V12

10V220n

C608AMP_EN

VDD

_AU

DIO

3V3_VCC 10kR1309

10kR616

3V3_STBY

L_A

UD

IO_N

L_A

UD

IO_P

R_A

UD

IO_N

PT23

33U

164

C3

C2

C1

B3

B2

B1

A3

A2

A1INP

GNDA

OUTN

VDDA

VDD1

GNDB

INN

SDB

OUTP

MA

IN_R

AMP_EN

VDD

_AU

DIO

R6144k7

R_A

UD

IO_N

_OU

T

50V10n

C1218

10V

220n

C612

C666

100n

10V

12

4k7

R613

BC84

8BQ

160

U16

3PT

2333

C3

C2

C1

B3

B2

B1

A3

A2

A1INP

GNDA

OUTN

VDDA

VDD1

GNDB

INN

SDB

OUTP

R_A

UD

IO_P

16V

10n

C729

JK6

76 54321

3V3_

VCC

4k7

R114

91

HP_

DET

ECT

10V220n

C617

60R

F283

BC85

8BQ

195

1

2

347kR1699

100n

C105

8

16V

AM

P_M

UTE

BC84

8BQ

185

1

2

3

S86

12

VDD

_AU

DIO

C1121

10u16V

R171

710

0k

10u

C1122

16V

680R

R196

0

VDD

_AU

DIO

C104

322

0n 25V

25V

220n

C104

4

25V

C104

6

220n

F282

60R

AMP_EN

R174

1

100R

1 2 3 45678

R4R1 R3R2

MA

IN_L

CO

NN

ECT

TO D

SP_M

_L G

ND

AN

ALO

G V

CC

POP

NO

ISE

CIRC

UIT

CO

NN

ECT

TO D

SP_M

_R G

NDAU

DIO

AM

P fo

r 26"

to 3

2"

W/2

.5W

opt

.

AU

DIO

AM

P fo

r 16"

to 2

4"SL

IM H

EAD

PHO

NE

OU

TPU

T

NC

NC

NC

NC

W/6

W o

pt.

3000

1734

KU

LLA

NIL

DI

NC

3004

9510

KU

LLA

NIL

DI

3V6

lik z

ener

kul

lani

lmal

i

3002

2132

KU

LLA

NIL

DI

3005

0557

KU

LLA

NIL

DI

3005

0557

KU

LLA

NIL

DI

3005

0557

KUL

LAN

ILD

I

3005

0557

KUL

LAN

ILD

I

NC

NC

X2

24MHz

100R

R196

81

2

4k7R1528

12

R15244k7

1 2

CN3

12

34

56

78

910

1112

1314

1516

1718

1920

DVD

_SPD

IF

S98

12

R15274k7

1 2

R15331M

R196

710

0R1

2

100R

R154

31

2

10kR1562

R156

710

kR1

568

10k

R1571220R 12

LED2

R156310k

BC84

8BQ

170

1

2

3

SCL_

SYS

S351 2

SDA

_SYS

47R

R193

61

2

R193

747

R1

2

CN709

1

2

3

4

5

6

Q17

1BC

848B

1

2

3

LED1

50V

C949

27p

12

F259

600R

12

IR_I

N

220RR1569

12Q17

4

BC85

8B1

2

3

BC85

8BQ

173

1

2

3 220RR1570

12220RR1572

12

S76

3V3_

STBY

600R

F249

12

KEYB

OA

RD

100R

R197

01

2

R13584k7

5V_S

TBY

100R

R196

9

12

100R

R195

4

3V3_

STBY

HP_

DET

ECT

SPI_

SDI_

1

50V

C95133p

10V

C630

100n

12

CN703

1

2

3

4

5

PCM

_CD

1_N

CN12

81234

S9912

TP53

11TP

54

TP55

1

TP56

1

TP57

1

R1 4k7

12

4k7

R161

51

2

D204

B5V1

U5

MSD

9WB9

PT-2

J21

J20

J19 B4 C5 V3 B6 C7 B5 C6 A6

A7

K6 M6

H19

H20 A4

Y6 AA

6

E5 B3 A3

W8

Y8 J9 H9

AA

19A

A20

AA

18W

18W

17Y1

8W

16Y1

7A

A16

Y16

AA

15W

15

W14

Y15

W13

Y14

AA

13Y1

3A

A12

W12

W11

Y12

W10

Y11

Y9 W7

AA

10Y1

0

B7 E6 F6G

PIO

7G

PIO

11G

PIO

10

GPI

O14

3G

PIO

141

SPD

IFI/G

PIO

139

GPI

O13

7

LVA

4MLV

A4P

LVA

3MLV

A3P

LVA

CKM

LVA

CKP

LVA

2MLV

A2P

LVA

1MLV

A1P

LVA

0MLV

A0P

LVB4

MLV

B4P

LVB3

MLV

B3P

LVBC

KMLV

BCKP

LVB2

MLV

B2P

LVB1

MLV

B1P

LVB0

MLV

B0P

GN

D1

GN

D0

USB

1_D

MU

SB1_

DP

USB

0_D

MU

SB0_

DP

HW

RESE

T

XOU

TXI

N

IRIN

DD

CR_D

AD

DCR

_CK

DD

CA_D

A/U

ART

0_TX

DD

CA_C

K/U

ART

0_RX

GPI

O14

SDO

SDI

SCK

SCZ

GPI

O12

SAR2

SAR1

SAR0

PWM

2PW

M1

PWM

0

4

F248

600R

12

KEYB

OA

RD

47R

R793

12

10n

C1215

16V

KEYB

OA

RD_O

NBO

ARD

STBY

_ON

/OFF

_NO

T

Ula

s D

erel

iG

PIO

s&U

SB&L

VDS_

OU

T8

17m

b62-

1

87

65

43

21

A B C D E F

AX

M

12

34

56

78

A B C D E F

OF:

A3

PRO

JECT

NA

ME

:

SCH

NA

ME

:

DRA

WN

BY

:

SHEE

T:

14-0

3-20

11_1

7:07

4k7R1617

1 2

R13574k7

100R

R124

81

2

SPI_

CSN

_1SP

I_SD

OSP

I_SC

K

3V3_STBY

FLA

SH_W

PN

TP411

TP111

TP151

TP401

U15

8M

X25L

512

1 2 3 45678

VCC

HO

LD#

SCLK SI

GN

DW

P#SOCS

#

TP121

TP141

100n

10V

C658

12

3V3_

VCC

R11834k7

3V3_

STBY

1N58

19

D16

5

BACK

LIG

HT_

DIM

MEC

H_S

WIT

CHD

VD_S

ENSE

3V3_

VCC

3V3_

STBY

SC_P

IN8

3V3_

STBY

FLA

SH_W

PN

SPI_

SCK

SPI_

SDI_

1

SPI_

CSN

_1

SPI_

SDO

TX/S

DA

_SC

DVD

_WA

KEU

P

RX/S

CL_

SC

SCL_

SYS

SDA

_SYS

3V3_

VCC

IR_I

N

RESE

T

33pC952

50V

USB

_DM

USB

_DP

TX_B

_4_P

TX_B

_4_N

TX_B

_0_N

TX_B

_0_P

TX_B

_1_N

TX_B

_1_P

TX_B

_2_N

R119

84k

7

TX_B

_CLK

_P

TX_B

_2_P

TX_B

_3_N

TX_B

_3_P

150RR1940

U14

5

AZ0

99-0

4S2

456IO

4

VDD

IO3

IO2

3

GN

D

IO1

1R8

4410

R1

2

R845

10R

12

USB

_DP

USB

_DM

MEG

A_D

CR_O

UT

TX_A

_CLK

_P

TX_A

_2_N

TX_A

_1_P

TX_A

_1_N

TX_A

_0_P

C610 10

V10

u

TX_A

_0_N

TX_A

_CLK

_N

TX_A

_2_P

PAN

EL_V

CC

R183

510

k

12V_

VCC

DIM

MIN

G

PIN

_04

12V_

VCC

MEG

A_D

CR_O

UT

PIN

_01

PIN

_01 S2

61

2

PIN

_02

PIN

_02

PIN

_03

PIN

_03

S27

12

OPT

ION

1

S28

12

BACK

LIG

HT_

ON

/OFF

S31

12

PIN

_04

PIN

_05

PIN

_05

CI_P

OW

ER_C

TRL

R16714k71 2

4k7R1672

1 2

R195

24k

71

2

LED

1LE

D2

3V3_STBY

3V3_STBY

TP34

1

TP32

1

TP30

1

TP28

1

TP26

1

TP24

1

TP22

1

TP20

1

TP18

1

TP16

1

TP17

1

TP19

1

S41

2

TX_B

_4_N

OPT

ION

1

OPT

ION

2

S61 2

CN13

61

2

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

2930

3132

3334

3536

3738

3940

4142

4344

4546

4748

4950

PAN

EL_V

CC

S57

12

TP21 1

TP23

1

TP25

1

TP27

1

TP29

1

TX_A

_2_P

TX_A

_CLK

_NTP31

1

S36 12

S34 12PANEL_VCC

S10

12

3V3_

VCC

R130

110

k1

210k

R126

61

23V

3_VC

C

MEG

A_D

CR_O

UT

TX_B

_0_N

TX_B

_0_P

TX_B

_1_N

TX_B

_1_P

TX_B

_2_N

TX_B

_2_P

TX_B

_CLK

_N

TX_B

_CLK

_P

TX_B

_3_N

TX_B

_3_P

TX_A

_0_N

TX_A

_0_P

TX_A

_1_N

TX_A

_1_P

TX_A

_2_N

TP33

1

TX_A

_CLK

_P TP35

1

TX_A

_3_N

TX_A

_3_P

MEG

A_D

CR_I

N

S32

12

TX_B

_0_N S1

51

2

TX_A

_3_N

TX_A

_CLK

_P

TX_A

_2_P

TX_A

_2_N

TX_A

_1_P

TX_A

_1_N

TX_A

_0_P

CN13

9

123456789101112131415161718192021222324252627282930

TX_A

_0_N

TX_A

_CLK

_N

TX_A

_3_P

TX_B

_3_P

TX_B

_3_N

TX_B

_CLK

_P

TX_B

_CLK

_N

TX_B

_2_P

TX_B

_1_P

TX_B

_1_N

TX_B

_0_P

PAN

EL_V

CC

PAN

EL_V

CC

S33

12

TX_B

_2_N

PANEL_VCC

CN1371

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

CN1381

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

S1312

R127410k1 2

S1912

PANEL_VCC

TX_A_0_N

S312

S1412

TX_A_0_P

TX_A_1_N

TX_A_1_P

TX_A_2_P

TX_A_CLK_P

TX_A_3_N

TX_A_CLK_N

10kR1300

1 2PANEL_VCC

S3012

PANEL_VCC 10kR1296

1 2

PANEL_VCC

S55 12

10kR1297

1 2

PANEL_VCC 10kR1280

1 2

OPTION2

OPTION1

OPTION3

S94

TX_A_3_P

TX_A_2_N

R129510k

1 2

PANEL_VCC

MEGA_DCR_INS56

12

MEGA_DCR_OUTS58

12

S371 2

OPTION5

OPTION4

TX_B

_CLK

_N

TX_A

_0_N

TX_A

_0_P

TX_A

_1_N

TX_A

_1_P

TX_A

_2_N

TX_A

_2_P

TX_A

_CLK

_NTX

_A_C

LK_P

TX_A

_4_N

TX_A

_3_N

TX_A

_3_P

TX_A

_4_P

TP7

1

TP6

1

TX_B

_4_P

TP8

1

TP9

1

TX_A

_4_N

TX_A

_4_P

10k

R183

3

R2310k

470RR7

R452k

SW5

E1

G1

G2

G3

G4

E2

1

2

T

C

3

4

S38

FPF2

124

U8

1 2 345

VOU

T

ISET

ON

GN

D

VIN

5V_V

CC

560R

R46

3V3_

VCC

KEYB

OA

RD_O

NBO

ARD

TP101

4k7

R195

91

23V

3_ST

BY

5V_S

TBY

16V100n

C1016

D189

1N4148

R166

81k

22u6V3

C103110k

R1667

3V3_

STBY

100n

C101

5

10V

12

R166

610

0R1

2

RESE

T

HP_

MU

TE

EXT

KEYP

AD

LED

SO

CKET

ON

BOAR

D K

EYBO

ARD

15.6

LVD

S O

PTIO

N

SERI

AL

FLA

SH

S57

& S1

0&S4

= 0R

RESE

T

PIN

12,1

6,18

,20

JUM

PER

TAKI

LACA

K

USB

USB

INTE

RFA

CE

TWIS

TED

PA

IR L

VDS

OPT

ION

19" TO 22" DOUBLE LVDS FFC OPTIONS

TOU

CH_P

AD_O

PTIO

N

PANEL_VCC = 5V/12V

PAN

EL V

CC =

5V/

12V

SIN

GLE

LVD

S FF

C O

PTIO

NS

PIN

6 L

VDS

KABL

OSU

ND

A n

.C Y

API

LMA

LI

15.6

" LVD

S O

PTIO

N

+-

NC

3 BU

TTO

NS

KEYB

OA

RD O

PTIO

N

NC

NC

NC N

C

NC

NC

NC

NC

AVDD2V5_REF

AVDD2V5_AUD

AVDD2V5_MOD

F305 1k

F307 1k 1k

F308

100n

16V

C122

1

16V

100n

C122

2

1u

C1128

25V

CN70

612

34

56

78

910

1112

1314

1516

1718

1920

10k

R168

51

2

3V3_VCC 4k7R1678

12

600R

F250

1

R167

910

0R

100R

R197

3

3V3_

VCC D

IMM

ING

PIN

_11

BACK

LIG

HT_

ON

/OFF

PIN

_11

PIN

_10

PIN

_9

PIN

_7_8

BACK

LIG

HT_

ON

/OFF

STBY

_ON

/OFF

16V

100n

C102

2

1k

F306

S8

6V3

10u

C108

1

F272

60R

BC84

8BQ

194

1

2

3

Q19

3BC

858B

1

2

3

STBY

_ON

/OFF

Q21

1

BC84

8B1

2

3

60R

F302

12

PIN

_7_8

3V3_

VCC

4k7

R174

81

2

BC84

8BQ

188

1

2

3

MSD9WB9PT-2U5

H15H16H17J14J15J16J17

H14

K14

N7N8

P7P8

T8

R7R8

U8

V8

E8F8G8

G9

E9F9

J8

H8

G16G17

G15

E15E16E17F16F17

K9

L9M9N9P9R9

D10E10F10G10H10J10K10L10M10N10P10R10D11E11F11G11H11J11K11L11M11N11P11R11D12E12F12G12H12J12K12L12M12N12P12R12D13E13F13G13H13J13K13L13M13N13P13R13D14E14

L14M14N14P14R14D15

K15L15M15N15P15R15D16K16L16M16D17K17L17M17K18L18M18

W2W3V4V5V6

D9D18 GND87

GND86

GND85GND84GND83GND82GND81

GND80GND79GND78GND77GND76GND75GND74GND73GND72GND71GND70GND69GND68GND67GND66GND65GND64

GND63GND62GND61GND60GND59GND58

GND57GND56GND55GND54GND53GND52GND51GND50GND49GND48GND47GND46GND45GND44GND43GND42GND41GND40GND39GND38GND37GND36GND35GND34GND33GND32GND31GND30GND29GND28GND27GND26GND25GND24GND23GND22GND21GND20GND19GND18GND17GND16GND15GND14GND13GND12GND11GND10

GND9GND8GND7GND6GND5GND4GND3

BYPASS

AVDD_DDR_4AVDD_DDR_3AVDD_DDR_2AVDD_DDR_1AVDD_DDR_0

AVDD_LPLL

VDDP1VDDP0

AVDD_EAR33

AVDD_AU33

AVDD_CVBS33_1AVDD_CVBS33_0

AVDD_DMPLL

AVDD_ALIVE_2AVDD_ALIVE_1AVDD_ALIVE_0

PGA_VCOM

AVDD_PGA25

AVDD_MOD25_1AVDD_MOD25_0

AVDD_AU25

AVDD_REF25_1AVDD_REF25_0

AVDD_ADC25_1AVDD_ADC25_0

AVDD_126

DVDD_DDR

VDDC6VDDC5VDDC4VDDC3VDDC2VDDC1VDDC0

6

12V_

VCC

L2

10u

R1810k

4k7R41

2k2R42

MEC

H_S

WIT

CH

100u

35V

C65

Ula

s D

erel

iPO

WER

_1&

LNBP

8

17m

b62-

1

87

65

43

21

A B C D E F

AX

M

12

34

56

78

A B C D E F

OF:

A3

PRO

JECT

NA

ME

:

SCH

NA

ME

:

DRA

WN

BY

:

SHEE

T:

14-0

3-20

11_1

7:08

S29

S95

SOFT_SWSOFT

_SW

VDDC_1V2

C6850V

15n

15kR43

C12

220n 25

V

D7

1N40

01

50V

1uC69

LNB_

OU

T

C70

470n

25V

3V3_VCCR1910k

F295

1k

SK24

D8

C13

220n 25

V

C64

35V100u

16V

C997

100n

SDA

_SYS

SCL_

SYS

3V3_

VCC

100n

16V

C100

5

C14

25V

220n

C107

0

16V

100n

C100

416

V10

0n

LNBH

23L

U6

27 4 19 18 6 9 14 29 30

22 13 21 11 12 1 2 3 7 8 16 17 23 24 25 26 31 32

1015285

20A_GNDP_GNDI_SELBYPADDR

NC_

13N

C_12

NC_

11N

C_10

NC_

9N

C_8

NC_

7N

C_6

NC_

5N

C_4

NC_

3N

C_2

NC_

1

DSQ

INPD

CVO

_RX

EXTM

VO_T

X

RSV_

2RS

V_1

TTX

SCL

SDA

VCC_

LVC

CLXV_

UP

12V_

VCC

S82

12

R163

610

k1

2

10k

R163

51

2

3V3_

TUN

ER

12V_

VCC

3V3_

VCC

VDD_3V3

1N5819

D6

5V_V

CC

DISEQC_OUT

R175

022

k

24V_

VCC

10k

R163

11

2

16V

100n

C100

9

10u

10V

C774

C974

1u 6V3

AVDD_DDR

AVDD_3V3

AVSS_PGA

AVDD_2V5_PGA

AVDD2V5_ADC

BAW56D184

12

3

10kR1639

12

BC84

8BQ

191

1

2

3

STBY

_ON

/OFF

3V3_

STBY

STBY

_ON

/OFF

_NO

T

10k

R163

81

2

Q17

8

BC84

8B1

2

3

Q18

0BC

858B

1

2

3

3V3_

STBY

R164

933

k1

2

D185BAW56

12

3

D186BAW56

12

3

100nC9

71 10V

12

PROTECT

TP2021

U7

LM80

91

3

2RS

TVCC G

ND

3V3_

STBY

R176

110

0R1 2 3 4

5678

R4R1 R3R2

R116

64k

71

2

50V

C840

220p

12

3V3_VCC

4k7

R115

81

2

BACK

LIG

HT_

DIM

DIM

MIN

G

C839

50V

220p

12

50V

220p

C838

12

4k7

R116

51

2

R12211k

12

S18

MEG

A_D

CR_

IN

S16

MEG

A_D

CR_O

UT

12V_

STBY

S17

Q18

9BC

848B

1

2

3

F277

60R

R20

10k

12

R40

20k

10k

R21

R172

733

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2

PIN

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100n

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5

16V

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410

0n16

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VDD

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2

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01

100n

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3

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0

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8

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C5

F270

60R

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A

100n

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8

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F271

60R

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60R

F274

100n

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7

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2

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

2728

1V8_

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1V2_

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C101

4

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D_3

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DIM

MIN

G

STBY

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FO

PAN

EL_V

CC

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CC

F290

60R

12

47R

R172

51

2

33kR1734

12 22kR1749

FDC642PQ199

1

34

5

6

2

TP2131

F288

60R

12

F289

60R

12

10k

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31

2

C104

210

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12

5V_V

CC

12V_

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Q19

0BC

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1

2

3

5V_V

CC

24V_

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R2 4k7

12

5V_V

CC

C7

16V22u

PIN

_7_8

12V_

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PIN

_7_8

3V3_

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S7 S24

5V_V

CC

PIN

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Y

S1 S23

PIN

_9

PIN

_11

12V_

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PIN

_10

12V_

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5V_S

TBY

S22

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CCS2

1PI

N_1

0

PIN

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LM11

17U

1

1

23

4

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PIN

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71

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16" t

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PW04

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NC

NC

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AD

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N

NC

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9

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12

S89

L116

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JK9

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DC

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12

DIM

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G

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1 2 3 4 5 6

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6

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TP37

1

TP39

1

TP451

TP239 1

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TP231 1

S83

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5

6

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6

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C121

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C108

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3

10n

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100RR1978

1

2

3

4 5

6

7

8

R4

R1

R3

R2

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100RR1979

1

2

3

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6

7

8

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L

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100R

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330R

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