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PhD Research High Performance Computing R Govindarajan Matthew Jacob SERC/CSA, IISc

PhD Research High Performance Computing

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PhD Research High Performance Computing. R Govindarajan Matthew Jacob SERC/CSA, IISc. Computer Architecture. Key Tool: Simulation. Experiments are often conducted using discrete event simulation Prototyping is typically not an option - PowerPoint PPT Presentation

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PhD ResearchHigh Performance Computing

R Govindarajan

Matthew Jacob

SERC/CSA, IISc

Computer Architecture

Key Tool: Simulation

• Experiments are often conducted using discrete event simulation– Prototyping is typically not an option

• Accurate simulators are large, intricate programs that run for long time durations

• Important decision: Choice of– Simulator– Simulation methodology

Key Publication Venues

1. ISCA: ACM/IEEE International Symposium on Computer Architecture (Jun)

2. HPCA: IEEE International Symposium on High Performance Computer Architecture (Feb)

3. MICRO: IEEE International Conference on Microarchitecture (Dec)

• ASPLOS (Mar), PACT (Sep)

Current Research Areas

Paper Sessions at ISCA 2010

1. Energy Efficiency2. Caches3. Emerging Technologies and Interconnect 4. Memory Subsystems 5. Productivity and Debugging6. Acceleration Architecture7. Threading 8. Simulation Technologies and Real System Evaluation 9. Cluster and Data Center 10. Security 11. Multi-Core 12. Reliability and Fault-tolerance

1. Translation Caching: Skip, Don't Walk (the Page Table)

2. High Performance Cache Replacement Using Re-Reference Interval Prediction (RRIP)

3. The Virtual Write Queue: Coordinating DRAM and Last-Level Cache Policies

4. Reducing Cache Power with Low-Cost, Multi-Bit Error Correcting Codes

Current Research Areas

• Memory– Hierarchy– Technology– Consistency

Current Research Areas

• Memory

• Prediction, Speculation, Prefetching

• Power efficiency

• Multicore architecture

Moore’s Law

Wikimedia, Intel

Multicore Die PhotosAMD dual core

Sun UltraSparc multicore

Intel Core i7 AMD, Sun, Intel, Benchmark Reviews

Multicore Cache Hierarchy

Core Core Core Core

L1 L1 L1 L1

L2 L2 L2 L2

Core Core Core Core

L1 L1 L1 L1

L2

Current Research Areas

• Memory

• Prediction, Speculation, Prefetching

• Power efficiency

• Multicore architecture– Memory hierarchy– Interconnect– Core design– Transactional memory

One Writing Guideline

• Every sentence should follow from– a preceding sentence– an experimental observation– a reported result from a cited publication

• “it is believed that”, “we think that”, “this is probably due to”