Upload
hoangtram
View
222
Download
1
Embed Size (px)
Citation preview
CSE 577 Spring 2011
Phase Locked LooppDesign
KyoungTae Kang, Kyusun Choi
Electrical Engineering
Computer Science and EngineeringComputer Science and Engineering
PFD and modified flip-flop
B.park, “A 1GHz, Low-Phase-Noise CMOS Frequency Synthesizer with Integrate LC VCO for Wireless Communications“, CICC 1998
Park Byungha? GIT PhD Samsung LSI RF/Analog IC GroupPark, Byungha? GIT PhD. Samsung LSI, RF/Analog IC Group
New Modified flip-flop by KT
•Reduce signal pathpath
•High speed
•10 Transistors
•Negative reset
•No oscillation
•Customized
Charge Pump (Drain–s/w)
•My first Charge pump.
E t d i d d t d h t•Easy to design and understand how to work
•Spike Noise from net76 when U2 turn on
•High noise contribution!
•If you designed CP like this, you got fired!
Charge Pump (Source-s/w)
•Low charge sharing
•Low noiseWhy? Cascode?
•Low noise
•Suppression the Spur
>High impedence>Pole!!!
Level?Level?
Charge Pumps
Rhee W "Design of high performanceRhee, W., Design of high performance CMOS charge pumps in phase locked loop", In Proc. ISCAS, 1999, Vol. 1, pp.loop , In Proc. ISCAS, 1999, Vol. 1, pp. 545-548
J S Lee M S Keel S I Lim and SJ. S. Lee, M. S. Keel, S. I. Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked g ploops,” Electronics Letters, Vol. 36, No. 23, pp. 1907-1908, November 2000.
Differential Delay Cell-Multiple pass
Negative Skewed Delay Scheme:Negative Skewed Delay Scheme:
Seog-Jun, Lee, ISSC, 1997
Yalcin Alper Eken, Solid-State Circuits, 2004
Multiple pass Ring OSC.
Which one is faster?
1. 3 stage single pass Ring OSC.
2. 5 stage multiple pass Ring OSC.
How to simulate Oscillator in Hspice?
.Option
Transient Step
Start-up time
Triggered Signal
Frequency Measure Tool: Cscope
Frequency Divider
•Input stage-high speed, low power, Following stages-High speed•Differential type-Suppression Noise
•Input buffer is required