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PHASE-LoCKED Loop

CIRCUIT DESIGN

Dan H. 叭lolaver

Worchester Polytechnic Institute

可缸

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,

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Llbrary of Congress Catalog1ng-ln-Publ1catlon Data

WOlaver , Dan H. Phase-locked loop clrcult deslgn I Dan H. Wolaver.

P. cm. -- (Prentice Hal1 advanced reference serles) Includes blbliographical references and lndex. ISBN 0-13-662743-9 1.Phase-1ock ed1oops.2.E1ectr-orI1E c 1FEu 1t des 1gr1. 工. Tltle.

TK7872.P38W65 1991 621.381' 5--dc20

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Prentice Hall Advanced Reference Series

Prentice Hall Biophysics and Bioengineering Series

。 1991 by Prentice也HalI， Inc. A Division of Simon & Schuster Englewood Cliffs, New Jersey 07632

AII rights reserved. No p位t of this book may be reproduced, in any forrn or by 組y means, without perrnission in writing from the publisher.

Printed in the United States of America 10 9 8 7 6 5 4 3 2 1

工 S8N 口-13-662743- 可

Prentice-HalI Intemational (UK) Limited, London Prentice-HalI of Australia Pty. Limited, Sydney Prentice-HalI Canada Inc. , Toronto Prentice--HalI Hispanoamericana, S.A. , Mexico Prentice-HaII of India Private Limited, New Delhi Prentice-HalI of Jap妞， Inc. , To妙。Simon & Schuster Asia Pte. Ltd. , Singapore Editora Prentice-HalI do Brasil, Ltd扎， Rio de Janeiro

90-23685 CIP

CONTENTS

PREFACE IX

1. INTRODUCTION

1-1 Carrier Recoveη2

1-2 Clock Recovery 3

1-3 Tracking Filter 3

1-4 Frequency Demodulation 4

1-5 Phase Demodulation 5

1-6 Phase 扎1odulation 5

1-7 Frequency Synthesis 6

1-8 Organization of Text 7

1-9 Other Information on Phase-Locked Loops 7

2. PHASE-LOCKED LOOP BASICS 9

2-1 Phase-Locked Loop Characteristics 9

2-2 Phase Detector Characteristics 11

Contents vii

5-8 Injection in Resonant VCOs 100 5-9 PLL Behavior with Injection 102 5-10 Spectral Purity 105

6. NOISE 107

6-1 Power Spectral Density 107 6-2 Noise Bandwidth 109 6-3 Noise-Induced Phase 111 6-4 Output Phase Noise Due to Input Noise 116 6-5 VCO Phase Noise 120 6-6 Output Phase Noise Due to VCO Noise 126 6-7 Output Phase Noise Due to Both Nosie

Sources 128 6-8 Cyc1e Slips 131

7. MAINTAINING LOCK 135

VI Contents

2-3 2-4 2-5 2-6 2-7 2-8

VCO Characteristics 11 Linear Model of PLL 13 Static Phase Error 14 PLL Bandwidth 15 Loop Filter 20 Static Phase Error with Loop Filter 22

3. LOOP FIL TERS 25

3-1 Active Loop Filter 26 3-2 Static Phase Error with Active Loop Filter 28 3-3 Altemative Active Loop Filter Designs 29 3-4 Active Loop Filter Offsets 31 3-5 PLL Frequency Response 32 3-6 PLL Step Response 36 3-7 Limited Loop Filter Bandwidth 38 3-8 Phase Error Response 43

4. PHASE DETECTORS 12345678

77

月，尸字水土'字月，戶，

47

4-1 Four-Quadrant Multipliers 47 4-2 Gilbert Multiplier 50 4-3 Phase Detector Figure of Merit 52 4-4 Double Balanced Multiplier 52 4-5 Triangular Phase Detector Characteristic 54 4-6 Exc1usive-OR Phase Detector 55 4-7 Two-State Phase Detector 59 4-8 Three-State Phase Detector 61 4-9 Z-State Phase Detector 65 4-10 Sample-and-Hold Phase Detector 67 4-11 Extended. Range: Frequency Division 68 4-12 Extended Range: 'T]-State Phase Detector 68 4日 Modified Phase Detector Characteristic 75

Hold-In Range 135 Input Frequency Deviation Llωi 136 Lock-In FrequencyωL 138 Transfer Function from Llωi to 6e 142 Handling a Frequency Step 143 Handling a Frequency Ramp 145 Handling Sinusoidal FM 148 Handling Random FM 151

8. LOCK ACQUISITION

8-1 Self Acquisition: Active Loop Filter 157 8-1-1 Pull-In Voltage vp 157 8-1-2 Pull-In Time Tp 160 8-1-3 Pull-In Range ωp 163

8-2 Self Acquisition: Passive Loop Filter 164 8-3 Acquisition with a Pole atω3 168 8-4 Acquisition with a Three-State PD 171 8-5 Aided Acquisition with a Three-State PD 174 8-6 Rotational Frequency Detector 177

5. VOLTAGE-CONTROLLED OSCILLATOR 81

5-1 Properties of VCOs 81 5-2 Voltage-Controlled Multivibrators 83 5-3 Resonant VCOs 86 5-4 Modulation Bandwidth 91 5-5 Q of the Resonant Circuit 92 5-6 Crystal VCOs 94 5-7 Injection in Multivibrator VCOs 97

155

9. MODULATION AND DEMODULATION 185

9-1 Phase Modulation 185 9-1-1 Bandwidth, Phase and Frequency

Ranges 186

viii

9-2 9-3

9-4 9-5

9-1-2 Spurious Modulation 187 9-1-3 Spurious Modulation with a Pole at

ω3 189 Phase Demodulation 192 Phase Demodulation with No Carrier 195 9-3-1 Squaring Loop 196 9-3-2 Remodulator and Costas Loop 200 Frequency Modulation 202 Frequency Demodulation 205

10. CLOCK RECOVERY

10-1 10-2 10-3 10-4 10-5 10-6 10-7

Data Formats and Spectra 212 Conversion from NRZ and RZ Data 213 Phase Detectors for RZ Data 216 Pattem-Dependent Jitter 218 Phase Detectors for NRZ Data 220 Offset Jitter 220 Jitter Accumulation 230

11. FREQUENCY SYNTHESIZERS

11-1 Single-Loop Synthesizer 239 11-2 Choosing the Bandwidth K 240 11-3 Synthesizer with Mixer 241 11-4 Spurious Modulation 242 11-5 Divided Output 248 11-6 Pull-In Time 248 11-7 Multiplexed Output 250 11-8 Multiple-Loop Synthesizer 250 11-9 Phase Noise 252 11-10 Prescaling 257

LlST OF SYMBOLS

INDEX

Contents

211

239

260

261

可-一

PREFACE

This book provides a practical introduction to phase-locked loops for the practicing electrical engineer. Beginning with basic principles , it covers applications such as clock recovery , FM and PM modulation and demodulation , and frequency synthesis. Each application includ巳s the development of design formulas for the system parametersbandwidth , noise , acquisition range and speed , dynamic range, stability , and accuracy. While providing the necesssary system theory , the book's main emphasis is the practical realization of phase-locked loop circuits. For example, it addresses stray coupling, current limitations , offset voltages , and bandwidth limitations. Many altemative circuits are described with extensive use of examples and figures.

The experienced specialist in phase-lock loops will find material here that extends his knowledge. Several new digital phase detectors are described. The choice between lock acquisition techniques is clarified. The often confounding problem of injection locking is treated in depth.

To simplify the connection between phase-locked loop theory and design , the text abandons the traditional natural frequency ωn and damping factor , of control theory. The parameterωn is often misleading since it has little relation to system behavior in a highly damped system. The parameters used in this text are the bandwidth K and the zero frequencyω2 ， which give a better description of system behavior. K is the 3-dB bandwith for all dampings except those near instability. The value of ω2 in relation to K essentially

x Preface

gives the damping through the expression ~ 0.5此間， and it is close1y tied to the circuit e1emer恥 BothK andω2 are clear1y evident i呵。de p10ts off叫uency responses , providing a visua1 1ink between design and petformance.

This text has been used for a course bn phase-1ocked 100p circuit design at the graduate level, where it has served those with immediate appiications for phase-locked loops and those who wish to consolidate their facility with circuit design in general.The study ofph帥-lockl叫 loops is amxcellentvehicle forputtingto use VMOIMis句1i拙。fe1ectrical engineering: communication theory , contro1 theo旬， signaI .analysis , noise characterization, de 呻1 wit由h 仕岫a訓扭nsiclrcαmt anaIysis.

The author is gratefu1 to his students at Worcester Po1ytechnic Institute for their he1p in refining the contents of thls book.The work assignments at Bell Telephone Laboratories and at TallmtrOI1, Inc.have provided the anvil on which to shape his understanding of phase-locked loops.The author has found the study and design of phase-locked loops to be a rich area for providing challenges to innovation and solutions to practicaI prob1ems. It is his hope 中的 this text will shorten t血he pat由h foro叫the加1泥悶e叮rd由e呻enjoy the disc∞overy and creativity avai1ab1e in phase-1ocked 100p circuit design.

CHAPTER

INTRODUCTION

Phase-Iocked 100ps are used primari1y in communication app1ications. For examp1e, they recover clock from digita1 data signals , recover the carrier from satellite transmission signa1s, perform frequency and phase modu1ation and demodu1ation, and synthesize exact frequencies for receiver tuning. In this chapter we 100k at the basic princip1es of phase-10cked 100p operation in these app1ications. The approach here is informa1 and nonnumeric in order to provide a quick overview. The intent is to provide heuristic descriptions that will raise questions to be answered in the following chapters.

A phase-1ocked 100p (PLL) is basically an oscillator whose frequency is 10cked onto some frequency component of an input signa1 Vi' This is done with a feedback contro1 100p, as shown in Fig. 1-1. The frequency ofthis component in Vi isωi (in rad/s) , and its phase is Oi' The oscillator signa1 V{) has a frequency ω。 and a phase Ow The phase detector (PD) compares 00 with Oi , and it deve10ps a vo1tage V d proportiona1 to the phase difference. This voltage is app1ied as a controI vo1tage V c to the voltage-controlled oscillator (VCO) to adjust the oscillator frequency ω。. Through negative feedback , the PLL causes ω。 =ωi ， and the phase error is kept to some (p.referab1y small) va1ue. Thus , both the phase and the frequency of the oscillator are “ 10cked" to the phase and the frequency of the input signal.

?

2 Jntroduction Chap. 1 Sec. 1-3 Tracking Filter 3

})j a''

,

••

凶四川

(l )1 ，。

1"

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{{ How will the noise affect the purity ofthe VCO signal Vo? Will the PLL be able to average the phase of Vi over many bursts , thereby reducing the effect of the noise?

。0:::::8i，凶。 =W; FIGURE 1-1 Basic phase-1ock巳:d loop 1-2 CLOCK RECOVERY

In Chaptershnd-3, we will add another component-a loop filter一to the simple P堅'LL岫g.I-1一-1. Thi叫ill忱s鉛蚓附e叮昕rv附ve t切omo峭伽PL扯Lba缸I帥蝴 an仙1

ror…nOw, w?simplify the PLL by omitting the loop filterin orderto better understand the basic operation of the PLL.

Seven applications are discussed briefly in this chapter. They will be more thoroughly covered in Chapters 9 through 11.

In this application, a clock signal Vo is to be synchronized to a digital data signal Vi . Forthe example in Fig. 1-3 , Vi repr，的ents a logic “ 1" by a pulse and a “ 0" by the absence of a pulse. The data sequence here is 1 ，0 ， 1 ， 1 力， 1 ， 1 ， 1 ，0 ，0，1. An analysis of the spectrum of this data signal shows that there is a component at 肉， where 27T!ωi is the spacing between logic symbols. There is also a background broad spectral density due to the random gaps representing O's in the data. A PLL can be used to lock an oscillator f自quencyω。 to the ωz component, producing the clock signal Vo shown.

The clock could have been recovered with a narrow-band filter rather than a PLL. However, the background spectral density in the vicinity of ωi will also pass through the filter , corrupting the clock. What effect will this background spectral density have on the PLL? Can the effective Q of a PLL match that of a crystal filter with a Q of 10,000? Can clock be recovered if there is no space between the pulses representing adjacent “ l's"?

1-1 CARRIER RECOVERY

Figure 1-2 shows a received signal Vi consisting of bursts of a sinusoid. This is l>imilar to thcfcolor bum' , 1n a TV signal The frequency and phase ofan osciIIMorin the TV recewer must bc locked to those of the bursts.ThIS oscillator signal vois then used to demodula能伽 color information in 伽 TV 位gnal. When a 趴削 occu忌， tl叫D (phase detector)has a chance to compare the phase of vo with that of vt-Any erTor produces a voltage vd that is appiied to the VCO(voltage『Controlled oscillator)to correct the phase. (A brief change in frequency changes the phase.)

A 恥伽m 仟 the input shows 伽t the input signal Vi has a compon叫“峙， the frequency of the SInusOId during the burst (see Fig.l-2).But there are many other spectral components nearby一-some only 10% away from ωi. One question is whether the PLL will choose the cOITECt frequency to lock onto.How does it acquire lock ln thc first place?Once it is locked to the proper frequency , wilithe vco phase drift too much between the bursts?Every communications signal is COInIpted by noise to some extent.

可-3 TRACKING FILTER

One advantage of a PLL over a narrow-band filter is its ability to track an input frequency ωi that is drifting with time. Figure 1-4 shows anωi that is ramping downward with time , perhaps due to doppler shift, as with a satellite passing overhead. The PLL tracks the component atωi and continues to recover the clock. If a narrow-band filter rather than a PLL were used to recover the ωi component, the component would quickly drift out of the narrow passband. In this application , the PLL acts about like a narrow-band fi1ter whose center frequency can move.

吋~.IJIIII.-.， V"Ol 111 ,, 11111 111 ,1, • ';W 0 0 0 0 0 0 0 ~ V""'1 WiJ 嗯，tall1lHIllllIEIHHUU1 日，←\"Wj 包3

1 1 叫的i wl ~LI … nnnnnnnnnn ~ 1.ωE的IVVVVVVVVVVVVVVIVIVVVVVVV'" 已'0 W

FIGURE 1-2 Carrier recovery FIGURE 1-3 Clock recovery

4

Wi

W。

的(“)

Vo(ω}

track ~

Introduction Chap. 1

Wi W

曲。 =ω，

W。 W

FIOURE 1-4 Tracking filter

How fast can ωi move without the PLL losing track? What is the relationship between the speed with which the PLL can track ωi and the effective bandwidth of the PLL? What limits the range over which the PLL can track ω，?

可-4 FREQUENCY DEMODULATION

Almost al1 FM receivers today use a PLL for frequency demodulation. In this application , the PLL output frequency ω。 tracks the input frequency ωi as it varies according to the modulation (see Fig. 1-5). If the VCO control voltage Vc is proportional toω。， it is also proportional toωi. Therefore , Vc is the demodulated signal.

Wj

"~ PD Iili口江\:一一τ一一」一一一-' I (曲。)

Wide bandwidth 50

仇九〈|ν 以'-/ -

FIOURE 1-5 Frequency demodulation

Sec. 1-6 Phase Modulation 5

Note that the bandwidth of the PLL must be wide enough that it has the necessary speed to track the variations in ωi. How wide must the PLL bandwidth be? What happens if it is too wide? How much noise does it take to cause the PLL to temporarily lose lock at times? (These “ cyc1e slips" are heard as “c1icks. ")

可-5 PHASE DEMODULATION

In a similar applicatíon , a PLL can be used for phase demodulation. Here , the received signal Vi is a carrier whose modulated phase 8i conveys the information (see Fig. 1-6). In this application , the PLL bandwidth is so small (the PLL is so “ sluggish") that 80 sits at the average of 8i rather than following it. The output phase 80 is nearly constant; that 尬， Vo

is the recovered unmodulated carrier. This serves as a reference for the phase detector to demodulate 8i. If the phase detector has a linear characteristic, its output V d is proportional to 阱， and V d is the demodulated output.

How narrow must the PLL bandwidth be? What is the relationship between the bandwidth and the length of time it takes the PLL to reach lock initially? How does the strength of carrier component of Vi depend on the amplitude of the phase modulation? Can thc PLL still recover a carrier if there is no can.ier component in vi?

可-6 PHASE MODULATION

In Fig. 1一7 ， a PLL is modified by summing a modulation signal Vm into the circuit to modulate the phase 80 • The voltage Vm tries to change the frequency ofthe VCO. But ifthe bandwidth of the PLL is wide enough , it can r臼pond quickly and adjust Vd ωcancel the effect of Vm . Thus , Vd = - Vm , and Vc = Vd + Vm remains essential1y constant. If the

→ PD~t仁 dj) L _ I IVo

平 1 (00)

Narrow bandwidth 50 。o average5 Oi

以 X <[一-v一一叮-"'ÇJ't

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FIOURE 1-6 Phase demodulation

TAlli---

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川

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川YyjiBρ川，

53

以lt川川叫ilddiM1i叫ti!#川巾

13

7

Chapters 2 through 5 give the mathematical analysis of phase-Iocked loops and describe their components-Ioop filt哎， phase detector , and voltage-controlled oscillator. Various circuit designs for the components are compared.

Chapters 6 through 8 answer some of the questions raised above that are common to many applications. These are questions about the sources ofnoise and its effects , the time required for lock acquisition as a function of initial frequency error, and the limits of frequency and phase variation that a PLL can track once it is in lock.

Chapters 9 through 11 look at specific PLL applications-phase and frequency modulation and demodulation , clock recovery from data signals , frequency synthesis. These chapters also address the questions raised above that are specific to the application.

Bibliography

可-8 ORGANIZATION OF THE TEXT

Chap. 1

h~^ V '--'7 V't

Introduction

Vm

Wide bandwidth so 一 Vd tracks Vm

6

可-9 OTHER INFORMATION ON PHASE-lOCKED lOOPS

The pu中ose of this text is to give the reader an understanding of the fundamentals of phase-Iocked loops and of their circuit design. From this introduction , the reader should be able to design phase-Iocked loops for most applications. For specialized and detailed information, the reader will want to refer to some of the literature listed in the Bibliography at the end of this chapter. The basics provided in this text should be a good preparation for such further advances.

Phase modulation

input phase ()i is constant (zero) , Vd is proportional to - ()o , and ()o is therefore proportional to Vm . Thus , the signal Vm modulates the phase ()o of the VCO.

What limits the amplitude of the modulated phase ()o? Can these limits be extended if necessary? Phase modulation implies some amount of frequency modulation. How large is this FM? Does it exceed the range of the VCO?

可-7 FREQUENCY SYNTHESIS

F!GURE 1-7

R. E. Best, Phase-Locked Loops: Theory , Design. and Applications , McGraw-Hill: New York , 1984.

A. Blanchard , Phase-Locked Loops: Applications to Coherent Receiver Design , Wiley: New York , 1976.

F. M. Gardn仗， Phaselock Techniques , Wiley: New York , 1979. W. C. Lindsey , Synchronization Systems in Communication and Control. Prentice-Ha!l: Englewood

Cliffs , NJ , 1972. W. C. Lindsey and C. M. Ch時， Eds. , Phase-Locked Loops , IEEE Press: New York , 1986. W. C. Lindsey and M. K. Simon , Eds. , Phase-Locked Loops and Their Application , IEEE Press:

New York , 1978. V. Manassewitsch , Frequency Synthesizers , Wiley: New York , 1987. U. L. Rohde , Digital PLL Frequency Synthesize月， Prentice-Hall: Englewood Cliffs , NJ , 1983.

A. J. Viterbi , Principles ofCoherent Communication , McGraw-Hill: New York , 1966.

BIBllOGRAPHY

A frequency synthesizer generates multiples of an accurate reference frequency ωi' For example , ifω1 krad怨， then the synthesizer might generate 100, 101 , . . . , 200 krad/s. That is ， ω。 =N，ωi ， where N varies from 100 to 200. Such a frequency multiplier can be realized with a PLL, as shown in Fig. 1-8. In this application , a frequency divider is included in the feedback path of the PLL. The integer N by which ω。 is divided can be selected b~ the user. When in lock, the PLL assures that the two frequencies ωi and ωo/N at the input to the phase detector (PD) are equal. Then ， ωo Nωi ， as desired.

What is the effect of the -;... N on the PLL bandwidth? What limits the size of N in practice? How long does it take the PLL to change frequency when N is changed? How do noise in Vi and in the VCO affect the purity of the synthesized frequency?

Frequency synthesis F!GURE 1-8

Vo

(凶。)

ω。 =N.的ω。/N=的

的

(ωi)

r

\

CHAPTER

2

PHASE-LoCKED

Loop BASICS

2-1 PHASE-LOCKED LOOP CHARACTERISTICS

We have seen that in some applications the PLL should be fast in following the input phase , and in others it should be slow. In other words , the bandwidth of the PLL should be either wide or narrow. This is determined by the characteristics of the phase detector (PD) , the voltage-controlled oscillator (VCO) , and the loop filter , which is introduced in section 2-7.

Another measure of a PLL's performance is the phase error-the difference between the input phase {}i and the VCO phase {}o . Consider the block diagram of a simple phase-Iocked loop shown in Fig. 1-1. When it is in lock, the VCO frequency ωo equals the input freqúency ωr﹒ (How the PLL initially attains frequency lock is dealt with in Chapter 8.) The control voltage Vc necessary to cause ω。 =ωi is provided by the PD output Vd' But the PD requires some phase error between {}i and {}o to produce this Vd' We will determine the size of this error in terms of the characteristics of the components of the PLL.

A PLL has other characteristics-frequency range over which it will acquire lock , lock acquisition time , tolerance of modulation without losing lock , output phase noise. These will be discussed in later chapters.

-11"

-11"

一11"/2

。e囂。d-()do言。i-()。

一宵/2

FJGURE 2-1

Vd

2

Vd

4

3

。00

(volts)

V d for no PLL input

Vdo

11"/2

(a)

(volts)

Vdo

Average Vd in lock ~

有/2

(b)

Vdo

(c)

11" 。d

For -~ <().< ~ 2 2

Vd=Kd(). + VdO

K/=~ ，，=一一一 =1.27V/r11" rad

11"

。e

Phase de紀ctor characteristic and model

~

Sec. 2-3 VCO Characteristics 11

2-2 PHASE DETECTOR CHARACTERISTICS

Let 8d represent the phase difference between the input phase and the VCO phase. The PD produces a voltage V d in response to this 8 d; a typical characteristic V d versus 8 d is shown in Fig. 2-1a. The curve is piecewise linear, and it repeats every 2 '11" radians. This periodicity is necessary since a phase of 2τr is generally indistinguishable from a phase of zero. When no signal V; is applied to the PD , it generates some 戶自-running voltage Vdo , which is shown as 2 V for this case. Corresponding to Vdo on the curve is some phase 8do (equal to τ!2 here).

The usual convention is to shift the characteristic so that a phase error of zero corresponds to v d Vdo ' Therefor巴， we define the phase error to be

8e 三 8d - (}do (2-1)

(see the characteristic in Fig. 2一lb). Because of this shift , 8e 0 does not usually co叮espond to V; and Vo being in phase , but for analysis purposes it is convenient to define it as zero phase error. We will also use the convention of defining the input phase 8i and the VCO phase 80 such that

oe=θ- 8，。 (2-2)

The plot of v d versus 8e in Fig. 2-1 b is called the PD characteristic. By definition , v d = Vdo corresponds to 8e = O. In the range τ!2三 8e 三 τ!2 there is a constant slope K，的

where

Kd三 dvjd8e (2-3)

In this case , Kd = (4 V)/(τradians) 1.27 V/rad. In the linear region , the PD can be modeled by

Vd Kße + Vdo (2-4)

which is represented by the signal flow graph in Fig. 2-1c. Kd is the PD gain , and Vdo is the free-running detector voltage.

2-3 VCO CHARACTERISTICS

A typical characteristic of a voltage-controlled oscillator is shown in Fig. 2-2a. Here , the VCO frequency ω。 is a linear function of the control voltage v c. The curve need not be linear, but it usually simplifies the PLL design if the slope is the same everywhere. As v c

varies from 0 to 4 V , the VCO varies over its range of 8 Mrad/s to 16 Mrad/s. Outside this range , the performance of the VCO is unacceptable in some way. When the PLL is in

12

ωo ! (r/s)

16M

12M

10M

8M

4M

Vco

4ωo ! (r/5)

6M

2M

一2M

的 is average of ω。 in lock

2 3 4 Vc

(a)

Aω0=凶。一 ω，

(b)

(c)

4ω。 = Ko(vc 一 Vco)

8Mr/ Ko= 一nrls =2Mr/sIV 4V

Vc

Phase-Locked Loop Basics Chap. 2

FIGURE 2-2 VCO characteristic and model

1ock ， ω。 =ωi. Suppose thatωi = lO Mrad/s. Then according to the characteristic in Fig. 2一站， ω。lO Mrad/s requires Vc 1 V. This is the static control voltage V("() corresponding toω。 =ωi. Notice that Vco is not a property of the VCO a1one; it a1so depends on the frequency ωi to which the PLL is 1ocked. (For examp1e, ifωi were 12 Mrad/s , then accordihg to Fig. 2-2 the Vc" wou1d be 2 V). This is in contrast to VdO' which is a property of the PD a1one.

r--

Sec. 2-4 Linear Model of PLL 13

The static operation of the PLL when it is in 10ck can be found from the PD and VCO characteristics. The 10ck condition isω。 =ωi. For the case ωi = lO Mrad/s , Fig. 2-2a shows v c = Vco = 1 V. This vo1tage is provided in tum by a PD vo1tage of v d = 1 V. From the PD characteristic in Fig. 2一 1 b, a phase error () e = - 0.79 radians is required to produce this v d . This average Oe in 10ck is called the static phase error ()eo . It is usually desirab1e to have ()eo near zero. It certain1y must not exceed :!::τ/2 radians , the 1imits of the 1inear portion of the PD characteristic. An expression for Oeo in terms of parameters of the PD and VCO characteristics will be deve10ped be1ow.

Sometimes it is convenient to refer to the output戶equency deviation Llw", where

Aω。三 ω。 ωt (2-5)

In 1ock, the average of ω。 equa1s ωi ， so Llω。 is a measure of how far ω。 is from its average in 1ock. A p10t of Llω。 versus Vc is essentially a shifted VCO characteristic , as shown in Fig. 2-2b. By definition , Llω。 o corresponds to Vc Vco •

The slope of the VCO characteristic in th巳 vicinity of the 10ck frequency is called the VCO gain Km where

K" 三 dω。/dvc = dLlω。/dv， (2-6)

Here we hav巳 Ko = (8 Mrad/s)/(4 V) = 2 Mrad/s!V. Then the frequency deviation can be mode1ed by

Llω。 Ko (vc - Vc,) (2-7)

where Vωis the contro1 vo1tage in 1ock. The signa1 flow graph in Fig. 2-2c represents Eq. (2-7).

2-4 L1 NEAR MODEL OF PLL

The descriptions of the PD and the VCO in Eqs. (2-4) and (2-7) are 1inear, a1though the 1inearities ho1d on1y for 1imited ranges. In Chapter 7 we will100k at the consequences of these range 1imitations. In this chapter, we assume that ()e and ω。 stay in the 1inear ranges of the PD and VCO. There are severa1 other texts [1-4] that treat this topic and may provide oth巳r usefu1 perspectives.

A1though the input and output signa1s of a PLL are often not pure sinusoids , for the moment we will assume they are , for the sake of phase no.tation:

Vi sin(ωl + 6J

Vo sin(ωit + 6,,)

全擎

14 Phase-Locked Loop Basics Chap. 2

where ωi is a constant, the average input frequency. As the dimension “ radians per second,, implies, frequency is the time derivative ofphase, where phase is the argument of the sine function.Thus , the output frequency from the VCO is

ω。== d(ωit + ()o)Jdt = ωi + d()oldt (2-8)

But as defined in Eq. (2-5) , åω。 =ω。 ωi. Therefore

Aω。 = d()jdt (2-9)

or

。10 = f åωo dt (2-10)

This relationship between ()o and åω。， together with the signal fIow graphs in Fig. 2-lc and Fig.22c, completes a linear model ofthc PLLbee Fig.2-3).The vco model now Includes an integrator to provide the phase tas the PLL output-This phase is fed back and compared by the PD with ()i of the input signal.

We have been referring to 峭的 the input frequency , but it is actually the average input frequency. The full expression for the input frequency isωi + d();fdt. This will be discussed further in section 7-2.

2-5 STATIC PHASE ERROR

By definition, when the PLL is in lock, the average ωo equals 峙， and the average åωn is zero. The sωic phase error ()eo is the average value of ()e in lock. From the signal fIow graph in Fig. 2-3 , we see that

Aω。 Ko(Kße + Vdo - Vco)

and taking the time average of both sides ,

Aω。 KoCKße + Vdo - Vco)

In lock, åω。= 0 , and ()e 三 ()eo. Therefore

()eo ( 一 Vdo + Vco)IKd (2-11)

For Kd = 1.27 V/rad , Vdo = 2 V , and Vco = 1 V, Eq. (2-11) gives ()eo = -0.79 radians , as determined graphically before.

--一

Sec. 2-6 PLL Bandwidth 可5

PD vco

VdD

。。FIGURE 2-3 Linear model of PLL

2-6 PLL BANDWIDTH

0;

In discussing the bandwidth of a PLL, we are concemed with the frequency at which ()i can vary and still be followed reasonably closely by ()o- This also holds for the frequency at which ωi can vary and still be followed by ω。 in the case of FM. Since bandwidth has to do with variations or ac signals , we form an ac model of the PLL by eliminating the dc parameters from the linear model in Fig. 2-3. The resulting ac model is shown in Fig. 2-4. The integration has been replaced by its Laplace transform 1紋， where s is complex frequency. When finding frequency response , we will replace s by jω.

Let the forward gain of the loop in Fig. 2-4 be G(s):

G(s) = KdKo1s (2-12)

The signal fIow graph in Fig. 2-4 is actually a system of equations which can be solved for the phase transfer function ()j()i. Those familiar with control theory can see by inspection that the transfer function is

。。如)

。I;(S)

G(s)

生一一些L0; I+G(s)

G(s)

1 + G(s)

GUω) (2-13)

1 + G(jω)

FIGURE 2-4 ac model of PLL

學


(s凹， for example , Phillips and Harbor [5]). It can be shown from this expression that IOolOil follows the smaller of unity or IG(jω)1. From Eq. (2-12) ,

IG(jω)1 = KdKo 1ω (2-14)

which falls off as 11ω. This is a straight line when plotted on log axes as in Fig. 2-5. For low w, IGuω)1 > 1, and IOolOil is about unity. For highω ， IG(jω)1 < 1, and IOolOil is about equal to IGuω)1. Therefore , the bandwidth ω3dB occurs when IG(jω)1 1. From Eq. (2-14) , this is when 1 KdKo

ω3dB KdKo (2-15)

For the PD and VCO characteristics in Fig. 2-1b and 2-2a, Kd = 1.27 V/rad , and Ko = 2 Mrad/s!V. Then ω3dB 2.55 Mrad/s.

Suppose we wished to reduce the bandwidth by a factor of 0.286 toω3dB = 0.73 Mrad!s. This can be realized by putting a voltage attenuator consisting of Ro and R2

between the PD and the VCO , as in Fig. 2-6a. The gain ofthe attenuator is represented by Kh , where

Kh = R2/(Ro + R2) (2-16)

For the values Ro = 25 k!1 and R2 = lO k!1, we have K;, = 0.286. The linear ac model for the PLL now includes Kh in the loop (see Fig. 2-6b) , and the forward gain is now

G(s) = KdKhKo1s (2-17)

As before , the bandwidth is determined by the frequency for which IG(jω)1 = 1. From Eq. (2-17) , this is at the frequency

gam

K"Kn IG(糾1= 寸土

0.7 缸，

I~I

FIGURE.2-5 Frequency response of PLL

?已

Sec. 2-6 PLL Bandwidth

(a)

G(s)

Kh = 一生一叮 Ro+R2

。\ o. I一「均 IIVc llA凶。rI 0。一~ +)-一吋的卡」叫你←干|ιL二二~ 11. ←?毛f

00 L

gam

I ~~ I

(b)

KdKhKo IG(糾1= 一一一一

w

(c)

FIGURE 2-6 Narrowed bandwidth PLL

ω3dB K~hKo

w

17

(2-18)

(see Fig. 2-6c). For Kd = 1.27 VIr祠， Kh = 0.286 , and Ko = 2 Mtad/s!V, the bandwidth has been reduced to ω3dB 0.73 孔1rad/s ， as desired.

Since the product of these three gains occurs often in the analysis of PLLs, it is standard notation to let

K=KdKhKo (2-19)

可8 Phase-Locked Loop Basics Chap. 2

K is called the “ loop gain ," although it does not inc1ude the integration 1心， which is also in the loop gain (see Fig. 2-6b). From Eq. (2-18) , K is also the 3-dB bandwidth of the PLL. From Eqs. (2-13) , (2啊 17) ， and (2-19) , the transfer function is

。。如)

。;(s)

K

s + K (2-20)

A PLL with a simple attenuator (as in Fig. 2-6a) is called afirst-order phase-Iocked loop because the transfer function has a first-order polynomial of s in the denominator.

While the attenuator gain Kh has satisfied the ac requirements of the PLL as far as bandwidth , it also affects the static behavior of the PLL. Returning to the complete characteristic of the PD in Fig. 2-1b , we see the maximum Vd is 4 V. Then , after attenuation by Kh 0.286 , the maximum Vc is now only 1. 14 V. According to the characteristic in Fig. 2一泊， this restricts the VCO to a maximu日1 frequency of 10.3 Mrad/s 一-barely enough range to let the PLL lock to an input frequency of 10 Mrad/s. In the next section we look at a solution to this problem , but first we will analyze an example involving the PLL in Fig. 2-6a.

EXAMPlE 2-1

A PLL has the VCO characteristic ωo versus Vc shown in Fig. 2-2a. The input frequency is ω10 Mr叫怨 giving a static control voltage Vco 1.0 V. The slope of the characteristic is Ko = 2 Mrad/s!V. The PD characteristic is that shown in Fig. 2-1b and reproduced in Fig. 2-7. The slope of the PD characteristic is Kd = 1.27 V/rad. There is a sinusoidally modulated phase at the input 8; 0.3 sin (ωmt) ， whereωm 5 Mrad/s.

We will analyze two situations: first with no attenuator (Kh = 1) , and then with an attenuator with Kh 0.286. In each case we will find the static phase offset 8eo ' the bandwidth K , and the amplitude of the output phase swing 80 ,

For Kh = 1, Vco = 1.0 V co位espondsωVd = 1.0 V , and from the PD characteristic in Fig. 2-7 , the corresponding static phase offset is 鈍。= - 'IT12 + (1. 0 V)/Kd = 二旦二旦

旦坐盟主﹒ The bandwidth is given by K = KdK~o = l .55 Mrad/~. The magnitude of the frequency 自sponse is obtained by taking the magnitude of Eq. (2-20) wi也jωreplacing s:

|如 1=11 了几 | K

Jω2 + K2 (2-21)

This response is plotted in Fig. 2-8a. At ω=ωm = 5 Mrad/s , Eq. (2-21) gives 18j8A = 0.45. Since the amplitude of 凹的 0.3 radians , the amplitude of 80 is 0 .45 x 0.3 =生135

旦坐全世﹒ Figure 2-8b compares the amplitudes of 8; and 80 , Note that there is also a phase shift of 63 deg. due to the phase of the response 8)8;.

For Kh = 0.286 , Vc = 0.286vd' or Vd = 3.5vc . Then corresponding to Vc = Vco = 1.0 V , we must have V d = 3.5 V. From the PD characteristic in Fig. 2-7 , the correspond-

Sec. 2-6 PLL Bandwidth

-"/1"

galn

0.14

一芷 -0.79 2

Vd .& (volts)

1.18.:!!... 2

"/1"

FIGURE 2一7 Phase detector characteristic for Example 2-1

。e (rad)

5M (rad/s)

w

(a)

FiGURE 2-8 Response to phase modulation in Example 2-1

ing phase offset is 8.旬， = -'IT/2 + (3.5 V)/Kd = 1.18 radian~. The new bandwidth is K' = Kß~o = Q.73 Mrad!~. The new response I可/8;J is plotte司 in Fig. 2-8a. At ω=ω = 5Mr;吋怨， Eq.(231)givesltF/Ozi=0..14.sincetheamplitudeofozisojradians， th;ar削itude of 80 ' is 0.14 千 0.3 = 0 .42 radian~. Figure 2-8b compares the amplitudes of 8; and OJ-Note that thueIs a phase shifk of 82deg.due fo the phase of the FesponsetF/Oi.

19

i


phase

0.3

0.135

0.042

(b)

FIGURE 2-8 ( continued)

2-7 LOOP FILTER

By putting an attenuator in thc PLL, we reduced theac galn k and therefore reduced thc bandwidth , as desired. But we also reduced the dc gain and therefore limited the dc voltage V

co which the PD can provide to the VCO. This greatly 則叫s the frequency

range of the PLL. The solution is to replace the attenuator in Fig. 2-6a with a loop filter. This filter wi1l sti1l act as an attenuator at high frequencies , but it wi1l have unity gain at

dc. A simple loop filter is formed by adding a capacitor to the attenuator，的 in Fig. 2-

9a. If the capacitor is large enough , th巳 ac attenuation is unaffected. But now the dc path to ground is blocked , and the dc component of Vd is not attenuated. The transfer function

of this loop filter is

where

F(s) = Kh s + ω2

s + ωl

Kh

<Ù f

ω2

R2

Ro + R2

(Ro + R2)C

R2C

(2-22a)

(2-22b)

(2-22c)

(2-22d)

r

s+ω2 月s)=Kh 一一一一

s+ω1

F(0)=1 ~ 546pF

(a)

G(s)

Kh=~ H 舟。 +R2

1 ω，=--可---

(Ro +R2)C

ω2= R2C

8j ~ r \ 8e _ I I Vd _ I I Vc 已 Illwo I I 80 一一~寸 r一一門的「一一~ F(s) I一←l 凡「一~ I/ s r一，.--

。。于|(b)

I F(jw) I

w, ∞2

w

Kh

(c)

gam

G(s) = KdF(s)κ戶/s

K=KdKhKo

requireω2<K

已d

(d)

FIGURE 2-9 Expanded frequency range PLL

告對

喜


The frequency response IF(jω)1 ofthe loop filter is plotted in Fig. 2-9c. At dc , the gain is F(O) 1, and at high frequencies (greater than ω2) ， the gain is Kh' as desired.

The signal flow graph of the PLL in Fig. 2-9b includes the gain F(s) of the loop filter. The gain of the forward path is

C(s) = Kf(s)Ko/s (2-23)

The frequency response of IC(j ω )1 is plotted in Fig. 2-9d. Ag伊伊a剖1I肌I10ιWο'J峙叫島蚓|仆is the lower of unity and IC(jω)1. At high frequencies , IF(jω)1 = Kh' and IC(jω)1

1 for ω = KdKhKo. Then , as in Eq. (2-18), the bandwidth is

ω3dB = KdK~o 三 K (2-24)

This result for the bandwidth has assumed IF(jω)1 = Kh when ω = K. But IF(jω)1 = Kh only for ω>ω2. Therefore , we require that

ω2 < K (2-25) .

as shown in Fig. 2-9d. If ω2 is less tha叫 K， t由hen(compare Figs. 2-6c and 2-9d). A thorough analysis of the effect of ω2 is carried out in Chapter 3.

The PLL traIÍsfer function is obtained from Eqs. (2-13) , (2-22a) , and (2-23):

Oo(s)

。'ls)

Ks + K，ω2

S2 + (K + ω')5+ K，ω2 (2-26)

Because the denominator has a second-order polynomial in s , a PLL with a loop filter is called a second-order phase-Iocked loop. In Chapter 3 we look at other loop filters; they also result in a second-order PLL.

2-8 STATIC PHASE ERROR WITH A LOOP FILTER

It is possible to design loop filters with dc gains other than F(O) = 1. Therefore , we will need a general expression for the static phase error in terms of F(O). The complete linear model (including dc parameters) in Fig. 2-3 is augmented to include the loop filter in Fig. 2-10. From this signal flow graph , we see that

âwo = OeKdF(S)Ko + Vdcf'(s)Ko - VcJ(o

and the average (dc or s 0) relation is

Aω。 = OeKdF(O)Ko + Vdcf'(O)Ko - VcJ(o

Sec. 2-8 Static Phase Error with a Loop Filter

Phase detector

Loop Voltage-controlled filter oscillator

-國--肉、---、

Vdo Vco

FIGURE 2-10 Full 1inear model of PLL

23

But the static phase error Oeo is defined as Oe when the PLL is in lock (when âω。= 0). It follows that

見。 - Vdo/Kd + Vco/KdF(O) (2-27)

For the particular case of F(O) = 1, this reduces to Eq. (2-11). In Chapter 3, we will see how to use an active loop filter to make F(O) essentially infinite so that Oeo is unaffected by Vco.

EXAMPLE 2-2

A PLL has a PD with the characteristic in Fig. 2-lb and a VCO with the characteristic in Fig. 2-2a. The input frequency isω12 Mrad/s. Design a loop filter to realize a bandwidth ofω3dB 0.73 Mrad/s. Find the static phase error.

From the characteristics , Kd = 1.27 V/rad, and Ko = 2 弘1rad/slV， Vdo = 2 V, and Vco = 2 V (the voltage for which ω。 =ωi = 12 Mrad/s). From Eq. (2-24) , Kh = ω3dB/

KdKo = 0.286. From Eq. (2-22b) , this is satisfied by Ro = 益主QandR2 = 盟主f!. First we will try a design with no capacitor; that 的， F(O) = 0.286. From Eq. (2-27)，仇。= 3.93 radians. But this far exceedsτ12 1.57 radians , the limit for which the linear model holds. Therefore, the solution is false , and the PLL can't lock to the input frequency.

Adding a capacitor to the loop filter will give back the necessarydc gain to let the PLL achieve lock. ThenF(O) = 1, and Eq. (2-27) gives Oeo = 旦， which puts the PD in the center of its range. The value ofthe capacitor must be chosen to satisfy Eq. (2-25) , which requires that the resulting zero atω2 be less than 0.73 Mrad/s. We choose a factor of four less and make ω2 = 0.183 Mrad/s. Then , from Eq. (2-22d) , C =豆豆 pF. The final design is shown in Fig. 2-9a.


REFERENCES

[1] A. J. Viterbi , Principles of Coherent Communication , McGraw-HilI: New York , 1966.

[2] A. Blanchard , Phase-Locked Loops: Applications to Coherent Receiver Design , Wiley: New York, 1976.

[3] F. M. Gardner, Phaselock Techniques ，嗎Tiley: New York , 1979

[4] R. E. Best, Phase-Locked Loops: Theory , Design , and Applications , McGraw-Hill: New York, 1984.

[5] C. L. Phillips and R. D. Harbor, Feedback Control Systems , Prentice-Hall: Englewood Cliffs , NJ , 1988

r

CHAPTER

3

Loop FILTERS

In Chapter 2 we saw that the PLL bandwidth

ω3dB = KdKhK，。三 K (2-24)

is determined by the gain Kd of the PD , the high-frequency gain Kh of the loop filter , and the gain Ko of the VCO. Since the PD and the VCO designs are usually less flexible , the design of the loop filter is the engineer's principle tool in determining the bandwidth. We also saw from

(}eo - Vdo/Kd + Vc)KdF(O) (2-27)

that a large dc gain F(O) of the loop filter is desirable. For a passive filter, the maximum dc gain is unity. In this chapter, we look at active loop filters that achieve an F(O) that is essentially infinite. In some applications it is desirable to add.a high呵frequency pole to the loop filter. Thus , the engineer has three parameters to choose in designing the loop filter: the high-frequency gain Kh' the placement of the zero that sends F(O) to infinity, and the placement of the pole. This chapter gives a number of circuits for realizing the filter design. It also analyzes the response of the PLL in terms of the loop filter's parameters.

27

The second part of the 100p filter design is to realize infinite gain at dc by an integrator, as in the circuit in Fig. 3一 1a. By summing the output of the amp1ifier

with the output of the integrator

V2 = Kh V"

Active Loop Filter Sec. 3-1

γ

Chap.3

The design of an active 100p filter begins with an amp1ifier with gain Kh to modify the bandwidth of the PLL. This is realized in Fig. 3-1 a by an active circuit with gain - Kh = -R

2/R

1• (For a review of op amp circuits , see Kennedy.[1]) When rea1ized by a passive

v01tage‘divider (as in s巴ction 2-6) , Kh wa剖sn間敝ec臼es鈴sa缸叩r討i句1)句y 1e巴鉛叫t血hanwith an active 100p fi1ter, but in practice, most PLL designs call for Kh < 1.

Loop Fi1ters 26

a-:.1 ACTIVE LOOP FIL TER

I v" dt RjC V3 =

we get the comp1ete contro1 voltage 地「1伽一

嘲-

L卅一「1

可w

v + 、'‘

v -一

C V 一關

m-m一

缸一「

i

R1C (3-1) I v" dt

的 diagrammed by the signa1 flow graph in Fig. 3-1b. The corresponding Lap1ace transform for this re1ation is

(3-2)

At high frequencies (s →∞) the second term goes to zero , and the gain Kh dominates. At dc (s 0) , the second term goes to infinity , and the gain l!R1Cs of the integrator dominates. The comp1ete gain F(s) of the 100p filter is therefore

(3司3)s +ω2

S Kh

R1C S F(s) = Kh +

志

學

Vc V2 + V3 Khv" + Vd

只 = Khv" + (l!R1Cs)v"

(3-4)

(3-5)

The frequency response ofthe FUw) given in Eq. (3-3) is p10tted in Fig. 3-2. As ωgoesto zero , the magnitude of FUω) goes to infinity，的 desired. For ωgreater than the break due to the zero atω2 ， the magnitude is about Kh .

Kh = R2/R 1

ω2 = l!R2C

where (a)

Vd

.q 4- t" .. F(s)=Kh 一一二土s

Frequency response of active filter FIGURE 3-2

w

凶官

|月(b)

向 I Vc

一一~ 月s) 卜一一，

s+ W2 F(s)=Kh 一三一-

Kh

Kh=R2/Rl' ω2= 1/R2C

Model of proportional-plus-integral loop filter (or "active" filter)

(c)

FIGURE 3-1

28 Loop Filters Chap. 3

3-2. STATIC PHASE ERROR WITH ACTIVE LOOP FILTER

A block diagram of the complete PLL including an active filter is shown in Fig. 3-3. It emphasizes the three main parts to the design of a PLL. This chapter deals with the loop filter, and the next two chapters deal with the phase detector and the VC0.

The linear model of the PLL in Fig. 3-3 has already been given in Fig. 2-10; it is repeated here in Fig. 3-4. In Fig. 2一10 ， F(s) represented a passive loop filter. Now it represents any form of loop filter, including an active one.An analysis of the linear model showed that the static phase error is

8eo - Vdo/Kd + V C(,IKdF(O) (3-6)

Now , V co is the VCO control voltage necessary to bring the frequency ωo equal to the input frequency ωi in lock. Therefore, Vco is not a property of the VCO alone; it depends on ωi in the particular application. For the designer to be in control of 8em it is usually important that 8eo not be a function of V co . For an active loop filter , F(O) ∞， and Eq. (3-6) becomes

8eo -VdjKd (3-7)

The disappearance of Vco can be explained from a circuit standpoint by considering the loop filter circuit in Fig. 3-1a. During lock acquisition, the integrator accumulates enough charge on the capacitor to provide the control voltage Vc = Vco needed by the VCO when in lock. This is the V3 component of V c. Once the PLL is in lock , V.的 the average of 凹，must go to zero so the integrator stops charging. Averaging Eq. (2-4) gives

V d = 6J(d + V do 8eaKd + V do

which leads immediately to Eq. (3-7). The remaining contributor to 8 eo in Eq. (3-7) is V do . This is the free-running voltage

of the PD when there is no signal at the PLL input. In Chapter 11 , it will be shown that designing for 8 eo 0 improves the purity of a synthesized frequency. From Eq. (3-7) , this transl泌的 into the desirability of designing for Vdo = O. We will see in Chapter 8 that acquisition is easier when Vdo O. In any case, a basic PLL design consideration is to keep the free-running PD voltage near 自ro:

Vdo = 0 (desired) (3-8)

FIGURE 3-3 PLL with loop filter

γ

Sec. 3-3 Alternative Active Loop Filter Designs

s+凶2月s)=Kh ~王一

PD

Vdo

FIGURE 3-4

LF

Vco

Linear model of PLL

29

vco

For this reason , Vdo is also called the phase detector offset voltage. The next section suggests some loop filter designs to help the PD achieve Vdo = O.

3-3 ALTERNATIVE ACTIVE LOOP FILTER DESIGNS

The circuit in Fig. 3-1a is a direct way to realize a proportional-plus-integralloop filter. The signal V2 is proportional to v d , and V3 is the integral of V d . A simpler way to realize this function is shown in Fig. 3-5a, where V2 and V3 are added by placing R2 and C in series. The only difference is that there is a sign inversion; the transfer function is now - F(s). To be consistent, our convention is that the input to the active loop filter is - V d so we still have Vc F(S)Vd.

In order to maintain negative feedback for the stability of the PLL , the inversion in an active loop filter must be accompanied by either a negative PD gain - Kd or a negative VCO gain - Ko. Since the sign of the PD gain is easily reversed by reversing the Vi 組d Vo

inputs , we will assume throughout this text that an active loop filter is coupled with a PD with gain - Kd' where Kd is always positive. Corresponding旬， the VCO gain Ko is always assumed to be positive.

The PD characteristic in Fig. 3-5a has Vd = 0 for 8e = 0; that 詣， V do = o. This is desirable according to Eq. (3-8). In practice, Vdo will not be exactly zero , of course, but a phase detector used with an active loop filter should have a Vdo that is nominally zero.

Suppose that a PD produces a nonzero voltage Vao for 8e = 0, as in Fig. 3-5b. This characteristic can still be used with an active loop filter if the op amp is referenced to Vr

rather than ground. Then the PD voltage is effectively

Vd = Vr 一九 (3-9a)

and the voltage for 8e 0 is

Vdo = Vr 一九。 (3-9b)

一 Vd

一 V2+ -v3+

Vd

().

Kh=R2IRl ，剖2=1/R2C

(a)

V.

Vd= V，- 均

7r/2 π12 ().

(b)

R1

().

Vd=Vb一均

。e(c)

FIGURE 3-5 Active loop filters using one op amp

Vc

Vc

v c

Sec. 3-4 Active Loop Filter 0行'sets 31

Now we can set V do 0 by choosing V r V.αo'

There is always some error in realizing Vr Vao . Therefore , it is better to take advantage of a natural balance when it is available. Some phase detectors produce a voltage Va and its complement Vb' as shown in Fig. 3-5c. Then if the PD voltage is taken as

Vd = Vb 一九 (3-10a)

the voltage for (Je 0 is

Vdo 丸。一九。 (3- lOb)

The symmetrical design of a PD producing Va and Vb tends to provide a good match between V ao and V bo ' which reduces V do . The transfer function F(s) is the same as that for the filter in Fig. 3-5a when the values of R t> R2' and C are the same. The penalty is that the circuit in Fig. 3-5c uses twice as many resistors and capacitors.

各-4 ACTIVE LOOP FILTER OFFSETS

In accord with Eq. (3-8) , we try to keep the PD free嘴巴running voltage Vdo as small as possible. Therefore, Vdo is also referred to as the phase detector ~加et voltage. But the loop filter , now with an active component, contributes its own share of offset to Vd.

Consider the loop filter in Fig. 3-6a. This is the same as the filter in Fig. 3-5b but with an extra resistor R 1 to mitigate the effect of the input bias current of the op amp. Let the input offset voltage of the op amp be VIO (this is the dc voltage that appears across the input terminals of the op amp). Let the input offset current of the op amp be 110 (this is the difference of the dc currents 1 B 1 and 1 B2 into the two input terminals of the op amp). It can be shown that these offsets effectively add a dc voltage VIO + haR 1 to 句， as the signal flow graph in Fig. 3-6b represents. The dc offset V r - V{/o is contributed by the error in setting Vr = Vao [see Eq. (3-9b)]. Our convention will be to combine the dc sources and label the whole as the PD offset voltage:

V do (Vr - V{/o) + 阱。 + haR l (3-11a)

This is represented by the signal flow graph in Fig. 3-6c. Note that the PD is now considered to be responsible for all dc offsets, even those originating in the loop filter. Although this doesn't correspond with the physical circuit , it simplifies our nòtation and analysis.

For the balanced loop filter in Fig. 3-5c , the expression for PD offset voltage is similar. Combining Eq. (3- lOb) with the op amp offsets:

V do (Vbo 一九) + V IO + haR l (3-11b)

32

PD

(a)

V，-\I已。的。 +R1/1O

(b)

Vdo = V,- Vao + 的。+爪的(c)

110軍 181 一 182

LF

Loop Filters Chap. 3

FIGURE 3-6 Offset voltage with an active filter

Typical specifications for an op amp a防 IVIOI 三 5 mV and Ihol 三 20 nA. Lasertrimmed op amps are available with IVIOI 三 0.1 mV , and FET間input op amps typically have 1/10 1 三 1 nA.

3-5 PLL FREQUENCY RESPONSE

We form the ac model for the PLL (see Fig. 3-7) by eliminating the dc parameters from the linear model in Fig. 3-4. This is the same as the model in Fig. 2一俑， but now F(s) is the response of an active loop fi1ter given in Eq. (3-3): F(s) = Kh(s + ω2)/ s. The forward gain of the PLL is given by

G(ωs) = K,

= K(s + ω2)/S2 2 (3-12)

~

H P

1

Sec. 3-5 PLL Frequency Response 33

6(s)

。 6(s)。 1+6(s)

FIGURE 3-7 ac model of PLL

where

K三 KdKhKo

The magnitude of G(}ω) is plotted in Fig. 3-8. Let the closed明loop phase transfer function be represented by H(s). Then from Eq. 2-13 ,

OoCs) H(s) ==一

O/s)

G(s)

1 + G(s)

Ks + K，ω2

S2 + Ks + K，ω2 (3-13)

For ω2 < K , it is roughly true that IH(}ω)1 follows the lower of unity and IG(jω)1 ， as illustrated in Fig. 3-8. There is some peaking in the response , but this becomes less the

w2<K

161

6(s) = KdF(s)Ko/s

K=KdKhKo

。 6(s)H(s) =一=一一一一-0; 1 +6(s)

w

FIGURE 3-8 Frequency response of PLL


farther ω2 is to the left of K. As we found for the passive loop filter in Chapter 2 , the active loop filter causes a second-order polynomial in s in the denominator, and the PLL is a second-order phase-locked loop.

The active loop filters shown in Fig. 3-5 and the corresponding transfer function in Eq. (3-13) serve in most PLL applications. Passive loop filters (see Fig. 2-9a) are used in some integrated PLLs , such as the National NE564 and the Exar XR-210 , but a better performance can always be obtained using an active loop filter in a custom PLL design. Therefore , all PLL applications in the following chapters use an active loop filter*.

The expression for H(s) in Eq. (3-13) is in terms of K and ω2' These two parameters are easily identified in the frequency responses (see Fig. 3-8) , and they are easily related to the PLL components [see Eqs. (2-24) and (3 日]. We mention in passing an altemative expression the reader will often encounter in other PLL literature. It expresses H(s) in terms of a damping ratio ~ and a natural frequency ωn ﹒ Equation (3-13) can be expressed as

n Eω

勻，心-

ω一+

+-J P一切

的叫一2

立一+

-2 -ed --CO H

(3-14)

where

~ = 0.5JKIω2 ， ωn = JKω2 (3-15)

This notation is derived from common usage in control theory , but it can be misleading. 吶閃閃<< K (when ~ >> 0.5) , the response IHI hardly depends onω2' But ωn 1S always a strong function of ω2 ， giving the impression that the bandwidth always depends on ω2' (Note thatωm the geometric mean of K and ωz， is halfway between them on a log frequency scale.)

Let the frequency for which IHI is a maximum be called the peaking j均quency ωρ(see Fig. 3-8). We can findω'1' by setting (d/d，ω)IH(}ωw = 0 and solving for ω ， where H(jω) is found from Eq. (3-13). The result is

ω'1' ω2[(2K/ω2 + 1)1/2 - 1]112 (3-16)

Let the peak value of IHI be H p 三個(jω'1' )1. From Eq. (3-13) and Eq. (3-16) , this gives

H p = [1 - 2α2α2 + 2α(2α+α2) 1丘] -112 (3-17)

where

α 三 ω2/K

These expressions for ω'1' and H p don 't lend much insight. Therefore , we give some approximations that hold for each of three different cases. The overdamped case isω2/K

* There are other types of activ巳 Ioop filter. In particul缸， a Ioop filter with two integrators provides zero phase error during a ramp of the input frequency. It makes the PLL a third-order phase-locked loop. This speciaIizedapplication is beyond the scope of this book; “ active loop fiIter" wiIl alwavs mean the 1000 filter shown in Fiρ 可『

r

Sec. 3-5 PLL Frequency Response 35

TABLE 3-1 PEAKING PARAMETER APPROXIMATIONS

Damping ω2/K Wp Hp

Over <0.25 1. 2ω23/4K'/4 1 +ω2/K

CriticaI 0.25

反1.15

Under >0.25 必互主

< 0.25 , the critically damped case isω2/ K = 0.25 , and the underdamped case isω2/K >

0.25. The corresponding approximations for ωl' and H p are given in Table 3-1. We will be most interested in the overdamped and critically damped cases. The

actual values of wp/K (the normalized peaking frequency) and Hp - 1 (the 伊拉ing

excess) are plotted in Fig. 3-9. These curves are compared with the approximations for overdamping (see the dashed curves in Fig. 3-9). For ω2/ K < O. 1, it holds within 1091: thatω'p/K = 1. 2(<村的3/4 ， or

ω'1' = 1. 2ω//4KII4 (3-18)

組d it holds within 30% that Hp 一 ω2/K ， or

Hp = 1 +ω2/K (3-19)

Equation (3-18) says thatω'1' is about a quarter of the way from ω2 toward K on a log axis (see Fig. 3-8).

10- 1

wplK

1.2 (叫21約3月

凶21K

10-2

10-3

10- 4 10-3 1。一 10- 1

w21K 一--

FIGURE 3-9 Peaking parameters H" and ωn

r

v v ./

v v

v / / /

v /

V

37 PLL Step Response Sec.3-6

30

百 20o

.J:. g

'" >o ... z g æ 10

Chap. 3

The response at {}o to a unit step of phase at (}i is found by taking the inverse Laplace transform of H(s)心， where H(s) is given in Eq. (3-13). The results for some selected dampings are given in Eq. (3-20).

(3-20a) 。'0 1 - e-Kt For ω2 0 ,

(3-20b) 1 - e-O.SKt(l - 0.5Kt) 。=O

{}~ = O

for ω2 = K/4 ,

1.0 0.8 0.6

ω2/K 一一---(a)

Overshoot parameters

It would seem from the step responses that it is always best to make ω2 as low as possible. This slows the response only slightly, and it makes Jhesystem very stable, avoiding overshoot. However, from Eq. (3-5) this requires a large capacitor, and we will see that a larger capacitor takes longer to charge during lock acquisition. Therefore, a good rule of thumb is to make ω2 K/4 when peaking is not critical; this assures fast acquisition. Chapter 10 looks at an application with many tandem PLLs. In that case, peaking of the frequency response is more of a problem than acquisition time , and ω2 is selected to limit the peaking to some small value.

Loop Filters 36

3-6 PLL STEP RESPONSE

0.4 0.2

(3-20c)

Figure 3-10 plots these responses as well as those for some other dampings. Note that as ω2 gets closer to K , the overshoot increases. The amount of overshoot is plotted as a function of ωzlK in Fig. 3-11a. For example, the overshoot is 13% for ω2/K = 0.25. The position of the peak of the step response along the normalized time axis Kt is plotted in Fig. 3-11 b as a function of ω2/K. For example, the peak is at Kt = 4.0 for ω2/K = 0.25.

FIGURE 3-11

\

\ k 、、、、........ t-- -

1.0

1 - e-O.SKt(cos 0.866Kt 一 0.577 sin 0.866Kt) for ω2 = K,

0.8 0.6

凶2/K 一一一←

(b)

0.4 0.2

8

7

6

4

3

2

5

HDDZg。〉chou-間。且這』心也

~2=K 11\ ~ /kfpk 、\

11 豆豆。\ ........... 、、、、、--

1--

1/ //Y /r- 、- -戶

A//;夕/

'1// IJ 于

10 9 8 7 6

Step response of PLL

5

Kt 一一一~

4 3

FIGURE 3-10

2

1.2

1.0

0.8

0.6

0.4

0.2

38

3-7 LIMITED LOOP FILTER BANDWIDTH


In Fig. 3-2, we assumed the response of the loop filter has a gain of Kh from ω? all the way out toω= ∞. In practice, the response IF(jω)|of an active loop filter rolls off at some frequency 峙， as shown in Fig. 3-12. The expression for the filter's transfer function is

|們

κh

s+ω。F(s)=Kh一一一一二i一

叫 s(s/.ω3+ 1 )

ω2 叫3

(a)

IGI 2

一+

旦河

b

s

一低仙也飢

-dnbr k-1 倒叫

ω3

(b)

w

w

FIGURE 3-12 Frequency response of (a) active loop filter, and (b) corresponding PLL phase transfer function H

r

Sec. 3-7 Limited Loop Filter Bandwidth 39

5+ω勻F(s) = Kh -, -. --"

s(slω3 + 1) (3-21)

Th巴 limited bandwidth of the op amp itself introduces a pole at

ω3 2τT R]

R] + R2

GBP = 2主-GBP1 + Kh

(3-22)

where GBP is the gain-bandwidth product. For example, voice-grade op amps typically have GBP = 1 MHz. Then , for Kh<< 1 ， ω3 = 2τ(l MHz). High-performance op amps such as the Harris HA-2540 are available with a GBP as high as 400 MHz.

How does ω3 affect the transfer function H(s) of the PLL? The forward gain G(s) 三KdF(S)Kols with the cutoff in Eq. (3-21) is then

5+ω勻G(s) = K? 臼

sL'(s1ω3 + 1) (3-23)

H(s) = G(s)

1 + G(s)

Ks + Kω2 s31ω3 + S2 + Ks + K，ω2

(3-24)

The responses IG(jω)1 and IH(jω)1 are plot能d in Fig. 3-12b, where the additional break due to the pole 前 ω3 is evident. If ω3> K , then IG(jω)1 still crosses unity 前 ω = K, and the PLL bandwidth is K. Provided thatω1 is not too c10se to K , the step response will still be about that shown in Fig. 3-10. For the case ω2 = KI4 and ω3 = 4K, it can be shown the step response is

Kt _-O.382Kt ~-2.6]8Kt {}o 1 - 3e- Kt + e-U.JðLKt + e

This response is plotted versus normalized time Kt in Fig. 3-13. The overshoot is now 18% (compared with 13% for the case ω2 = KI4 and ω3 ∞). Therefore, a good rule of thumb is to keepω3 三 4K ， and then it can be roughly ignored in the analysis of the PLL response. The choice of ω3 is also influence by the desired acquisition range (see section 8-3).

In some applications , it is desirable to purposely introduce a cutoff at some lower ω3' One method for implementing this is shown in Fig. 3-14. The resistor R] has been split in two , and a capacitor C3 bypasses to ground the frequencies above ω3' The relationship is

ω3 = 41R]C3 (3-25)

As before , we still have Kh R2IR] and ω2 l1R2C The introduction of a pole atω3 may be necessary to suppress high-frequency

components that the op amp cannot handle. The op amp , through feedback , must be able to maintain 三 0.3 Vp-p at its input to avoid overloading its input stage. In Chapter 11 we will see thatω3 can be used to reduce phase jitter of a synthesized frequency.

40

1.2

1.0

0.8

0.6

0.4

0.2

-Vd

/""T~---: 同~1---

/ 1多〈LJ4K 文-迋泣;;;;~

ω3 ∞

/ w

“2=K/4

VL 2 3 4 5 6 7

Kt 一一一#

FIGURE 3-13 PLL step response with pole at 的方

C3~ Kh=R2/爪， ω2= lIR2C， ω3=4/R， C3

FIGURE 3-14 loweredω3

EXAMPLE 3-'司


8 9 10

Active loop filter with

The input frequency to a PLL is 叫= 52 Mrad/s. The desired PLL bandwidth is K = 50 krad/s , and the peak response is to be H p = 1.01. The PD and VCO characteristics are those shown in Fig. 3-15a and b. The op amp specifications are VIO = 5 mV , 110 = 20 nA , and GBP 1 MHz. The capacitor value C is to be kept less than 0.2μF (small enough not to be polarized). Compare designs using (a) an unbalanced active loop filter, (b) a balanced active loop filter , and (c) a passive loop filter.

(a) The PD has balanced outputs Va and Vh available , but suppose we use only VαThen the op amp must be referenced to Vr = 丸。= 2.5 V，的 in Fig. 3-15c. Since Vd =

~

Sec. 3-7

V.

Vr

Limited Loop Filter Bandwidth

L門a 1

... 5 ←一一一一事、

|2.5i..品。|

F

-'1r π 0.

一'1r一 1品

。;。

Vb

'1r

(a)

10 kO 0.2μF

Vr = 沌。士 5%

(c)

均可;:亨 μ

(e)

。e-2.5

V.

Vb

Wo (rad/s)

55M

Vco

2.5

(b)

640kO 10 kO 0.2μF

R, R2

(d)

均可;:

亨(f)

FIGURE 3-15 Characteristics and loop filters for Examples 3-1 and 3-2

41

Vc

2.5 V 一九， then Kd is the negative of the slope of the Va curve: Kd = 5 V/27r rad = 0.8 V!rad. The VCO gain is Ko (1 0 Mrad/s)/5 V 2 Mrad/s!V. But K KdKhKo' Therefore , Kh = K/KdKo = 0.0313. From Eq. (3-19) , H p = 1 +ω2/K. Hence

ω2 (Hp 一 I)K = 0.01 K = 500 rad/s

Since ω2 - I/R2C , choosing C as large as possible will allow R2 andRI to be as small as possible. According to Eq. (3-11a) , this will reduce Vdo ' Therefore , we choose C =生2


蛙f. Then R2 = 11ω2C = 1旦主f!. Now , Kh = R2/R 1, so RI = R2/Kh = 10 kÛ/0.0313 =

32立kÛ. From the VCO characteristic , the static control vo1tage is Vco 1.0 V; this is provided by charge on the capaciωr bui1t up during lock acquisition. Suppose Vr matches Vao to within ::1: 5%. Then Vr - Vao = 0.05 x 2.5 V = 125 mV , and from Eq. (3-11a) , Vdo = (Vr - Vao) + VIO + I f(ßI = 125 mV + 5 mV + 6.4 mV = 136.4 mV. From Eq. (3-7)，仇。 - Vdo/Kd = -=0.171 radian~ ， or 一 10 deg. From Eq. (3-22) ， ω3 = 6.1 Mrad/s. This is so much greater than K由at it has virtually no effect on the PLL response.

(b) Now we wiI1 use both Va and Vb outputs of the PD and apply their difference to the loop filter in Fig. 3-15d. Then Vd = Vb 一九， and Kd is the difference of the slopes of the two curves: Kd = 0.8 V/rad - (一 0.8 V/rad) = 1.6 V/rad. Since Kd is now greater, Kh must be reduced ωmaintain K = 50 kradis: 凡 = KJKdKo = (50 krad/s)/( 1.6 V/rad x 2 Mrad/slV) = 0.0156. As before ， ω2 = O.01K = 500 rad/s , and R2 = 1旦kÛ still. Now RI = R2/Kh = 10 kÛ/0.0156 =也o kÛ. Suppose Vao matches Vbo within 2%. Then Vao

Vbo = 0.02 x 2.5 V = 50 mV , and from Eq. (3-11a) , Vdo = (V，伽 - Vbo) + VIO + ftaR I = 50 mV + 5 mV + 12.8 mV = 67.8 mV. From Eq. (3-6) ，忱。 - Vdo/Kd =一0.042 radian~ ， or about - 2.4 deg. This is about a factor of four better than the previous design.

(c) If we use a passive loop filter , we must use the PD characteristic Vb with a positive slope Kd = 0.8 V/rad. Then , as for the filter in Fig. 3-15c, Kh = 0.0313. The components of the passive fi1ter in Fig. 3-15e have the relationship ω2 = 1IR2C , soR2 = 1且主f! as before. Bl,lt now Kh = R2/(Ro + R2 ) rather than Kh = R2/R l' Then Ro = R 1 -

R2 = 320kÛ 一lO kÛ =旦旦主Û. Since Vdo = 2.5 V，叭。= 1.0 V , and F(O) = 1, Eq. (2-27) gives Oeo = - Vdo/Kd + Vco/KdF(O) = 一 1.88 radian~ ， or - 107 deg. A1though this is a large static phase error, it is acceptable in some applications such as FSK demodulation. Then the simpler passive loop filter here might be preferable.

EXAMPLE 3-2

Repeat Example 3-1 replacing the requirement that Hp = 1.01 with the requirement that the step response have 10% overshoot.

From Fig. 3-1 1, a 10% overshoot requires ω2'/K 0.16 , or

ω2' 0.16 K = 8 krad/s

This is 16 times the value of 500 radls in Example 3-1. This can be realized by reducing C to C' = 0.2μFIl 6 =旦旦12豆...l:!E in each filter design. Since the bandwidth doesn't change, all other component values stay the same, and the values of Oco are the same. For example, the passive filter would be that shown in Fig. 3-15f.

r

Sec. 3-8 Phase Error Response 43

3-8 PHASE ERROR RESPONSE

We have developed the transfer function H(s) to find 00 in response to the input Oi' It wiI1 also be useful to find the phase error Oe at the PD in response to Oi. In particular, if 0 e is too large , it will exceed the linear region of the PD characteristic , and the PLL may lose lock.

By definition , the phase error is Oe 三 Oi - 00 , Therefore, the transfer function from Oi to 0 e is gi ven by

Oe(s) Oo(S) 一一一一三 1 - H(s)

。'ls) Oi(S) (3-26)

This transfer function is usually represented by He. With Eq. (3-13) , this can be expressed as

Oe(s) C(s) 三 He = 1 - H(s) = 1 一一一一一一一 = 一一一一一一 (3-27)

。'/s) --e 1 + C(s) 1 + C(s)

where C(s) is given in Eq. (3-23). It can be shown from Eq. (3-27) that I叫 follows the lower of unity and 11Icl. Figure 3-16 shows frequency responses of 11/cl and IHeI. (Note that the 11IcI curve is simply the Icl curve in Fig. 3-12 flipped about the unity-gain line.)

ω2 ω3

w

|Hel Et

FIGURE 3一 16 Phase eηor response

44

0.287

(rad)

10

7r:

2.87

一 1.88

-7r:

4.75

ω2

0.5 k

IHel


凶m K 15 k 50 kω(r/5)

IHI

(a)

(b)

FIGURE 3一 17 Phase error in Example 3-3

It is apparent that I叫 is a high-pass r的ponse with cutoff atω = K. This amounts to the fact that at low frequencies 80 tracks 8i well , and there is little phase error.

Ifω3 > 4K, the pole atω3 can usually be ignored in the analysis. Then the expression G(s) K(s + ω2)/S2 in Eq. (3-12) can be used , and

He伊1 + G(s)

2 S

S2 + Ks + K，ω2 (3-28)

r

References 45

EXAMPLE 3-3

A PLL has K = 50 krad/s and ω2 = 500 rad/s , and the modulated input phase isθi = 10 sm ωmt， where ωm 15 krad/s. The PD characteristic is that shown in Fig. 3一15a. Find 8n and compare the performance of the PLL when 8eo = 0 with the performance when 8eo -1.88 radians.

The response IHel is sketched in Fig. 3-17a for the given values of K and ω2. Evaluating Eq. (3-28) at the frequency of the phase modulation yields He(}ωm) =

0.287丘J deg. Then the amplitude of 8e is 0.287 x 10 radians = 2.87 radians. For 8eo = 0 , the waveform is centered on the t axis , as shown in Fig. 3-17b. The peak values of 8e

are less than 甘， so the operation stays in the linear range of the PD (see Fig. 3-15a). If 8eo

-1.88 radians , the waveform is shifted down so the negative peak of 8e is -2.87 - 1.88 -4.75 radians (see Fig. 3-17b). Since this exceeds -71", the linear analysis doesn't hold , and the PLL loses lock.

REFERENCES

[1] E. 1. Kennedy , Operational Amplifier Circuits , HRW: New York , 1988 , Chapters 1 and 2.

r 恥

CHAPTER

4

PHASE DETEcToRs

The linear model we have established for a phase detector (PD) is

Vd Kße + Vdo (4-1)

where Kd is the PD gain , Oe is the phase error of the VCO output relative tö the input signal , and Vdo is the offset voltage or “ free-running voltage. " This linear model breaks down for large enough Oe. The values of Oe for which the linear model is valid are called the range of the PD.

A variety of devices , both analog and digital , can be used as PDs. We will compare them on the basis of range , offset, and gain. All of them can be thought of as multipliers in some sense.

4-1 FOUR-QUADRANT MULTIPLlERS

A multiplier acts as a PD through the trigonometric identity

sin(A)cos(B) == 0.5 sin(A - B) + 0.5 sin(A + B) (4-2)

48

Let the inputs to the multiplier be

V; V;sin(ω;t)

Vo Vocos(ω;t - 8e)

The output of the multiplier is

Vd Kmv;vo

Phase Detectors Chap. 4

(4-3a)

(4-3b)

(4-4)

where K~ is a constant associated with 仕le multiplier. This is represented by the signal flowgraphinFig.4la.Tth1eu叮unitsdimension of volts. Then by Eqs. (4-2) , (4-3) , and (4-4) ,

Vd O.5KmVYosin(8e) + O.5KmVYosin(2ω;t - 8e) (4-5)

Figure 4-1 plots vd for 8e increasing linearly with time. The two terms in Eq. (4-5) are evident as two sinusoidal components-For a constant Opthe output of a PD should be constant according to Eq.(4-1).But the second term of Eq.(4-5)varies with a frequency 2ω;. In most PLL applications , this frequency is high enough that the second term has no effect, or the second term is removed by a filter. In any 問拭 the first term isωlsidered to be the output V d of the PD:

Vd O.5KmV;Vosin(8e) (4-6)

Thus , the symbol Vd we have been using for the output of a PD is actually the average of the complete output V d' This average is taken over a long enough period to eliminate the 2ω; component, but not so long as to affect the relationship in Eq. (4明6) when 8e is a function of time. The accepted convention is to speak of V d as the PD output voltage , but the designer should not completely lose sight of the second term in Eq. (4-5). Its frequency ωa-the detector frequency-is twice the input frequency ωi﹒

The notation in Eq. (4-6) can be simplified as

Vd Vdmsin(8e) (4-7)

where the maximum value of V d is

Vdm O.5KmVYo (4-8)

This sinusoidal characteristic is shown in Fig. 4-1c. For small values of 鈍， sin(8e) = 見，組d

Vd = O.5KmV;Vo8e (4-9)

Comparing Eqs. (4-1) and (4-9) , we see that the PD gain for small values of 8e is

Sec. 4-1 Four-Quadrant Multipliers

的一~. /"\

( x ←一叫你←---- Vd v。 ----f' 、、-'

(a)

A/\. /\. /\. /\. /'\ / ~ |\J\/\/\/\J\./

zu\ A í\ AA í\í\ l\泛 \/\/\/\/\/\Jrt

kAZ長~系主、 A1"-- - +~ V.V 、

3:1:卡孟云三于(b)

Vd

Vdm

11" 11"/2 。e

Kd= Vdm =O.5 KmV;昕一

(c)

FIGURE 4-1 Four-quadrant multip1ier phase detector with sinusoidal inputs

49

Kd O.5KmV;Vo (4-10)

Note that the PD gain depends on the amplitude of the input signals; it is not a property of the circuit alone.

The waveforms of a four-quadrant multiplier are illustrated in Fig. 4-1b. The adjective fourψwdrant refers to the ability of the multiplier to handle both positive and negative values at both of its inputs.

50 Phase Detectors Chap. 4

4-2 GILBERT MULTIPLIER

One common implementation of a four-quadrant multiplier is the Gilbert multiplier circuit

[1] shown in Fi已 4-2a. Here , Vo splits the 叫according to the characteristic shown in Fig.42b.The current il is split in turn by vt acco咖;to the characteristic shown in Fig 4IC Amilarctmc紀ristic holds for i2

The four re叫ti時 currents are combined to produce

Vd = (i4 + i6)R 1 一 (i3 + is)R2

= (i4 + i6 - i3 - is)R

where nominally RI R2 R. (In practice, of course , RI and R2 are not exactly thesame.)If vz and vo are kept in the linear region of thecharactcrlsucs in Figs.4-2b and 4-2c (amplitude less than 52 mV) , it can be shown that

Vd Kmv

where

Km = Rl!(52 mV)2 (4-11 )

A mismatch in the transistors can cause input offsets VIO of a few millivolts that add to Vi

and Vo- Similarly , a mismatch between RI and R2 causes an offset

Voo (R 1 - R2)I!2 (4-12)

to be added to the output. These relationships are summarized in the signal flow graph in Fig. 4-2d. The total expression for the output is

Vd = Km(Vi + VIO) (Vo 十几0) + Voo

Kmv凡 + Km(VIOVi + VIOVo + VYo) + Voo

Taking the time average [as when we went from Eq. (4-4) to Eq. (4-7)],

Vd Vdmsin(8e) + KmV70 + Voo

The dc terms can be combined as an effective offset voltage at the PD output:

Vdo KmV70 + Voo (4-13)

?

一 52mV

的

Vo

52mV Vo

Vcc

+ 的

VEE

(a)

RI '‘一一川 (52 mV)2

52mV

(~ (cl

的。

V口。= (R, -R2)112

Vdo = Voo+Km的。2

(d)

FIGURE 4-2 Four-quadrant multiplier circuit

52mV 的

Vd


EXAMPLE 4-1

The Gilbert multiplier circuit in Fig. 4-2a has 1 = 2 mA and R = 5 kO. R 1 and R2 differ by 2% , and VIO 5 mV. Find Vdo and the maximum Kd .

From Eq. (4-11) and Eq. (4-10) , Km = (1 0 V)/(52 mV? = 1/(0.27 mV) and Kd =

ViV)(0.54 mV). Unfortunately , Kd is not a property s01ely of the circuit but depends on the input 1evels. The maximum Kd corresponds to Vi = V 0 = 52 m V, the largest signals for which Eq. (4-8) holds. Then Kd = (52 mV)2/(0.54 mV) 主主主l且已

From Eq. (4-12), Voo (0.02R)I12 (100 0)2 mA!2 100 mV. AIso , KmVTo (5 mV)2/(0.27 mV) 93 mV. Then by Eq. (4-13) , the total offset is Vdo 93 mV + 100 mV 盟主旦V.

4-3 PHASE DETECTOR FIGURE OF MERIT

Is the Vdo 193 mV in Example 4-1 a large offset? It depends on how much useful voltage Vd the PD is capable of producing per radian , which is its gain Kd. Therefore , the ratio KdlVdo is a meaningful indication of how small the offset is. We will call this the figure of merit M of the PD:

M三 KdlVdo (4-14)

From Eq. (3-7) , M = 1I0eo with an active loop filter , where Oeo is the static phase offset. In Example 4-1 , M = (5 V/rad)/(1 93 mV) = 26. A PD should reasonably be expected to have M 三 15 ， and M as high as 500 is possible with careful matching.

4-4 DOUBLE-BALANCED MULTIPLlER

Another form of four-quadrant multiplier is shown in Fig. 4-3a. This circuit is called a diode ring mixer or sometimes a double-balanced mixer (a mixer is a multiplier). Unlike the multiplier in Fig. 4-2a, this circuit consists entirely of passive components. This allows it to operate at frequencies as high as 26 GHz , such as the DMS1-26A manufactured by Anzac. [2]

The circuit operates with any shape of waveforms , but its operation is most easily analyzed if one of the waveforms is a square wave, as the Vo in Fig. 4-3c. Then Vo may be considered a switching voltage , tuming on either the bottom two diodes or the top two diodes depending on the polarity of V 0 . When Vo is positive, the bottom two conduct, and Vx equals the voltage at the midpoint ofthe secondary winding oftransformer T2 , which is ground. Then vy 利， and Vd = 0.5vy = 0.5Vi. Similar旬， when Vo is negative , vy is

f

Sec. 4-4 Double-Balanced Multiplier

白玉山几Vd

Vdm 的

π 。e

Kd= Vdm = I再/πVd

(a) (b)

扒/\^ /\. /'\. /".. J 〉 1〉〉〉八〉可〉三

1.6門 R r=l r=l CJ CJ_ J]]]]] L Ft

v y

的

ot勻ft v̂t\f-\咐:AA 叭叭叭 L\J ~\J 、J-、E~「『4-et

(c)

FIGURE 4-3 Diode ring phase detector

曰:叫侃起i單純昨日iciiEtVdm Kd \名I7r (4-15)

This assumes that both transformers have pdmary tums equal to secondary turns.For the best fIgureof merit, the signal amplitude Rshould be kept high to keep Vdm high.For the

53


operàtion as described above , V; should not be so large as to cause a diode pair to conduct. This corresponds to V; 三1.2 V for the transformer ratio here.

with well-matched diodes in an integrated circuit, vdocan be kept to less than a millivolt , for a figure of merit M 三 400 (see for example th巳 Anzac MD-158). [3] The weak link then is usually the active loop filter with perhaps 5 mV contribution to Vdo '

However, high-performance op amps are available with VIO as low as 0.1 mV. For further discussion of double-balanced mixers , see the Anzac catalog [4] and

Clarke and Hess. [5]

4-5 TRIANGULAR PHASE DETECTOR CHARACTERISTIC

In applications where noise is not a consideration , it is an advantage to overdrive the multiplier. We will see that this maximizes Kd' eliminates its dependence on the amplitude of the PD inputs , maximizes M , and provides a triar p叭lec巴wis鉛e-linear.

The multiplier PD in Fig. 4-4a models the overdriven condition by a "slicer" at its output. This causes the output V d to 叫urate at ::!:: Vdm for all input signallevels. Since only the polarity of 伽 input signals matters now , we represent V; and Vo as sq的re waves 1月Fig.4一4b. As 8 p increases linea征rl句y with t位im巴丸， the average component v叫d mcreases ana d豆ecreases li翩d叮夕 The 削Ilt i臼s 伽 t肘ria嘲characteristic is linear for 一 0.5甘 <8札e < 05Tτr ， and the PD gain ís

Kd = Vdm/0.5τ (4-16)

The output 恥， shown in Fig. 4-4b, has an average component V d.It also has a highfrequency square wave component whose duty cycle depends on 8.. This square wave , which is not a desired part of the output, has a fundamcntalfrequency (thedetector

frequency ωd) that is 2ωγ The characteristics for the four-quadrant multiplier in Fig. 4-2b and Fig. 4-2c show

that the circuit is overdriven when V; and Vo exceed 52 mV. For V; > 52 mV and Vo > 52 m V , all of the currentI is directed through R 1 in Fig. 4-2a; there is no current through R2 .

Therefore V d RI, which is its maximum value:

Vdm RI (4-17)

From Eqs. (4-16) and (4-17) we have the PD gain Kd = 2RI/甘， which no longer depends on V; and V

n• It is also true that mismatches in the transistors do not contribute to VIO '

However, as we will see，的ymme昀 of the square waves effectively causes 則由 VIO '

Sec. 4-6 Exclusive-OR Phase Detector

的

Vd

Vo

(a)

h11 11 11 鬥〔尸I LJ

于「門〔鬥鬥鬥鬥 h

55

I LJ LJ LJ LJ LJ LJ L >>"t

dhn門鬥「內偉的鬥 D n I n ~

ij卡云空竺(b)

Vd

Vdm

(c)

11"/2

K,,= Vdm 一-

11"/2

FIGURE 4-4 Four-quadrant multiplier phase detector with over-driven inputs

4-6 EXCLUSIVE-OR PHASE DETECTOR

。e

... t

An exclusive-OR logic circuit is essentially the same as an overdriven multiplier circuit. When overdriven, the multiplier output is saturated at either a positive value, corresponding to a logic "high," or a negative voltage , corresponding to a logic “ low." For a multiplier, the output vd is positive when both inpllts V; and Vo are negative or both are

56 Phase Detectors Chap. 4 Sec. 4-6 Exclusive-OR Phase Detector 57

~ ~ ~ ~=J[至二:TABLE 4月 MULTIPLlER TRUTH TABLE

+ (a)

十

+ + 十 ÷ 口口口口

Lt positive, and Cd is negative when one input is positive and the other 1s negative-This is Summarized in Table 4I Compare this with 伽仙th table for an exclusive-ORlNOR circuit in Table 4-2.(The exclusive-OR/NOR symbol is shown in Fig.4-5aj The VH? Table 4-2 represents the logic “ high" voltage , and VL repres巳nts the logic “ low" voltage.It isAClear that m overdriven multiplier is essentially an exclusive-NOR with “+ " correspo耐時 to logic “high" and “一刊 coπesponding to logic “low." Then an exclusive-OR/NOR can beused as a PD, and the PD characterIStICIS triangular, aslt was

for the overdriven multiplier in Fig. 4-4. In order to obtain an output V d that is both positive a吋 negativ巴， it is usual to u臼 the

balanced output V d 九一丸， where V" is the exclusive-OR output and Vb is its complement. The characteristics for the average voltages Va ' 內， and Vd as functions of Oe are shown in Fig. 4-5c. The voltages corresponding to Oe 0 are

~鬥鬥鬥 h

h-n-~_I_-~一叩一仟市竹TVb卅付計可刊仟r+4l~n_ 1__1-

(b)

V"o VbO (VH + Vd/2 (4-18)

(4-19)

Vd and the maximum V d is given by

Vdm VH - VL

Vdm

Altematively , the Va

characteristic can be used together with a Vr = VaO ' 的 in Fig. 3-5b.

Then Vdm = (VH - VL )/2. Again , the advantages of using 伽 digital exclusive-OR as a PD are greater Kd' less

V恥 a沾 greater linear phase range. However, the nonlinearity of the digital cα肌肌r此cuaggravat盼es the effect of noise , as we will see in Chapter 6.

So far we have assumed the square waves at the input are symmetrical-that 詣，出eyhave a 50% duty cycle. Suppose that Vi has a duty cycle of Oi = 0.5 組d V() has a duty

一 0.5π 0.5π 。e

0.5宵。e

Vd=Vb- V•

們b , h • A

Vbo V \

、-.../ VL I F

-0.5 11" 0.5π Oe

Vdm=VH-VL

(c)

FIOURE 4-5 Exclusive-OR/NOR as a phase detector

TABLE 4-2 EXCLUSIVE OR/NOR TRUTH TABLE

V, Vo V G Vb cycle of 00 = 0 .4, as in Fig. 4-6b. The effect of O.。手 0.5 is to produce a nonzero freerunning voltage and to reduce Vdm of the PD characteristic.

The free-running voltage Vdo is defined as the PD (average) output voltage when there is no input at Vi. For a logic signal , this means that Vi is always “ low," or Vi VL .

Then Vd = VH - VL when Vo = VL , and Vd = VL - VH when Vo = VH • Therefore , the average of V d is

LHH V川

VVV

LHLH VVVV

HH

VVVV 九九九九

58

的=jC主二 γ=0.5Vo ----1/ ~ - 00 =0.4

(a)

的 L-:e=0.31r

VH 1 ï

的Llle=O.41rr-

VL l BB " h! t t

「M j 帥，「，Vd t Vd

/

VH-\在

吭一 VH

(b)

Vd

For Oj=0.5 Vdm

0.5π

一 Vdm

(c)

Phase Detectors Chap. 4

的Llle=0.51r .-

BB

阿甘t

Vd /

Vdm =(1 一 11-2 ooP (VH- Vd Vdo =(1-2 δo) (VH- Vd Kd= (VH- Vd/0.5宵

。e

FIGURE 4-6 Exclusive-OR phase detector with õ。手。.5

Vdo = (l - 00 ) (VH - VL ) + o()(VL - VH )

= (1 - 20()) (VH - VL )

Note that Vdo is not zero for δ。手 0.5.

(4-20)

The other effect of 丸子正 0.5 is to reduce Vdm . Because Vi and Vo no Ionger have the same waveform , there is no phase for which they exactly match each other and produce Vd = VH - VL • The best match is when Vo = VH occurs only during the time Vi = VH .

γ

Sec.4一7 Two-State Phase Detector 59

Figure 4-6b shows three phases for which this is true. In all cases , the average of Vd is the same: Vd = 0.8(VH - Vd. This is aIso the maximum of 旬， so Vdm = 0.8(VH - VL ) for 00 0 .4. In generaI ,

Vdm = (l - 11 - 200 1) (VH - VL ) (4-21)

For 00 子正 0.5 , this is Iess than the Vdm given by Eq. (4-19). The PD characteristic in Fig.

4-6 shows that the peak of the function has been truncated; for 00 = 0 .4, the function is fIat for O. 31T三 Oe 三 0.5τr. The PD gain , however, is not a function of 00 :

Kd = (VH - VL)/0.5τ (4-22)

This agrees with Eqs. (4-16) and (4-19) for the case 00 0.5.

4-7 1WO-STATE PHASE DETECTOR

A circuit with two states such as a set-reset fIip-fIop can be used to realize a PD with a characteristic that is Iinear over a range of ::t甘， as shown in Fig. 4-7d. The two states are represented in Fig. 4-7a, where R and Vare the two inputs , and the arrow • indicates a rising edge on the input. A rising edge on R causes the circuit to go to State 2 (v d positive) , and a rising edge on V causes the circuit to go to State 1 (Vd negative). The timing diagram in Fig. 4一7c shows how the average component V d varies as 0 e increases Iinearly. It rises continuously over the whole 21T range , resulting in the “ sawtooth" PD characteristic in Fig. 4-7d. The gain is

Kd = Vdmhr (V H - VL )/1T (4-23)

The circuit in Fig. 4-7b realizes an edge-triggered set-reset fIip-fIop. Input Vi is connected to R , and Vo is connected to V. A rising edge on Vi causes Q, Q2 , so Vd is "high" (the “ set" state). A rising edge on V 0 causes Q2 Q" so V d is “ low" (the “ reset" state).

One advantage of the two-state PD is the increase in the Iinear range--double that of an exclusive-OR PD. Another is that the duty cycles of Vi and Vo are not important-于-ûnlytheir rising edges.

One disadvantage of the circuit is that it is more sensitive to noise than the exclusive-OR PD. In effect, the fIip-fIops remember an error due to noise , while the exclusive-OR is memoryless. Another disadvantage is that the high-frequency ωd of Vd (see Fig. 4-7c) is only ωi for the two-state PD , rather than the 2ωi for the exclusive-OR PD. In Chapter 9 it is shown that a lower ωi can cause more spurious phase modulation because it is closer to the cutoff frequency K of the PLL.

Our standard definition of free-running vo1tage Vdo is the V d when there is no signal at Vi. But for the two-state PD this would result in Vd = Vdm , which is far from the desired

State 1 State 2

(a)

的

Vo

(b)

Vo -.............,'"',. .................，.....叫“_. ~叮叮 width

的 l(Rl

Vd

V dm I r--"1 I---l ，---，，..........，已『鬥鬥，......， ,....-,\, r---1仁可尸，可』

-Vdm fJ L-J W U U ~ L.....J L-J> U U L;t

(c)

Vd

Vdm = VH - VL

7r 。e

(d)

FIGURE 4-7 Two-state phase detector

Sec. 4-8 Three-State Phase Detector 61

value of zero. A more useful definition of Vdo when studying acquisition is Vd averaged over all Oe. From Fig. 4一7c ， this is given by

Vdo (Vdm - Vdm)l2

where Vdm VHb - VLa is the maximum , and - Vdm VLb - VHa is the minimum. Then

Vdo (VHb - VHa + VLb - VLa)l2 (4-24)

where the second subscript a or b refers to the logic voltage at 九 or 丸， respectively. Ideally , Vdo 0 when all logic levels are matched.

4 -8 THREE-STATE PHASE DETECTOR

The concept of an n-state PD may be extended to as many states as desired. The threestate PD is widely used because it is simple , has a linear range of :t 2τradians ， and can act as both phase detector and frequency detector.

A state diagram for the circuit is shown in Fig. 4-8a. Again , states are changed on rising edges of R and V一-R moving to higher states, and V moving to lower states. Suppose the circuit is initially in State 1. Then altemate rising edges on R and V will cycle between states 1 and 2. If V is constantly falling behind R in phase, as in the timing diagram in Fig. 4-8c , then eventually there will be two R rising edges without an intervening V rising edge. This will take the circuit to State 3, and thereafter it will cycle between State 2 and State 3.

The corresponding PD characteristic in Fig. 4-8d grows linearly over a range of 4τr radians. Thereafter it remains positive , repeating a cycle every 2τradians. If Oe decreases, the characteristic decreases linearly over a range of 41T radians. Thereafter it remains negative , repeating a cycle every 21T radians.

The action of a three-state PD as a frequency detector is now clear. For ωi>ω。， Oe

increases with time , and Vd remains positive. For ωi<ω。， Oe decreases with time , and Vd

remains negative. This is a great aid in acquiring lock when the two frequencies are initially different. The details of acquisition with a three-state PD are analyzed in Chapter 8.

The frequency detector action requires that the PD characteristic be multiple-valued (see Fig. 4-8d). This makes it unsuitable in applications where a pulse on Vi may be missed, causing Vd to jump in value by Vdm . Therefore , a three-state PD can't be used in high-noise situations or for clock recovery from data. The consequences of a multiplevalued characteristic are examined further in section 4-13.

For Oe = 0 , the rising edges of R and Vare coincident, and the PD remains in State 2 almost all the time; there are brief excursions to State 1 or State 3 as V or R comes slightlyearlier. Figure 4-8a shows that in State 2 the output is Vd == Vu - VD = VL - VL

0, as desired for Oe O. But in practice, the two VLs are not identical , and there is some offset:

Vdo VLb - v:μ (4-25)

的

Vo

volE 日

i State: 2 2 2 2 3 2 3 2

FIGURE 4-8

(a)

Vu +

Vd

Vo

日口口鬥nr可

LJ 且IÃ一門一門-FT于1

3 2 3 (c)

Vd

(d)

2 3 2 3 2 3 2

Vdm=VH - VL

Three-state phase detector

3

L

-t

正

L 且』一

2 3 2 3

。e

γ

Sec. 4-8 Three-State Phase Detector 63

The maximum Vd corresponds to the PD at State 3 almost all the time. There, Vd = V dm = V H - VL . Then from Fig. 4-8c the PD gain is

Kd = (VH - VL)/2τ (4-26)

One realization of the three-state PD is that devised by Shahriary et al. [6] shown in Fig. 4-8b. Suppose VD and Vu are low (state 2) initially. A rising edge on Vi causes Vu to go high (state 3). Then when a rising edge of Vo occurs, both VD and Vu are high for an instant. Within a couple propagation delays , the AND gate has reset both flip-flops , and both VD and Vu are low (State 2 again). This is shown more clearly in the expanded view of the waveforms in Fig. 4-9a. Note that there is a short transient state where both VD 組d Vu

are high. However，心= 0 for both State 2 and the transient state, so they can effectively be lumped together as State 2.

The maximum useful frequency for this PD is limited by the minimum duration of State 2. The duration τT of State 2 is given by 1T TH + TVL , where TH is the duration while Vu = Vd = V H , and TL is the duration while Vu = VD = V L (see Fig. 4-9a). Then the minimum duration of State 2 is

Tmin TH + TLmin

where TH is the propagation delay of the AND gate plus that of the flip-flop from R to Q, and TLmin is the propagation delay of the AND gate plus the recovery time of the flip-flop from a reset. Therefore , the greatest duty cycle of time spent in State 3 is

δ= max 1 - Tmin/T 1 - Tminω/2τ

where T = 2τr/ωi is the period of the input frequency. Then the maximum Vd is V dm = 8max (VH - VL ) , and the maximum phase ()em within the linear range is given by

()em 2τ8max 2τTmin( (4-27)

(See Fig. 4-9b) Note that the PD gain remains Kd = Vdm/()em = (VH - VL)/2τas in Eq. (4-26).

EXAMPLE 4-2

A three-state PD realized as in Fig. 4-8b has an input frequency ωi = 2τx 20MHz , an AND gate propagation delay of 2 ns , a flip-flop propagation delay (R to Q) of 3 ns , and a flip-flop recove可 time after reset of 4 ns (this last specification is often not supplied by the manufacturer). Find the usable phase range of the PD.

Adding the propagation delays gives TH = 2 + 3 = 5ns and TLmin = 2 + 4 = 6 ns. Then Tmin TH + TLmin 11 郎， and ()em 2甘一(1 1 ns) (1 25.6 Mrad/s) = 4.9 radians. This is 78% of the ideal 21T radians phase range.


.o tJJ .u ~l r

市斗

鬥UIH

T=2 1C/Wi

L T

口 ... t

~

t

4門川U

Vd=VU-VD

L--7→「(a)

Vd

。e

(b)

FIGURE 4-9 Three-state phase detector characteristic at high frequeucies

Another realization of the three-state PD is manufactured commercially by Motorola [7] in both TTL (the MC4044) and ECL (the MCI2040). However, Egan and Clark [8] have shown that these do not make a smooth transition from negative V d to positive 旬，causing a nonlinearity in the PD characteristic at the origin. Therefore, the realization in Fig. 4-8b is prefeηed.

f

Sec. 4-9 Z-State Phase Detector 65

4-9 Z-STATE PHASE DETECTOR

A variation of the three-state PD is to have the VD and Vu outputs drive two CMOS switches, as in Fig. 4- lOa. This circuit is intended to be used with a passive filter, as shown. The result is equivalent to an active filter with very low offset. There is no established name for such a PD; we suggest Z-state PD , with "Z" referring to the highimpedance state. A commercial version of such a PD is the 74HC4046 manufactured by Harris Semiconductor. [9]

In State 1, VD is high , and the lower switch connects 11" to ground. In State 2, neither VD nor Vu is high, and neither switch is c1osed. Since no current flows through Ro, 11" equals the V3 across the capacitor. In State 3, Vu is high , and the upper switch connects 11" to VDD . The resulting 11" waveform as Oe increases is shown in Fig. 4-10b. Note that 11" is not determined solely by the PD circuit; at times it equals the voltage V3 in the loop filter.

The result is the PD characteristic shown in Fig. 4-1 Oc. The slope K" depends on 呵，and in general the K" for Oe > 0 is different from that for Oe < O. But the important feature is that with both switches open , the free-running voltage Vdo equals V3. But in the steady state, V3 = Vc == \仁。. Therefore

Vd.υ= 咒。

For a passive filter F(O) 1, and the static phase error given by Eq. (2-27) is

鈍。 - V",)Kd + VcoIKdF(O)

= (V，ω - V"o)IK" 0

Thus , there is no static phase error, which is usually not true of a passive filter. In practice , though , the bias current I B to the VCO is not zero. The resulting voltage drop IBRo across Ro leads to a small static phase offset

Oeo IBRolKd (4-28)

I B can be kept to picoamperes with FET buffering at the VCO input. The result is a PD with an effective figure of merit M in the thousands!

Such a tremendous M is sometimes worth the nonlinearity that occurs in the PD characteristic at the origin. Another limitation, though , is that it takes time for 11" to settle to V3 when both switches are open-a result of some 25 pF of stray capacitance at the 11" node that must discharge through Ro. This restricts the circuit to rather low-frequency applications when variation in Oe is expected.

fit

67 Sample-an小Hold Phase Detector Sec. 4-10

4-10 SAMPLE-AND-HOLD PHASE DETECTOR

The sample-and-hold circuit shown in Fig. 4-lla can act as a phase comparator. Pulses on v 0 cause a switch to close momentarily , charging the capacitor to the current values of Vi. The following buffer keeps the charge from leaking off the capacitor while the switch is open. As Oe increases , successive values of Vi are sampled, and V d has the form of Vi but at a lower frequency. (This is the effect of aliasing.) Therefore , the form of the PD characteristic is sinusoidal if Vi is sinusoidal , and the characteristic is triangular if Vi is triangular.

的一一-o-lc

均一一一一」

Vd=Vd

2扒 r\ /\ /\ /\. /\ I\/\/\/\/\J\./-

3 (a)

L ~

t

H R 3-state Vu t一-bud| 叫一

D • n n n

h仟鬥

且+門 nnll

(a)

口口B

的

Vo

.. t

c • t

8e

(b)

FIGURE 4-11

(c)

Sample-and-hold phase detector

Vd

。e2π

Z-state phase detector

(b)

(c)

Vd

-2π

FIGURE 4-10


The one advantage of a sample-and-hold PD is that V d contains no high frequency at ωi or 2ωi' If the phase is constant , then Vd is a straight dc line. This is desirable in applications such as frequency synthesis , where any spurious modulation by Vd degrades the spectral purity of the synthesized frequency.

4-'甘 EXTENDED RANGE: FREQUENCY DMSION

In PM demodulation applications and phase jitter smoothing applications , it is sometimes necessary for the PD to handle large values of (}e. The largest range we have seen so far is that of the three-state PD with :::'::: 21T radians. With more complex designs , there is no limit as to how wide the range can be made, but there are some tradeoffs.

The circuit in Fig. 4-12a uses the same two-state PD we analyzed in Fig. 4-7. But now there is a frequency divider in front of each input , so the frequencies at 叫 and V:) are 1/3 those at Vi and Vo. The phase at Vo must slip three cycles relative to Vi in order for the phase at v~ to slip one (long) cycle. This extends the range of the two-state PD from :::':::τ

to :::':::3τT radians (see Fig. 4-12c). The high-frequency ωd that appears at vd (see Fig. 4一12b) is now ω/3 rather than the

ωi for the two-state PD by itself. This makes it more difficult to keep ωd out of the passband of the PLL. In general

ωd ω/N (4-29)

for an extended range PD with -7- N frequency dividers.

4-12 EXTENDED RANGE: n-STATE PHASE DETECTOR

Another method of extending the range of a PD is to increase the number of states in an n-state PD beyond the three-state we have already seen. Oberst [10] refers to this as a “ genera1ized phase comparator." The method for realizing four or more states involves combining a three-state PD with a shift register. [1 1]

Consider the six-state PD represented in Fig. 4-13a. The number of each state here refers to the number of output variables 廿五， Vu , v\> V2 , and V3) in Fig. 4一13b that are high. For simplicity of notation, let 1 stand for logic high and 0 stand for logic low. Then the condition V [iVUVjV2V3 = 10000 and the condition V [iVUVjV2V3 = 00100 are both State 1. Rising edges on R move the circuit to a higher state , and rising edges on V move the circuit to a lower state.

The connection of the PD to the passive loop filter is shown in Fig. 4-13b. the analysis can be simplified by replacing the PD and the five resistors of value 5Ro with the Thevenin equivalent in Fig. 4-13c. The Thevenin voltage is

Vd = k VH /5 + (5 - k)vd5 (4-30)

F

Sec. 4-12 Extended Range: n-State Phase Detector

時 b

VíLJ

的

Vo

Frequency dividers

(a)

R

V

2-state PD

i- I I I I I I I I I |I I L

L F

t

dh仁+-Ll鬥 /vdn F斗向-t

u U 1---j1三::::H-- U L

Vd

(c)

FIGURE 4-12 Extended range: frequency division

69

where k is the state (0 through 5) of the circuit, and V H and VL are the high and low logic voltages. The Thevenin resistance is Ro , which completes the loop filter. Fig. 4一13dshows Vd as {}e increases with time for the case VH 5 V and VL = O. The PD first alternates between states k = 0 and 1, then between 1 and 2, etc. The average value Vd

correspondingly increases from 0 to 5 V as k goes from 0 to 5. The resulting PD characteristic , shown in Fig. 4一 13己; has a linear range of :::'::: 5甘

radians. Note that as {}e increases beyond 5τT radians , Vd stays between 4 and 5 V , and as {}e decreases beyond - 51T radians , Vd stays between 0 and 1 V. This is similar behavior to the three-state PD , and it allows all n-state PDs for n 三 3 to act as frequency detectors.

71 Extended Range: n-State Phase Detector Sec. 4-12 Chap.4 Phase Detectors 70

C R2

5R1

V3

V2

Vl 6-state

PD

R Vo

R

R

V V

R

V

R

V (a)

R

V

R

V

Vc

Vu V 5Ro

Vi ν3 Vr= (VH+\在)/2

Vr

(a)

Vi5

Vd

Vc

For state k vd=kVH/5+ (5-kH'L/5

Vd

時

5Ro

5Ro

V2

Vu

Võ

的6-state

PD

R

V

叫

Vo

。e9π 7π

(b)

Vdm= (VH一此)/2

(4-32)

[compare Eq. (4-30)]. The sign inversion introduced by the active loop filter has been compensated by reversing Vi and Vo at the inputs R and V to the PD. Otherwise the negative feedback would have become positive, and the PLL would be unstable.

The PD characteristic is shown in Fig. 4-14b. The maximumvalue is given by

Six-state phase detector with active loop fiIter

- Vd = k VH/5 + (5 - k)vd5 - Vr

FIGURE 4-14

The PD output is effectively

(c) (b)

VH=5，院 =0

句句54321

(d)

971" 。e971" 771" 571" 371" 一71" π

(e)

371" 一5宵-771"

(4-33)

(4-34)

Vdm = (V H - VL)12

The maximum value of the phase range is 8em 5τr. In general ,

where n is the number of states. The PD gain is ,(VH - VL )1101T. In general ,

1)τ 8em (n 一

Extended range: n-state phase detector

The use of a six-state PD with an active loop filter is shown in Fig. 4-14a. Here , the five summing resistors with value 5R I act in parallel as R I of the loop filter. The op amp is referenced to a Vr halfway between the maximum Thevenin voltage of V H and the minimum Thevenin voltage of VL :

Vr = (VH - VL )12 (4-31)

FIGURE 4一13

72

Kd Vdm

(Jem

VH - VL

(n - 1)2τ

Phase Detectors Chap.4

(4-35)

The offset voltage Vdo really has meaning only for n odd. Then it is defined as the value of Vd for the middle state，的 it was for the three-state PD. For n even , the PD spends equal time at each of the two middle states when there is no phase modulation. For n odd, the PD spends almost all its time at the one middle state, greatly reducing the ac component of Vd.

The unwanted high-frequency component of Vd for the n-state PD (see Fig. 4-13d) has a frequency (the detector frequency) of

ωd ωt (4-36)

as is true for the two-state and three-state PDs. This is a great improvement over the frequency divider method in Fig. 4-12 , for which ωd is inversely proportional to the range [see Eq. (4-29)]. The tradeoff is that the n-state PD has more complex circuitry.

A circuit realizing a six-state PD is shown in Fig. 4-15a. It incIudes a three-state PD with output Vu and output complement V[). Two “ slip detβctors" monitor the three-state PD for rising edges of R and risingedges of V that don't cause a state change. These events correspond to the end loops in Fig. 4-8a; the three-state PD slips 21T radians here. The slip detectors note these events and record them in the up-down (or left-right) shift register. When a risirig edge on R causes a slip, a slip detector causes the shift register to shift up , shifting a logic "1" into the bottom stage. When a rising edge on V causes a slip , the other slip detector causes the shift register to shift down , shifting a logic “。" into the top stage. Thus , a slip either adds or subtracts a "1" from the contents of the shift register, which appear at 叭， V2 , and V3. The “ 1" makes up for the 21T radians either lost or gained by the slip.

A state diagram of the six-state PD is shown in Fig. 4-15b. There are actually twelve states , but we lump together states that have the same number of ‘ 'l's" at v[), Vu , Vb 巧， and V3. For example , State 2 comprises states 11000, 10100, and 00110. Movement between rows corresponds to a state change of the three且state PD , and movement along the top or bottom row corresponds to a slip changing the state of the shift register. EventuaIIy the six-state PD itself wiII have a slip-一the end loops at State 0 and State 5. These slips can be put off further by adding stages to the shift register; a fourstage shift register would raise the circuit to a seven-state PD with a linear range of ::t 61T

radians. The realization of the slip detectors in Fig. 4-15a needs to be addressed. When a

rising edge onR causes no state change ofthe three-state PD , this is defined as a slip. The state diagram of the three-state PD , shown in Fig. 4-8a, is redrawn in Fig. 4-16a. The transient State 2' is shown explicitly here; it lasts for only a couple propagation delays and reverts spontaneously to State 2. Note that when R changes the state from 1 to 2 (via 2') or when it changes the state from 2 to 3, it causes a rising edge on Vu (from VL to V H). When R occurs during State 3, it causes no state change (a slip) and no rising edge on Vu.

Therefì

F

V

Sec. 4-12 Extended Range: n-State Phase Detector

/

State 0

--、-巴

的

Vo

νo Vu V, V2 V3

R

V

State 1 -、--、

3-State PD

Vu

Vo

State 2 月-"、-、

(a)

State 3

-、

。

均

V2 Q2

V,

Vu

State 4 --、-、

Vi5

FIGURE 4-15 Realization of six-state phase detector

State 5 ---、-、

73

R

A circuit realizing the slip detector is shown in Fig. 4-16b. The first flip-flop records a rising edge on Vu as Z high. The rising edge on R (that caused the rising edge on Vu) samples Z after a delay of 'T. (The delay can be either the propagation delay of a few gates , a delay line , or a monostable multivibrator.) It finds Z high , rp.aking Vo low , and immediately resets Z (see Fig. 4-16c). If X' , the delayed R , samples Z and finds it low , Vo goes high , indicating no rising edge on Vu since the last time Z was reset. This is a slip , and it causes a pulse 叩門﹒

The delay 'T must be long enough to allow a state change to propagate through the three-state PD and through the first flip-flop. (It must not be longer than the interval between rising edges on R.) This necessary delay causes a delay of 'T between the occurrence of a slip and its detection at VS • The effect is a 'T-wide transient in Vd. In wide-

V

R

Vu

R

Vu

X'

z

地

State 1 V

State 2 State 3

(a)

(b)

Slip: no corresponding ! on Vu

+

~ I (c)

FIGURE 4-16 Slip detector circuit

?

R

Sec. 4-13 Modified Phase Detector Characteristic 75

band applications where it is not negligible , the transient can be eliminated by inserting delays of 'T in the Vu and VD lines in Fig. 4-15a.

4-13 MODIFIED PHASE DETECTOR CHARACTERISTIC

In Chapter 6 we study the PLL response to noise , in Chapter 8 the transient response during acquisition , and in Chapter 9 the response to modulation. In some situations, two or more of these conditions are present simultaneously. With a linear system this would be easily handled by superposition. But because of the nonlinearity of the PD , superposition is generally not valid for a PLL. In this section we analyze how the PD characteristic vAOe) behaves when there are two independent components to Oe- Let the total phase error be

Oe = 0; + 0; (4-37)

where 0; is the component of interest and 0; “ the “ interfering" component. For instance , 0; could be the phase error due to Oi' and 0; the phase error due to noise. We will see that the presence of 0; effectively presents a modified PD characteristic v~(f);) to the other component 0;.

We will assume that 0; has zero mean and that it has an even probability density function p(O;). Then 0; can be thought of as the average of Oe over the variable 0;. If the PD output Vd(Oe) is averaged over 0; , then this average v~ as a function of 0; is the modified PD characteristic:

v~(O;) = f:oo

p(O~) Vd(O~ + 吩咐九 (4-38)

If V d(Oe) were linear, the presence of 0; and 0; together wouldn't affect the characteristic , and we would have v~( 0;) = v ct( 0;), an unchanged PD characteristic. But for large enough 呵， the nonlinearity causes v ~(O" e) 共 Vd( 0;).

Because we have assumed that p(O;) = p( - 0;) , Eq. (4-38) can be seen to be the correlation of p and Vd:

v~(Oe) = p(Oe) * Vd(Oe)

and therefore

V~(ω) = P(ω) X Vd(ω) (4-39)

where V~ ， P , and Vd are the Fourier transforms of v~ ， p , and Vd' Use of the Fourier transform usually simplifies the ca1culation of v~( 0,).

Figure 4-17a shows an example of obtaining the modified PD characteristic v~( 0;) from a sinusoidal PD characteristic

76

v,ÆO.)

Vdm

。e

。.=0;+0;'

。rms 0;'

vd(O;) Vd=P勢Vd

0;

同1)

0.5

Phase Detectors

一j7r Vdm j7rVdm

月ω}

一 1

Vd=Px Vd

一j7r Vdm /宵Vdm

1

Vdm =月 1 )Vdm

(a)

P(叩 =_1一-exp[ 一 (0;'1Orms)2 121 ~()rms ...."....L \V é" "'rms

月ω)=exp[ 一 (Orms w)2/21

月 1) = exp[ - Ofms/21

2

(b)

3 Orms (radians)

FIGURE 4一I7 Modified SinusoidaJ phase detector characteristic

vAee) Vdmsin(ee) Vdmsin(e~ + 叮)

Chap.4

w

w

w

(4-40)

Suppose that noise is the cause of e;“ee Chapter 6) so its probability density function is Gaussian with standard deviation erms:

p(e;) r 一 (e;f 1

巨石Eexpl 互互了 l (4-41)

?

Sec. 4-13 Modified Phase Detector Characteristic 77

The Fourier transform of Vd(ee) is

VAω) = 一jτVdmÔ(ω+ 1) + jτVdmÔ(ω- 1) (4-42)

where δis the Dirac-de1ta function (see Fig. 4-17a). The Fourier transform of p(叮) is

P(ω) = exp( 一 ω2e\ms/2) (4-43)

Then from Eq. (4-39) ,

VJ(ω) = P(ω)VAω) = jτVJmÔ(ω+ 1) + jτVJmδ(ω - 1) (4-44)

where the amplitude of the modified PD characteristic is

VJm P(1) Vdm exp( - e2 nn/2) Vd,

Tak.ing the inverse Fourier transform of Eq. (4-44) gives the modified PD characteristic

VJ( e;) VJmsin( e~) (4-45)

with a modified gain (slope at the origin) of

KJ = KdP(1) K"exp( - e2rm/2) (4-46)

The reduction factor P(1) is plotted in Fig. 4-17b for our Gaussian example. If the rms value of e;“1.0 radian , then VJm is about 60% of Vdm . Kd is also reduced to 60% of its original value. The consequence of e; is also seen in the acquisition of lock (see Chapter 8) when e; is due to the transient and e; is due to ei or noise.

The same technique can be used to analyze the effect of e; on triangular and sawtooth PD characteristics. The resu1t is always a rounding of the comers of vJ(e~) as P(ω) attenuates the “ harmonics" of v,,( ee)' See Pouzet [12] for the modified characteristics of these other phase detectors.

The three-state (and higher-state) PDs have characteristics with double-value functions (see Fig. 4-18a). This hysteresis complicates the analysis somewhat in determining the modified PD characteristic. Let e; be limited to some maximum magnitude emax; the uniform probability density function p(e;) in Fig. 4-18b is an example. If ee remains entirely on a linear portion of the characteristic (see cases 1 and 2 in Fig. 4-18a) , then the characteristic is unchanged (see cases 1 and 2 in Fig. 4一18c). But if ee ever touches a discontinuity in the characterist眩， the operation jumps to a new linear portion (see case 3 in Fig. 4-18a). Therefore , vJ can't have the higher value that v" does for that average phase error e~.

The modified PD characteristic in Fig. 4-18c plots vJ asa function of e~ for the case 。'max = 05rr. The effect is to reduce the modified phase range of the PD to ::!:: 1. 5τr. In general , the modified range is reduced by emax on each end.

For emax >甘， another phenomenon occurs , as shown in Fig. 4一 18d. There

。max = 1.5π

F!GURE 4-18

Vd

(a)

rn 8max 8max

(b)

的

(c)

Vd

false lock

(d)

。e=O; +IJ;'

-0;'

0;

Modified three-state phase detector characteristic

γ

。e

0;

References 79

continues to be a usable linear range about the origin , but a spurious linear range appe訂S

at O~ = τ. This provides a stable point of operation for the PLL, but with Oeo = τrather

than the desired Oeo O. One situation in which this can occur is when O~ is due to modulation of Oi while the PLL is acquiring lock, and 0; is the phase transient during acquisition. Then to avoid a false lock at 0; = 官， the modulation of Oi must be such that

。;F<τ (4呵47)

If O~ is unbounded , as in the cas巴 of noise-generated phase error, then the analysis of three-state PD behavior is intractable. The double-valued function v,,(Oe) makes it impossible to know even the probable value of v". For this reason , three-state PDs can't be used in applications where noise is significant.

REFERENCES

[1] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits , Wiley: New York, 1984, Section 10.3

[2] Anzac RF & Microwave Signal Processing Components , Adams-Russell: Burlington: Mass. , 1989, p. 341.

[3] Anzac Components , p. 272.

[4] Anzac Components , pp. 234-41.

[5] K. K. Clarke and D. T. Hess , Communication Circuits: A間加is and Design , AddisonWesley: Reading , Mass. , 1978 , Section 8.4.

[6] I. Shahria句， G. Des Brisay , S. Avery , and P. Gibsan,“GaAs Monolithic Phase/Frequency Discriminator," IEEE GaAs Symposium , 1985 , pp. 183-86.

[7] Motorola MECL Device Data , Motorola, Inc.: Phoenix , Ariz. , 1989 , Section 6.

[8] W. Egan and E. Clark,‘ 'Test Your Charge-Pump Phase Detectors," Electronic Design ，詣，

no. 12 (June 7 , 1978), pp. 134-37.

[9] Data Book: RCA High-Speed CMOS Logic ICS , Harris Semiconductor: Melboume , Florida, 1989, pp. 493-509

口的 J. F. Oberst,“Generalized Phase Comparators for Improved Phase-Locked Loop Acquisition," IEEE Trans. on Communication Technology , v. COM-時， pp. 1142-48, December, 1971.

[1日 D. H. Wolaver,“Extended Range Phase Detector," Patent 4 ,920,902, owned by General Signal!Tau-tron , Inc. , February 訝， 1990.

[12] A. H. Pouz仗，“Characteristics of Phase Detectors in Presence of Noise , Proc. 8th lnt. Telemetη Co彤， Los Angeles , Calif. , 1972, pp. 818-28.

?

5.....;司

CHAPTER

5

VOLTAGE-CONTROLLED

OSCILLATORS

PROPERTIES OF VCOS

In Chapter 2 we introduced the VCO characteristic as a linear function of the VCO frequency ωo with respect to the control voltage v C" The linear model is

ω。= dω。 +ω Ko(vc - Vco) + ωi (5-1)

where ωi is the average input frequency and Vco is the value of v c such thatωo ωi. Ko is the VCO gain. Since Vco depends on the input to the PLL, it is not considered a property of the VCO itself. In the simple examples so far, Ko has a well-defined value because the VCO characteristic has been linear. In practice, this is only an approximation at best.

Figure 5-1a shows an ex紅nple of a VCO characteristic more like one would encounter in practice. Because the slope of the curve is not constant, the VCO gain Ko has a range of values from zero to 5 Mrad/s/V. Suppose for some particular application an acceptable range is 4 Mrad/s!V三 K。三 5 Mrad/s!V. Then the VCO can't be used for ω。<1 Mrad/s , where Ko < 4 Mrad/s!V. In this example , if v c > 2.5 V is applied (correspondingtoω。> 10 Mrad/s) , the VCO stops oscillating. Thus , the range ofthe VCO is 1 Mrad/ s <ω。< 10 Mrad/s. When the range is small , it is sometimes expressed as some

82

Wo

10Mr/s

1 Mr/s

|亡|κ戶

Voltage-Controlled Oscillators Chap. 5

stops oscillating beyond here

κ口 =5Mr/s/v

lv 2v Vc

(a)

凶3

2Mr/s W斤7

(b) F!GURE 5-1 VCO characteristics

deviation abouta center frequency , such as 5 Mrad/s ::t 10%. Similarly, Ko can be expressed as a center value with a deviation , such as Ko 4.5 Mradls/V ::t 11%. The percent deviation of Ko is a measure of the linearity of the characteristic. There is obviously a tradeoff between range and linearity.

The VCO characteristic implies that there is a fixed relationship between V c and ωo no matter how quickly V c changes. But if V c is modulated at too high a frequency , the modulation of ωn is less than that indicated by Ko. Fig. 5一1b shows a typical modulation respon紀; the ac gain Iwjvcl is Ko tvr low fl叫uencies of modulation 旬， but it falls off for ω>ω3. This reflects a pole atω3 in the VCO transfer function:

ω。(s)

vc(s)

K O

1 + slω3 (5-2)

whereω3 is called the modulation bandwidth. As shown in section 3-7 , a pole atω3 in the forward loop gai I1 G(s) can cause instability ifω3 < K. If的 is to have little effect on the PLL responSl:、~ good rule is to keep ω3 三 4 K (see Fig. 3-13).

Sec. 5-2 Voltage-Controlled Multivibrators 83

In this chapter, we look at three kinds of VCOs-astable , multivibrators , L-C oscillators , and crystal oscillators. Each has advantages and disadvantages in terms of range , linearity , modulation bandwidth, and immunity to outside influence. This last property is seen in the VCO phase noise , which is analyzed in section 6-5. It is also seen in susceptibility to being “ pulled" in frequency and phase by other signals. This important practical consideration, called injection locking , is the subject of the last third of this chapter. In general , VCOs less sensitive to noise and injection are also less sensitive to temperature and to variations in power supply vo1tage.

5-2 VOLTAGE-CONTROLLED MUL TIVIBRATORS

There are two general classes of oscillators: relaxation oscillators (or astable multivibrators) and resonant oscillators (or Vanderpole oscillators). Figure 5-2 shows a circuit for a voltage-controlled multivibrator. A current ιcharges and discharges a capacitor cx between two values of the threshold voltage vt-between 2 V and 3 V in this case (see the waveform for Vl). The output V o is a square wave. The frequency of oscillation is determined by the rate of charging Cx, which is proportional to I叫 ic ， which increases with vc. The relationships are ic = (vc 一 0.6 V)/R , and TI2 = V1C)丸， where V1 is the difference between the thresholds and TI2 is the time to charge the capacitor by V1• But T is the period of the oscillation, so ω。 27rIT. Therefore

ω。= 7r一 (Vc - 0.6 V) V1RCx

ι (5-3)

In commercially available oscillator chips , the capacitor Cx is left as 組 extemal component so the user can select the frequency of operation. For the circuit here , R = 1 kü and V1 = 1 V. IfCx = 628 宵， then Eq. (5-3) gives ω。= (5 Mrad/s!V) (v c - 0.6 V) , and the VCO characteristic is that shown in Fig. 5一1a.

It is usually not necessary to construct a circuit like that in Fig. 5-2; commercial integrated circuits are available , such as the Motorola MC4024. The published characteristic [1] for the MC4024 (see Fig. 5-3a) gives the productfoCx as a function of V c

Corresponding to V c = 4.3 V (about the center of the linear range) isfoCx = 330 MHzpF. Selecting Cλ110 pF, for example, gives.ι= 330/1 10 = 3.0 MHz , orω。 =2πι=

18.8 Mrad/s. Then as V c varies from 3.7 V to 4.9 V (the linear portion of the characteristic) ,fo varies from 1.8 MHz to 4.2 MHz , or 3.0 MHz ::t 409毛 (see Fig. 5-3c). The VCO gain is Ko 2τr(4.2 - 1.8 MHz)/(4.9 - 3.7 V) = 12.6 Mradls!V.

In some applications , the VCO range needs to be constrained to keep the PLL from locking to the wrong frequency component (as in the example in Fig. 1-2) or to reduce the time required to attain lock.

+5

LM1茲別LM311 1 kO

+2.5 Vo

Vt I

vc -0.6 V

Vc +2.5

3

2

I-- T/2刊

Vo

←--T一→| 凶。 = 21r/T

5

FIGURE 5-2 Voltage-controlled multivibrator

九Cx

5∞

4∞ /

(MHz-pF) / /

v

~ v

-

300

2∞

100

L.J\ 3v 4v 5v Vc

(a) FIGURE 5-3 Reducing VCO range

Sec. 5-2 Voltage-Controlled Multivibrators

fo • (MHz)

4.2

3.3 3.0 2.7

1.8

3.7

V~

4.15 4.3 4.45

(c)

110 pF

(b)

4.9 Vc -3.5

FIGURE 5-3 (continued)

EXAMPLE 5-1

85

只b

3.5 v~

(d)

The voltage vc' from the loop filter is constrained to - 3.5 三抖，三 3.5. Design a VCO whose range is constrained to 3.0 MHz :t 10%. By choosing Cx = 110 pF, we get the characteristic in Fig. 5-3c with 10 centered in the linear range. According to this charactedstic, we constrain 2.7MHZ<jL<3.3MHz by constrainmghto the range 4.15 V 三九三 4.45 V. Then we need a resistor network to attenuate the swing of V

c' by (4 .45

- 4.15)/(3.5 + 3.5) = 0.043andshifttheO-Vcenterofv企 to the 4.3-V center of v r' The resistor network shown in Fig. 5-3b provides the necessary relationship: 心

V c = 4.3 V + 0.043 Vé

Specifica1ly , Vé = -3.5 Vresults in V c = 4.15 V, and Vé = 3.5 Vresults in vr

= 4.45 V. The modified VCO characteristic is that shown in Fig. 5-3d with the range li出ited 的 2.7MHz 三10 三 3.3MHz.with the voltage divider now part ofthe VC0 , the gain is reduced to Ko' 三 Aω。/ßv去= 2τ(3.3 - 2.7 MHz)17 V = 0.54 Mrad/slV.

γ

87 Resonant VCOs Sec. 5-3 Chap.5 Voltage-Controlled Oscillators 86

VR

+1 代?平 T

\ MVl404

\ 代

\ h、\

h\ --1--.

10 B 6

(volts) 4 2

CT (pF)

160

40

120

80

5-3 RESONANT VCOS

Resonant oscillators can operate at higher frequencies than multivibrators , and they are less influenced by noise, stray signals , temperature , and supply voltage. Figure 5-4a i1lustrates the principle of a resonant oscillator. A resonant circuit-a parallel L-C tank一converts the current i\ from a current source to a voltage v ,. At resonance , that is at the

frequency

the admittances of L and C cancel, and the tank has the impedance rp" This resistance is usuallv not an actual resistor but rather a model of effective resistance due to losses in the current source and the inductor. [2] The quality factor or Q of the tank is

Then at resonance , V\ = r，η.p i\. But the source of i\ is dependent on V\: i\ = gm V叫\， where gm 1誌st由h叫et缸ran剖叩n削1

unity loop gain we must have g仇m = l!r，η.p" This relation is often maintained by 祖 a叫ut切oma滋tl眩c

gain cωon恥tro叫01. Th晦e result is oscillation at the frequency ωo given by Eq. (5-4).

(5-4)

(5-5)

ω。=吋c

Q = r,JwaL

Varactor characteristic

The frequency ωo may be controlled by varying C electronically, converting the oscillator to a VCO. The oscillator in Fig. 5-4b includes a varactor diode 的 p訓 of the tank capacitance. A varactor is a reverse-biased diode whose junction capacitance Cr is a function of the reverse bias VR; a typical varactor characteristic is shown in Fig. 5-5. In the circuit in Fig. 5-4b, VR is applied by the control voltage Vc through a buffer resistor Rr which keeps the source of V c from loading down tl叫a也 A series capacitor Cs blocks dc current that would otherwise flow through Rc and L. Therefore , VR V c for slow variations in V c- The total capacitance is given by C CsCrf(Cs + C

T).

gm=llrp

Design a resonant VCO with a range from 67 Mrad/s to 134 Mrad/s. (This factor-of-two range is called 組 octave range.) Make the VCO gain Ko vary as little as possible over the range. The circuit has the form shown in Fig. 5一帥， where the transconductance amplifier (with AGC to maintain the proper gain) has been provided by the Motorola MC1648. The varac伽 is a Motorola MV1404 , with the characteristic shown n Fig. 5-5. The series C叩acitor C s and the p紅allel capacitor Cp provided flexibiIity in designing the VCO characteristic.

The relationships goveming the design are Eq. (5-4) relating ω。 to C

(5-6) CoCr ---一 +CC

s + Cr -p

EXAMPLE 5-2

一

C

FIGURE 5-5

ω。 =1/.JTC

gmv, +

V,

Resonant oscillator FIGURE 5-4

C= CTCs 一-

CT+Cs

(a)

(b)

Vc

gmv, +

V,

?

89 Resonant VCOs

TABLE 5-1

Sec. 5-3

。》。

2.8 V

1.8

0.8

77.5

96.2

117.2

135.。

F、JAYA

廿"、J

422I 7005 A

峙，丹、d

司，缸，且

A峙，、JζO

弓，

勻，缸勻，但勻，-7H

AVg1

勻，hqJ

Chap. 5 Voltage-Controlled Oscillators

44.2 Mrad/s 50.2

61.3

C

138 pF

107

71

88

CT

160 pF

120

77

νR

V ﹒I

司EL弓3

V,

Vo

(ECL) MC1研8

Oscillator

-3.8V 問，= vc+3.8

C CeC7n =---一 +CnCs+CT

(a)

Design a resonant VCO with a frequency range of 100 Mrad/s :::l::: 5% (that is , 95 Mrad/s to 105 Mrad/s). The VCO gain Ko is to be as small as possible while maintaining a 士 10%

tolerance on K~ over the frequency range. One solution would be to use the same Cs and Cp values in Example 5-2 and

constrain the control voltage to 1.4 V 士 275 mV. But this is a very small range for 丸，corresponding to a high value of Ko. This makes the VCO more sensilÌve to noise and dc offsets.

To reduce Ko , we need to make the totaI capacitance C, caIculated in Eq. (5-6) , be less sensitive to CT . This can be done by both increasing Cp and decreasing Cs . Increasing Cp tends to fIatten the upper end of the VCO characteristic by swamping out CT when CT

becomes small. Decreasing Cs tends to fIatten the Iower end of the VCO characteristic by dominating CT when CT becomes large. Trial and error is required to find values of Cp and Cs so that the slope (or VCO gain) Ko is as small as possible while maintaining less that a :::l::: 10% variation in Ko over the desired :::l::: 5% range of ωo. A spreadsheet computer program is useful here.

Two designs are shown in Fig. 5一7a. In Design 叭， Cp = 300 宵， Cs = 200 pF , andL = 0.286μH. This achieves low gain; the whole available range from V c = - 2.8 V to 3.2 V is used to go from ω。= 95 Mrad/s to 105 Mrad/s. But because the infIection point is too far to the left, Ko varies a great deal over the range-from 2.6 Mrad/s/V to 0.7 Mrad/s/V. The excessive fIattening of the curve at high frequencies indicates Cp is too large. In Design 缸， Cp is decreased to 120 前， and Cs is 60 pF to again require a 6-V change in v c for a 10% change in ω。. The Iast step is to choose L 0.68μH for the desir，叫 frequency range about 100 Mrad/s. The infIection point is now centered, and Ko varies from 2.45 Mrad/s!V to 1.05 Mrad/s!V. This is Iess variation, but it stiII exceeds the specified :::l::: 10% variation. We need to increase Ko and discard the ends of the curve.

Two more designs are shown in Fig. 5一7b. In Design #3 , the gain is increased by decreasing Cp to 17 pF. For Cs = 22 前， there is a quite linear range over the desired 10% changeinωo. Choosing L = 3 .40μH centers this range on 100 Mrad/s. The variation of Ko over the range 95 三 ω。三 105 Mrad/s is only :::l::: 10% about a value of 3.5 Mrad/s!V. To constrain ω。 to this range , we need to constrain - 0.5 三 Vc 三 3.1 V. This is easier to do if the voltage range were centered on 0 V.

EXAMPLE 5-3

(Mrad/s)

, 一，一一一一一一---"

Ko=18 Mrls/V:l:: 15%

Resonant VCO example

relating C to 斗， and Fig. 5-5 relating CT to VR . The largest possible range is achieved when C = CT bychoosing Cp = 0 and Cs Iarge compared ωC.，-say ， Cs = 1000 pF. From Fig. 5-5 , CThas a lO-to-l range , and from the square root in Eq. (5-4) ， ωo therefore has a ~aximum -jl0-to-l range. This is greater than the required 2-to-l range , but linearity is impro~ed if we are not forced ωuse all of the VCO range.

Table 5-1 shows the computed parameter values for the choice Cp = 0 and Cs =

1000 pF. Because the anode ofthe varactor is at - 3.8 Vdc , VR = V c + 3.8 V. The values of ω的 versus V r in Table 5-1 are plotted in Fig. 5-6b. L = 3.71μH was selected to put the infIectio呵。int in the center of the desired range 67 Mrad/sω134 Mrad/s. This achieves the greatest linearity. The gain Ko is a maximum in the center and a minimum on the two ends: Kn = 18 Mrad/s!V :::l::: 159毛. For ωo to be limited to the desired range , V c needs to be lin帥d to the range - 0.5 V 三 Vc 三 3.1 V. This can be done with a resistor蚓work， as in Fig. 5-3b , or diodes can be used to limit 吭，的 in the next example.

Wo

134

，-一/

/ /

/ /

-" ---FIGURE 5-6 Vc 4 3 2 一 1一 2-3

1∞

Cs =1∞o pF

Cp=O

L=3.71 μH

CT:MV1404

「91

v c

Modulation Bandwidth

-1 .4V三 Vc :5 1.4V

Sec. 5-4

一 Vd


(Mrad/s) 凶。(Mrad/s) ω。

110

90

Limiting v,

Further information on the theory of resonant oscillators can be found in Clarke and Hess. [3] More on the design of resonant VCOs is available in Rohde. [4]

Note that we still need to chose a value for Rc in Fig. 5-6a. This value depends on the desired modulation bandwidth.

FIGURE 5-8

5-4 MODUlATION BANDWIDTH

To change ω0' V c must change VR by charging Cr and Cs through Rc (see Fig. 5-6a). C" is essentially 砌的d out by the inductor since V c cha時es slowly comparedωthc oscillation frequency. A model is shown in Fig. 5-9 to find the transfer function from V

r to V". This

is simply VR/Vc 1/(1 + s/的)， where the mo吻你的1 bandwidth of the VCO is

90

Vc 3 2 一 1一 2。。Vc 3 2 1 -2 -3

(b)

#4

60 pF

65 pF

1.08μH

FFUm 約恥川和

。。

#2

60 pF

120 pF

0.68μH

Design: #1

Cs: 200 pF

Cp: 鈞。 pF

L: 0.286 μH

(a)

VCO characteristic for Example 5-3 FIGURE 5一7

(5-7)

Since Llω。 = Ko VR' the complete transfer function of the VCO is that given by Eq. (5-2):

包}O

V C

I/Rc(Cr + Cs)

K O

1 + s/ω3

ω3

(5-8)

I~I Wm

Wm ω3

VCO modulatioIÌ 'bandwidth

I~I

FIGURE 5-9

Rc 戶r一一

CT :

句=一一一L一一Rc(CT+Cs)

In Design #4, the linear portion of the curve is moved to be centered horizontally on V c = 0 V. Cs is increased to 60 pFωmake the lower part of the curve more linear. Cp

= 65 pF provides a 10% change in ω。 for a 2.8-V change in V n andL = 1.08μH centers the range vertically on 100 弘1rad/s. The gain is again Ko = 3.5 Mrad!s!V ::!:: 10%. Table 5-2 gives the parameter values for this final design.

To constrain 95 三 ω。三 105 Mrad/s , we need to constrain - 1 .4三 Vc 三 1.4 V. This can be done with diodes , as shown in Fig. 5-8. Since V d develops little vo1tage across R2' V c is not more than two diode drops away from ground.

TABLE 5-2

“》。

2.8 V

1.8 0.8

0.2

1.2

2.2

3.2

92.3 Mrad/s 93.8

96.8

100.6

104.3

107.5

109.6

C

109 pF

105

99

91

85

80

77

CT

160 pF

120

77

47

30

20

15

VR

V 1

旦司

EL句、UA-I

戶、以辰。句，a

V C

92 Voltage-Controlled Oscillators Chap. 5

It is important to keep ω3 high enough that it doesn't affect the loop response H(s). A good rule is to keep ω3 > 4K, where K is the PLL bandwidth. Then for the worst case, we must look at the maximum CT over the operating range of the VCO.

EXAMPLE 5-4

The VCO designed in Example 5-2 is to be used in a PLL with K = 0.1 MradJs. Choose Rc to maximize the Q of the tank.

In Example 5-2, the lower end of the range (ω。= 67 MradJs) corresponded to the maximum CT = 70 pF. For K = 0.1 MradJs, we need at least ω3 = 0 .4 MradJs. Since Cs

= 1000 悶， Eq. (5-7) gives Rc = 2.主過. As we will see in the next section , this is a rather low value which spoils the Q of the tank circuit.

EXAMPLE 5-5

The VCO of Design #4 in Example 5-3 is to be used in a PLL with K = 0.1 MradJs. Choose Rc to maximize the Q of the tank.

In Design #4, the lower end of the range (ω。= 95 Mrad/s) corresponded to CT = 101 pF. For K = 0.1 Mrad/s , we need at least ω3 = 0 .4 Mrad/s. Since Cs = 60 pF, Eq. (5-7) gives Rc = 盟主û. This value will be high enough to preserve a good Q.

5 -5 0 OF THE RESONANT CIRCUIT

The tank in a resonant VCO needs a high Q for low phase noise and low injection sensitivity for the VCO , as will be shown in sections 5-8 and 6--5. A high Q is associated with low lossiness , and much of this loss is in the inductor. The inductor loss can be modeled by a parallel resistance

rL = QLω。L (5-9)

where QL , the quality factor of the inductor, is a weak function of ωO. The function depends on the physical design of the inductor, but a rough relationship between ωo and QL is given in Fig. 5-10a.

Another loss, one that we have introduced for the sake of control, is in the resistor Rc. In the model in Fig. 5-lOb , the grounding of the left end of Rc assumes that the impedance of the Vc source is negligible. Since Rc is only across CT, it doesn't see the full voltage across the resonant circuit, and it degrades the Q less than if it were across the

Sec. 5-5 Q of the Resonant Circuit 93

QL

位 =QL ωoL2∞

100

。 0.1 10 100 ∞o wo(Mr/s)

(a)

也二) R~ rL

R~=(CT/Cs+1)2月c

(b)

FIGURE 5一10 Q of resonant circuit

total C. Clarke and Hess [5] show that the loss due to an Rc' across the total C (see the second model in Fig. 5- lOb) is the same as that due to Rc if

Rc' (CT/Cs + 1)2Rc (5-10)

Since small Rc' degrades Q the most, the worst case must consider the minimum CT .

In the final model in Fig. 5-lOb, Rc' and rL are in parallel , constituting rp. Then from Eq. (5-5) , the Q of the resonant circuit is given by

叫一叫

Q (5-11)

EXAMPLE 5-6

Find the Q of the oscillator tank in Exarnple 5-4. The values in Example 5-4 were CTmin = 16 pF for ω。= 134 Mrad/s , Cs = 1000

pF , L= 3.7 μH ， andRc = 2.38 kû. From Fig. 5-10a, QL = 135 , and rL = QLω。L = 67 kû. Then from Eq. (5-10) , R; = 2 .45 kÛ , and Eq. (5-11) gives Q =生75 ， which is quite low.

-94 Voltage-Controlled Oscillators Chap. 5

EXAMPLE 5-7

Find the Q of the oscillator tank of Design #4 in Example 5-5. In Design #4 we had CTmin = 28 pF for ω。= 105 Mrad/s , Cs = 60 pF, L = 1.08

μH， and Rc = 15 kû. From Fig. 5- lOa, QL = 130, and rL = QLω。L = 14.7 kÛ. Then from Eq. (5-10)，見= 32 帥， and Eq. (5-11) gives Q 鈕， which is very good.

Comparing the two 巳xamples ， the moral is to keep Cs as small as possible, consistent with other design criteria. Otherwise the modulation bandwidth requires too low an Ro and the Q is degraded excessively.

5 -6 CRYSTAL VCOs

When an extremely low PLL bandwidth K is needed , it is usually not satisfactory to simply make a very small Kh (see the loop filter design in Chapter 2). This would greatly attenuate 丸， which would have trouble competing with noise and injection signals. The better approach is to make Ko very smal1 by using a crystal oscillator for the VCO. The result is a voltage-cdntrolled cηIstal oscillator, called a “ VCXO."

Figure 5-11a shows a circuit for a VCXO with a varactor used for tuning the

v c

C.CT C=-"一一Cx+Cr

(a)

XTAL 「一一一一一一一一-7

Cr

(b)

MC12061 osc.

MC12061 osc.

Vo

νb

ω。 = -τ-、 LC

在~.~.T~ ...， ζ11 、T^1t~CTP_(，內n廿'011吋 p何吋~I osci1lator (VCXO)

「

95 Crystal VCOs Sec. 5-6

frequency. The amplifier portion of the osci1lator is provided by a commercial circuitKMotomla MC12061.In Fig 5llb the crystal has been repla叫 by its equivalent círcuít-a series R-L-C circuit. The crystal manufacturer usually specifies the frequency ω叫他eω。 corre叩onding to CT = 30 pF) , the Q of t血he cη恥u啪tal (令re叩pres臼s巴叩n叫l此t紀edhe旭間er，昀eb句y Q，ι‘x) a吋伽 eq恥咖ui廿valen削仙tserie臼s削s“啪蝴t臼仙a缸ncε r九's' From叫1 血伽e郎s鉛叫e theL a祖n叫dCι'x for伽 mod配制el ca組n的bef，臼ou…hthrough the relationships

Qx = ωoJ.，/rs

ω。o - 1/丘之1/Cxo 三 I/Cx + 1/(30 pF)

(5-12)

(5-13)

(5-14)

(Sometimes the manufacturer specifies some capacitance other than 30 pF, such as 22 pì'.)

The crystal oscillator is voltage-controlled by adjusting VR across the varactor to V訂Y CT . As with a parallel resonant circuit, the oscillation frequency is given by

ω。 = 1/ jLC (5前 15)

where

1/C = 1ICx + 1ICT

1ICxo + I/CT 一 11(30 pF) (5-16)

Because the effective capacitance Cx is extremely small-ùn th巴 order of 0.01 昕一-CTmust 也o be small to make any significant change in C. Figure 5-12 shows th已characteristic of a low-capacitance varactor with a minimum CT of 5 pF. (It is difficult to

Cr (pF)

50

40

30

20

10

2 3 4 5 6 7

(volts)

8 VR FIGURE 5-12

也 characteristicLow-capacitance varactor

? 學們

97 Injection in Multivibrator Oscillators

VR

1 V

2

3

4

5

6

7 8

ω。 40 Mrad/s

-2.667 krad!s 0.0

4.444

10.000

16.862

24.102

29.697 33.333

CT

50 pF

30

18

12

8.5

6.5

5.5

5.。

TABLE 5-3

Sec. 5--7 Chap. 5

go much lower than this because of case capacitance and stray wiring capacitance.) But even this small CT is still about 500 times C肘， and this allows us to make simplifying approximations in findingωo in tt<rms of CT •

From Eqs. (5-13) through (5-16) , we have

Voltage-Controlled Oscillators 96

J1ICxo + 1ICT 一 11(30 pF)

!i J1 + CxolCT - Cx)(30 pF)

jLCxo

。}。==

=ω叫1 + CxolCT 一 Cx)(30 pF) 5-7 INJECTION IN MULTMBRATOR OSCILLATORS

Suppose that a periodic signal is injected into a multivibrator osc i11ator with a frequency near to that of the oscillator's frequency. It is possible for the frequency of the oscillator to be pulled to that of the injected signal and to be actually phase-locked to the signal. This is essentially the pro臼ss by which the time base of an oscilloscope is synchronized to the viewed waveform. In the case of the VCO in a PLL , the i吋ected signal of concem is the unintentional introduction of the input signal Vi directly into the VCO. This injection usually causes the PLL to behave in a way that it was not designed to behave.

The effect of injection in a multivibrator is illustrated in Fig. 5-14a. An injected

(5-17)

z ω。0(1 + 0.5Cxo ICT - 0.5Cx)30 pF)

ω。 ω00 = 0.5ωooCxo( 1ICT 一 1130 pF)

The approximation above uses F王三= 1 + x/2 伽 x<< 1

or

(krad/s) ω。 -40Mr/s

35

25

20

FIGURE 5-13 Voltage-controlled crystal oscillator characteristic

% ω

± V ',f en-',,

lf}Ill--

rI LK 弓，

EU --O K

VR

30

8 7 6 5 4

34 kr/s (鈞。 ppm)

3

15

10

5

。RU

EXAMPLE 5-8

A crystal is specified to osc i11ate atω。o = 40 Mrad/s for CT = 30 pF. The Qx is 50,000 , and the effective series resistance is r, = 50 il. Find L and Cxo for the crystal model. If a KV 1401 varactor manufactured by Frequency Sources (see characteristics in Fig. 5-12) is put in series with the crystal , plot the osci11ation frequency ω。 as VR is varied from 1 V to 8 V. Find the range of the VCXO for which the gain Ko varies by ::'::40% or less.

From Eq. (5-12) , L = 旦主旦旦 From Eq. (5-13)，已。=生旦1且.1:， and Eq. (5-17) becomes

ω。一 40 Mrad/s (200 krad/s-pF)/CT - 6.667 krad

Table 5-3 lists values of CT taken from Fig. 5-12 and corresponding values of ω。 40

Mrad!s. These data are plotted in Fig. 5-13. At the upper end of the VCO characteristic , Ko

degrades quite a bit. If we limit VR to the range 1 V 三 VR 三 7 V, then Ko is 5.7 krad/slV ::'::409毛， and ωo varies over a range of 34 krad/s. This range is only 850 ppm of the 40 Mrad/s oscillation frequency , reflecting the extremely small Ko.

For more information on crystal oscillators, see Clarke and Hess. [6]

瞬間F

98

+2.5

「士一、〈叫

_ .... ---

Voltage-Controlled Oscillators Chap. 5

+5

Vo

+2.5

(a)

--_....-

(b)

.... _ ....

F!GURE 5-14 Frequency puIling by injection in a multivibrator

signal VI = V1sin(ω/ + 8) is added to threshold voltage Vf (compare Fig. 5-2). The phase 8 here uses the rising edge of V f to define t = o. In the steady state, the ramping voltage v, rises to meet the perturbed threshold at the same point in the cyc1e every time. In the example here , v, tums around before it would have if there were no injection. The result is that the oscillation frequency ωo of the multivibrator is higher than normal--enough higher that ω。 =ωi﹒

Let the frequency of the multivibrator without injection be ω仰， and let the amount the frequency is pulled by injection be

Aωo ω。一 ω。。 (5-18)

f

Sec.5一7 Injection in MUltivibrator Oscillators 99

The difference between the two (unperturbed) threshold vo1tages is 吭， the time v, would have risen without injection is T )2 , and the time v, rises with i吋ection is T/2 (see Fig. 5-14b). The slope of v, is a constant v ,. Then

T)2 = V，月 1

and from the geometry in Fig. 5-14b it can be seen that

T/2 (V, - 2V1sin 8)iV ,

But ω。 2'IT/T， and ω。o 2'IT/To . Therefore

ωJω。o = V,/(V, - 2時sin 8)

1/[1 - 2(V/V,)sin 8]

= 1 + 2(們lV，)sin 8

for ~也<< V j • But from Eq. (5-18)

ω。/ω。o ω。o + Llω。)/ω。o 1 + Llω。/ω。。

Then from Eqs. (5-21) and (5-22) ,

Aω。= 2ω。00心lV， )sin 8

This can be expressed more compactly as

Aω。 KIsin 8

where the injection constant KI is given by

K1 =2ω。o(引IV，)

(5-19)

(5-20)

(5-21)

(5-22)

(5-23)

(5-24)

The relation between Llω。 and 8 in Eq. (5-23) is actually part of a feedback loop since the phase 80 of the oscillator is the integral of LlωV' and θis the difference between 80 and the phase 81 of the injected signal. This is summarized by the signal flow graph in Fig. 5-15. Note that this is identical to the flow graph for a first-order PLL with bandwidth KI (compare Fig. 2-4). Therefore , it is possible to have phase locking with no phase detector-just an oscillator and an injected signal

「floe-6

可01Injection in Resonant Oscillators Sec.5-8

+

ví ~

d~ 1 φ1 F

Vl

Resonance (c)

(a)

gmví ví

;三昕一一→|Injection

φ2=φ1

Chap.5 Voltage-Controlled Oscillators

/戶\I一---.~ω。「一---.

。/一→(+~心 L→1 t< 仁~J吋'th刊。

10。

Model of oscillator with injection FIGURE 5-15

5 -8 INJECTION IN RESONANT OSCILLATORS

Resonant oscillators have a similar behavior in the presence of an injected signal (see Adler [7]). Figure 5-16a gives a model for a resonant oscillator with injection (compare Fig. 5-4). The voltage across the resonant circuit is Vl = V1sin(wot). The injected voltage is VI = 叫sin(ω;t + (}), where ω。 =ωi in lock, and (} is the phase of V[ relative to Vl' The effect of injection here is to produce V; = Vl + V[ with V; shifted in phase from Vl by φ2 ，

where

φ2 = tan- 1[(V[sin (})1V1] (5-25)

for V[ < < V1 (see phasor diagram in Fig. 5-16b). For oscillation to be sustained, the tank circuit must produce a compensating phase shift - <1>1 between V; and Vl (see Fig. 5-16c). Let V1/V; be the transfer function of the transconductance amplifier and tank. This transfer function has a pair of poles a distanc~CT 0 from the imaginary 缸is. The oscillation frequency for no injection is woo 11冉jiC.-Frorr叫Iclear that

slope= 一 σ。-1

ang (Vl/víl

7r/2

I叫

ω

A

、

BEEt--JIt--EF

。

OO 甜甜Ar φtan一 1 [(ω。一 ω00)/σ。]

tan -1[àω。/σ。]

已3

向一lliu

Q ω00 =--2σ。

(5-26)

where àω。三 ω 一 ω00 as in Eq. (5-18) , and the Q of the tank is related to its bandwidth 2σ。 by

= tan- 1 [2Qàω。/ω。0]

一 φ1

-7r/2

(e)

Frequency pulling by injection in a resonant oscillator

σ

(d)

FIGURE 5一16

-σ。

(5-27)

The phase of the transfer function Vl/V; function is ang(V1/V;) tan- 1 [(ω 一 ω00)/σ。] ; this is plotted in Fig. 5一16e.

For sustained oscillation, we must have φl (5-26) ,

Q=ω。012σ。

=φ2' Then from Eqs. (5-25) and

(5-30)

Comparing Eq. (5-24) , we see that Eq. (5-30) can include the case of a multivibrator if the “ Q" of a multivibrator is taken as 114.

where for the resonant oscillator,

K[=(ω。of2Q)(V/V1 )(5-28)

(5-29)

Aω。= (ω。of2Q)(V/V1 )sin (}

This can be put in the form we had for the multivibrator oscillator:

Aω。 Kßin (}

102 Voltage-Controlled Oscillators Chap. 5

5-9 PLL BEHAVlOR WITH INJECTION

When injection exists in a PLL, the VCO frequency Llω。 is controIled in two ways: by a voltage Vc derived from a phase detector (as desired) and by injection [Eq. (5-29)]. This situation is modeled in Fig. 5-17a, where the loop filter is represented as in Fig. 3-1b. The injected signal is simply the input signal Vi attenuated to an amplitude ，心 and shifted by a constant phaseα. That 訟， the injection phase {}[ is given by {}i +α. Using the relations K = KdKhKm Kh = Ri丸，組dω2 - l!R2C, we can simplify the model as in Fig.5一17b. This is a large-signal model including the nonlinearities of the PD and of the injection. Note that {}三{}[ - {}o = {}[一 ({}i - (}e) = α + {}e.

We can develop a small-signal model about the steady-state operating point. In the steady state, the integration in the loop filter assures that {}e = O. Therefore , {}e is small , so sin {}e = 孔， and cos {}e = 1. We have the trigonometric identity

sin {} = sin(α + (}e) == sin {}ecos α+ cos {}esinα

= {}eCOS α+ sin α

These smaIl-signal approximations lead to the linear model in Fig. 5-17c. The term (K + K[Cos α)(}e dominates the term K，ω2 f {}e dt for ω>ω2. Therefore, injection has changed the PLL bandwidth , from K to

K' = K 十K[Cos α (5-31)

and a frequency offset K[sin αhas been added. Since we wish to þe in control of the bandwidth , and since αis not known in

general , K[ should be keprìnuch less than K. As a rule of thumb , the designer should keep

K> 4K[ (5-32)

Then for a PLL with small bandwidth , every precaution should be made to minimize injection. This involves filtering the power to the VCO , shielding the VCO with a metal box , filtering th令 input Vc to the VCO , buffering the output Vo from the VCO , and eliminating ground loops that would include the VCO.

Even with the most care, some i吋ection always exists. With careful circuit layo吼 a

typical value of (科1V1 ) is 111000. Then Eq. (5 < 24) gives a typical K[ = ω。.，/500 for a multivibrator VCO. For a resonant VCO , Q is typically at least 20, and from Eq. (5呵30)K[is typically less th組 ω。.，/40 ，000. The crystal in a VCXO typically has a Q of at least 20 ，000，組d K[ is typically less thanω。)40，000 ，000. Then Eq. (5-32) gives the foIlowing rules of thumb for a minimum practical bandwidth to avoid injection problems:

K> ω。，/ 125; multivibrator VCO

K> ω。，/10 ，000; resonant VCO (5-33)

K> ω。)10，000 ，000; crystal VCXO

γ

。i

自

。i

。。

PD Loop Filter VCO

(a)

自

(b)

(j;

(c)

FIGURE 5一17 Models of PLL with injection. (a) and (b) are equivalent; (c) is a small-signal model

γilrift

105 References

5-10 SPECTRAl PURITY

Ideally , an oscillator produces a single frequency ω。; the output has a frequency spectrum consisting of a line of zero width (see Fig. 5-18a). In practice , the frequency is modulated by noise一一thermal and shot noise originating within the oscillator itself. This causes the spectrum to have some width, as shown in Fig. 5-18b.

The mechanism causing the spectral width may be understood from the model for injection in an oscillator. Let the injected signal Vi in Fig. 5-16a be random noise rather than a sinusoid. It will be shown in Chapter 6 that noise can be represented as a sinusoid with random amplitude ，而 and random phase (}. Then from Eq. (5-28) , the noise causes frequency modulation of the VCO signal. The sidebands corresponding to the modulation give the spectral width. The modulation by the noise is inversely proportional to Q, so the spectral width decreases as Q increases. We will look at this more quantitatively in Chapter 6.

REFERENCES

[1] Motorola MECL Data Book, Motorola, Inc. , Austin, Tex. , 1986, Section 8. [2] K. K. Clarke and D. T. Hess , Communication Circuits: Analysis and Design , Addison

Wesley: Reading, Mass. , 1978, Section 2.3. [3] Clarke and Hess , Communication Circuits , Chapter 6. [4] U. L. Rohde , Digital PLL Frequency Synthesizers , Prentice-Hall: Englewood Cliffs , N.J. ,

1983, Section 4一1.[5] Clarke and Hess , Communication Circui俗， Section 2.4.

[6] Clarke and Hess , Communication Circui俗， Section 6.7. [7] R. Adler,“A Study of Locking Phenomena in Oscillators," Proc. IRE and Waves and

Electrons , vol. 34 (June 1946) , pp. 351-357.


Spectral density of Vo

104

Ideal

(a)

w 已ð。

Spectral density 。，f Vo

w

Oscillator spectral width due to intemal noise

Wo

(b)

Spectral width proportional to

1/Q

FIGURE 5一18

For KJ > K 組d 'IT12 < α< 3'IT/2 , it is possible that K + KJCos α< O. Then the model in Fig. 5-17c shows that the feedback is positive and the PLL is unstable. The result is an oscillation of (}o at a frequency around ω2' This symptom is a c1ear indication of excessive injection.

A test for the amount of injection in a PLL is to ground the VCO input (Vc = 0) , and adjust the input frequency ωi until the PLL injection locks (wo = ωi)' For small K]， ωimay have to be very c10se to the free-running VCO frequency ω。o (for Vc = 0) to obtain lock. Seek the center of the lock range so that (} = O. Then a small frequency change ßωi (with a corresponding ßω。 =ßω;) will cause a ß(} in the phase between Vi and Vo ' For (} = 0, Eq. (5-29) gives

(5-34) KJ = ßω，/ß(}

「

CHAPTER

6

NOISE

We have considered the perforrnance of phase-locked loops with perfect signals-perfect sinusoids or square waves with no noise. In fact , though, some noise is always present, and the noise may be significant , as in communications applications involving long distances. Noise appears at the input to the PLL along with the input voltage 內， and there is a small amount of noise actually generated within the VCO. Both of these sources of noise contribute to phase noise at the PLL output. This chapter reviews the characterization of noise in the frequency domain and resolves the noise into an amplitude component and a phase component. Once we can view noise as phase , we can bring to bear on it the phase responses that we have developed for a PLL.

We begin with a review of some noise and random signal concepts. See Davenport and Root [1] and Papoulis [2] for more on these basics.

6-1 POWER SPECTRAL DENSITY

An example of a random noise waveforrn n(t) is shown in Fig. 6-1a. A measure of its strength is the mean-square va1ue 旱， also called its “ power." This is defined by

京三JZJ; 正的 dt (6-1)

vzflit

令: 109

The distribution of the power in the frequency domain is given by the one-sided power spectral density φn的 for the variable n(t). [The term one-sided means that φn的 iszero for f < 0.] A typical power spectral density is shown in Fig. 6-1c; it gives for each frequency the mean-square value within a l-Hz band centered on that frequency. Therefore , the total mean-square value is the area under the curve:

(6-3)

φ(f) is traditiona11y ca11ed the power spectral density rather than the mean-square spectral density; it is simpler, and the two concepts are related by some constant impedance. It is also traditional to define φ的 so that the mean-square is given by the integral over f (in cyc1es per second) rather than by the integral overω(in radians per s即ond).

The equivalence of the two areas in Fig. 6-1 is a convenient tool for finding time averages [Eq. (6-1)] from frequency-domain information [Eq. (6-3)].

φn(f) df j 京=

Noise Bandwidth Sec. 6-2 Chap. 6 Noise

t (sec)

(V) n

2

108

6-2 NOISE BANDWIDTH

Most sources of noise , such as shot noise and thermal noise, are white; they have a spectral density that is essentially flat for all fr，叫uenc帥，的 in Fig. 6-2b. In accord with standard notation , No is the constant value of the white spectra1 density. Now , Eq. (6-3) says that this white noise n' has infinite power. In practice, though , there is always some filtering function limiting the bandwidth and therefore the power of the noise. The noise bandwidth of a filter is a value related to the 3-dB bandwidth that makes it easy to calculate this finite power.

Suppose n' is filtered by a transfer function HL(s) to produce an output signal n , as shown in Fig. 6-2a. The spectral density φn of n is given in terms of the spectral density φn' of n' by

t(sec)

(a)

<Pn

2

1 sec

(b)

(V2/Hz)

(V2) ri2

4

2

Area =n2 0.1

(6-4) φn(丹 =φn'的 IHL(j2削12

Since the noise is white, we can replaceφn' by a constant: f(Hz) 20 10

(6-5) φn(丹 = No IHL(j2可)12(c)

FIGURE 6-1 (a) Noise as a function of time; (b) mean-square noise in the time domain; (c) power spectral density of the noise We will be concemed first with HL(s) a low-pass filter:

(6-6)

This function has unity gain at dc and a first-order cutoff at ω3dB ﹒ The corresponding spectral density φn given by Eq. (6-6) is plotted in Fig. 6-2c.

Now we use Eq. (6-3) 的 get the mean叫uare noise at the output:

n2 = (6-7) f N.。他(β削12 df

HL(s) = ω3dB/(S +ω3dB)

The integral in Eq. (6-1) can't strictly be shown as an area because it involves a limit. However, it can be thought of as the area under n2(t) for one unit of time , if n(t) is “ typical" during that time. Figure 6-1b shows an example. The root-mean-square (rms) value is defined as

(6-2) nrms =拉

f

可喔，

It is convenient to define a noise bandwidth BL for a low-pass transfer function HL(s) such that

(6-8)

1.] From Eqs. (6-7) and (6-8) it follows that the noise

ftJ L 勻，-A

μ

用“

可申

.,I FaU

H ∞

FEEEMO

一一-

ZL B

一斗~~

Noise-Induced Phase Sec.6一3

n →巨于n 京 = NrßL

[This is for the case HL(O) bandwidth is given by

。'3dB的 (5)= 一一一一一5+叫3dB

(V也1Hz)<Pn'

(6-9)

For the case of the low-pass filter in Eq. (6-6) , carrying out the integration in Eq. (6-9) glves

(6-10)

wheref3dB 三 ω3dBI21T. For the purpose of calculating the mean-square noise ， φn may be modeled by a rectangular spectrum with bandwidth BL as shown in Fig. 6-2d. The area under this curve is the same as that in Fig. 6-2c.

We similarly define a noise bandwidth Bi for a bandpass filter

(6-11)

with unity gain atωi and a 3-dB bandwidth of ω3dB ﹒ This filter acts on noise n' to produce an output n (s臼 Fig. 6-3a) , Again , n' has a flat spectral density No ' as shown in Fig. 6-3b. Thenφn的 = No IHlj21Tf) 1

2 , as shown in Fig. 6-3c. The noise bándwidth is defined such that

。)3dBS

S2 + ω3dBS + ωf Hμ) =

f 3f3dB 2f3dB

(c)

f3dB

(6-12) 京 = Nrßi (model) <Pn

BgEJJHz(j2吶12df= (甘12)后dB

It follows that Bi is given by v A間=n2

BL = (,r/2)f3dB (6-13)

wheref3dB ==ω3dB/21T， For the pu中ose öf calculating mean-square noise ， φn may be modeled by a rectangular spec仕um with bandwidth B i centered on后， wherefi = ω/2τ

(see Fig. 6-3d). (d)

6 -3 NOISE-INDUCED PHASE

In applications where noise is significant, the PLL petformance is improved by using a pr，φlter before the PLL to reduce the noise n' as much as possible without materially

No

BL ω3dB/4 (1T/2) f3dB

f

(b)

<pno(f) = NoIHdj2".fJ!2

<Pn

No

Area= n2

No/2

No

f

FIGURE 6-2 Noise through a low-pass function HL(s) , and equivalent noise bandwidth BL

BL

n' 一→1 H，{s) ←一~ n H，{s)= 令叫B ?

8"" +s，ω3dB+ωf

(a)

4>n' .. (V2 /Hz)

No

f

(b)

4>n 學no(f) = NoIH;U2πfJ12

No

Nol2

再 f

(c)

學n ... (model)

No 4

一-B;_

Area=n2

= NoB; B;=(π12)f3dB

再 f

(d)

FIGURE 6-3 Noise through a bandpass function H，μ) ， and equivalent noise bandwidth B;

Sec. 6-3 Noise-Induced Phase 113

affecting the signal V; (see Fig. 6-4a). Let the input signal be a sinusoid without any modulation:

V; V;sin(ω;t)

We will see that the filtered noise n induces both amplitude modulation x and phase modulation ();:

V; + n (V; + x) sin(ω;f + (};)

The effect of the amplitude modulation x is only to vary the PLL bandwidth K slightly by changing the PD gain [see Eq. (4-10)]. The PLL responds mostly to the phase 阱， acting as a transfer function H(s) to pass phase (}o to the output:

Vo = Vo cos(ω;f + (}o)

(See Fig. 6-4b.) Consider the case of a bandpass prefilter with noise bandwidth B; centered on ω;l2'Tr •

If the unfiltered noise n' is white with spectral density No , then the noise n after the filter has the spectral density model φn shown in Fig. 6-5. (The spectrum is not actually rectangular, but the area under the curve is correct.) The mean-square noise appearing at the input to the PLL is n2 = N fi口的 in Eq. (6-12) ,

The noise n can be divided into two components:

n = nx + ny (6-14)

where

nx x sm ω戶， ny=Ycos ω;t (6-15)

prefilter

叮=的 sin (帥;t) Vo= Vo cos (剖;t+(0)

叮+n= (V;+a) sin (w;t+9;)

(a)

。;---1 H(s) ~之

(b)

FIGURE 6-4 Prefilter，吋 noise n inducing phase (); at PLL input

115

of Vi , and 丸， comprising the other half of 伽 noise pow札 induces phase modulation 01 Vi .

The expression for nx in Eq. (6-15) has the form of suppressed-carrier amplitude modulation, where x is the baseband signal occupying a bandwidth ofBt/2(see Hg.6-5) what is the spectral density of x?Since x and sin w areindependent vaItables

Noise-Jnduced Phase Sec. 6-3 Chap.6 Noise

Area=n2

吾n

No

114

P =否可玄宗 =P 5;FZ:f=ZEf2

But Eq. (6-17) has n/ = 宗/2 = Ncß;f2. Therefore

(6-18)

Because the bandwidth of φ'x isBρ， its height must be 2No to give the area in Eq. (6-18). A similar development leads to the spectral density φy shown in Fig. 6-5 and to

豆 = n2 = Ncßi

8;

f ω;!27r

F一什

AT--卜liiL

mn '9

川句

-f A↑

l卜||l

Y

勻，h

n/ @M

句(6-19)

Vi sin ωit. Using the

y n2 Ncßi

Now let the noise n be added to the input signal Vi expressions in Eqs. (6-14) and (6-15)

-f

Vi + n Visin ω;t + x sin ωit 十 y cos ωit

CÞ y

2No

CÞX

2No

(Vi + x) sin ω;t + Y cos ωit Area= y2 Area= x2

For x < < V; and y < <阱， the phasor diagram in Fig. 6-6 shows that

(6-20) Vi + n = (Vi + x) sin (ω;f + ();)

where the random time function (); is given by f 8;/2 f 8;/2

。1; = tan-' [yI(V; + x)] = tan-' (yIVJ = ylV; Power spectral densities of noise components

and x and y are random time functions. Since nx and ny are orthogonal

FIGURE 6-5

for y << V; . This together with Eq. (6-19) gives

P =尹IV? = Ncß川2可一一2: ，..，于n-nx+2nλny + ny

2 ._ 2 nx~ + ny

(6-21)

「/".Jl 吋←x→l

。';~y/的

(6-16)

But since the phase referenc~was arbitrary that established the sin and cos functions in Eq. (6-15) , it must be 伽 P =之 Then from Eq. (6-16)

ny

V;

Noise-induced phase

V;

FIGURE 6-6

」

(6-17)

Since the spectral densities of nx and ny have the same bandwidth B; as n , it follows from Eq. (6-17) that the power spectral density of nx and ny is Nj2 (seeφ盯 andφny in Fig. 6-5). We will see that 阱， comprising half the noise power, induces amplitude modulation

P= 可 = n2/2 = Ncßρ

116 Noise Chap. 6

The spectral density φ9i(f) for Oi is shown in Fig. 6-7 , where 0 0 representsφ9i(0). The area under the curve is

O? = 0ßρ (6-22)

which , together with Eq. (6-21) , gives the phase spectral density at low frequencies:

。o 2 NJV? (6-23)

By comparingφn in Fig. 6-5 with φ9i in Fig. 6-7 , it can be seen that

恥的 = (2IV?)風(f + f); f 三 O (6-24)

Sometimes the noise is specified in terms of its spectral density Nm as in Eq. (6-23). Sometimes the relative noise power is specified as a signal-to-noise ratio at the PLL input:

SNRi 三 Vi三In2 = γ/2Nßi (6-25)

where the signal power is v? , and the noise power is n2. Then 企om Eqs. (6-23) and

(6-25) , the phase spectral density is

。o lJBiSNRi (6-26)

See Blanchard [3] for a more rigorous development of the results in this section.

6 -4 OUTPUT PHASE NOISE DUE TO INPUT NOISE

Part of the noise-induced Oi passes through the PLL to produce phase noise 00 at the output. In Chapter 3 we saw that a PLL acts as a phase low-pass filter. The transfer function of a second-order PLL with an active loop filter is

θ O

院=H(s) =

Ks + Kω2 S2 + Ks + K，ω2

As in Eq. (6-9) , the noise bandwidth BL is given by

BL 三 jo iH(j2qf)|24

BL = (K + ω2)/4

(3-13)

(6-27)

From now on , the symbol BL will be used only for the PLL noise bandwidth as defined in Eq. (6-27). For ω2 → 0， Eq. (3-13) has the form of Eq. (6-6) with K = ω3dB' and Eq. (6-27) reduces ωEq. 的-10) with BL = (1TJ2抗拙， where f3dB κ121T. Note that Eq.

? Sec. 6-4 Output Phase Noise Due to Input Noise 117

<ÞØi

。。0 o = 2No/Vf

A間=存

8;/2 f FIGURE 6-7 SpectraI density of noise induced phase

(6-27) has the dimensions Hz on the left and rad/sec on the right; the factor of 21T is included already. For the pu中ose of phase noise cakulations, the frequency r，的ponse IHI of the PLL can be modeled as in Fig. 6-8a; it has unity gain up to f = B L and zero gain beyond that. Then as in Eq. (6-4) , the spectral density of the output phase 0

0 is given by

φθο=φθilH(j2τif )1 2 (6-28)

These spectral densities are shown in Figs. 6-8b and 6-8c for the case BL < B/2 , which is usually true in practice. The mean-square of 0

0 is the area under φ。O.

存 00 BL 2BLNJV? (6-29)

or in terms of the signal-to-noise ratio

正主 = BdBiSNR (6-30)

It is also of interest to know how much of the phase noise Oi appears as phase error Oe at the phase detector. For example, Eq. (4-46) shows the effect on .((d of noise-induced 0 e. The transfer function from Oi to 0 e is

Oe 島

From Eqs. (6-3) and (6-4) ,

三 HeCs) = 2

S

S2 + Ks + K，ω2

Oe2 = C φ9i(f) IHe(2τifì)12 df

=@of|吼叫1 2 df

=@ord2[1(1-lRiw

(3-28)

r

119 Output Phase Noise Due to Input Noise

fJ rb

rfu

lyrb 勻，句e

、'，J

叫阿戶叫

|于H

l-Jaaz‘、

-I

Zit B00) PJcfh O

>

@戲一

Z2 D戶口叭

叭叭

一一~~ (6-31)

for BL < B;f2. (The second term is the “ missing area" betweenf = 0 andf = BL 一 ω212

in Fig. 6一個.) Evaluating the integral in Eq. (6引) for He given in Eq. (3-28) , we find

fo(1-1坑。可 )12)df = (K 一 ω2)/4f BL (6-32)

Therefore

(a)

A閥=()~(r2 /Hz) 'ÞOi

(6-33) 正主 00[B;f2 一 (K 一 ω2)/4]@ o

Using Eq. (6-27) , this can be put in terms of BL :

0/ 00[B;f2 一 (BL ω212)]

三 (2 NjVi力 [B;f2 一 (BL ω2/2)]

f B/2

(6-34) (b)

On this basis , a “ noise low-frequency cutoff" for He can be thought of as (K 一 ω2)/40r

BL 一 ω2/2，的 indicated in Fig. 6-8d. Note that while it is true that Oe Oi 一見，一方一一室一2:

acωrding to Eqs. (6-22) , (6-29) , and (6-34) , it is not true in general that Oe 一 = 0/ - 00". However, it is approximately true as ω2 becomes much less than K.

A間=()~

'ÞOO= IHI2墊。，

f BL

EXAMPLE 6-1

Given:fo = 10 MHz , the Q of the input bandpass filter is 20 , SNR i = 10 at the PLL input , K = 400 krad/s ， ω2 = 100 krad/s , and the PD has a sinusoidal characteristic. Find 0 00 rms' and Oe rms. Find the effect of Oe rms on the gain Kd of the PD.

The 3dB-bandwidth of the input filter isfjQ = 500 kHz. From Eq. (6-13) , the noise bandwidth is Bi = (τ厄瓜dB = 785 kHz. From Eq. (6-27) , the noise bandwidth of the PLL is BL = (114)(400 + 100) krad/s = 125 kHz. From Eq. (()-~豆)， the spectral density is 0 0 = 1IB ;SNR; = 1.27 x 1。一 7 rad2/Hz. From Eq. (6-22) , O? = 0fi/2 =

0.05 rad2, and Oi rms = JO.05 = 生22生旦Q. From Eq. (6-29) , 002 = 0fiL = 0.016 rad2,

and 00 rms = )0.016 三位益型 From Eq. (6-34) , 0/ = 00個ρ BL + 些/2)= 0.040rad2, and Oerms = 、 0.04ο= 生2旦1旦Q. From Eq. (4A6) , K.i = Kd exp( - Oe勾2)

0.98 Kd' only a 2% reduction.

Sec. 6-4

(model for noise analysis)

BL=(K+ω2)/4

暈。。

@。

Phase noise in a PLL FIGURE 6-8

f

Area= lI~

B/2

IHI

(c)

(d)

BL -ω'2/2

善。e

@。

/

120 Noise Chap. 6

6-5 VCO PHASE NOISE

+

ví

Noise within an oscillator causes phase noise ()n at its output: V 0 = Vo sin(21Tfo + ()n). In the next section we willlook at how ()n contributes to ()o when the oscillator is in a PLL. First we wi11 characterize the spectral density of ()n when the oscillator is not in a PLL.

A model of a resonant oscillator is shown in Fig. 6-9a. This is the same model used in Fig. 5-16a to analyze injection in an oscillator. Here a noise vo1tage n(t) rather than V[

is added to the oscillatio!!-yo1tage Vl . The amplitude of Vl is 吭， and the oscillation frequency is fo l!21TJLC. The n(t) is thermal noise , shot noise, and flicker noise generated within the osci11ator and represented here as all originating at the amplifier input. The thermal and shot noise contribute a flat spectral density

φn(fo + 后n) No; ι > fa

v; ________. ~

d呵 I n J...---φ/

(6-35a)

gm阱， v,

(a)

'Þn

No 父二fm=f-fo

ι

(c)

FIGURE 6-9

'ÞOn

@。

再n

2比一;-;rV~

fa

Phase noise ()n in an osciIlator

(b)

。ofaf~/f:"

8of~/f已

fo/2Q

fb 心(d)

γ

Sec. 6-5 VCO Phase Noise 121

where

'".~f - fo

is called the l.J.伊etfrequency fromfo' At frequencies nearfo (Smallfm) , the flicker noise dominates with a spectral density proportional to l !fm:

φn (fo + ι) = NoÜι; ι <fa (6-35b)

The spectral density φn is shown as a function of the offset frequency fm in Fig. 6-9c for fm > O. (The portion of φn forι< 0, not shown , is symmetrical aboutfo-) The frequency fa below which flicker noise dominates cannot be ca1culated; it must be measured. The value offa depends on the construction, materials , and environment of the oscillator, but it is typically around 10-5 x f o-

The addition of n(t) in Fig. 6-9a is represented as a phasor sum V; = Vl + n in Fig. 6-9b. As in the phasor diagram in Fig. 5-16b, the effect is that n produces a phase diftì巴renceφbetween V 1 and v;. But since n is a noise phasor, we need the analysis in section 6-3 to find the relationship between n and φ. By a development similar to that of φOi in Eq. (6-24) ,

φφ(fm) = (21V1 2) φ'n(fo + fm)

where φφis the spectral density of φ， and V1 is the amplitude of the oscillation voltage Vl = V同n 211似. Then with Eq. (6-35) ,

where

φφ 00 fa!fm;

φφ=@。;

。。三 2NjV?

ι <fa

Zη > fa

(6-36a)

(6-36b)

(6-37)

Because the phaseφis a baseband effect, fm is no longer offset frequency but the entire frequency for which the spectral density φφis defined. At this point, convention supports either f or fm for notation; we will retain the fm through this section.

The bandwidth of the oscillator tank is f,jQ, where the Q of the tank is discussed in section 5-5. Let the half-bandwidth be represented by fh:

fb = f,j2Q (6-38)

Spectral components of n(t) that fall within the tank's bandwidth (ι < fb) cause frequency modulation of the oscillator as V[ did in the case of i吋ection. Let the frequency deviation Llω。 due to n(t) be represented by ωn' Then Eq. (5-26) for i吋ection becomes

φ = tan- 1(2Qωnl2甘rfo) = 2Qωn/2τrfo = ωn/2τrfb

ωn (2τrfb)φ

零

123

shown in Fig. 6-10. The full expression for th巴 phase spectral density of an oscillator not in a PLL is

VCO Phase Noise Sec. 6-5 Chap. 6

for φ< < 1. (The unperturbed oscillator frequency ω00 is represented by 2πιin the analysis here.) Then the corresponding spectral densitiesφ"，n andφ中 are related by

Noise 122

(1η + fa)(fm 2 + fb 2) f/

正，，3 (ι2 + f/) fm <fb φ的n (2τrfb)2φφ;

(6-42) φIIn(fm) = 0。

where 0 0 2No1VJ2, andfb = fo/2Q.

Then with Eq. (6-36)

(6-39a) ι <fa φ的n 0 0 (2吼)2fa!fm;

φωn 0oC2τTfbf;

EXAMPLE 6-2

A 50-MHz oscillator has a tank with a Q of 25. The signal amplitude at the tank is V J

1 Y, and noise with spec仕al density No = 5 X 10- 14 y 2/Hz adds intemally to this signal. Below the freq由此y fa = 3 kHz , flicker noise dominates. The output of the oscillator is filtered by a bandpass filter with half-bandwidthfc = 10 MHz. Find the spectral density of the oscillator phase noise.

From Eq. (6-37) , the spectral density forfb <ι<兵的 00 = 10- 13 rad2/Hz , where Eq. (6-38) givesfb = 1.0 MHz. Therefore , the spectral density <Þlln( ωis that shown in Fig. 6-10.

V1 =1V

No =5x 1O- 14V2/Hz

fo=切 MHz

Q=25

(rad2/Hz) <l>on

1。一6

10-7 (6-41a) 此<品φIIn(fm) = 0。

(6-39b)

Since the phase modulation (J1l is the integral of the frequency modulationωm then (Jn(S) = (1 /s) ωn(S) and

Therefore

(6-40a)

For fm > fb' the feedback in the oscillator is effectively broken , and (Jn φ.

Therefore

fa < ι <fb

ι <fb

。'n(j2τrfm) = (lIj2τι)ωn( j2τrfm)

φIIn = (1/2πι)2φωm

/

(6-40b) fb <fm

后n3 ，

φIIn φφ=0。;

Nofaf02

2VI2Q2

Then from Eqs. (6-37) through (6-40) ,

fafb2

ι3

0 0 一卜一一

ι fb

10-8

一勻，h

l-rh Nof02

2VI2Q2

勻，--弓

A-rh

φIIn(fm) = 0。10-9

(6-41b) fa < ι <fb

且V

(109 scale)

fm (Hz)

Example of osciIIator phase noise spectraI density

10M 1 M 100 k 10 k

FIGURE 6-10

3k 1 k

10- 10

10- 1'3

10- 11

10- 12

(6-41c)

This piecewise approximation to the phase spectral density is shown in Fig. 6-9d. Leeson [4] has confirmed experimentally the phase noise model expressed by Eq. (6-41).

In communication applications , it is desirable to keep the phase noise (Jn as small as possible. Equation (6-41) shows that (Jn is minimized by maximizing Q , the oscillation amplitu缸片， and the noise figure of the active components. Rohde [5] and Manassewitsch [6] give more detailed suggestions for the reduction of oscillator phase noise.

The flat portion of φIIn does not extend forever; otherwise the phase noise would have an infinite mean-square. In practice, the curve breaks at some cutoff frequency fc' 的

fb < ι φIIn(fm) 0 0

γ

--

(dBm/Hz) <Þvo

一 20

一 40

Vo = Vo sin (271"1戶t+ θn)

的/2=10 dBm -60

-80

一 1∞

一 120(linear scale)

f ι (a)

。

<Þvo ! (dBc/Hz) ~/2

一 30

Chap.6

Since it is impractical to fully characterize the noise source n(t) ， φ8n must be determined by measurement. There are several techniques for making this measurement. [7 , 8] A simple method is to use a spectrum analyzer to measure the spectral density φvo

of the oscillator output Vo . [9] The oscillator output is

Noise 124

(6-43)

Just as Eq. (6-24) gives φ8i for 8i in Eq. (6-20) , in a similar manner φ8n for {}n in Eq. (6-43) is given by

VO = VO sin(27Tlot + (}n)

/'

一切

-70

一ω

110

-130

(6-44)

where 10 is the oscillation frequency (or “ carrier") andιis the offset frequency:ι=

1-10' The dimension of φ叩 is y2/Hz, but a spectrum analyzer reads φvo的 in dBrnlHz , as

shown in Fig. 6-11a. The two dimensions are related by

‘民n 三三 O φ8n( 五n) = (2!V02) φvo(/o + 1m);

y2/Hz

50 a x 1 mW (6-45)

The spectrum is converted to dBc/Hz (dB relative to the carrier per Hz) by dividing the spectral density in y2/Hz by the “ carrier" power V0

2J2, as shown in Fig. 6-11b. This is part of the conversion from φvo toφ8n indicated by Eq. (6-44). The carrier power is usually expressed in dBm by

10 log dBrnlHz =

(linear scale)

f fo 。V/J2

50 a x 1 mW (b)

(rad2/Hz) <ÞOn

(6-46)

For example , VO

= 1 Y corresponds to 10 dBm. Then from Eqs. (6-45) and (6-46) , we have the dimension

10 log dBm (ca虹ier)

10-3

d>ν'n(fn + fm ) <ÞRn(fm ) = 一丘斗一 'm'叫川 ~/2

f=ι +fm

10-5

10-7

dBc/Hz = dBrnlHz - dBm (ca叮ier)

y2/Hz

V0

2J2 10-9

10-11

(6-47) 10 log

10- 13 When the spectrum is translated down to baseband，的 indicated by the conversion in Eq. (6-44) , the dimension in Eq. (6-47) has the interpretation (linear scale)

再n

(c)

Phase spectral density from voltage spectral density FIGURE 6-11

。(6-48)

For example, -30dBc/Hz corresponds to 10- 3 rad2/Hz. This translated spectrum is shown asφ8n in Fig. 6-11c. Note that this plot is with a linear frequency axis , as most spectrum analyzers provide. Wh巴n converted to a log frequ巳ncy axis , the plot of φ8n appears as in Fig. 6-10.

10 log rad2/Hz dBc/Hz

/

126 Noise Chap. 6

The characterization here of oscillator phase noise was for the case of an oscillator (or a VCO with Vc grounded) not in a PLL. We will see that a PLL can improve the phase noise of a VCO by locking it to a frequency source with less phase noise , such as a crystal oscillator.

6-6 OUTPUT PHASE NOISE DUE TO VCO NOISE

In Chapter 5 we ignored phase noise , and the VCO phase was determined by the control voltage: (}o = vc(K)s) (see Fig. 2-4). In the previous section we assumed Vc = 0, and the VCO phase was entirely the phase noise {}n. When the VCO is in a PLL, both Vc and (}n

influence the VCO , and the VCO phase is

。o vc(Ko/s) + {}n (6-49)

This is represented by the signal flow graph in Fig. 6-12a. Here the input phase {}i is assumed to be zero so we can see the effect of {}n alone. Within the PLL bandwidth , {}n is mostly canceled by the first term in Eq. (6-49) 的 the PLL tries to lock {}o to (}i'

From control theory , Fig. 6-12 leads to the transfer function

。o/{}n = 11[1 + G(s)]

But this is His). Then from Eq. (3-28) ,

。O

o n

= His) = 2

S

S2 + Ks + K，ω2

From Eq. (6-4) , the spectral density of the output phase is

φøo(f) = φØn的 IHeU21TfW

where from Eq. (6-51)

(2τrf )4

(2τrf)4 + (K2 - 2K，ω2)(2τrf)2 + K2ω22 IHe(j2τrf)12 =

G'(s7 凡r--\ (J. I 札，-\0。

令=0 一---<+卜一叫心卜~月s) 卜一-1 Ko/s 卜--f+卜寸-

。o-IL-

__________________________________________________ ~

FIGURE 6-12

仇 1--一一一一 =H.(s)

。 1+G(s)

Transfer function from On to 00

(6-50)

(6-51)

(6-52)

(6-53)

于Sec. 6-6 Output Phase Noise Due to VCO Noise 127

(We retum to the simpler symbolfhere 叫her than fm') The mean叫uare phase noise 存is the area under the curve given by Eq. (6-52):

。 2o {φ叫4 (6-54)

Substituting Eqs. (6-42) , (6-44) , (6-52) , and (6-53) into this equation and evaluating the integral yields

e;; = <Þ9n(K/21T) [ 子

where

+ fa

Y

y=Jl士忌又

?(其 - fb) 8。 (6-55)

This approximation holds for fa < KI21T <敢4 andfb 三 fc. For the caseω2 = K/4 , Eq. (6-55) becomes

互主 z φ叫 ω2 = K/4 (6-56)

For the case ω2 << K/4 , Eq. (6-55) can be approximated by

(}o空白 φ以K/2τ)[K/4 + fa Cn(K/W2)] + (τ12)(五 - fb) 80

; ω2<< K/4 (6-57)

Note that for fa < <訓，正主 is not a function of ω2

EXAMPLE 6-3

The phase noise spectra1 density of a VCO is that shown in Fig. 6-10. A bandpass fi1ter with a lO-MHz half-bandwidth reduces the phase noise above f = 10 MHz (seeφ9n m Fig. 6-13). The PLL has K = 21T(100 kHz) and ω2 2τ(10 kHz). Find (}o nns for the VCO in the PLL.

A Bode plot of IHl is shown in Fig. 6一13. It is unity for f > KI2τr and is proportional to f 2 between ωρ1T and KI21T. Therefore , the productφ。o φ9nlHlfollows φØn for f > 100 kHz and is flat for 10kHz < f < 100 kHz. The value where it is flat isφøn(K/21T) = 8 0 (21TfJ的2 10 一 11 rad2/Hz [see Eq. (6-41b)]. Then from Eq. (6-55) , Y = 0.775 , and

。三 =(10一 11叫2/Hz)[(τ/2)(1 00 kHz) + 30.5 kHz] + (1 0-13rad2/Hz)(如2)(9 MHz)

1.87 X 10- 6 + 1.41 x 10- 6 3.28 X 10- 6 rad2

Then the square root gives (}o nns 旦企旦1主主豆豆.

128 Noise Chap. 6

<þ .l (rad2/Hz) IH.12

10- 7 IH.12 10- 1

10-8 10-2

10-9 10-3

----- 10- 10

<Þ6n = 1凡 12，φ6n10-5

10- 11 10-6

10- 12 10-7

10- 13 10-8

1 k 3 k 10 k 1∞ k 1 M 10 M

f(Hz)

FIGURE 6-13 PLL phase noise 00 due to VCO phase voise 0"

6-7 OUTPUT PHASE NOISE DUE TO 80TH

NOISE SOURCES

Let <ÞOon be the portion of φ00 due toφ加， as analyzed in section 6-6. Let φOoi be the portion of φ00 due toφ缸， as analyzed in section 6-4. Then，的 in Eq. (6-52) ,

φOon(f) φOn( f) IHeC j2τif )12 (6司58)

and as in Eq. (6-28) ,

恥。的 =φ0;( f) IH( j2Tif )f (6-59)

Since these phase noise components are from different sources , they are independent, and the powers sum to give the spectral density at the output:

丸。(丹 =φOon(f) + φoo/f) (6-60)

Then 穹的 the area under thisωve.

Sec.6一7 Output Phase Noise Due to 80th Noise Sources 129

EXAMPLE 6-4

φOi at the input to a PLL is flat with spectral density 10- 9 rad2/Hz. The VCO phase noise spectral densityφOn falls as 1!f 2 and is 10- 9 rad2/Hz forf = 10 kHz (see Fig. 6一13).(Here we are making the simplifying assumptions fa = 0 a吋fb = fc.) AI帥， for simplicity, we assume ω2 << K so that BL = K14. Find {)o rms for (a) K = 2τ(3.2 kHz) , (b) K = 2 '1T(l O kHz) , and (c) K = 2τ(32 kHz).

The five spectra are plotted in Fig. 6-14a for the case K = 2τ(3.2 kHz). The flat portion has the value φ以KI2τ) = 10- 8 rad2/Hz. φOoi follows φOi - 10- 9 forf< KI2Ti and falls as 1!f 2 for f > KI2Ti . As can be seen from the plots ， φOoi is always a factor of 10 below φOon ﹒ Therefo白， φOoi is negligible , and φ00 φOon for this case. For fb 兵， the 時cond term in Eq. (6-55) disappωs ， and 哥 =φ以KI2τ) KI4 = 10-8 X (如2) (3.2 kHz) 5.0 X 10- 5 rad2, and {)o rms = 0.00707 radians.

For the case K = 2τ(1 0 kHz) , the spectra are as shown in Fig. 6-14b. The plots for φOon and φOoi coincide here because KI2Ti happens to be at th巳 intβrsection of φOn and φOi. The flat density of each is 10 • 9 rad

2/Hz forf < 10 kHz. The total φ。o is their sum , with a flat density of 2 X 1ωO 一 9 伽f戶< lO k闢Hz. The叩nt倪he area ur叫Irad2赴Iz吋)KI坪4 = (ρ2 X 10 一 9 rad2叮1Hz吵) 15.7 kHz = 3.14 X 1ωO 一 5 rad2, and {)札o rms 旦去旦豆6radians.

For the case K = 2τ(32 kHz) , the spectra are as shown in Fig. 6-14c. As can be seen from the plots ， φOon is always a 些ctor of 10 belowφ。i. Therefor巴， φ。= φOoi for this case. The area under the curve φ。o is {)/ = (10- 9 rad2/Hz)Kl4 = (10- 9 rad2/Hz) 50 kHz

5.0 X 10- 5 rad2, and {)rms Q.00707 radians.

Of the three cases , note that the minimum {)o rms is realized when Kl2Ti is at the intersection of φOn and φ。i. Let this value of K be represented by K':

φO，， (K'12τ) =φOi (6-61)

This value of K minimizes {)/ when φOi(f) is flat and φ0" is dominated by Eq. (6-41b) , falling as 1!f 2. Then the minimized mean-square phase noise is

否?=2φOiK'/4 φoiK'12 (6-62)

Because K affects other performance parameters , the best choice of K may not be K'. In Chapter 9 we will see that reducing K reduces spurious modulation of {)o.

Therefore , the best tradeoff is sometimes achieved by some K less than K' . In that case ， φ

Oon dominates as in Fig. 6-1徊， and

。。2z (K/4)φ(Jn(KI2τ)

(rad2/Hz)

<l>on = <l>Oon + <1>00; 、不/

dboo/ n

10-9

\ 、 <1>00;

、、、\/

K/27f

10- 111 \ 1 k 3.2k 10 k 1∞ k f(Hz)

(a)

(rad2/

10-8

/

10-9

岳。on= q,Ooi

10-11: K /27f -----.....

100 1 k 10 k 1∞ k f(Hz)

(b)

(rad2/Hz)

卡\\/恥

叫一一一一一一一一_L o;\ \ \

/ <1>00;'" <1>00 \ <l>oon \、 \

10- 10 卜 \

K/2，π/\ 、‘、、、\‘主、、\λ 、10- 11i 迪、\

100 1 k 10 k 32k 1∞ k f(Hz)

(c)

FIGURE 6-14 Phase noise both at input and in VCO

Sec. 6--8 Cycle Slips 131

Here we are assuming thatφenV) falls as 1!f 2 [see Eq. (6-41b)]. Then φen (K12τ) is proportional to lIK2 , and

EZ=G/K; K< K' (6-63)

where a is a constant. Equation (6-63) indicates that, for the conditions assumed here , increasing K reduces phase noise. But increasing K increases spurious modulation of 80

(see section 9-1-2 and section 11-4). Therefore , a tradeoff is involved.

6-8 CYCLE S LlPS

In the noise analysis so far we have assumed that the noise n was small enough compared with the signal V; that the resulting phase 8; was small-small enough that tan 8; = 8; (see Fig. 6-6). But Gaussian noise has occasional large excursions , even for small 8; rms. These can cause cycle slips (jumps of 21T) between the phases of V; and VO • The energy in these cycle slips is much greater than the amount of phase noise predicted by Eq. (6-30). This effect becomes significant at low SNR; and causes the '‘clicks" in FM demodulation.

Consider the phasors for V; and for V; + n shown in Fig. 6-15a. Since v;(t) is unmodulated , V; stays horizontal. The noise n causes V; + n to deviate from 吭， but usually not too far , as shown by the locus. Occasionally n becomes larger than V; (the length of v;) and of the opposite phase from v; so that v; + n goes around the origin (see the counterclockwise loop in Fig. 6-15a). This is a noise-induced phase change of 21T in 8; [see the plot of 8ρ) in Fig. 6-15c].

If the PLL bandwidth B L is large enough to pass all the frequency components of 阱，then v 0 will follow the phase of v; + n，的 shown by the locus in Fig. 6一15b. Unlike the magnitude of Vj + n , the magnitude of V o is constant. (The loops in the locus are separated only so they are distinct.) Figure 6-15c shows 80 = 8; for large BL . As 8; and 80

settle down around 21T, there is one cycle difference in phase v 0 and the noiseless input 竹，which never varied in phase. This is called a cycle slip.

Let BL be reduced to the point that 80 can't follow 8; as it rises rapidly toward 21T

radians. This is shown by the dashed curve of 8oCt) in Fig. 6-15c. Once the difference between 8; and 80 exceeds 甘， Vo finds it closer to approach V; + n in a clockwise direction , and 80 starts to decrease. Eventually , 8; settles down around 21T, and 80 settles down around zero; 80 has avoided a cycle slip.

The probability of a cycle slip depends on the power of n that falls within the bandwidth BL compared with the power V?12 of V;. But from Eq. (6-29) , this is proportional to 哥 The exaωn砌的 of cycle slips i昀s dif配fic此Cω叫u吭I址lt beω1閻 of t伽he咒e non叫叩nlinea唸e間ar na削aof the PLL for large noi的se. Viterbi [10] has derived an approximate expression for the mean time Ts between cycle slips for a first-order PLL:

Ts = (1T/4BL) exp(21802); ω2<< K (6-64)

Vj+n

(a)

(b)

(radians)

211" 1-一一一一一一一一一一一一一一一一一一

11"

(c)

。。(smalll在)

一{一

\//\\ ~/一

FIOURE 6-15 Cycle slip due to noise

References 冒33

We see the expected dependence on 哥 The exponential function is about inversely proportional to the probability that 00 exceeds 2 radians.

Equation (6-64) holds for highly damped cases with ω2 much less than K. Experimental data by Ascheid and Meyr [11] show that for the critically damped case ,

Ts = (τ/5.6BL) exp( 1. 66/荐); ω2 = K/4 (6-65)

Almost all applications fall between these two situations. Therefore , Eqs. (6-64) and (6月65) effectively serve as upper and lower bounds on 丸. See Blanchard [12] for a mathematical treatment of cyc1e slips.

EXAMPLE 6-5

A PLL has a noise band"，恤h BL = 125 krad/s andω2 = K/4. For 00

2 = 0.016 rad2 (see Example 6-1) , find the mean time between cyc1e slips.

Equation (6-65) 重，!es Ts = 5.1 X 1039 sec = 1.6 x 1032 yr. If the output phas巴noise is increased to 0/ 0.09 rad2, then Ts 7.6 minutes. If the damping were increased so thatω2 <<K, then from Eq. (6-64) , the 7.6 minutes would be increased to 7.8 hours.

This example indicates that cyc1e slips are generally negligible for 002 三 0.09 rad2, or

。o rms 三 0.3 rad (6-66)

REFERENCES

[1] W. B. Davenport and W. L. Root , Random Signals and Noise , McGraw-Hill: New York ,

1958 日] A. Papoulis , Probability , Random Variables , and Stochastic Processes , McGraw-Hill: New

York , 1965 [3] A. Blanchard, Phase-Locked Loops: Application to Coherent Receiver Design , Wiley: New

York, 1976, Chapter 7 [4] D. B. Leeson,“A Simple Model of Feedback Oscillator Noise Spectrum," Proc. IEEE ,

February 1966, pp. 329-330. [5] U. L. Rohde , Digital PLL Frequency Synthesize月， Prentice-Hall: Englewood Cliffs , NJ ,

1983, s巴ction 4-1-2. [6] V. Manassewitsch , Frequency Synthesize口， Wi1eY: New York , 1987 , section 2-2.

γ fw

CHAPTER

7 Chap. 6

[7] Manassewitsch , Frequency Synthesizers.

[8] Rohde , Digi的1 PLL Frequency Synthesize悶， section 2-8

[9] Hewlett Packard Associates,“Phase Noise Characterization of Microwave OsciIIators , " Product Note 1J729C-2 Palo Alto , Calif. , September, 1985.

[10] A. J. Viterbi , Princ伊les of Coherent Communications , McGraw-HiII: New York , 1966, Chapter 4.

[11] G. Ascheid ar州 M取“Cyc1e SIips in Phas巴 L叫ed Lo恥 AT肌凶 Survey ，" IEEE 1'rans. on Com. , VoI. COM-30 , No. 10 (October 1982) , pp. 2228-41 , Fig. 18.

[12] Blanchard , Phase-Locked Loops , Chapter 12.

Noise 134

LOCK MAINTAINING

/

Our analysis of phase-locked loops in Chapters 2 and 3 used linear models of the PD and the VCO. If the input frequency deviation is too large , those models no longer hold. When the PD reaches the limit of the voltage it can put out or the VCO reaches the limit of the frequency it can generate , the PLL loses lock. In this chapter, we look at limitations on input frequency so the PLL will maintain lock.

HOLD-IN RANGE

Consider a PLL that is in lock (ω。 =ωi) ， and let the input frequency ωi be changed very slowly. The range of frequencies over which the PLL can stay in lock is the hold-in range.

This is essentially the range of frequencies the VCO can reach given the limitations of its VCO characteristic and the limitations on its control voltage 抖. This rather simple concept of hold-in range is best illustrated by an example rather than by developing general forrnulas.

7-1

137 Input Frequency Deviation ßω， Sec. 7-2

。e

Vd

γjilli!

Chap. 7 Maintaining Lock 136

EXAMPLE 7-1

A PLL has a PD with the characteristic shown in Fig. 7-1a, a VCO with the characteristic shown in Fig. 7-1b, and one ofthe loop filters shown in Fig. 7-1c , d, ore. (Note thatKh

= 0 .4 for each of the loop filters.) Find the hold-in range of the PLL with each of the loop fi1ters.

The hold-in range can't exceed the range from 7 MradJs to 23 Mrad/s since the VCO characteristic doesn 't extend beyond this range. Any further restriction of the range is due to restriction of V c. The maximum steady-state control voltage is

(a)

Vc

Vc

(Mrad/s)

9

(b)

5 2

Wo

23

15

9 7

(7-1)

where F(O) is the dc gain of the loop filter and Vdm is the maximum V d the PD can put out. By the symmetry of the PD characteristic in this example, Vc min - Vc max'

For the voltage divider “ loop filter" in Fig. 7-1c, F(O) = 0 .4. Since Vdm = 5 V, Eq. (7-1) gives Vc max = 2 V. From the VCO characteristic in Fig. 7-1b , the corresponding upper limit of the hold-in range isωo max 旦旦旦坐. The minimum V c is - 2 V , which exceeds the lower end of the VCO characteristic. Therefore, the lower limit of the hold-in range is ωo min 主主f且也E﹒

ForthepassiveloopfilterinFig. 7-1d , F(0) = 1.0. ThenEq. (7-1) gives Vcmax = 5 V. From the VCO.characteristic , the corresponding upper limit of the hold-in range is

15 MradJs. The minimum V ß is - 5 V. which exceed the lower end ofthe VCO =~==='-'. ... &&- .................................................... • c .... ....

characteristic. Therefore , the lower limit ofihe hold-in range is still ωo min 1盟且必.Forthe active loop filter in Fig. 7-1巴， F(O) = ∞. Then V c is unlimited , or in practice as

high a vo1tage as the op amp can provide. We wi1l assume thatthis is greaterthan 9 V , and the upper limit of the hold-in range is 23旦旦坐. As before , the lower limit is I盟且也s.

Vc max F(O) Vdm

Vc Vd Vc Vd

Vd

U 7-2 INPUT FREQUENCY DEVlATION å叫

(e)

derivative of the argument ω;f + ei • Let this complete input frequency be represented by ωi + Llω; ， where Llω; ， is the frequency deviation. Then

(7-2)

ω; + Llω; == d/dt (ω;t + ei) =ω; + de/dt

Example of hold-in range

Aωz 三 d(J;ldt

FIGURE 7-1

F(O) =0.4

(c) When the input frequency changes rapidly, the PLL may lose lock before the limits ofthe hold-in range. This is because IF( jω) I 三 F (0) which , together with Eq. (7- 1), says Vc is more restricted for high modulatibn frequencyω. The physical reason is that the capacitor in the loop fi1ter doesn't have time to charge in following rapid changes. The rest of this chapter will find limits on input frequency deviation so the PLL will be able to maintain lock.

We need to define input frequency deviation. In Chapter 2 ， ω; was defined as a constant in the expression for the input signal: V; = sin(ω;t + e;) , where (}; is a function of time. Therefore, any deviation of the input frequency must come through e;. For zeromean 斜， ωis the average input frequency , but the complete frequency is the time

可

。e

Vd

Multiplier PD

Chap.7

In fact , phase modulation and frequency modulation are indistinguishab1e. Deviations that are 1arge enough to cause 10ss of 10ck are usually thought of as Âωi rather than (}i'

Therefore , we will find 1imits on Âωi so the 10ck is maintained. If desired, corresponding limits on (}i can be found through Eq. (7-2). Before 100king at a more exact derivation of these 1imits, we will first establish some physica1 insight as to what allows the PLL to handle a frequency step without losing 10ck.

Maintaining Lock 138

。e

Vd

7-3 LOCK-IN FREQUENCY W L

In this chapter, we assume the 100p filter is active , which provides the best performance in maintaining lock. The PLL circuit in Fig. 7-2 uses a simp1e version of such a 100p filter (see Fig. 3-5 for other versions). The PD in Fig. 7-2 is modeled by one of the characteristics in Fig. 7-3. Usually a PLL 10ses lock when (}e exceeds the PD rangewhen the PD is asked to provide more vo1tage than Vdm • Figure 7-3 shows the phase error (}em that corresponds to V d = Vdm for a number of phase detectors. The VCO is mode1ed as in Chapter 2 by

(7-3) ω。 Ko (vc - V co) + ωi

。e

Vd Note that the control voltage Vc is made up of the voltage across R2 plus the voltage across the capacitor in the 100p filter:

/

Vc = V2 十 V3 (7-4)

Consider the case of a constant input frequency ωi' In steady state (after 個y acquisition transients have died out) ， ω。 =ωi' From Eq. (7-3) , this requires Vc Vco . This is provided by the capacitor in the 100p filter having been charged to V3 Vco during the acquisition. Then from Eq. (7-4) , V2 can be zero. But

。e

Vdm

九/

Vd

3-State PD __-J J J J JJ

--三二二J

(7-5) V2 = (R2/R 1) Vd = Kh Vd

-地+ -V3+

1~Q

Maximum phase error for maintaining lock while tracking FIGURE 7-3

Vo

Example of second-order PLL circuit FIGURE 7-2

的

141

(7-6)

If àωis not too large , then Vd doesn't try to exceed the V dm that the PD can provide, and the PLL stays in lock. The maximum àωfor which this holds is called the lock戶equency

Lock-In Frequency WL

Vd = V2/Kh àω/KJ(h

Sec. 7-3

and from Eq. (7-5) ,

r ?!這

Chap.7

Therefore , Vd is also zero , and from the PD characteristics in Fig. 7-3 , ()e O. (This assumes the PD offset voltage Vdo is zero.)

Consider now a step change of height àωfor the input frequency deviation àω;， as shown in Figure 7-4a. Then ifω。 is to maintain lock , the VCO frequency ω。 must follow with a step àωo ofheight àωas in Fig. 7一4b. This is achieved by a step àvc in the control voItage:


包)L:

(7-7)

(In Chapter 8 we will see 也isω'L has another interpretation in terms of acquisition behavior.)

For a piecewise-linear PD characteristic, ()e ViKd. Then from Eq. (7咱6) ，

Vdm ωdKJ(h

K J(hVdm 。)L

àvc àω。/Ko àω/Ko

Which component of Vc in Eq. (7-4) provides this àvc? Since V3 can't change instantly , it plays no part in the early part of the step. To simplify the study in this section, we will assume that C is very large (ω2<< 的叩門 is essentially a constant for the duration of the analysis. Then 巧， which was zero , becomes

V2 àvc àω/Ko

()e = àw/KJ(hKd = àω/K

四lÏs r，的ponse is plotted in Fig. 7-4c. Let ()em be the maximum ()e for which the characteristic is sti1l linear. Figure 7-3 shows that

Aωi

XOR PD ()em τ/2 radians , Aω

2-State PD ()em τradians;

(7-8)

For a piecewise-linear PD characteristic, there is a simple relationship between the Vdm in Eq. (7-7) and ()em:

(7-9)

3-State PD

Then Eq. (7-7) can be represented in the simpler form

()em 2τradians;

V dm Kßem

/'t

(a)

.ð.wo

Aω

(7-10)

where K is the PLL bandwidth. For a multiplier PD with a sinusoidal characteristic , V dm = Kd' as shown in section

4一l. Then from Eq. (7-7) ， ω'L = K J(hKd = K. This case can be inc1uded in Eq. (7-10) if we use

ωL K J(hKd()em K()em

(b)

(assumes 均 constant)

1 radian; Multiplier PD

()e will actually go to '1T/2 radians before losing lock, but using the value ()帥 1 radian will give the correct re叫“ for a linear analysis. (The dashed line in Fig. 7-3a is the linear

()em

FIGURE 7-4 Simplified responses to a step change in input frequency (c)

。e

Aω/K

司43Handling a Frequency Stop

Then the transfer function from âωi to (}e is given by

Sec.7-5 Chap. 7

model for the sinusoidal characteristic.) Then for the various PD characteristics , Eqs. (7-8) and (7-10) give


S 一

CU R --s (}eCs)

Aωi(S) (7-12)

S2 + Ks + K，ω2 Multiplier PD ωL = K;

XORPD ωL = τr/2)K; For ω2 < < K , the transfer function in Eq. (7-12) can be approximated by

(}eCs)

Aωi(S)

2-State PD ω'L τrK;

(7-13)

with a corresponding frequency response plotted in Fig. 7-6. The response has high- and low-frequency cutoffs atω2 and at K and a “ midband gain" of 1IK.

7-5 HANDLlNG A FREQUENCY STEP

S

(s 十 ω2)。十的3-State PD

The PLL will maintain lock for a step change âωif âω<ωL﹒

The analysis here was greatly simplified. It assumed the phase error {}e could change instantly to provide the needed voltage for the VCO to follow âωi' In fact, though, {}e is the integral of the frequency error (which equals âωimmediately after the step) , and it takes {}e a short time to get to its new value. We also assumed V3 across the capacitor was constant. Actually V3 changes slowly, gradually taking over the voltage that V2 had to provide initially. These details are treated more formally in section 7-5.

ω'L 2τK;

Suppose the change âωi in the input frequency is a step of height âω ， as shown in Fig. 7-7a. This is essentially what happens when a user changes the frequency of a frequency synthesizer, for instance. Since {}e1âω2 月 11K for the band of frequencies from ω2 to K,

U

、山

、恥

、趴

A A

A A

A A

、心44

ll

心

川崎

b、

11

、、.、、

/J\\\\? \

\ \

\ \

\ \

\ \

18e/ Ll的1 = 1 (I /s)He(s) 1

7-4 TRANSFER FUNCTION FROM åω，;TO θe

We will find the peak {}e for different waveforms of âωi and then establish bounds on Aωi so that {}e < {}em-so that the PLL maintains lock. The waveforms of âωi examined in the following sections are a step, a ramp , a sinusoid, and a random signa1.

An ac model for a PLL is shown in Fig. 7-5. In particul缸， the PD is modeled by the gain Kd' although this holds only near {}e = 0 for a multiplier PD. From Eq. (7-2) , {}i is the integral of âωi' Therefore , {}i is shown in Fig. 7-5 as (l /s)âωi ， where 1Is represents integration , and âωi represents the change in the input frequency. For an active loop filter , we determined in section 3-8 that the transfer function from {}i to (}e is I/K

(7-11) 2

S 三 He(s) =

(}eCs)

。';(s)

Frequency response of O/f!J.ωi transfer function FIGURE 7-6

S2 + Ks + Kω2

FIGURE 7-5

A

Transfer function from 叫 to Oe-a linear model

144

Aω，

.:lw

0 •

.:lw/K

0.

O.74 .:lω/K

--1 f.- I/K

一-Tl

f.-

斗三|←

FIGURE 7一7

q哥「、~士

、、、、\

1/ω2

、、

(a)

、、、、、、

、、、

(b)

(c)

Maintaining Lock

ω2=K!25

、\

、、、、\‘、、、

、、、

叫

\

Response to a frequency step

Chap.7

then Oe is approximately a step of height LlωIK. The high-frequency cutoff at K causes a finite rise time, and the low-frequency cutoff atω2 causes sag in the Oe waveform, as shown in Fig. 7-7b. Using Laplace transforms together with Eq. (7-13) , we can solve for the transient

O/t) = (Llω/的 (ε一岫2t _ e- Kt); ω2 < KI4 (7-14)

For ω2 < < K , the Oe waveform reaches a peak vaIue of almost LlωIK. (For ω2 = KI25 , the peak value is 0.87 LlωIK.) The highest design value of ω2 in practice is ω2 = K14. In that case, Eq. (7-12) gives OjLlWl sl(s + KI2)2 , and Laplace transforms give

O/t) = Llωt E KU2; ω2 = KI4

?

Sec. 7-6 Handling a Frequency Ramp 145

which has a peak value of 0.74 LlωIK (see Fig. 7一7c). In any case ,

Oe(t) < LlωIK

holds for aIl ω2' In order to maintain lock, we need to ensure that Oe(t) < Oem for aII t. This wiII be satisfied for aIl ω2 if

AωIK < Oem (7-15)

This bound for a frequency step relies on a parameter within the PLL design-Oem of the PD characteristic. By contrast ， ω'L is a parameter that can be measured extemaIIy to the PLL. Therefore , it is often useful to use Oem = ω'LI K from Eq. (7-10) to present the bound for a fr叫uency step in the form

Aω<ωL (7-16)

This is , in fact , our definition of ω'L from the previous section , but now it has been established on a more formal basis.

The bound in Eqs. (7-15) and (7-16) assumes that the PLL has an active fiIter and that the initial phase error is Oe = O. If there is a static phase error Oem or if the PLL had not reached steady-state before the 取p change in Ll峙， then the bound may not be adequate to ensure lock is maintained. Suppose ω2 = KI25 and a second step occurs at a time 251K after the first step，的 in Fig. 7-8a. Then from Eq. (7-14) , Oe = 0.37 LlωIK at the time of the second 晦p ， and the peak vaIue of Oe due to the second step wiII be about Oe max = (0.37 + 0.87)LlωIK = 1.24 LlωIK (see Fig. 7-8b). Then to satisfy Oe (t) < Oem = ωL疵, we would need to restrict 1.24 Ll ω < 凹 , or Ll ω <0.8 ωL . T祖h血is i必sa刊tig剖偵ht伽e叮rb加ounthan Eq. (7-16)

7-6 HANDLING A FREQUENCY RAMP

The input frequency change Llωi is said to be a ramp if its time derivative is a constant AO(see Figure 7-9a).Since a ramp primarily consists of lower frequenc-longer characterize the transfer function Oel Llωi = (l!s) He by its midband gain l!K sho in Fig.7-9b.(For convenience, Fig.7-9b is drawn for the case k<1.)

For low frequencies , Eq. (7-12) reduces to the approximation

O;ILlω slK，ω2; for ω<ω2 (7-17)

The frequency response of this approximate transfer function is plotted in Fig. 7-9c. This -s just a differentiatOLwhich is basically due to having the loop filter (an integrator)in the feedback path.The corresponding phase responseo;is shown in Fig.7-9d.It is a constant of height Llw I K，ω2'

F

146 Maintaining Lock Chap. 7

Aω，

2Àw

Aω

k 25/K ~

(a)

。e

1.24 LÌω/K

0.87 LÌω/K 凶'2=K/25

0.37 LÌω/K

25/K

(b)

FIGURE 7-8 Response to multiple steps

We can get a better approximation to the transfer function by including the second term in the denominator of Eq. (7-12);

S

Ks + Kω2 。I;/ÂωS

Kω2 s/ω2 + 1 (7-18)

The frequency response now includes the break atω2 ， as shown in Fig. 7-ge. The effect of the break is to low-pass the response 0; to give the better approximation

。1; (Âw /K，ω2) (1 - e 一ω2t )

which is graphed in Fig. 7-9f. Note that the response stil1 doesn't exceed Âw /K，ω2.

We could go on to include the effect of the break at K , but for K 三 4 的 the effect is smal1, and the phase error still doesn't exceed Âw /K，ω2. To maintain lock, we must have O;(t) < Oem' which is satisfied if

Âw/K，ω2<Oem (7-19)

「4ω，

|之|

I/K

/他2 ω2

w

。 sLÌWi KW2

(c)

∞2 。3

Oe-s A凶 Ks+K，ω2

(e)

FIGURE 7-9

(a)

(b)

O~

LÌ~ Kω2

O~'

LÌ~ Kω2

。 sA帥 i2 +Ks+ K.凶2

(d)

一封 1/ω2 卅一

Response to a frequency ramp

w

(f)

會F


Together with 8em ωdK from Eq. (7-10) , the bound can be put in the forrn

Ll <ωLω2 (7-20)

This corresponds to the maximum rate the PD voltage can charge the capacitor in the loop filter. The PLL will eventually lose lock when it reaches the limit of its hold-in range , and Eq. (7-20) no longer holds.

EXAMPLE 7-1

A rocket accelerating at 30 Gs receives a communication signal with a 1.6-GHz ca位ier. A PLL with a multiplier PD is used to track and recover the carrier. What is the minimum bandwith K the PLL may have and still maintain lock?

An acceleration of 30 Gs is a = 30 x 9.8 mls2 = 294 mls2. The speed of light is c

= 3 X 108 mls. Therefore , the rate of change of Llωi is Ll = (a/c)ωi = (0.98 X 10-6)

271" x 1.6 GHz = 10000 rad/s2. For a multiplier PD ， ωL = K. Then Eq. (7-20) becomes Ll< K，ω2. K is minimized here by maximizing ω2. Let ω2 = K/4. Then K2/4 > Ll =

10000 rad/計， or K > 'J.旦旦主鎧/s.

7-7 HANDLlNG SINUSOIDAL FM

Consider the case when Llωi is frequency modulated by a sinusoid:

Aω Llωsin(ωmt) (7-21)

(See Fig. 7- lOc.) The resulting 8e depends on the transfer function 8iLlωi ， whose frequency response is shown in Fig. 7- lOa. Figure 7- lOb shows that the magnitude 18iLlwil is bounded from above by each of three different functions of ωm'

18iLlωil 三三 ωm/K，ω2

18iLlωil 三 lIK

18e/Llωil 三 1/ωm (7-22)

Then the peak value of 8e is 8e max = 18iLlωil Llω ， and all of the following bounds hold:

8e max 三三 Aω ωm/K，ω2

8e max 三 Aω/K

8e max 三 Aω/ωm (7-23)

f

A剖，

4ω

。e{}e max

l主l

I/K

包'm

(a)

Wm

(b)

(c)

(phase depends on ωm)

(d)

FrGURE τ10 Response 10 sinusoidal FM

1"'"""

150 Maintaining Lock Chap. 7 Sec. 7-8 Handling Random FM 151

(See Fig. 7- lOd.) Maintaining lock requires that 8e max 三。帥， where 8em is the PD phase range. According to Eq. (7-23) , this wiII be satisfied if any of the following bounds are satisfied:

Then we must choose K to satisfy at least one of the foIIowing:

Aωωm/K，ω2 S 8em

Aω/K 三三 8em

.:lω/ωm 三三 8em

K 這 )(8/甘).:lωωm 3880 叫S

K 三三 (2/τr ).:lω 2000 rad/s

Aω/ωm 1. 67 三 τr!2 = 1.57

(7-24) The last bound cannot be satisfied. Then ωminimize K, we choose to just satisfy the second bound: K 2旦旦旦主且也已 and ω2 = K/4 500 rad/s. Using 8em = ωdK from Eq. (7-10) , this can be stated in terms ofωL' The PLL wiII handle

sinusoidal modulation of .:lωi if any of the following are satisfied:

的可

fA

J中

U

ωω!

叫叫

ω間

〈一〈一〈一

ωωω

AAA

7-8 HANDLING RANDOM FM 、‘•• ,

J

W、J

守中

寸I', .. ‘、、

、、、、The first ihequality says the voltage across the capacitor in the loop filter is alone able to

cause the VCO to track ωi' The second inequality says the voltage across R 2 is alone able to cause the VCO to track ωi' The third inequality says it is not necessary for the VCO to track ωi; the phase error 8e never exceeds the range of the PD.

SinusoidaI FM is not very interesting in itself; it conveys no information. But it approximates some modulations of interest, such as band-limited frequency shift keying (FSK).

When a carrier is frequency modulated by an analog signal , the modulation usually has a broad spectrum and is best characterized as a random signal. For simplicity , we assume that the power spectral density φ的i is flat out to a bandwidth of B仰 as shown in Fig. 7- l1a. (See Chapter 6 for a discussion of power spectral density.) The area under the curve is .:lω? ， where .:lωi has a zero mcan. Then the spectral density must be

J .:lω加m' f < B_ φω1 A. (7-26)

Lυ f> Bm

EXAMPLE 7-2 The power spectral density for 8e is given by

Consider data transmitted using FSK with a baud of fB 600 bits/sec with 1200 Hz representing a “ mark" and 2200 Hz representing a “ space. " A PLL with an XOR PD is used to demodulate the data by tracking the modulation. Find the minimum K for which the PLL wiII maintain lock.

For the bit sequence 1 刀， 1 ，0 ， etc. , the frequency deviation .:lωi is a square wave with frequency ωm 21T X fB/2 = 1880 rad/s. If the transmission is band limited, the modulation becomes more sinusoidal, as .:lWi in Fig. 7- lOc. The mark and space frequencies can be expressed as 1700 Hz ::':: 500 Hz , so ωi = 2τr X 1700 rad/s , and .:lω

= 2τX 500 rad!s 3140 rad/s. For an XOR PD , 8em = 1T!2. Considering the first bound in Eq. (7-24) , choosing ω2

large as possible wiII help minimize K. Therefore , let ω2 = K/4. Then Eq. (7-24) says at least one of the following must be satisfied:

φBe = 18/.:lωil 2φωi (7-27)

where 18/.:lωil is plotted in Figure 7-11 b. This is the same response as the plot in Fig. 7- lOa, except the function is in terms off, wheref = ωm!21T. As in the previous section, 18/ .:lωil is bounded by either of the functions shown in Fig. 7-11b:

18/ .:lωil 三 2τrf!K，ω2 (7-28a)

18e/ .:lωil 三三 l!K (7-28b)

(A thi吋 bound 18/.:lωil 三 1/2πfis not useful here.) From Eqs. (7-26) , (7-27), and (7-28) , we have the two bounds

4 .:lωω~K2 三 τ!2

Aω/K 三 τ!2

.:lω/ωm 三 τ/2

( (21Tf)函2

φOe 三 i BmK2ω2 、 0;

f< Bm

(7-29a)

f> Bm

153 Handling Random FM Sec. 7-8

(7-31b)

We would like to be in a position now to use Eq. (7-31) to get bounds of {}e in tenns of bounds on LlWi. But for Gaussian random Llωi there is no bound on either Llωi or {}e" As a practical matter, we define the maximum {}e as that value that is exceeded only 0.05% of the time. From a nonnal distribution table , this corresponds to

{}e rms 三 Aωi rm/K

思?

Chap. 7 Maintaining Lock 152

Area= l:>wf

<þω，

4叫，f/Bm

(7-32)

Maintaining lock requires {}e max 三 {}em. Then Eqs. (7-31) and (7-32) give two bounds , either of which being satisfied will assure that lock is maintained:

{}e max 3.5 {}e rms f

(a)

Bm

(7-33a)

(7-33b)

Using {}em = ωd K from Eq. (7-10) , this can be stated in tenns ofωL. The PLL will handle random FM of Llωi if either of the following is satisfied:

三 (}em

3.5 Llωi rm/K 三。

s-IE I---r-2 4ω

ω一

A!-K J叫方

寸J

一\

f

10./1:>的|

I/K

j3 ωLω2 77rBm

(7-34a) Llω 〈1 nns -一

(b)

(7-34b) Aω1 rms 三 ω'L!3 .5Response to random FM

f< Bm l psJ; φ，，~三 1一 I 0;

FIGURE 7一11

(7-29b)

EXAMPLE 7-3

An FM radio station transmits music with a unifonn spectrum out to a bandwidth Bm = 15 kHz. The frequency deviation Llωi corresponds to the amplitude of the music , where the Gaussian distribution of the amplitude causes the frequency deviation to exceed 75 kHz only 0.05% of the time. A PLL with a multiplier PD is used to demodulate the signal. Find the minimum bandwidth K for which the PLL will maintain lock all but 0.05% of the tlme.

The maximum frequency deviation in rad/sec is 3.5 Llωi rms 2τx 75 kHz = 471 kradl s, or Llωi rmS 135 krad/s. For a multiplier PD， ω'L = K. Let ω2 = K/4. Then Eq. (7-34a) gives

f> Bm

φ'øedf，闊的ing out the integra-

Taking the square root of both sides of Eq. (7-30) gives bounds on the root-mean-square

of {}e:

(7-30a)

(7-30b)

f

互至三高?/K2

Since the mean 哪位.e of {}e is given by {}/ = tion of Eq. (7-29) gives the two bounds

oe2 三三

U 三 4 x 77rBmωi rm沾 102500 (krad/sf K 三 320 krad/s

(7-31a) 2τBmLlωrmS

ßK ω2 。三e rms

F


and Eq. (7-34b) gives

K 三 3.5 ßωi nns 471 krad/s

To minimize K , we choose to satisfy the first bound with K = 32且主旦些E﹒ Then ω2 = KI4 80 krad/s.

\

CHAPTER

8

LOCK ACQUISITION

We have been assuming in our analyses of PLLs that they are in lock一-that the average VCO frequency (1)0 equals the average input frequency ωi' However, the two frequencies are not the same when power is first applied to the circuit or when Vi is first applied to the PLL input. The process of bringing ω。 to equal ωi is calledfrequency acquisition. After the frequency error has been brought to zero , there is a transient process during which the phase error is also brought to zero. There is no clear definition of when the PLL is actually in lock, but it is reasonable to define lock acquisition as synonymous with frequency acquisition. Any remaining phase transient is similar to the ()e transient studies in section 7-5; it can be considered as taking place in lock.

In a second-order PLL , most of the voltage to bring the VCO to the proper frequency is provided by the capacitor in the loop filter. For example, the active filter in the PLL shown in Fig. 8-1a provides the control voltage Vc = V2 +巧， where V2 is across R2 and V3 is across the capacitor. The frequency acquisition process amounts to charging (or discharging) the capacitor until V3 provides the correct control voltage for 石。 =ωrAfter lock, V2 provides the small changes in frequency necessary to provide phase error correctlOn.

.In some cases, a frequency detector is added to a PLL to help charge the capacitor. But we will see that the unaided PLL is able to acquire lock for a limited initial frequency error.

一句+ 一句+

的

們已

(a)

V2

~

。e

(b)

Vc !

vc = 地 +V3

-7r -7r/2 7r/2 7r 0.

(c)

• ω. I (-0.)

ω.=κ~vc fast ωκ戶V3

-7r 一 π/2 π/2 7r 。e(d)

FIGURE 8-1 PLL out of lock

\

Sec. 8-1 Self Acquisition: Active Loop Filter 157

To simplify the analysis of lock acquisition, the input frequency and phase will be assumed constant ({}i = 0). The effects of {}i 手 o can be taken into account through a modified PD characteristic (see section 4-13). For a constant input frequency , any deviation ofω。 from ωi is considered a frequency error. Therefore , in this chapter we relabel Llwo as the frequency error ωe.

。且e=Wo - Wi (8-1)

where ωi is a constant and {}i = O. [Compare Eq. (2-5).] The maximum ωe for which the PLL will attain lock is called the pull-in range. In this chapter we will find the pull-in range and pull-in time for a PLL to acquire lock with different phase detectors and different acquisition aids.

8-1 SElF ACQUISITION: ACTIVE lOOP FllTER

The process of a PLL acquiring lock without the aid of a frequency detector is called self acquisition. In this case, the PD is responsible for charging the capacitor in the activc loop fi1ter. There must be at least a small dc component to the PD output 叫， and the polarity must be such that the VCO frequency ω。 is brought c10ser toωi. When a PLL is out of lock, the dc component is small, but it can be enough to pull the PLL into lock.

8-'唱一1 PULL-IN VOLTAGE Vp

The dc component (or average) of v d during acquisition is called the pull-in voltage vp • To understand the origin of vp ' consider a PLL that has no modulation of the input signal: {}i = O. Then the phase error is {}e == {}i - {}O = - {}O. When the PLL is out of lock, ω。手 ωi on average , and the frequency error ωe 三 ω。一 ωi is not zero on average. But

ωe {}O -{}e (8-2)

Then θe is either constantly increasing or constantly decreasing. What is the control vo1tage Vc as a function of {}e? Consider a PD with a sinusoidal

characteristic:

Vd V dm sin {}e (8-3)

The voltage V2 across R2 is proportional to Vd:

V2 KhVd KhVdm sin {}e

F 158 Lock Acquisition Chap. 8

as shown in Fig. 8-1b. To simplify the analysis , let the capacitor be large enough (ω2 is smaII enough;ω2 三 K/4) that its voltage V3 is essentiaIIy independent of 8e . Then the total control voltage is

Vc = V2 + V3 KhVdm sin 8e + V3

as shown in Fig. 8-1c. Ifthere is some 8e for which Vc causes ωe = 0 , then the PLL wiII lock at that phase. Without loss of generality , let us assume that Vc = 0 causes ωe = O. Then the VCO characteristic is simply

ωe Kovc

KoKhVdm sin 8e + KoV3 (8-4)

But Vdm Kd for a sinusoidal PD , and K KoKhKd . Then

ω K sin 8e + ωc (8-5)

where

ωc 三KoV3 (8-6)

is the portion of the f記quency error due to the incorrect capacitor voltage V3' A plot of the function ωe in Eq. 的-5) is shown ip. Figure 8-1d. For the case of 島 o during acquisition , Eq. (8-2) gave ωe - 8 e' Then Eq. (8-5) can also be represented as

- 8 e K sin 8e + ωc (8-7)

Thi.s gives the rate of change of 8e in terms of 8e- As shown in Fig. 8-1d, when 札記甘12 ，

一 8 e is large , meaning th'!t 8e decreases rapidly (the motion to the left along the curve is fast). For 8e = 一τ12 ， - 8 e is smaII, and the motion to the left is slow. Since ωe never goes to zero , the PLL never locks for any 8e •

In order for lock to occur, V3 must decrease (with a corresponding decrease in ωJ until the curve in Fig. 8-1d touches theωe = 0 axis. Can Vd supply the necessary average current to discharge the capacitor in Fig. 8-1a? Consider the PD characteristic in Fig. 8-2a. If 8e moves smoothly to the left when the PLL is out of lock, then V d is sinusoidal in time, and its average is zero. There is no average current , and the capacitor neither charges nor discharges on average. But as we have seen, 8e does not move smoothly; it lurches along , spending more time in the vicinity of 1.5甘，一 O.51T， etc. (see Fig. 8-2b). This means that Vd spends more time with negative values , as shown in Fig. 8-2c. What is important is that the asymmetry of the waveform about the t axis has produced a nonzero average component 恥， which in this case is negative.

? Vd

Vdm=K fast

。e

slow

(a)

。e

2"11"

1.5"11"

"11"

0.5"11"

。

0.5有一-4--T-111

一什一十一-1- 十1 1 一!1.5π 一-J一一一-J-J 十一一一十一一十一 l

叫一午 J 十J-J-LJ一(b)

Vd

Vdm

(c)

FIGURE 8-2 Beat note asymmetry

FF

160 Lock Acquisition Chap. 8

The expression for Vd as a function of time can be found by solving Eq. (8-3) together with Eq. (8-7). The average voltage 予'd is called the pull-in voltage vp . Richman [1] showed that

η=ι[ωc反 - J(ω月2 一 1] (8-8)

for the case we are considering here: sinusoidal PD characteristic, active loop filter， ω2 三

K/4 , and f}i = O. Equation (8-8) can be approximated by

vp = -KdK/2ωc (8-9)

A plot ofvp and its approximation are given in Fig. 8-3. For ωc > 2K, the approximation is within 7%. For ωc > K , the approximation is conservative; it estimates less pull-in voltage than there actually is. For ωc < K , the PLL has locked, and pull-in voltage is undefined.

8-1-2 PULL-IN TIME 九

For large frequency error ω口 the asymmetry in Vd is slight, and the pull-in voltage Vp is small (see Fig. 8-3). Therefore , the capacitor is discharged slowly , and ωc decreases slowly at first (see' Fig. 8-4). Asωc approaches K , vp gets quite large , and the final descent of ωc is more rapid. The pull-in is complete when ωe can equal zero for some f}e.

According to Eqs. (8-4) and (8-6) , this is when ωc = KoKhVdm' This is called the lock-in range ωIL:

ω'L KoKhVdm (8-10)

K 2K 3K 4K 5K

。)c

Kd /2

Kd

FIGURE 8-3 PulI-in voltage

Sec. 8-1 Self Acquisition: Active Loop Filter

W.o

」五三 WL 一

T" ", .!ω，01的2 一!自 "'-一一-一一一一一

ω2

ω.=ωc+Ko1也

T ρ

Wc

FIGURE 8-4 PulI-in time

司61

An equivalent definition of lock-in range is the maximum frequency error ωe for which acquisition is almost instantaneous; the PLL slips less than one cycle. (ln section 7-3 , the lock-in range was shown to be the maximum frequency step the PLL could handle and still maintain lock.) For a sinusoidal PD , Vdm Kd' and from Eq. (8-10)

ωL=K (8-10')

From the approximation for vp in Eq. (8-9) , we can find an expression for the curve ofωc versus t show叭n Fig. 8-4. From this we can find the pull-in time Tp as a function of the initial frequency errorωeo﹒ Analyzing the circuit in Fig. 8一 1 ， ωc changes due to the capacitor being charged by the current i viR 1:

ωc 三KoV3

。c K。有 KoilC KoviR.C KoV~hω2 (8-11)

where Kh = R2/R 1 andω2 = lIR2C. Then with Eq. (8-9) ,

。c = - KaKdKhKw212wc - K2w212wc

2ωc äωc = -K2ω2 dt

Integrating both sides gives

ωc22=ωe/ - K2ω2t (8-12)

會o


where ωeo 2 is the constant of integration such that ωcωeo for t = O. The pull-in time T

n is the time forωc to reach 伽 lock-in range ω'L = K. Solving Eq. (8-12) for t such 出ωc K yields

1> z(ωeo/K)2 - 1

W2 (8- l3)

If the exact expression for v p given in Eq. (8-8) is used in Eq. (8-11) , the exact result is

Tp [x2

+ x，[x2三I f仰 +P了。- 1]/2ω2 (8- l3')

where

X 三 ωejK

The exact value of the normalized pull-in time 耳ω2 [Eq. (8- l3')] and the approximati forTpω2 [Eq. (8-13)] are plotted in Fig. 8-5. Thé appro~imation is conservative in that it gIVes too great a value. For ωeo > 3 K, the approximation is in error by less than 8%.

25

20

15

10

5

(W;o) 一 1

2 3 4

actual ω2九

5 甜甜/K

FIGURE 8-5 Pull-in time VS. initial frequency e叮or

Sec. 8-1 Self Acquisition: Active Loop Filter 163

EXAMPLE 8-1

Given a PLL with K = 8 krac拙， ω2 = 2 krad悠， and a sinusoidal PD with Kd = 2 V/rad ,

find the pull-in time for initial frequency errors of 鈍。= 5 krad怨，鈍。= 100 krad/s , and 鈍。 2 Mrad/s.

From Eq. (8- l3), Tp = 0 for 鈍。= 5 krad/s (Weo is within the lock-in range). Tp = 78 ms for ω。 100 krad/s. and L = 31 sec for ω= 2 Mrad/s. In the last case , it is eo ~~~ ~~--，....， ..........._.....p ~~ ...._- ~~~ ~eo

probable that the PLL would actually never lock because the initial vp is so small [Eq. (8-9) gives an initial vp 4 mV]. Such a small vo1tage could be overwhelmed by dc offset vo1tages , causing ω。 to move away from rather th組 toward ω/.

8-1-3 PULL-IN RANGE W p

The pull-in range of a PLL is defined as the largest frequency error ωc for which the PLL will acquire lock. Suppose the PD has an offset voltage Vdo - Then during pull-in, when the PLL is out of lock , the average voltage from the PD is

Vd = V do + vp = V do - KdK12ωc (8可 14)

(See Fig. 8-6.) For ωc small enough, Vd is still negative , and the PLL pulls in. But for ωζ larger than some value , Vd is positive, and the frequency errorωc actually increases. Then the pull-in range ω'p is that frequency errorωc for which Vd = O. From Eq. (8-14)

ω'p = K dK12Vdo = MK/2

Vd

Vdo 1-一一一一一一一一一

K

Vdo-Kd

Vn+V", 血 Kd K W ,.:=:::: -一一

Vdo 2

FIGURE 8-6 Pull-in range

(8-15)

“'c

F


where M is the PD figure of merit defined as M 三 KjVdo ﹒ A typica1 va1ue for M is 20 , so ωp can typically be 10 x K. With care , a PD can be made to have an M as great as 400. Then ω'p can be as great as 200 x K. (This is subject to 1imitation 峙的， as shown in section 8.3.)

The ana1ysis of pull-in time Tp and pull-in rangeω'p has depended on Eq. (8-9) for vp

that ho1ds for a sinusoida1 PD characteristic. Meer [2] has carried out a simi1ar ana1ysis for triangu1ar and sawtooth PD characteristics. The tab1e in Fig. 8-7 compares the pull-in parameters for a sinusoidal PD , a triangu1ar PD (such as an exclusive OR gate) , and a sawtooth PD (such as a two-state PD). The pull-in times are within a factor of 7 of each other, and the pull-in rang臼 are a1so within a factor of 7 of each other. The expressions for 勻，丸，組dω'p are approximations that ho1d for 鈍， ωem and ω'p greater than 2ωL﹒ See

Meer for the exact expressions.

8-2 SELF ACQUISITION: PASSIVE LOOP FILTER

For an active 100p fi1ter , the requirement for pull-in is simp1y that Vd be negative for positive frequency error， ω口 and V d be positive for negative ωc﹒ This is because the po1arity of the charging current i depends on1y on Vd' For a passive 100p filter , however, i depends on both V d and V3' and V3 depends on ωr

We will ana1yze the behavior of the passive 100p fi1ter in Fig. 8-8a during acquisition. The charging current is given by

Vd

Vdm

ωL

v p

T P

Wp

碎片司令; 叫到Kd (,r/2) Kd 7rKd

K (7r /2)K 7rK

k 'dK k 'dK Kd'k

2ωc 1.2wc O.3wc

峙。/1<) 2 一 l (ωeo/的2-2.5 (Weo/1<)2 一 10

ωz 1.6w2 6.6w2

MKI2 MK/1 .2 MKIO.3

-FIGURE 8-7 Pull-in parameters for thr，巳e phase detectors

Sec. 8-2 Self Acquisition: Passive Loop Filter

的Vdm

Vdo - Vdm

Ro

Vd

(a)

(b)

Vc

Vco = Vdo =ωeo/Ko

均=ωc/Ko

FIGURE 8-8 趴Ill-in with passive loop filter

i = (Vd - v3)/(Ro + Rz)

165

Wc

Both V d and V3 are functions of ωc during pull-in, as shown in Fig. 8-8b. We assume without 10ss of genera1ity that v c = 0 causes ωe = 0 , and therefore v3 = 0 causes ωc = O. Initially the free-running vo1tage V do of the PD charges the capacitor to 月 Vdo ' which is a1so the initia1 Vc since V2 Rzi O. Then the initia1 frequency error is

ωeo KoVdo

For V do positive ， ωeo is positive and has the proper po1arity (negative) for pullin provided Vd is be10w V3' This is true everywhere for the case in Fig. 8-8b, but at the point where the two curves get close , i becomes smal1 , and the pull-in process becomes slow.

F 166

Lock Acquisition Chap. 8

wc fInd the pup-in time 7}for a PLL with a 仰的ive loop filter and a PD with a tríangular characteristic.

ωc=KoV3

Wc KoV3 KoilC Ko(Vd - v3)/(Ro + R2)C

Ko(v ct - v3)Khω2 KoCvct 一 ωc/Ko)Khω2

whereι R2/(Ro + R2) andω2 l!R2C. From Fig. 8-7 ， η -KdK!l .2wc for a triangular PD characteristic. Then

Vd = Vdo - KdKI 1. 2ωc 鈍。1Ko - KdK!l .2ωc

and

W c Ko(weolJ<.。一 K~I1 .2ωc 一 ωJKo)Khω2

=ωeJ<hω2 - K2ω2/ 1. 2ωc - Khω2ωc

Then

ωc d，ωcf( 一 a + bωc 一 cω/) dt (8-16)

where

a K2ω211 . 2 ， b = Khω2ω旬， c - Khω2

As ωc goes from ωeo toω'L τrk/2 ， t goes from O to T Integrating the left side of Eq. (彷8-1廿峙l泊昀6白) 仕伽枷Oω叩I虹叭I

1耳p [tan- 1 (.收xl抄y - 甘/抄y) + t仿an- I (.收xl抄'y)刀] xl(付yK，ιhω2)) - (l12Khω2) 如(l + 3Kh - 6K~1τ) (8-17)

where

X三 ωeo店 y=而石瓦亡三三 (8-18)

Th恤圳i必s叫吋h…1

as a function of the no叩alized initial frequency errorωejK in Fig. 8一-9. N愉ot臼e t血ha叫t t伽he e :Z::: 江t:2:::;ιs:11dl叫u叫nc昀t臼I叫d由伽蚓1泊叫c叫l岫O∞op抖川州f白臼ïl伽l

;叮J;;?立九i沛峙;L正均占:正AA;土主5E-i諾吋:2誌詰:i5i3;叫t誌抓!:日凱ii♂jf!曰侃L苦i:抓::z古品謊i;;拉莊::;三:itii;k肘!叮叫吉剖喘3市f 門 =τKlj3K;， (8-19)

Sec.8一2 Self Acquisition: Passive Loop Filter

160

150

140

130

120

110

100

90

九ω280

70

60

50

40

30

20

10

(fo PD characteristic)

Kh =0.2 0.1 0.04 0.02[

l 0.011

l 世/川2

/ / 11 v v ~ L

/ V v 位L

/ /夕已/l I/h 后/l / d 伊以W

W " 戶d2 3 4 5 6 7 8 9 10 11 12

峙。/K 一一一-FIGURE 8-9 Pull-in time for passive loop filter

EXAMPLE 8-2

167

A PLL has a triangular PD with Kd = 2 V/rad , a VCO with Ko = 0.2 孔1rad/s!V， and a passive loop filter with Kh = 0.02 and ω2 = 2 krad/s. Find the lock向in range , the pull-in range , and the pull-in time for 鈍。= 8 krad/s , for 鈍。= 80 krad/s , and for 鈍。= 800 krad/s.

The bandwidth is K = K~hKo = 8 krad/s. From Fig. 8-7 , the lock-in range isωL =τ KI2 = 12.主主且也~. From Eq. (8-19) , the pull-in range isω'p = 1旦3 krad/s. Forωeo

= 8kra仇， Tp = 0 becauseωeo is within ωL. Forωeo = 80 krad/s , Fig. 8-9 gives Tpω2= 109 , or Tp = 54 ms. For ω= 800 krad/s , the PLL fails to lock becauseω o exceeds ωp﹒

-一一一一一 -eo

FV

Chap. 8 Lock Acquisition 世68

w “'c E吋-

\4

W3

凶c=5ω3

K IF'I

1/5

8-3 ACQUISITION WITH A POLE AT ω3

Whena 且L is out of lock , V d varies periodically, and a portion of 恥 appears a缸cros俗吋sRι勻

It i必s t血hi必s va巾時 C∞on叩onen臼n肌1

VCO frequency to vary in such a way t由ha前t the beat note a剖t V叫'd slows down a泓t J戶us仗t t血hemo 宇平le叩nt It 1昀s ne愕ga瓜tive. (For negative frequency error, the beat note slows just as Vd is positive.) If伽 amplit他 of V2 is attenuated or if its phase is shifì削 by an additional pole in the loop , the pull-in voltage Vp will be reduced.

Consider a PLL with a pole atω3 in the loop. This may be due to the modulation bandwidth-of the VC0, the bandwidth of the op amp in the active loop filter, or it may have been introduced purposely to smooth V c when in lock. Let this pole be modeled by an additional filter in the loop with the transfer function

Wc K ang(F1

。。

、、lπ14

1.37\、

π/2

(8-20)

The frequencymponse of the magnitude VF|and of the phase aIlg(F') , shown in Fig. 8- lOa, are given by

F'(s) = ωi(s + ω3)

!F'! = ω3/(ωf+ω32)的(a)

(b)

(-0.)

Vd

Vdm

W.

Wc

ωc- K15

ωc+ K15

(8-21)

(8-22)

It is c1ear that the attenuation by !F'! wiII cause a proportional reduction in Vn

• To understand the reduction due to ang(FF)we need to look at some examples Thecasc shown in Fig. 8-10 is for ωc 5ω3' Therefore , !F'! = 115 , and a時(F') = 一1.37radians. This phase shift of almost 'IT12 radians between Vd and the VCO causes the beat note to slow down when vd is passing-through zero rather than when it is negative (see Fig. 8一lOb). This has the effect of maki月 Vd n叫y symmetrical about the t axis , g昀m羽treducing its average , which is the puII-in voltage.

Let the pull-in voltage with ω3 present by V\ If ang(F') were 一 τ12 ， then V~ would be reduced comple昀 ωzero. If ang(F') we昀z 一 τ(it cannot be here) , the beat note would slow down when Vd is positive , and 叫=一句. This would be the opposite of the polarity that is needed to puII in , and “ push-out" would occur, preventing lock of the PLL. These examples are a heuristic explanation of tl叫'act that V; is further attenuated by a factor of cos[ang(F'汀， where cos( - 'IT/2) 0, and cos( 一 τ) =一1.

The pull-in voltage reduced by both the magnitude and phase of F' is given by

一 tan- I (ωJω3)ang(F') =

and

IF'(ωc)1 = 1/5 ang[F'(ωc)]= -1.37,

(c)

(8-23)

where vp is the pull-in voltage with no F , in the loop.For our case of a single pole, Eqs. (8-21) , (8-22) , and (8-23) give

V; = !F'! cos[ang(F')] vp

Effect of pole atω3 on pull-in FIGURE 8-10

cos[tan - \ωJω3)] Vp

包)3

(ω/+ωl) 1J2 F

V~ p

F 170

Lock Acquisition Chap. 8 Sec. 8-4 Acquisition with a Three-State PD 171

But cos[tan -IX] == 1!(X2 + 1)112. Therefore,

F V~ p p v

一勻，中

-司‘

d

一ω

弓，--叫

一IT

-7臼

-c 一ω (8-24)

whereFis-the pull-in VoltaFgiven 1n Fig.87for no ω3' For the case ofωc 5ω3 shown in Fig. 8一10 ， V; 叫26.

'Equation (彷8-24) i臼s not int紀ended tωo be used tωodes釗ign and analyze pu叫ll-in for ωc> ω恥，;.

;氾凶l玄♂:立口沉:立立t立;2;立st: :;口:i3f￡βr誌臼:f土扣It3叮:2;ωC.Stated another way, In a practical sense the pull-in frequency is

ωIp :::=:::::ω3

or that given in Fig. 8-7, whichever is smaller

也忱的。衍)tto;:ot;2;;此?1:JZZe;;:立忍心jiJt::::1:ultiple poles are introduced by an IF filter in the PLL.

FIGURE 8-11 PLL for study of pull-i日 range

Before acquisition , the VCO sits at either 95 Mrad/s or 105 Mrad怨， while ωi = 100 Mrad/s. Therefore , the initial frequency error isωeo = 5 Mrad/s , which is less than the improved ω'p- The loop filter's zero frequency isω2 = I/R2C = 15 krad/s. Then from Eq. (8-13) , the pull-in time is Tp ωe}l昕一 1)/ω2 些Z且~. If this is too long , an acquisition aid such as that described in section 8-6 is required.

EXAMPLE 8-3

Find the pull-in frequency and the pull-in ti中e of the PLL circuit shown in Fig. 8一1 1. The PD is a double-balanced mulhplier with a SInusoidal characteristic, gain Kd=O.4V/危'rad ，組叫司 dc 0晶臨et 凡O戶= 一 lrr耐I

a組nl1刊mpu叫叭t off:缸f臼蚓tv叫O叫It翎ag伊eV阱VIO站}扣o - 1 m V, and an input offset current ho =ωOn叫A. The詭e VCO is t血ha叫td配你蚓e臼叩s位ig伊ne吋dü吋X油amp抖le臼s 5-3 and 5-5 臼rag伊ain K丸o = 3.7 Mradψ仇/旭s/V ， a rang伊e from 95

立垃::盯?訂叩::; ;立:. Y空!7於:口t;f付j?1，;;在芯扣;口ι:仁LIL1J:品;;:The 10叩 fIltcr's high-frequency gain is kh=67O Q/IO KO=0.067 , so thc PLL

bandwi4thISK=kdkhko=IOOK削/s. The reference voItage is 咒= OV，則he to凶 JoffsetgmnbYEq(5lIa)hyh 于(院一九0) + 吧。 + hoR1 = 1 + 1 + 0.1 = 2.1 的 The PD f句I喀g脫 of me叩nt九IS g♂附lvel問en b句yE陶q. (件4牛-1昀4勾)ω叫AMf L k丸bdJ/VO=190 庇 1(防佫伽8-糾-1吼5

bandwidth p抖la缸，ce臼s a pole a叫tω3 = 400 krad/s (see Example 5-5) , so a practical value for the pull-in frequency isωp = ω3 生旦旦主rad/s.

There are methods of exten平時 the VCO modulation bandwidth and therefl悅 thepull-in frequency. The 15 kO resi吼叫 could be replaced by a 10-μH choke and a 600-0

瑞拉:HZHltHf咐:iiigreater than M K/2 = 9.5 Mr帥， the improved pull-in frequency i川=位盟主必

8-4 AcaUISITION WITH A THREE-STATE PD

The advantage of a three-state PD in acquisition is that it acts as both a phase detector and a frequency detector. As we saw in section 4-8, Vd is always positive whenωe < 0 (when (Je is increasing) , and Vd is always negative when ωe > O. From the characteristic in Fig. 4-8d , it would appear that Vd = Vdm/2 if (Je is increasing smoothly to the right. This is approximately correct. In fact , V d becomes even greater as the rate of increase of (Je is greater, as shown by the following discussion.

Consider the case when ω0' the frequency of V , is slightly greater than ωi ， the frequency of R. Then the PD will eventually be cyc1ing between State 1 and State 2 in Fig. 8-12a. A rising edge on V sets VD high , and a rising edge on R resets VD low. The waveforrns are shown in Fig. 8-12b. Here R and Vare represented as they would appear on an oscilloscope synchronized to R. Because ω。 is higher in frequency , V drifts in phase to the left. This causes the rising edge of VD to drift to the left, increasing the duty cyc1e of VD (many rising edges are shown in Fig. 8-12b). When the rising edge meets the falling edge (shown heavy here) , it snaps back to a duty cyc1e of zero and beings drifting to the left again. If the phase drift is uniforrn , the average duty cyc1e is 50% , and Vd

-0.5Vdm

Now consider the case when ω。 is slightly greater that 2ωi as in Fig. 8-12c. Then V again drifts in phase to the left , causing the rising edge of VD to drift to the left and


State 1 R State 2 R State 3

V R

V V

Vj=R, vo=V

(a)

RIL一「工」

VI1二FLJ

汀11111111111111111111111111 111111111111111111111111lL;

Vu I|

R I1-J一L-.J

VrL.1l.::f=LflJ VDlØ 且lJlill] -l

句||

(b) (c)

Vd

Vdm Vdm(l 一 ω。/2叫j) Vd=VU-VD

Vdm=VH - VL 0.5 Vdm

Wj 2ω， 3wj 在"j 5wj ω。

Case 1 Vdm( 一 1+ω;/2ω0)

-Vdm

(d)

FIGURE 8-12 Pull-in with three-state PD

increasing the duty cycle of VD . When the rising edge meets the falling edge , it snaps back to a duty cycle of 50% (not zero) and begins drifting to the left again. This time the average duty cycle is 759忌， and Vd -0.75Vdm .

In general , the expression for Vd is given by

Vd = Vdm( 一 1 +ω/2ω。);

Vd = Vdm(l ω012ωJ;

ω。 >ωz

ω。 <ωz (8-25)

可F

Sec. 8-4 Acquisition with a Three-State PD 173

which is plotted in Fig. 8-12d. For Ú>o very close to 叫 (within 3 K), there is an additional

Vd component (not shown) similar to that in Fig. 8-3 due to the asymmetry of the beat

note. In the analysis of three-state PD pull-in behavior, we will neglect this small effect.

For this PD the only limit to the pull-in range is the hold-in range (see section 7-1).

To get a simple expression for the pull-in time 丸， we will use a conservative

approximation for Eq. (8-25):

Vd = -0.5Vdm 一 τrKd (8-26)

for ω。>峙， or ωc > O. For a three可state PD we have

ωL 2τK (8-27)

The ca1culation of the pull-in time Tp is 泣milar to that for the sinusoidal PD. Substituting Eq. (8-26) into Eq. (8-11) , integrating, and solving for t = Tp such thatωcωL' we obtain

一

P T ωeo/K - 2τ

'ITÚ>2

(8-28)

In many applications , the range of the three-state PD is extended with -7- N frequen

cy dividers , as was done for the two-state PD in Fig. 4-12. In that case, Eq. (8必)

becomes

Vd = -0.5Vdm 一 τrNKd (8-26')

Eq. (8-27) becom的

ω'L = 2τNK (8-27')

and Eq. (8-28) becomes

一

nr T ωeo/K - 2τN

τNω2 (8-28')

Comparing Eqs. (8-28) and (8-28') with Eq. (8- l3), we see that 耳 increases only

proportionally with ω帥， rather than as its square. Note , however, that a three-state PD can

be used only with strict1y periodic signals. If there are any inissing pulses , as in clock

recovery applications or high-noise applications , then the three-state PD will not operate

properly.


EXAMPLE 8-4

A PLL has K = 8 krad/s and ω2 2 kradls. The initial frequency error isωeo 2 Mrad/s. The PD is a three-state phase detector. Find the pull-in time.

From Eq. (8-28)，耳= 39 ms. Compare this with the 31 seconds in Example 8-1 with similar conditions but a sinusoidal PD.

8-5 AIDED ACQUISITION WITH A THREE-STATE PD

If the acquisition time that a three-state PD can provide [see Eq. (8-28)] is not fast enough , a frequency detector (FD) must be added to the PLL. The pu中ose of the FD is to provide a strong pull-in signal in response to a frequency error ωe (or ωc if we ignore the small frequency fluctuations due to V2 across R 2). All FDs used in conjunction with a PLL operate on the basis of sensing cycle slips between ωi and ω。 . We have already seen these cycle slips as the beat note in V d (see Fig. 8-2c). We also saw cycle slips in section 4-8 in the operation of three-state PDs. Referring to the state diagram of a three-state PD in Figure 8-12a, the looped arrow at the left corresponds to a cycle slip when ω。 >ωn

where ω。 is the frequency of V and ωi is the frequency of R. The looped arrow at the right corresponds to a cycle slip when 叫 >ω。. A circuit to detect these cycle slips was presented in section 4-12 (see Fig. 4一16).

A PLL using cycle sIip detectors to implement a FD is shown in Fig. 8-13a. A cycle slip is shown 扭曲e waveforms in Fig. 8-13b for the case ω。 >ωi' Whenever a rising edge on V is not accompanied by a rising edge on VD , a slip has occurred , and a pulse appears on viJ. This pulse , which occurs at a rate equal to the frequency err肘， charges the capacitor in the direction to reduce the frequency error. The amount of charge each slip pulse delivers determines the acquisition speed.

The op amp in the loop fiIter is referenced to a Vr halfway between the logic high V H

and the logic low VL .

Vr = (VH + VL )/2 (8-29)

Assuming V2 across R2 is negligible , Vx = Vr- During a sIip pulse on 咕，也 = VH , and the charging current is

i3 九一 viJ)IR3 = (吭一 VH)IR3

(VH - VL )/2R3

where the diode voItage drop has been neglected. Similarly, during a slip pulse on v~，

時=凡， and the charging current is

i3 (vx - v;;)IR3 (VH - VL)/2R3

的 R Vu

3-state PD

Vo .-l V VD Vó

V,= (VH+ VL)/2

(a)

R

V

VD

il---------三也一一一卅一~T斗

(b)

FIGURE 8-13 Three-state PD with aided acquisition

... t

重7


Let 1 be the magnitude of i3 during a slip pulse. Then

1 = (VH - VL)/2R3 (8-30)

The width of a slip pulse is the period of the signal at V:

T = 27r/ωo = 27r/ωz (8-3 1)

Thecha時e in capacitor voltage due to a slip pulse is ILlv31 = IT/C , and the correspo凶ingchange in frequency error is

I Llωcl = KoILlv31 = KJT/C (8-32)

Then with every cycle slip , the frequency error is reduced by Llωρand the acquisition rate is proportional to Llωc ﹒ But if Llωc is too large , the PLL may never reach steady-state; it may always jump over the lock-in rangeωL as it approaches ωc = O. Th巴refore ， it is necessary to satisfy I Llωcl < 2ωL﹒ In practice , it is good to leave a factor-of-two margin and choose 1 in Eq. (8-32) so that

I Llωcl =ωL (8-33)

For a three-state PD ， ωL 27rK, so

I Llωcl = 2τK (8-33')

is a good design value for the circuit in Fig. 8-13a. Then Eqs. (8-32) and (8-33') give

1 = 2甘KCJKoT (8-34)

What is the pull-in time Tp achieved by the acquisition aid in Fig. 8一13?Wewillapproximate the frequency error's rate of change by äωJdt = LlωJ Llt , where Llt is the interval between cycle slips. But by definition ,

Llt 三 2τ/1ωcl

Since ωc and Llωc have opposite signs ,

dwJdt = LlwJLlt = 1ωcl LlωJ2τ= 一 ωcl Llωcl/2τ

dωJωc dtl Llωcll2τ (8-35)

As ωc goes from an initial 鈍。 to a fina1 lock frequency ofω'u the time goes from 0 to 耳Then integrating the left side of Eq. (8-35) from 鈍。 toω'L and the right side from 0 的 Tpyields

耳= (2τ/ILlωcl) t'n(鈍。/ωL) (8-36)

Sec. 8-6 Rotational Frequency Detector 177

For a practica1 maximum of 凶ωcl = 2τK as in Eq. (8-33') , the minimum Tp is

Tp = (1!K) 如(ωe)2τ的 (8-37)

The waveforms during acquisition are illustrated in Fig. 8-14a. The cycle-slip pulses viJ produces steps of Llωc in ω口 which get farther apart in time as ωc decreases. At the same time , the sawtooth waveform of V2 also affects the total frequency error ω ωc + KoV2 (which happens to be a smooth curve for I Llωcl =ω'L)' When ωc finally jumps within the lock range ωμthere are no more cycle slips , and the frequency acquisition is said to be complete.

The pull-in time Tp may be reduced somewhat by increasing I LlωCI. But if I Llωcl> 2ω'L ， thenωc may never jump to within the lock-in range，的 illustrated in Fig. 8-14b.

EXAMPLE 8-5

A PLL has K = 8 krad/s , Ko = 0.2 Mrad/s!V, a three-state PD , and a loop filter with R 1

= 50 kü , R2 = 5 kü , and C = 0.1μF. The input frequency isω10 Mrad!s. The digitallogic levels of the PD are VH = 5 V and VL 0 V. Choose R3 in the FD for minimum pull-in time. Find the pull-in time for ωeo 2 Mrad/s.

From Eq. (8-29) , the reference voltage is Vr = (VH + VL )12 = 2.5 V. From Eq. (8-31) , the input signal period is T = 2τr/ωi = 628 ns. From Eq. (8-34) , 1 = 2τKC/KoT = 40 mA. But the most load current that the PD can handle is 10 mA. One way to scale down 1 is to reduce C by a factor of four. In order to preserve F(s) of the loop filter , all of its impedances have to be increased by a factor of four: Rí = 200 kü , R; = 20 KÜ , C' = 0.025μF. Then I' = 10 mA , and from Eq. (8-30) R3 = (2.5 V)汀， = 205 Ü. If a diode drop of 0.7 V is taken into account , then R3 (1.8 V)汀旦旦旦.

1 could be reduced further by scaling up the impedances of the loop filter further. Eventually , R 1 becomes so large that the input offset current of the op amp creates too much offset voltage Vdo (see section 3-4).

For ωeo = 2 Mrad怨， Eq. (8-37) gives Tp = (8 krad/s) -1 X t'n(2000/50) =生生豆旦旦Compare this with the 39 ms for similar conditions and an unaided three-state PD in Example 8-4.

8-6 ROTATIONAL FREQUENCY DETECTOR

We have seen that an unaided three-state PD does a good job of acquisition , and with the aid of an FD , it does an excellent job. But there are applications where a three-state PD can't be used. Since it doesn't forgive a missing pulse in R or V, it can't be used with data or in high-noise applications. The FD described in this section does work with data and with high-noise applications. Richman [4] described the original version , which he called

山 [

.<lwc = ωL

ωe=∞c+几V2

--• 一-----'、、、、一一一一一一一一一一一一-~--= 一

‘、.‘、.-﹒陶﹒

-WL \\ 「

ω00閃下4ωc>2ωL (too large)

.<lwc Wc

/' 。'e

ωL r-一一一「可~_______+L亡三一一一一 I~互之:一一一一、、、、“---

一ωL r-一一一一一一一一 -î三~一.....-一-一-一，戶一-一一←一一一一一一一一一-(b)

FIGURE 8-14 PuI1-in wavefonns with aided acquisition

了Sec. 8-6 Rotational Frequency Detector 179

.. t

a "quadricorrelator." Messerschmitt [5] described a digital version which he ca11ed a “ rotational FD." At about the same time , Afonso et al. [6] published a circuit realizing such a frequency detector.

The rotational FD circuit in Fig. 8一15a generates pulses corresponding to cycle slips-negative puls的 at v~for úlo < ωi and positive pulses 欲地forω。 >ωi﹒ These charge or discharge the capacitor in the loop filter to bring úlo equal toωz﹒的 in Eq. (8-30) , the magnitude of the charging current Î3 is 1 = (v H - Vd2月. To avoid jumping over the lock-in range , we again choose I Liωcl =ωL as in Eq. (8-33). Then in a similar development to that of Eq. (8-34) , we have here

1 = ωLc!Ko'T (8-38)

where ωL depends on the particular PD that is used. The designer is free to choose 'T here , but it must be bounded by

T 三三 2τ/ωeo (8-39)

道，

t

so the pulses at 時or 也 don't overlap. The basis of detecting cycle slips is to divide the phase of the VCO signal v 0 into

four quadrants and sample the quadrants with the pulses of the input signal Vi. The sequence of quadrants tells the direction of cycle slips. The clock Vo is delayed by 90 deg. to forrn the signal v~. These two signals define four quadrants of phase in which V 0 and v~ are 1,1, then 0,1, then 0 ,0 , then 1,0 , where high and low logic levels are represented by 1 and O. The signal Vi in Fig. 8-15b is RZ data with a “ mark" represented by a pulse and “ space" represented by a missing pulse. Ifω。 is greater than ωi (ωc > 0) , then the rising edges of vi advance through the quadrants , causing A and B (the sampled quadrant) to be 1,1, then 0 ,1, then 0 ,0, then 1,0, etc. (see the sequence in Fig. 8-15b). This is clockwise rotation through the quadrants in Fig. 8-15c. We wish to generate a pulse at vh every time the heavy line in Fig. 8-15c is crossed in a clockwise direction (a “ D cycle slip"). This corresponds to Vi sampling the quadrant 0,0 immediately after the quadrant 0,1. The circuit in Fig. 8-15a remembers the previous quadrant as C and D (the previous va1ues of A and B). Then a D cycle slip corresponds to the state, A,B,e,D = 0,0,0,1, or the truth of the Boolean expression A'B'C'D. This is realized by an AND gate in Fig. 8-15a which produces a pulse at F for every D cycle slip. A monostable multivibrator stretches each pulse to a width of 'T at vh. Similarly, a counterclockwise (or U) cycle slip produces a pulse at 吋.

If the difference ωc between ωi and ω。 is too great or if there are too many sequential pulses missing from the data signal 川， it is possible for the circuit to miss some vh pulses when Vi jumps ov巳r either the 0,1 quadrant or the 0,0 quadrant. Even worse , the sequence of the sampled quadrants may appe訂 to go backwards , gerierating some spurious v~ pulses. Letfu be the average rate of v~pulses ， and letfD be the average rate of vhpulses. For the case of all-ones data (no V; pulses are missing) , fu - fD is given by the function

181

g(ωc) in Fig. 8-16. For 0 <ωc< ω/4， aIl D cyc1e slips are detected, and there are no U cyc1e slips.

(8-40a)

As ωc goes beyond ω片， the probability of jumping over the 0 , 1 quadra~t or the 0 ,0 quadrant increases (fD decreases) until no cyc1e slips are detected for ωc 叫2:

(8-40b)

For ωc> ω/2 ， aliasing makes the sequence of sampled quadrants appear to go backwards , and pulses start occurring on V 'u (fD = 0, andfu increases). g(ωc) becomes positive, and the FD pushes out rather than puIling in. Therefore , the puIl-in range for aIl-ones data is

0<ωc< ω/4

ω/4 三 ωc 三 ω/2

一fD

一 ω/4τT +ω)2τT;

g(ωc) =fu - fD =

一 ω)2τ;

Rotational Frequency Detector

g(ωc) =

Sec. 8-6

?!l

的

Vo

(8-41)

To find the pull-in time for aIl-ones data , we can proceed as in the development of Eq. (8-35) by approximating the time derivative with

ω'p ω/2 (a)

時

dw)dt = I ð.ωcl(fu - fD) = ωLg(WJ

Using the expressions for g(ωc) given in Eqs. (8-40a) and (8-40b) , choosing I ð.ωcl=ωb and integrating between the appropriate limits as in the previous section, we find )\\?\\i;\\;\;\l\\?\A;\;

;\Ai \1? \13 、;\;一九\tlx?\丸。

v o

ABCD

' Vó

(8-42a) O 三 ωeo 三 ω/4了~ = (2τ/ωL) t'n(ωedωL);

(8-42b)

All-ones data is not interesting in itself, but it models a sinusoidal carrier. Even for a noisy carrier, the FD misses few ofthe cyc1es (pulses) , and the g(ωc) characteristic in Fig. 8-16 applies. Messerschmitt [7] used a rotational FD to acquire lock with good results for signal-to-noise ratios as low as 15 dB.

When Vi is random data, the effect of not detecting cyc1e slips and detecting apparently reversed cyc1e slips is aggravated due to the many missing pulses. For all-ones data [to which g(ωc) applies] the spacing of the Vi pulses is T = 27T/ωi' For random data, the probability is 1/2 that the spacing is T. The probability is 1/4 that the spacing is 2T, which has the effect of a frequency error of 2ωC" The probability is 1/8 that the spacing is 3T , which has the effect of a frequency error of 3帖， etc. Therefore,fu - fD for random data is given by

g'(ωc) = (8-43)

ω/4 三 ωeo 三ω/2

ZI2n l g(胸J

Tp = (2τT/ωL) t'n[ω?/8ωL(ωi - 2ωeo)]; F司一

ji----一同一一一一一一一月!• 7•• T • j t

FIGURE 8-15

T=27r/ωi

(c)

Acquisition aid for clock recovery

(b)

J-2T一斗F

182

fu-fD

Wj

8π

Wj

8霄

Lock Acquisition Chap. 8

。。g'(ωc) = 1:: 2- n - 1g(nωc)

n=l

FIGURE 8-16 Net pulse rate for acquisition aid in Fig. 8一 15

This function , plotted in Fig. 8一16 ， agrees with the experimental data of Afonso et al. [8]. For ωc< ω/20 ， practically no cycle slips are missed , and g' (ωJ=ωcf21T. But for ωn =ω/4， for example , a net of only 22% of the cycle slips are effective, and g' (ωJ J 0.22ωcf21T. Beyond ωc ω/3 ， the pull-in effect is so small as to be not reliable or useful Therefore , the pull-in range for random should be practically taken as

ωpzω/3 (8-44)

且目der to get an expression for the pull-in time for random data , we make a (conservatIve) piecewise linear approximation:

g'(ωc) = 一 ωcf21T; 0 三三 ωc 三三 ω/20 (8-45a)

g'(ωc) = 一 ω/40τ; ω/20 三三 ωc 三三 ω/3 (8-45b)

To find the pull-in time for random data, we again begin with the approximation

dwcfdt = /ilωc/(fu - fD) = ω'Lg'(ωc>

References 百83

and substitute into it the expressions for g' (ωJ in Eq. (8-45). Integrating between the appropriate limits yields

Tp = (2τ/ωL) fn(ωedωL); O 三三 ωeo 三三 ω/20 (8-46a)

了~ = (2τ/ωL) 如(ωβ0ωL) + (40τωeof卅一 2τ)/ωL; ω/20 三 ωeo 三 ω/3 (8-46b)

EXAMPLE 8-6

A PLL is used to recover a clock from random data. The phase detector is a two-state PD with a sawtooth characteristic, and K = 8 krad/s. The VÇO has a gain of Ko = 0.2 Mrad/s/V , and the capacitor in the active loop filter is 0.1μF. For ω10 Mrad!s and ωeo 2 Mrad/s , choose T and !, and find the pull-in time.

For a two-state PD ， ωL τK = 25 krad/s. In accord with Eq. (8-39) , we maximize T by choosing T 2τ/ωeo 3.14 μs. Then from Eq. (8呵38) we get the minimum Tp

[given by Eq. (8-46)] by designing for! =ωLc!KoT = 4mA. For ωi = 10 Mrad/s ， ωeo

2 Mrad/s > w/20 , and Eq. (8-46b) gives Tp 0.75 + 0.75 = l.主旦旦﹒

REFERENCES

[1] D. Richman,“Color-carrier Reference Phase Synchronization Accuracy in NTSC Color Television," Proc. IRE , vol. 43 , pp. 108-33 , January 1954.

[2] S. A. Meer, 'ιAnalysis of Phase-Locked Loop Acquisition: A Quasi Stationary Approach ," IEEE International Convention Record, vol. 14, pt. 7, pp. 85一106 ， 1966.

[3] F. M. Gardner, Phaselock Techniques, WiIey: New York, 1979 , pp. 151-56. [4] Richman,“Color-carrier Reference Phase Synchronization." [5] D. G. Messerschmitt,“Frequency Detectors for PLL Acquisition in Timing and Carrier

Recovery," IEEE Trans. on Communications , vol. COM-27 , pp. 1288-295 , September 1979

[6] J. A. Afonso , A. J. Quiterio, and D. S. Arantes,“A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery," IEEE National Telecommunications Conference , pp. 14.4 .1一14 .4 .5 ， November 28-29 , 1979.

[7] Messerschmitt,“Frequency Detectors." [8] Afonso , et al.,“Phase-Locked Loop."

γ!!!

CHAPTER

9

AND MODULATION

DEMODULA TION

Some PLL applications that involve modulating and demodulating a carrier were described briefly in Chapter 1. In this chapter, we willlook more in depth at the following: phase modulation, phase demodulation , frequency modulation, and frequency demodula且tion. In each case the proper PLL bandwidth K will be determined , and the necessary ranges of the PD and the VCO will be considered. Until now we have ignored the highfrequency component of the PD output (the difference between Vd and Vd)' We will see that it can cause spurious phase and frequency modulation.

9-'可 PHASE MODULATION

Let the modulating signal be m仰 with a bandwidth Bm' where Bm is in Hz. The objective is to modulate the phase 80 of a ca虹ier so that 80 (t) = α m(t) ， where αis some constant. This can be done by adding the signal m(t) into a PLL after the PD , as in Fig. 9-1a. The input to the PLL is a carrier V; = sin(ωρwith no phase modulation (8; = 0). If the PLL bandwidth is great enough , V d can follow m(t) to effectively cancel it [v d = - m(t)]. But this Vd must be produced by a proportional 80 from the VCO , producing the desired phase modulation.

186 Modulation and Demodulation Chap. 9

m(t)

句 /\I Vc I 昕一一叫 PD ←一-< I; 卜一叫 LF 卜一~ vc。卡寸~ Vo

(a)

m(s)

。。

(b)

I (lolml

1/Kd 。o(s)一一 = ~H(s) m(s) Kd

w

(c)

F!GURE 9-1 Phase modulation

9-1-1 BANDWIDTH, PHASE AND FREQUENCY RANGES

A signal flow graph of the PLL is shown in Fig. 9-1b. We need to ensure that the transfer function from m(s) to (}oCs) has a flat frequency response of sufficient bandwidth. Let the forward gain from m to (}o beA '= F(s)K。心， and let the feedback from (} 0 to m be B '=

Kd . Then from control theory (see PhilIips and Harbor [1] for example) ,

。'o(s)m(s)

A

1 + AB

F(s)Kols

1 + KdF(S)Kols

JSA-cd g叫一叫

“一+

-',A

~~ cd H

I-L K1Kd

s + K (9-1)

Sec.9-1 Phase Modulation 187

where H '= G/(1 + G). H(s) has unity gain with a high-frequency cutoff atω = K. Therefore , (}o(s)lm(s) has a gain of l!K d with a high-frequency cutoff atω = K , as shown in Fig. 9一lc. Then if we design the PLL to have

K 三三 2τBm (9-2)

alI the spectral components of m(t) wi1l be passed with a gain of l!K，的組d

。o(t) = (l IKd)m(t) (9-3)

as desired. Since the input phase (}i is zero , alI of the output phase (}o appears as phase

difference (}e across the PD. Therefore , the output (}o must not exceed the linear range of the PD:

/ (}o/ 三 (}em (9-4)

For example, if a three-state PD is used , the peak (}o can't be greater than 2 'IT. If a larger (}o

is desired, then the range of the PD must be extended by one of the methods discussed in section 4-11 or 4-12. The most common means is to precede the PD with two -':- N frequency dividers , as shown in Fig. 9-2a. The dividers are realized by digital countersbinary counters when N is a power of 2, or programmable counters for other values. The dividers extend the phase range by a factor of N; the extended-range PD has a range of (}em 2τN (see Fig. 9-2b). Then for this extended-range PD , the maximum phase modulation is

/ (}o/ 三 2τN (9-4')

As m(t) modulates 此， it is also modulating Llω。 through the relationship Llω。'= (} o'

Since ω。 =ωi + Llω。， the VCO must have a range of at least

ω。 =ωi ::!:: (} 0 (9-5)

9-1-2 SPURIOUS MODULATION

The disadvantage of using -':- N dividers is that the high-frequency component of V d

is lowered , and it may result in excessive spurious phase modulation of (}o . [This is an undesired modulation not in response to m(t).] The connection between Vd and (}o is iIIustrated in Fig. 9-2c. After the -':- N , the frequency into the three-state PD isω;fN. The low-frequency component of the PD output V d is 叫， which is proportional to (}e- But there is also a high-frequency component Vd - vd with a frequency.

ωd ω;fN (9-6)

189 Phase Modulation Sec. 9-1

(9-7)

The most severe spurious modulation is when V d - V d has a 50% duty cycle，的 in Fig. 9-2c. This corresponds to Vd = Vdm/2 (see section 4-8 on the three-state PD). In practice , ωd is always high enough (> >ω2) that the gain of the loop filter is essentially Kh . Then the deviation of the VCO control voltage is .:lvc Kh(如一 Vd) with a peak-to-peak amplitude of Kh Vdm . The spurious modulation of the VCO frequency is .:lω。 = Ko.:lvc with a peak-to-peak amplitude .:lω = KaKh Vdm . But for a three-state PD with -:- N frequency dividers ,

Td = 2TiN/ωi

The period is Td = 2Ti/ω的 or

F

。e

Vd

Krl= Vdm 一

2πN

Vdm

l 己了1 |i L一一一一一一一一一一一一-J

3-state PD

(b) (a)

(9-8) Vdm 2τNKd Vd-Vd

(see the characteristic in Fig. 9-2b). Then the amplitude of the spurious FM is (for Vd= Vdm /2) T

伽土

(9-9)

The spurious phase modulation 00 is the integral of .:lωo. Therefore , its peak-to-peak rise .:l0 is the area under a positive half-cycle of .:lω。:

Aω= 2τrNKaKhKd = 2τNK 2Td

(9-10)

The resulting triangular modulation of 00 shown in Fig. 9-2c is present while m的 is also modulating 00 • The spurious .:l0 will vary as m(t) increases and decreases the duty cycle of Vd 一句， but it will never be larger than that given by Eq. (9-10) .

.:l0 = (.:lω/2) (T/2) = 付的世/ωz

T，，=~ -wω;/N ÁVc

了几土

9-1-3 SPURIOUS MODULATION WITH A POLE AT 003

The spurious modulation can be attenuated by adding a pole to the response F(s) of the loop filter as shown in Fig. 9-3a. This can be realized by an additional capacitor as in Fig. 3一14. For stability, we require

4ω=κ戶KhVdm

2Td

Area=ÁO A凶。

下旬土

(9-11 )

The roll-off of IFI beyondω= 的叫uces the amplitude of the unwanted waveforms with frequency ωd when ωd> ω3. For ω>ω3 ， the loop filter acts essentially like an integrator:

ω3 三三 4K 。。

Tu土 (9-12)

(see Fig. 9-3a). The worst-case Vd - Vd is shown in Fig. 9-3b with 50% duty cycle , peak-to-peak

amplitude Vdm , and period Td 2TiN/ωz ﹒ This unwanted signal is integrated by the transfer function in Eq. (9-12) to deviate the VCO control voltage:

.:lvc = Khω3J(Vd - .vd)dt

Isl>ω3 F(s) = Khωis; (c)

Spurious FM and PM FIGURE 9-2

mr.'

JFJ

你)，.，守主

κh

ω2

(a)

Vd-Vd

Area=A

Th土

Td=27rN/甜，

Ll. vc

下ω土4ω。

T心止

。。

Tu土

(b)

w

FrGURE 9-3 Spurious FM and PM with pole atω3

Sec.9-1 Phase Modulation 191

Then the peak-to-peak amplitude of ~Vc is Khω片， where A is the area under a positive half-cyc1e of (Vd - Vd): A VdmTi4 仰的2Kiwi [see Eqs. (9-7) and (9-8)]. The spurious F孔1 is ~ω。 Ko~vc with a peak-to-peak amplitude

Aω = KaKhωy4 = KaKh的忱的2Kiωz

= (τN)2K'ωjωz (9-13)

This amplitude is minimized by choosing the smallest ω3 within the bounds of Eq. (9-11): ω3 4K. Then the amplitude of the spurious FM is

~ω= (2τrNK)2/ωi， ω3 4K (9-13')

The spurious phase modulation (}o is the integral of ~ωo. Therefore , its peak-to-peak rise ~() is the area under a positive half-cyc1e of ~ω。:

~() = (~ω/2) (Ti2)/2 = 付的恆的/4ω2

=忱的3(K/ωi)2; ω3 = 4K

(9-14)

(9-14')

Further reduction of ~ωand ~() is possible by making a multiple pole atω3. For each additional pole, the spurious modulation is reduced by an additional factor of ω3/ωd = N，ω3/ωi. For a total of n poles at 的， Eqs. (9-13) and (9-14) become

Aω=τ2NK(N，ω3/ωiY (9-15)

~() = (τ3N2K/4ωJ (NωiωJ (9-16)

With multiple poles ， ω3 must be kept more than a factor of four away from K. Otherwise, the in-band phase of the multiple poles will cause instability. The phase atω = K due to the multiple poles atω3 should be kept less than about 0.5 radian (or 29 deg.).

EXAMPLE 9-1

A carrier with frequency ω10 Mrad/s is to be phas巳-modulated by m(t) = Vm sin(ωmt)

to produce (}oCt) = 7τsin(ωmt)， where ωm 10 krad/s. The phase detector is a three-state PD with Vdm = 2.5 V together with two +N frequency dividers. Choose N , Vm, and the PLL bandwidth K. Find the range required of the VCO , and find the spurious PM amplitude ~(). Add a pole atω3 in the loop filter if necessary to keep Llθless than 1 % of the peak (}o .

Equation (9-4') requires a minimum N = 1. Then Kd = Vdm/27rN = 0.1 V/rad. For a peak 恥的 of 7τradians ， Eq. (9-3) requires a peak m(t) of V m 7甘Kd 三二三 V.

Equation (9-2) requires K > 27rBm ωm 10 krad/s. Choose K 20主且也s. The


frequency modulation is Llω。 =()o=7τωm COs(ωmt) = (220 krad/s) cos(ωmt). Then Eq. (9-5) requires a VCO range of ω。 o :t: 0.22 Mr吋/s.

From Eq. (9-10) , the spurious PM is Ll() =仰的全/ωi=(τ4)2(20 krad/s)110 Mrad/s = 0.316 radian~. This is slightIy greater than 1 % of the peak ()o of 22 radians. With a pole atω3 = 4K = 80krad!s, Eq. (9-14')gives Ll() = 2仰的3(K/ωi = 2(τ4)3(0.02110)2 = 0.016 radians.

9-2 PHASE DEMODULATION

In phase demodulation , the modulated phase ()i of a carrier is converted back into a voItage m(t) α你)， whereαis some constant. The demodulation is preformed by locking a narrow-bandwidth PLL to the modulated carrier Vi sin(ωit + ();). If the bandwidth is small enough , the VCO phase ()o won't fo l1ow the phase modulation , and ()o

serves as a reference against which to compare ()i. The PD compares ()i against 見， and the PD output Vd is the demodulated output m(t) (see Fig. 9-4a). A low-pass fiIter (LPF) is usually necessary to remove high-frequency components from Vd' leaving Vd m(t).

A signa1 f10w graph of the PLL is shown in Fig. 9-4b. The low-pass filter has a transfer function F'的 with an in-band gain of unity and a cutoff atωLP ﹒ For an active loop filter, the transfer func tÍon from ()i to ()e is H eCs) = S2/(S2 + Ks + K，ω2) ， and the transfer function from ()e to m(s) is KdF'(S). Then

(s) 一一 = KfleCs)F'(s) = ();(s) 它

的

(a)

(b)

?kd? F'(s) (SL + Ks + K，ω2)

Vo

FIGURE 9-4 Phase demodulation

(9-17)

。。

可r

Ii,{t)

v,Æ t)

m(t)

Sec. 9-2 Phase Demodulation 193

The frequency response of Im/()il is il1ustrated in Fig. 9-5c. It has a mid-band gain of K，的 alow-frequency cutoff at K , and a high-frequency cutoff atωLP (compare the response IHel in Fig. 3-16b).

A typical time waveform for 劑。 and its spectrum are shown in Fig. 9-5a. The bandwidth of ()ρ) is from Bml to B m2 . The whole PD output Vd is actual1y a pulse-widthmodulated signa1 with a “ carrier" frequency ωd and low-frequency component Vd' as shown in Fig. 9-5b. The spectrum viω) is also shown; it has upper and lower sidebands around ωd and a baseband component that is the spec甘um OfVd . To recover the baseband component, it is clear from the response Im/蚓 in Fig. 9-5c that both of the fo l1owing bounds must be satisfied:

Vd(t)

K 三 2'ITBml

2τBm2 三三 ωLP < ωd - 2τBm2

何

')鬥

Vd(ω)

(b)

!可\

m，w，) 鬥

(9-18)

(9-19)

口ωd

凶d- 27rBm2

(linear) ... w

-u

-w

-w

FIGURE 9-5 Phase demodulation waveforms and spectra

194 Modulation and Demodulation Chap.9

In some applications , the low-pass filter must be of high order (such as a fifth-order Butterworth) if the bounds in Eq. (9-19) are tight. If Eqs. (9-18) and (9-19) are satisfied, then

m(t) = vþ) = Kß;(t) (9-20)

as desired.

Since (}o = 0, (}e(t) = {}ρ). Then for {} e to stay in the linear range of the PD , we must satisfy

I (};(t) I <見m (9-21)

As with phase modulation in the previous section , it may be necessary to extend the PD range ifθ;(t) is large. Leave enough margin to avoid faIse lock during acquisition if a three-state PD is used (see section 4-13).

EXAMPLE 9-2

A digital data signal has accumulated phase jitter, and the recovered cIock signal has this same JItter ot(t).(JitFcr and dock mcovery amdiscussed in chaptsr l0.)The baud of the data is 1.544 Mb/s , so the frequency of the cIock isωi = 2τ( 1. 544 MHz) = 9.7 Mrad/s. The spectrum of the jitter {}; extends from Bm1 10 Hz to Bm2 = 40 kHz. The peak jitter is 5 cycIes , or 101T radians. Design a PLL 的 demodulate the cIock jitter so it may be observed and characterized. The low-pass filter is to attenuate the out-of-band components by at least 50 dB.

The largest PLL bandwidth which satisfies Eq. (9-18) is K = 2τB~l = 62.8 rad/s. This is very small: K ω;1 154000. Therefore , the VCO must be a c句stal志函函VCXO to avoid injection problems (see section 5-9). This g記atly res甘icts the VCO range , but for phase demodulation the required VCO frequency range is vanishingly smalI.

Equation (9-21) requires that {}em > 10τ. For a three-state PD , {}em is only 21T. We will try extending the phase range with -;-N frequency divider~ ， as in Fig. 9-2a. To avoid false lock with a three-state PD during acquisition, it is necessary to make the PD range even gFeaterthmthat Fvcn by Eq.(931).For our application, Eq.(4-47)gives the bound I{}el <τωavoid fal臼 lock when there are no freque配y dividers. This may be extended to incIude the use of frequency dividers as follows:

I{}el < N官

where {}e = {}; for our application. Therefore , we choose N = 11 so that N甘 >10τ.For the extended-range PD in Fig. 9-2a，伽 detector frequ已叫 ISωd ω;lN =

(9.7Mrad/S)/II=882krad/s.Now, 2TrBm2=25I krad/s.Then Eq.(9-19)requires the

Sec. 9-3 Phase Demodulation with No Carrier 195

low-p的s filter bandwidth to satisfy 251 krad/ s 三 ωLP < 631 krad/s. Ifω'LP = 251 krad/s , aseventh-order filte! will provide an attenuation of (63 1!251? = 56 dB at 631 krad/s.

We will now try a design that doesn't require such a high-o吋er low-pass filter. Let the phase det叫or range be extended by using an也旦旦PD. According to Eq. (4-34) , {} em

for an n-state PD is (n - 1)1T, and Eq. (9-21) requires (n - 1)可T > 101T. But it is necessary to make n even greater than this to avoid false lock. The condition for avoiding false lock given by Eq. (4-47) can be extended to an n-state PD as follows:

I{}el < (n - 2)τ

where {}e = {}; for our application. Then to satisfy (n - 2)τ>1加， we choose 旦二 13.A

13-state PD requires a lO-stage shift register (compare the six-state PD in Fig. 4-15). The advantage is that the detector frequency is higher now:ωd- ω; = 9.7 Mrad/s. Then Eq. (9-12) requires the low-pass filter b叩dwidth to satisfy 251 krad!s 三 ωLP < 9 .45 Mrad/s. Ifω'LP = 251 krad/s , a~econdcorder filte! will provide an attenuation of (9450/251? = 63 dB at 9.45 Mrad/s. This design trades off a more complex PD for a simpler low白pass

filter.

9-3 PHASE DEMODULATION WITH NO CARRIER

For some phase modulation , the carrier (the spectral component atω;) actually disappears. Then there is nothing for the PLL to lock onto , and the phase demodulation process described in the previous section won't work.

A simple example of phase modulation for which there is no carrier is {}ρ) = xsinωmt， where x 2.4 radians and ωm is some modulation frequency (see Fig. 9-6a). Then the input signal is

v;(t) sin(ω;t + (};) sin(ωit + x sinωmt)

= lo(x) sin ω;t+ 言。 ln(x) 血(ω;+ 削mt) (9-22)

(See Lathi [2] for a discussion ofthe BesseIfunctions ln.) For X = 2.4 radians , lo(x) = 0, and the carrier atω; disappears. Figure 9-7 shows the spectrum of V; for x = 2.4 radians; there is no component atωz一-only the sideband components from the second term in Eq. (9-22). The phasor representation of V; in Fig. 9-6b gives some understanding of why the carrier disappears. The many phasors show 1'; at many instants of time , but the carrier (with fixed frequency and phase) is the average of these positions over time. By symmetry , the average points neither up nor down , and for {}j max 2.4 radians , the average points neither left nor right. Therefore , the average. is zero (no carrier).

A more common example of phase modulation for which there is no carrier is phase-shift keying (PSK). For binary PSK , data is transmitted with {}; =τ!2 representing


(Ji .l (rad)

2 .4

-2.4

w (~

FIGURE 9-6 Sinusoidal P此1 with no carrier

a “ mark" and ()i =一τ/2 representing a “ space." Figure 9-8a shows an example of oρ)for random data.The corresponding phasors for vz are shown in Fig.98b.If the probabilities of a mark and a space are equal , the average of the phasor over time is zero (no carrier).

If a phase-modulated Vi like that in Fig. 9-6b or Fig. 9-8b is applied to the input of a PLL, the-output phasor vo will now vrif the bandwidth k is large enough.But if the bandwidth IS very nauow (as for phase demodulation) , Vo tdcs to follow the average of 吭，which doesI1,texist-The PLL fails to lock, and phase demodulation is not possibleusinp the si中Ple tech-iqu?S in theprcviousection.However, itispomblctogeneMeacardJ by using a nolinearity-by squaring Vi'

9-3-1 SOUARING Loop

The modulated signal for the PSK in Fig. 9-8 can be represented by

Vi cos[ω/ 一(甘/2) m(t)] (9-23)

v，{ω)

for ωm=ωi/ 1 0

Wi

FIGURE 9一7 Spectrum of signal with PM in Fig. 9-6

W


(Ji i (rad) mark Vi

1r/2 。i

一 1r/2space

space

w (~

FIGURE 9-8 PSK modulation with no carrier

where m(t) is the modulating data signal with values of :i: 1 (see Fig. 9-9a). As m goes from + 1 to -1 , it changes the phase of the carrier by 1T radians. But this is just an inversion of the signal. Therefore , an equivalent representation of the phase modulation is

Vi m(t) sin ωit (9-24)

An example illustrating the phase reversals in Vi is shown in Fig. 9-:9b. The product of any sinusoid with Vi given in Eq. (9-24) has zero average because m(t) has a zero time average. Therefore, a PLL cannot lock to Vi.

If we square the modulated signal , we get

V/ m2 sin2ω/ = O.5(m2 - m2 cos 2ω/) (9-25)

(see Fig. 9-9c). It is the carrier portion of v/ we are interested in , so we throw away the first term in Eq. (9間25) and use v/ = - m2 cos 2ω/. Since m2 is always positive , it has a nonzero average, and there is a strong spectral component at 2ωi--double the carrier frequency.

A scheme for recovering the carrier from Vi by using a squarer is shown in Fig. 9-10. After bandpass filtering to limit the noise , Vi is squared, doubling the frequency to 2ωi [see Eq. (9-25)]. A PLL locks onto this component , and provides Vo = sin(2ωit -()e) , where ()e 0 in steady-state (see the waveform in Fig. 9-9d). A --;.- 2 frequency divider reduces the 2ωi to the carrier frequency ωi (see the waveform vo' in Fig. 9-ge). This is the recovered carrier, which is used to demodulate Vi. The multiplier in Fig. 9- lOa does the job of demodulation performed by the PD in Fig. 9-4a. The waveform of the product Vi X V 0' 三的 is shown in Fig. 9-9f. Low-passing recovers the baseband component m. The cutoff frequency of the low-pass filter must be great enough to pass the signal m:

ωLP 三三 21TBm (9-26)

where Bm is the message bandwidth in Hz.

月7

一 1

(a) 的

的=m sin Wjt

phase reversal

(b)

2 V

F Frequency is 2:旬， no phase reversal

m

(c)

1AAAAAAAAAAAAAðððAAAðA^^^^^^^^^^^^^^ ~VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVv (d)

Frequency is ω，

YnnnDDDOODoooooono JUUDDDDDDDUUUUUUUb (e)

(f)

FIGURE 9-9 Waveforms for sauaring loon

-t

.... f

可F

的


m SJn Wjt

(a)

Vd stable

。e

(b)

FIGURE 9-10 Squaring loop to demodulate PSK

Note that the PD output in Fig. 9- lOa is Vd = sin 2()e. This PD characteristic is shown in Fig. 9- lOb. We have been assuming that the PLL settl郎的 the stable point at ()e = O. But there is another stable point at ()e = τ. If the PLL happens to settle at () e = 甘，

then the demodulated output m cos ()e is 一 m rather than m. This ambiguity cannot be resolved by the demodulation circuit; some pattem in the data must tell which phasor in Fig. 9-8b is “ up."

It is the nonlinearity of a PD characteristic that gives rise to the cycle slips discussed in section 6-8. The nonlinearity of the characteristic in Fig. 9-9b comes at half the ()e

compared with a normal sinusoidal characteristic (see Fig. 4-lc). Therefore , a squaring loop encounters cycle slips at lower noise levels. The guideline for negligible cycle slips was given in Eq. (6-66) 的。o rms 三 0.3 radians. For a squaring loop , the same performance requires

。o rms 三 O. 15 radians (9-27)

where ()o is the phase of v~ with noise present at the input.

會芳: 200 Modulation and Demodulation Chap. 9

In section 9-2, the bandwidth K of the PLL had to be small enough that 80 didn 't try to follow 8;. In a squaring loop , there is no such requirement since the signal v? into the PLL doesn't have any phase modulation. However, it is still desirable to keep K small to reduce the 80 due to n哇~. If squaring were not involved , then Eq. (6-29) would apply, giving the phase noise 8} = 2BLNjV? It can be shown [3] that the squaring causes the phase noise to be greater by a factor (1 + B/vjV，力:

存 = (2BLNjV?) (1十 B/vjV?)

= (2BLNjVi力 (1 + 1!2SNR;)

(9-28)

(9-29)

where B; is the noise bandwidth of the bandpass filter at the input. If B i could be reduced to zero , there would be no phase noise penalty for the squaring. But to pass the modulation , it is necessary to make

B; 三三 2Bm (9-30)

where Bm is the bandwidth of the baseband modulation.

9-3-2 REMODULATOR AND COSTAS loop

Two techniques similar to the squaring loop are the remodulator and the Costas loop [4] shown in Fig. 9-1 1. They have the advantage of not doubling the carrier frequency , which relaxes the speed requirements of the circuit components.

Consider first the remodulator in Fig. 9-11a, which is more similar to the squaring loop. Rather than multiply m sin ω;t by itself (squaring) , it multiplies m sin ω;t by m. This gets the desired m2 factor without doubling the frequency. The input to the PLL is m2

sin ω;t， which does have a spectral component atω; that the PLL can lock onto. The recovered carrier (after a phase shift of 一 τ12) is used to demodulate V; exactly as with the squaring loop.

Before steady-state with 8e = 0 is reached , the recovered signal m at the output is actually m cos 8e .This function of 8e causes the PD output to be Vd = sin 28e , and the PD characteristic is again that shown in Fig. 9一lOb. Therefore , 8e = τis also a stable point , producing a demodulated signal - m at the output. As with the squaring loop , this ambiguity is unavoidable.

Although the remodulator doesn't involve squaring, it has been shown [5] that the phase noise at the PLL output is still that given in Eq. (9-28).

The bandpass filter at the input limits the noise. From Eqs. (9-28) and (9-30) , the optimum bandwidth is Bi = 2Bm. But this small a bandwidth is often not attainable due to physical limitations on the Q of a resonant circuit, where Q ω;l2B;. This limitation is avoided by the Costas loop.

The Costas loop shown in Fig. 9-11b is mathematically identical to the remodulator. The order of multiplication has merely been reversed by putting the PD ahead of the multiplier (the PD is actually a multiplier too). The advantage is that the bandpass filter

γ


msin ω;t

的

m cosOe (a)

何lsin ω;t

的 l/

m cos Oe

(b)

FIGURE 9-11 Remodulator (a) , and Costas loop (b)

can be replaced by a lowpass filter (LPF) after the PD brings the signal down to the baseband. The LPF must pass the modulation , so its cutoff frequency must satisfy the same constraint given by Eq. (9-26) for the LPF at the output:

ωLP 三 2τBm

Since the LPF is taking the role of the BPF in the remodulator, 2ωLP replaces B; in the

expression for the phase noise:

存 = (2BLNjV?) (l + 2ωLplÝ月2) (9-31)


[compare Eq. (9-28)]. It is best if the two LPF cutoff frequencies are identical so that the delay of the m factor is the same in the signals m sin ()e and m cos ()e arriving at the multiplier.

Note that the LPF is inside the PLL. Therefore , it constitutes a pole atω3' 的discussed in section 3-7. Consequently , the same rules apply toω凹的 toω3: stability of the PLL requires that

K 三 ωLPI4 (9-32)

The demodulator circuits shown in Figs. 9-9a and 9-11 apply to binary PSK. PSK with more phases such as quatemary PSK requires more complex circuits along the same lines. [6]

9-4 FREQUENCY MODULATION

A signal m is to modulate the j均quency ωo ofthe ca叮ier so that ω。 =ωi + Llω0' where Llω。(t) = αm(t) , and αis some constant. This can be done in simple applications by applying m(t) to a VCO 個ot in a PLL) so that Llω。 = K~(t). But some applications require more accurate con仕01 of the average frequency (carrier). For example , the FCC requires that commercial FM stations maintain their carrier frequency to within 0.001 % of their assigned frequency. In these applications , a PLL can be used to lock the average frequency to an accurate reference such as a crystal oscillator.

Let the spectrum of m extend from Bml to Bmz, as shown in Fig. 9-12a. Figure 9-12b shows the configuration of a VCO modulated by m(t) with a PLL locking the average frequency to the constant frequency ωi of the reference signal Vi. If the PLL bandwidth is too large , the loop fi1ter output Vcd will follow and cancel m的 in its attempt tomatch ω。 toωi. If the bandwidth is small enough , only the average ofω。 is matched toω，.

A signal flow graph of the PLL is shown in Fig. 9一12c. We need to ensure that the transfer function from m(s) to Llω。 has a flat frequency response over a sufficiently wide range. Let the forward gain from m to Llω。 be A = Ko , and let the feedback from Llwo to m

be B = KdF(s)/s. Then

Aω。(s)

m(s)

A

1 + AB

K O

1 + KdF(s)K)s

Kj Ko 一 = Kjfe(s) 屯。 (9-33)1 + G(s) (s +ω2)(S + 的

where He == 11(1十 G). But H eCs) has unity gain with a low-frequency cutoff atω = K. Therefore , Llω。1m has a gain of Ko with a cutoff at ω = K , as shown in Fig. 9一12d. Then if we design the PLL to have a bandwidth that satisfies

K 三 2τBml (9-34)

Sec. 9-4 Frequency Modulation

m們

Bm1

(a)

m(t)

的

(b)

m(s)

(c)

l .:lω。Iml (叫/s!v)

κ一

Bm l

(d)

FlGURE 9一12 Frequency modulation

the spectrum of m wi1l be passed，組d

Aω。(t) = K~(t)

as desired. By definition ,

。I(}(t) 三 f Llω。(t) dt

膏，

f

v p

f

203

(9-35)

204 Modulation and Demodulation Chap. 9 Sec. 9-5 Frequency Demodulation 205

10e的1 = If ßω。(t) dtl 三 Oem (9-36)

the injection problems-However, the239th hamorlic of the 2.5105-Mrad/s square wave is 600M叫s， and伽∞mponent c側的 some inj叫ionmtheVCO Forasq間ewthe nth harmonic is un of the fundamental amplitude, so the Injected signal VI is l/239as large.This reduces thc injection constant kf=(ω0)2Q) <'行!Vl) by 11239 , and our rule of thumb becomes K > ω/2 ，390 ，000. This allows the design value K = 314 rad!s.

The resonant VCO has k=5Mrawuv.From Eq.(9-35) , the voltage neces produce the modulation ßω。三 2τr(75 kHz) cos ωmt is m(t) ßω)Ko = (份94 mV)

C…:已L;LLt刊th叫1Then V

dm = VH 一 VL = 1 V , andKd = Vd.的，j2τ甘rN = 1/4801官T = 663μV!rad (se巴 Fig.9-

2b) 咐::;1:認iiEJ;lzzrt叫叮叮可避:Then fkOIn Eq.(9-131the spudous frequency modulation is Aω= (2τN的一/ωi = 373 ad!s. Tl心州 0.049晰ro (仙仙O凹r 一 6“8 dB酌) of叫t伽he川ep阱e閻叫恥a站怯kι峙-k尬ra吋dl旭s = 94位2k缸ra叫dl旭s. Further r昀ed由uc叫世肋O∞n would r跨.equ叫ir昀e another pole a瓜t ω3

The pull-in time for a three-state PD with ÷N frequency diviSIonmgiven by Eq.

(8-28'):

Since for our application here Oi = 0, then Oe = - 00 • Then to stay in the linear range of the PD , we need to satisfy

where Oem is the limit of the linear PD range. If the range needs to be extended , -7 N frequency dividers can be used as in Fig. 9-2a. For large N , the spurious frequency modulation ßw may be excessive [see Eq. (9-9)]. A multiple pole in the loop fiIter at ω3 helps reduce ßω[see Eq. (9-15)].

Another way to extend 0 em to meet Eq. (9-36) is to use an n-state 凹， asinFig. 4-l3.

Then there are no frequency dividers (N 1), and there is no spurious frequency modulation. [Equation (9-9) indicates ßω 21TK for N 1, but this variation is all within one cycle of ωsince ωd ωi.] Sometimes a combination of -7 N frequency dividers and an n-state PD provides adequate performance with the simplest circuitry .

EXAMPLE 9-2 Tp

= (ωe)K - 2τ的/甘Nω2 (9-37)

A commercial FM radio station wishes to frequency-modulate a 95.5-MHz carrier with a 50-Hz sine wave so that the peak frequency deviation is 75 kHz. That is ， ω

21T(95.5品位fz) = 600 Mrad/s ， ωm = 21T(50 Hz) = 314 rad/s , and ßω。= 21T(75 kHz) cos ωmt = (471 krad/s) cos ωmt. A PLL performs the frequency modulation using two -7 N frequency dividers to extend the range of a three-state PD as in Fig. 9-2a. A crystalcontrolled VCO is available with Ko = 100 krad/s!V, and a resonant VCO is available with Ko = 5 Mrad/s!V. Find the necessary modulation voltage m(t). Design Kh' ω2 ， and ω3 of the loop filter so the spurious modulation is at least 60 dB below the desired modulation. Find the acquisition time Tp for ωeo = 0.05ω30 Mrad/s.

From Eq. (9-36) , the effective phase modulation is

To minimize 耳， we pick 凹的 large as possible:ω2 = KI4 = 互型Is﹒ Then for weo = 30

Mrad!s，耳= 1.丘旦旦﹒

9-5 FREQUENCY DEMODULATION

oþ) = 471 krad/s

。}m

sm ωmt = 1500 sin ωmt

The frequency of a caETier has been modulated with some variation Aωρ) that is limit巴d to

a bandwidth Bm (see Fig. 9一13a). The objective of demodulation is to produce a

proportional voItage m(t) αAωρ) ， where αis some constant. The configuration of a

PLL used as a frequency demodulator is shown in Fig.9-13b.If the PLL bandwidth is

great enough，位1e VCO frequency will follow the input frequency , and Aω0= ßωi. But

l ω Knvr, So Vc = ß ω 爪 , which is the desired d伽e位凹mo0

w e ;

一get叫t由h血i拯s 昀削s釗叩u仙no昀叫f臼ormally fj仕rorωI叫

t缸ra組nsfe叮rft曲i.m缸1芯ct討ionfromßω叫i tωoV抖cc祖 be s紀ee凹ni泊n three stages: 0島O/ßω叫i = 11均S ， O)Oi 三 H(s吋)， and

V几νJOo slKo. Then t由he product of the three s仗tages IS

K 三三 2τBm (9-38)

ill---

Then the range of the three-state PD must be extended to 2τN > 1500, requiring N =

239. To satisfy Eq. (9-34) with the highest K possible , let K = 314 rad/s. This is a very low bandwidth: K = ω/1 ，900 ，000. Only a crystal-controIled VCO (or VCXO) can avoid injection problems under these conditions [see Eq. (5-33)]. However, a peak-to-peak deviation of 2 x 471 krad/s 942 krad/s for ßω。 is 1570 ppm of ωi = 600 Mrad!s , which exceeds the Iinear range of most VCXOs (see Fig. 5-l3 for example).

The rule of thumb for a resonant VCO is K > 叫/1 0，000 (see Eq. (5-33)]. We can improve on this rule by eliminating the -7 239 that divides the 600-Mrad/s Vi down to 2.5105 Mrad/s (see Fig. 9-2a份) and providing a 2.510仿5PD. This eliminates the 600 Mrad/s signal that was "leaking" into the VCO and causing

VJßωi = (l IKo) H(s)

with a fIat gain of lIKo out toω = K (see Fig. 9- l3d). To pass the whole spectrum of ßωt

we reqmre

γ

207 Frequency De鬥lodulationSec. 9-5

But to maintain lock in the presence of random FM , an even greater K is required:

7τ B_ 6.ωI r......." k 三 δ

J3 ω2 (9-39)

for a sinusoidaI PD characteristic [see Eq. (7-34a)]. Therefore, a lower cutoff at fLP is provided by a low-pass fiIter to better limit noise. Let the transfer function of this fiIter be F'(s). Then

A

且Il--FIli--L

) 4' ，先們

凶A

-f

(9-40)

A freque虹y response for 1m! 6.wi l is show叭n Fig. 9-13d for the case of a high-order lowpass F'(s) with a sharp cutoff atfLP. As in the bound for K in Eq. (4-38) , we also require

丘p 三 Bm (9-41)

K!KA 一一.--VTT F' (s) s + K

H(s)F'(s) = K O

m(s)

Aωi(S)

(a)

Then aII the frequency components of 6.ωi are passed , and

(9-42)

as desired. A noise component n(t) at the PLL input causes random frequency modulation that

we wiI1 caII the frequency noise ωn(t). The standard practice is to limit this noise with a bandpass fiIter before the PLL. The spectral density of n(t) has power density No and noise bandwidth B; as shown in Fig. 9-14a. The noise power is given by n2 = Nßi. As showh in sectionι8 ， the power density of the phase noise 8n is φ8n = 2Nj肘， where Vi is the amplitude of the carrier Vi. Since ωn(s) s8n(s) , the power density spectrum of the frequency noise is

m(t) = (1 !Ko)6.ω正t)

(9-43)

outto B/2 (see plot in Fig. 9-14c). The p側ion of可 that gets through the low-pass fiIter is the area under the curve out to f = fLP . This area is minimized by the lower bound of Eq. (9-41): fLP = Bm . Integrating Eq. (9-43) from f = 0 to f = Bm,

φωn=ls|2φ8n = (2τrf)22Njvf

m(s)

虫。ω

A

(b)

(c)

(V/rad/s) [ml<l的|

[vcl <lω;[ I/ t<.。

fLp'?:Bm

(9-44) 可 26.3 Bm3NjVf 13.2 Bm3!BiSNRi f fLP Bm

where the carrier-to-noise ratio is (d)

(9-45)

(9-46)

SNRi 三早早 V;!2Nßi

The signal-to-noise ratio after demodulation is

SNRo 三 (6.ωi rms)2!可

Frequency demodulation FIGURE 9-13


(a)

1'en

2No/v"f

8;/2 f

(b)

l'ωn

(27!"f)21'en

\/1 Area=ωi (portion that gets through LPF)

.. fLP 8;/2 f

(c)

FIGURE 9-14 FM frequency noise

EXAMPLE 9-3

A carrier is frequency-modulated with a signal that has a bandwidth Bm 15 kHz and causes an effective peak frequency deviation of 3.5áωi rms 2τ(75 kHz) , or áωi rms 135 kradJs. A PLL is to demodulate the signal. The noise bandwidth of the bandpass filter at the PLL input is B; = 200 kHz , and the carrier司的-noise ratio is SNR; = 20 dB = 100. Find K and the signal-to-noise ratio after demodulation.

Equation (9-38) requires K > 94 krad/s. But to maintain lock , Eq. (9-39) requires K =旦旦主且坐個dω2 = 80 krad/s (see Example 7-3). Satisfying the lower bound of Eq. (9-40) , we set丘p = Bm = 15 kHz. Then Eq. (9-44) gives ωn2 = 2.23 (krad/s)2 , andEq. (9-46) gives SNRo = (1 35)2/2.23 = 8173 = 1主豆豆.

?!

209 References

REFERENCES

[1] C. L. Phillips and R. D. Harbor, Feedback Control Systems, pr巴ntice-Hall: Englewood Cliffs , NJ , 1988.

[2] B. P. Lathi , Modern Digital and Analog Communication Systems, HRW: Philadelphia, 1989, section 4.13.

[3] F. M. Gardn仗， Phaselock Techniques , Wiley: New York, 1979, Appendix B. [4] J. P. Costas,“Synchronous Communications," Proc. IRE, vol. 44 (December 1956), pp.

1713-1718 [5] S. A. Butman ímd J. R. Lesh,“The Effects of Bandpass Limiters on n-Phase Tracking

Systems," IEEE Trans. Commun. , vol. COM-25 (June 1977) , pp. 569-576.

[6] Butman and Lesh,“Effects of Bandpass Limiters."

V-1-iiis

CHAPTER

10

RECOVERY CLOCK

In digital communication systems , information is conveyed by a series of bits-1's and O's. A typical binary data signal Vi is shown in Fig. 1O-1a. The bit sequence here is 1,1,0,1,0,0,1,1, where a pulse repr'臼ents a 1, and the absence of a pulse represents a O. The bit rate is called the baud fB. To process the data correctly, the receiver usually synchronizes a clock to the data so the clock frequency fo equals fB. The process of synchronizing the frequency and phase of the clock is called clock recoveη心 and it is usually accomplished by a PLL. Applications requiring clock recovery include compact disk players , floppy disk readers , and satellite data links.

1、he application of PLLs to clock recovery has some special design considerations. Because of the random nature of data, the choice of phase detectors is restricted. In p訂ticular， three-state PDs won't work, and other means must be used to aid acquisition. One useful method is the rotational frequency detector described in section 8-6. The random data also cause the PLL to introduce undesir巳d phase variation in the recovered clock. This is called timing jitter, and it is the principal topic of this chapter. Through proper design of the PLL, this jitter can be minimized. Trischitta and Varma [1] provide a comprehensive reference on jitter sources , effects, and standards.

212 Clock Recovery Chap. 10

的(f)

吟出

• 口且且，

fs 2fs f

(a)

的川 < 妙的，{f)川

• f (b)

』4, -f

(c)

FIGURE 10-1 RZ data and c10ck

10-1 DATA FORMATS AND SPECTRA

Consider the data signal in Fig. 1O-1a, where the first two bits are adjacent 1 's. Because the signal goes to zero between adjacent pulses , this format is called return-to-zero (RZ) data. The resuIt is a signal that is a periodic square wave with period TB but with some of the pulses missing. Therefore , the spectrum v;(ω) has a line component atfB = 1ITB. The spec汀um also has a continuous component that extends beyond f = 4品; this corresponds to the random pattern of missing pulses.

In communication application缸， the data is filtered by a low-pass filter to eliminate as much noise as possible , as in Fig. 的一1 b. The resuIt is a rounded waveform Vi in the time domain and a narrower spectmm Vi(ω) in the frequency domain. Note that the fiItering is broad enough that the sigilal still returns to zero between pulses , and there is still a line component atfs in the spectrum. Clock recovery amounts to extracting this line component as either a sine wave or a square wave Vo (see Fig. 1O-1c). The desired phase is to position the rising edges ofvo at the center ofthe Vi pulses. Then the clock can sample the data at the optimum time (see the dots on the Vi waveforms) to determine whether the bit is a 1 or a O.

Another data format is th巳 non-return-to-zero (NRZ) data V;' shown in Fig. 1O-2a. Again the bit sequence is 1,1,0,1,0 ,0,1,1, but the signal does not go to zero between

寸

Sec.1 。一2 Conversion From NRZ to RZ Data 213

1| 鬥 rm~~ (a)

vj 八 L ..~f)~ • f

(b)

1nnnnJlJ1ruvo(f) fBs',-一

一

BO

悶

，ι

『

•• tat--

•••• LE

E-BEEBEE--aM

』'，

.. f

(c)

FIGURE 10-2 NRZ data and c10ck

adjacent pulses representing 1 's. That is , the pulse width equals the pulse spacing TB . It can be shown [2] that the corresponding spectrum v;' (ω) has no line component at fB (see Fig. 的一2a). In fact , the continuous part of the spectrum actually goes to zero atfB' The band-limited form of the NRZ data is shown in Fig. 1O-2b. Most of the spec甘um of this signal lies below fB/2 , a result of filtering to reject noise.

Since NRZ data has no component at品， a PLL will not lock to the data to produce the clock signal. As we found in section 9-3-1 , a nonlinear process can create a line component at 品， and a PLL can recover the desired clock signal v 0' 的 in Fig. 1O-2c. When in lock , the PLL usually phases the clock so that its rising edges are centered on the data pulses (see the dots on the v/ waveforms). If the PLL aligns the falling edge of v 0 in the center of the Vi pulses , the complement of the clock can be used for data sampling.

10-2 CONVERSION FROM NRZ TO RZ DATA

One way to recover clock from NRZ data is to convert it to an RZ-like data signal that has a line component at fB , and then recover clock from that RZ data with a PLL. The conversion process for band-limited NRZ data is illustrated in Fig. 10-3. Since the phase

?

Sec.1 。一2 Conversion From NRZ to RZ Data 215

' 的的

information is in the transitions of the data V/ , the data is first differentiated to generate a pulse (either positive or negative) corresponding to each transition (from 0 to 1 or from 1 to 0). These pulses are made to be all positive by squaring the differentiated signal 中 2 人

(Squaring produces fewer harmonics and reduces the in-band noise compared with fullwave rectification.) The result is signal Vi that looks just like RZ data; puls的 are spaced at intervals of Ts , and some pulses are missing. But here a pulse stands for a transition rather than a 1.

In low-noise applications , other options are available for converting NRZ data to RZ data. A method useful at high data rates 的> 20 Mb/s) is shown in Fig. 的一4. The data v/ is delayed by Tsl2 and compared with itself by an exclusive-OR gate. Each time that v/(t) and v/(t - Tsl2) are different (after a transition) , the exclusive-OR generates a pulse. For example，的 a data rate ofjs = 50 Mbitlsec the bit spacing is Ts = 20 肘， anda delay of Ts/2 = 10 ns is needed. Since signals propagate through delay lines at about 0.2 m1ns , this requires 2 m of cable. Since logic devices decrease the effective signal-to-noise ratio , this method is not used in recovering clock in low signal-to啊noise applications. But for clock recovery from a logic sign祉， the circuitry here is simpler than that in Fig. 的一3.

For low data rates , the cable length to realize Ts delay may be excessive. In that case, the method for converting NRZ to RZ data shown in Fig. 10-5 is simpler. Each

vf卡\久/~

• ' 的

八八〈企~ FIOURE 10-3 Converting band-limited

NRZ to RZ-like signal

' 的' 的的

ví t 叫什

L_ _1 「可

~TB斗

「「 ',

一--1 ~ TB/2

口口 • t

口口 • t ~TB刊

/U1Jl 口" t

FIOURE 10-5 Converting NRZ logic signals to RZ-like signal (low-data rates)

(a)

AaT伊llltlL

qL '', s γ'

et 研， |n

~石刊

鬥鬥鬥口 ... t

(b)

FrOURE 10-4 Converting NRZ logic signal to RZ-Iike signal (high-data rates)

空14


rising and falling edge of the NRZ data triggers a monostable multivibrator with pulse width TB/2 , and an OR gate combines the pulses.

10-3 PHASE DETECTORS FOR RZ DATA

Inhigh自noise applications , a multiplier is usually used as a phase detector, as in Fig. 10-6a. (Multipliers as phase detectors were discussed in section 4-l.) For the case shown here , the data pulses Vi are positive, and the clock signal Vo goes both positive and negative. In steady-state with (}e = 0, each falling edge of Vo splitsa data pulse (the solid Vo waveform in Fig. lO-6c). Then the product Vd consists of pulses with equal positive and negative areas , and Vd' the average , is zero. For positive phase error 見， the clock is delayed slightly

Vd high pulse density

的

。e

人Vd

Vo

(a) (b)

時h八〈斗‘

，

nυ

斗〉一

九。

八八 ~ t

只b

Vd

(c)

FIGURE 10-6 Phase detector for high-noise RZ data

可

Sec. 10-3 Phase Detectors for RZ Data 217

compared to the data (the dashed Vo waveform) , the Vd pulses have more positive than negative area, and Vd is positive. The resulting PD characteristic of Vd versus (}e is shown in Fig. lO-6b. The characteristic is sinusoidal with a maximum value that depends on the density of data pulses. If half the pulses are missing on average , the characteristic is half the height it would have with no missing pulses.

In low noise applications , a simple exclusive-OR gate can be used as a multiplier, as in Fig. 1O-7a. Again , the falling edges of the clock Vo split the data pulses evenly in steady-state, and Vd' the average OfVd' is zero , (see Fig. 1O-7c). For positive (}e> the clock Vo is delayed (dashed waveform) relative to the data 巧， and the average of Vd is positive. Note that during the time that there are no Vi pulses , the average of Vd is zero even for nonzero (}e. Then for (}e = τ/2 ， V d will be V H - VL half the time and an average of zero half the time if the pulse density is 50%. Therefore , Vd = (VH - VL)/2 corresponds to

Vd

(VH- VL)/2

;二3亡三二2 。e

For 50% pulse density

(a) (b)

的出口

Vo

Vd

VH - ~也

(c)

FIGURE 10一7 Phase detector for low-noise RZ data


Oe=τ/2for a 50%pulse density (see the PD characteristic in Fig. 的一7b). The corresponding PD gain is

Kd = (VH 一九)/π; 50% pulse density 、‘-a'，

I

且nυ

咀aA

',, ..

、

10-4 PATTERN-DEPENDENT .JITTER

We have been assuming that the PLL responds to 句， the average of 卡， because of the

::侃;泣口臼此Z口試泣1立立叫叫;zr叫吋1?泣泊s芯芯♂品站;泣:r口?1況;咒t:土詰記叫立迂UU:泣泣J品;C叭叫:tr叮叮:叮咒叮:2z::::口;立:盯缸:2叮吋7叮泣:立;?心已」芯;泣::LLt泣扣叫古叮f咒叫mih廿加ir位口i:已立叭;L泣ri;r:?uwhich IS zero for 04e=O.However, for a wide-band PLL the pattem of Pd, which depends on the data , does have an effect on fJ~.

The 祖a叫ly戶sis he旭er，昀eh叫old也s fo叫

in Fig. 10-8 w抽出e comspondmz hpa位em for fJe = O. We can a叫yze the effect of ií d

by COIlsidedrlgIt a phase-moduIatIOIIInput at m(f)in Fig.9-1.From Eq.(9-1) ,

。'aCs)丸!.s) (10-2)

吟片而且H H 門鬥 ..

t ~均純

Mn v

FIGURE 10-8 Pattem-dependent jitter with XOR PD

可F向嘲向觀叫輔驛阻體體體間輛輛輛髒嘲蹦蹦喃喃囉嘲鸝鵬聽聽輛轎懿輛輛

Sec. 10-4 Pattern-Dependent Jitter 219

The resuIt ofthis low-pass transfer function is shown by the fJo(t) waveform in Fig. 的一8.

During pulses on 吭， fJo is a triangular wave with a peak-to-peak amplitude of /l.fJ. When there are no pulses on 竹， fJo is a triangular wave with a peak-to-peak amplitude of 2/l.fJ. There is also a decaying exponential transient when the data pattem changes; this transient is the short-term average of fJo . The ampliωde of the transient is /l.fJ/2.

The value of /l.θcan be obtained easily in terms of K and TB as follows. For frequencies on the order offB (and therefore greater than 10 , Eq. (1 0-2) can be approximated by

。aCs)iíJs)

位互KdS

Rearranging, and taking the inverse Laplace transform , we get

s fJaCs) = iíþ) K/Kd

。 o(t) = iíjt) K/Kd

When a data pulse is pr，自ent on 肉， then iíd = VH 一九 for an interval TB/4 (see Fig. 10-8). Then the change in fJo during this interval is

Aθ fJo TB/4 = (V H - VL)K/Kd)TB/4

But from Eq. (1 0-1) , the PD gain is Kd = (VH 一九)l7r for 50% l' s density in the data pattem. Therefore

/l.fJ = (τ/4)K 九 (10-3)

When pulses are not present in the data pattem V; , the interval during which fJo ramps becomes 九12 ， and the change becomes 2/l.fJ (see Fig. 的一8). Since the exponential 仕個sients have amplitudes of + /l.fJ/2 and - /l.fJl2, the peak-to-peak phase jitter of fJo is the /l.fJ given by Eq. (1 0-3).

The specific form of the transient behavior is of course dependent on the data pattem. If the pattem is altemate 1 's and 0池， then the jitter is virtually nonexistent. But if there are long strings of 1 's and O's , then the jitter amplitude given in Eq. (10-3) holds.

EXAMPLE 10-1

A PLL with an excIusive-OR phase detector is used to recover cIock from RZ data. The PLL bandwidth is one-tenth the baud; that is , K 0.1 x 2τrfB' Find the pattemdependent jitter.

SincefB = 1ITB, we have K = 0.2'IT/TB, and from Eq. (10-3) , /l.fJ = 0.2τ2/4 = 0.5 radian. This is a significant 8% of a bit interval!

jlll

+ Vd

R

Fd=;也 (Vx+Vy)

。

的

Y

Chap. 10

The pattem-dependent jitter that accompanies an exclusive-OR PD can be avoided by using a two-state PD. The performance ofthe two-state PD was ana1yzed in section 4-7 for both Vi and Vo periodic. Here , Vi is RZdata applied to the two-state PD , as in Fig. 1O-9a. The result is a waveform vy of positive pulses with width proportional to the phase difference between the data Vi and the recovered clock Vo (see Fig. 1O-9b). For ()e = 0, the pulse width equa1s that of the RZ data, and vy = 一九. Then Vd = l/2(vx + vy) = 0 , and there is no pattem at the output of the PD for ()e = O. Therefore , there is no pattemdependent jitter. Another advantage of the two-state PD is that the phase range is ::t甘， or

double that of an exclusive-OR PD (see Fig. 1O-9c).

Clock Recovery 220

Vo

(a)

的』且

~

t

f1 門

Vo

.. t

叭↑鬥_ ...1..-1 ....J.-..----J門「UU 0 DU

Vy

VH-VL

To recover clock from NRZ data, the NRZ data is usually converted to RZ-like data, as in Fig. 10-4, and then applied to an RZ phase detector, as in Fig. 10-7 or Fig. 10-9.

It is also possible to compare the phase ofNRZ data directly with a clock, as in Fig. 10一lOa. This circuit behaves essentially like a two-state PD , with a phase range from 一 τto 甘， as shown in Fig. lO-lOb. The data Vi is sampled by the rising clock edge 凡， and the sampled data Ql is compared with the data by an exclusive-OR gate. The result is a signal Vb with pulses whose width goes from zero to TB as ()e goes from 一 τtoτ(see Fig. 10-lOc). For ()e = 0, the pulses have width TBI2, but the average of Vb depends on the data transition density (the number of Vb pulses). Therefore, the waveform 九 is needed as a reference. It maintains (independent of ()e) the waveform that Vb would have for ()e = O. Then Vd = 九一九 always has a zero average for ()e = O. This corresponds to Vd = 0 for ()e = 0 in the PD characteristic (see Fig. 的一IOb). The maximum value ofthe characteristic depends on the transition density; for a 50% density , the maximum is (V H 一九)/4 ，

where V H is the logic high level , and 几 is the logic low level.

哩。-5 PHASE DETECTORS FOR NRZ DATA

「口U

r;

]

/ 'd>O

O/LJ J U

Vd

VH-VL

(b)

Vd

(VH- Vd/4

10-6 OFFSET .JITTER

When the PD has dc offset Vdo ' another kind of pattem-dependent phase jitter arises. A brief explanation is that the offset voltage causes the clock phase to drift when there are no data pulses (no phase information). The drift will be longer or shorter according to the variations of the data pattem. To be quantitative in our analysis of this effect , we need a model for the PD in the presence of a data pattem.

Let an RZ data signal vi be considered the product of two waveforms: 。e

For 50% pulse density

Two-state PD with data input

(c)

FIGURE 10-9

V;(t) = δ(t) Vim(t)

where δis the corresponding NRZ waveform and Vim is a square wave to reduce the last half of each RZ pulse to zero (see Fig. lO-llb). The periodic signal Vim is one that we

223

have worked with before in section 4-6 , and we will be able to apply some of that

;h揣在HZ研制;研把

Offset Jitter Sec. 10-6

可

。e

D-二b+

D二a 一

時f

Vo

(10-4) == Vdml(τ12) Kdm For 50% transition density

Fig. 10-llb). This can be expressed as When 8 0 , v~ = 0 (see the waveforms in

8 = 1

8 = 0

E A佇

間,d

k fl

」ltL

AU v~ =

or

(b)

• • 』且

(a)

|-i l (10-5)

Thi 可 tionship is inco叩orated into a signa1 flow graph for the PLL in Fig. 10一12a. The

喘l呻卅;i;峙湘;;滑端:控加投姑:;叫i甘E:昂站志品i封仿古投罵喘架if且ii ; :拉:立立;立;立r芯了ι5f iL泣且心:立江拉t1芷1J;:且斗LL;;LL」u句蝴削i旬刷p抖凶伽1ibe 巳 r紀'es叩01廿ve吋d i泊ntωod缸c and a缸c c∞ompo∞ne凹nt“怔s缸:

v~ = 8Kdm(}e -t

1nJ1n_

亡

•

口8(t) == 80 + 8(t)

。e(t) == (}eo + (}e(t)

•

了:;1:;231:1;::s tzzrtt比如;三;);1品:LZCtzrlo-12b.The variables 80and ko are of the same magnitude , but wc can make the

approximatíon

-t L 回rn rn rn

口

4阿川]

Ul 8e(t) << (}eo

Then the product in Fig. 的一12a can be approximated by

'O(t)ØeCt) = ('00

+ 8(t) ]Ø/t) = ôßeCt) + 8(t) ((}eo + Õ/t)]

Z 扎扎(t) + 8(t)Øeo H lF|L

石一2一

斗ll:b (1 0-6)

:::tz:;;EZTZFEJEtu;:;ZZ;JJf;:1:古i::;2;;4忍!e;(c)

Phase detector for square-wave NRZ FIGURE 10-10

222

224 Clock Recovery

δ

E三二?時m

Vo

(a)

十一一-Y-二十一十一

時出

口 H H hnnnnn l1ru

Vdm

-Vdm

(b)

FIGURE 10-11 Decomposilion of RZ waveform V1

.. t

.. t

.. t

-t

Chap. 10

sum on the right. Equation (10-6) can also be put in the form ôOe = ôo((Je + ðOeo/ö,J. The flow graph in Fi售﹒的一12c substitutes this sum for the product in Fig. 1O-12a. The input variable is now δ， a zero-mean signal determined by the data pattern (see Fig. 的一13a).The form of the flow graph in Fig. 1O-12c is the same as that of a PLL with a PD gain of

Kd Ô,j{dm (10-7)

可

δ

(a)

0=00+0

':Er仟一一鬥一\一rr仁一。e

。.=0'0+ 0•

(b)

(c)

FIGURE 10一 12 Offsel jitter 8" due 10 8，ρ

.... t

-......,...-F

227

and with an input phase of S{}eol'ôo. Although this is not a phase that can actually be measured anywhere , let us define this effective input phase as

(10-8)

One of these sources of this effective phase is the pattem of gaps in the data reflected by o. The other source is the static phase error {}eo caused by dc offset voltage:

{}s 三 ({}eol'ôJS

Offset Jitter Sec. 10-6

↑-一斗石|←

盯鬥鬥鬥「

(10-9)

[See Eq. (3-7).] Let {}o be the ac component ofthe output phase (}o. Using the PLL phase transfer function H(s) developed in section 3-5 , we can find Ôo in terrns of {}s:

{}eo - VdolKd 訴(丹 =1平血h主主

2 (7rT Bf)2

Area = Ô2 = 0.25

(10-10)

This unwanted phase is called offset jitter. If we can find the spectral density of S, then from Eqs. (10-8) and (10-10) we can get the spectral density of the jitter {}o and its rrns value.

A typical waveforrn for S is shown in Fig. lO-13a. It has zero mean and varies between 0.5 and -0.5 with the data pattem. Its mean squ訂e value is O.詣， and it can be shown (see Lathi [3] for example) that its spectral density is

。IO(S) = (}.(s )H(s)

f 21TB IITB

(a)

<Þã

石12

8L

面Þes

sin2 (τTBf) (τTBf)2

TB

2 <ÞOs= (0.0Iô)2<Þ;5,

<ÞOs(O)

、、•• ,F

IA --AU --且

'，EE‘、

as illustrated in Fig. lO-13a. Since the bandwidth BL of the PLL is usually much less than lITB , we will be able to approximate

φ6(f) = <ÞOs(O) = (0'01品。)2TB12

f 8 L @品 ~ (model)

(10-12) φ6(f) = φ6(0) = TB/2 墊。0=JHJ2吾Os一

<ÞOs(O)

But from Eq. (10-8) , the spectral density of (}s is ~ Area=O~

(10-13) φ0.(0) ({}e)'ôo)2φ6(0) = ({}eo l 'ôo)2TBI2

As deterrnined in section 6-2, the noise bandwidth of the PLL is f 8L

(10-14)

Then the spectral density φÓo of Ôo can be modeled by cutting off φOs abruptly at B v as shown in Fig. 的一13b. The area under the curve gives the mean-square jitter:

(10-15)

BL = KI4

存 <ÞO.(O)BL ({}e) 'ôo)2TBK/8

(b)

Spectral densities in the analysis of offset jitter FIGURE 10一13

"直


For random data , both the l's density and the transition density are 80 = 0.5 , and Eq. (10-15) becomes

好 =φ!J.(O)BL = 0.58e02K TB (1 0-16)

Since 島= 0 in this analysis and 8e = 8i 一丸， therefore 8e = - 8m and we also have

在主 =φ!J.(O)BL 0.5 8e02K 九 (10-16')

A typica1 PLL bandwidth might be K = O.位/TB . Then Õe主 0.01 8e} , or fJerms = 0.1 8eo. This justifies our assumption that 8e is negligible in Eq. (10-6).

While Eqs. (10-16) and (1 0-16') give a measure of the offset jitter, they tell very little about the probability distribution of the offset jitter. If the distribution ware Gaussian, then the mean (8 eo) and the standard deviation (8e rms) would comp1ete1y characterize the distribution of Oe. But the distribution is not Gaussian. Figure 10-14 shows probability distribution for Oe for pseudorandom data. This was obtained by a computer simulation of a first -order PLL (ω2 0) with a pseudorandom data pattem of length 220 一 1. (See Golomb [4] for a description of pseudorandom pattem generators.) The case simulated here is for KTB = 0.02. From Eq. (1 0-16') , this results in a normalized standard deviation 8e rm/8eo = 0.1. Figure 10-14 also shows a Gaussian distribution with the same mean and

" <

10-

10-2

J 10- 3

、、ω

"" b .0 1l 10-4

。已

10-5

1。一6

10-7

、心I I I

ν 2?-日一 1 word length

、KTB =0.02 v x=1 ， σ'x=0.1

\\ ?\

Gaussian 杆--門 h\ 主=1 ， σ'x=0.1

L::::t \

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 , 2.0 2.2 2.4

x--刊~

FIGURE 10-14 Offset jitter distribution

可

229 Sec. 10-6 Offset Jitter

叫dard de叫ion for cor恥rison. Wh加t叫aussian distributionωeedsfivestmdard deviations (x = 1.5 on the 油sci叫 with a probability of only 7.2 x 的一九 the ac叮lOJOeo exceeds 1.5with a probability of 0.OO2.WhIlc the Gaussian dstribution excews x = 2.27 with a probability of only 3 不 10- 37 (this is off the plot) , the actual OiOeo

exceeds 2.27 with a probability of 10-0

•

EXAMPLE 1。一2

Clock is recovered from a 1.544Mb/S RZ data stream by a PLL with a bandwidth k=2TT × 5kHz =31.4kradA.Thc phase detector in the PLL is a cbfOS exclusive-OR gate with logic levels VH=5V and VL=O v.The PD offset voltage can be as great as Vdo= 一 0.15V.The erTor rate after sampling the data with the recovered clock is to be 106or less.How much has Vd reduced the timing margin for alignment of the clock?

The optimum cdlhOcL 肉nn捌Ipulse趴， aωs in Fig. 10-1. Then the timing margin isτ/2 radians before the clock edge eaches the edge ofthe datapulse and causes eITOTS-The PD offset voltage Vdb=-0.15v

causes a statIc phase offset O=-VdJKd [see Eq.(10-9)]-The exclusive-OR phase detector has a gain kd=(VHe三 VL)/τ=5V/3.14rad =159V/radIseeEq.(10-1)lThen oe=0.0942rad, which reduces the timing margin by this much.But offset jitter MKr:educes th timing margin The data spacing is 九 1/ 1. 544 Mb/s = 648 n

立E::2;:已戶;立;::J立:，:沾O立::已3Z:艾;!b:立f土::±r土Ysr吭r:?r;l:ej!叮35;J戶Jι;汙t{吉ιfLiιFig. 的一14 ， which shows 出atoreaches about IZYtTIns away kOInthe mean Oeowith a probabi1ity 10-6. The叫叫otaf叫uction of timi時 margin is Oeo + 12.7 êe rms = 0.214 radians-The margin with optimum alignment iSTT/2=1.57radianLSO the reduction IS

0.214/1.57 = 13.6%

A few comments need to be made to allow generalizations from Examp1e 10-2. It was assumed that the 10-6 error rate specification was for a pseudorandom data pattem with 1ength 220 - 1, for which Fig. 10一 14 applies. The bandwidth K = 0.02/TB was a1so chosen in Example lO-2so that Fig.lO-14applied-For other bandwidths , the lo-6point is roughly UAms away from OEO-For example, if k were increased to2τx 40 kHz , then kT=0.16 , and from Eq.(14161，在e rms 0.0267 radians. Then the timing IMmhudiorlwouldbeao+l3Arms =044l mdia瓜 or28IC/This isamug1 estiLMC;themder should write his own program for other pseudorandom pa悅ms an other va1ues of KTB • The discrete-time difference equatlOn IS

Xn+1 = Xn(1 - 2K TBDn) + K TB

where X 8j丸， and Dn is a pseudorandom sequence of 1 's and O's. Note 心 if伽悶。;的d clock samples NRZ d詢問伽伽nRZda肌伽tJmmg

margin for optima1 a1ignment isτrather thanτ/2.


10-7 ", 'ITER ACCUMULATION

While offset jitter is seldom a problem in one PLL, it can accumulate to a significant level in a series of tandem PLLs. This is the case in a chain of data repeaters , shown in Fig. 10-15a. Data V; transmitted at the head end has the clock recovered by a PLL , and the data is regenerated (cleaned up) as V;. After some distance of transmission , distortion and noise require that the signal again be regenerated. Repeated cock recovery may occur as many as 1000 times in long-distance transmission. Each clock recovery circuit in the transmission path adds its own offset jitter to the total jitter.

The accumulation of jitter is modeled in Fig. 1O-15b. Each PLL has an effective phase (}s due to offset and the data pattem. This is added to the phase jitter ofthe data from the previous repeater. The PLL then filters the combined phase by its transfer function H(s). The data pattem is the same for each PLL, and if we assume in the worst case that the static phase error (}eo is the same for each PLL, then they all have the same (}s' As can be seen from Fig. 的一15b ， the transfer function from (}s to the last output phase (}N is

(}N(S) 一止一 = H(s) + H 2(s) + . . . + HN(s) 。，(s)

H(s) ..N 一一一一一 [1 - HV(s)] 1 - H(s)

For ω2 = 0 , H(s) + l!(s/K + 1) , and Eq. (1 0-17) becomes

。'N! (}s = (κIs)[1 - l!(s/K + 1)叮

的

(a)

(10-17)

(10-18)

VN

所)已-f岳。

(b)

IIN(s) 句~一 = H(s) +H2(S) + . . . + ~(s) 。s(s)

H(s) uN 」且主L [1-HN(S)]

1-H(s)

FIGURE 10-15 Jitter accumu1ation in a chain of N regenerators

可司，

Sec. 10-7 Jitter Accumulation 231

Then , as in Chapter 6, the spectral densities of 8N and (}s are r巴lated by

φO~φOs = 18N/8s12 (10-19)

For the case ω2 = 0 , Eqs. (10-18) and (10-19) give

φθN/φOs = (K!2τβ2 11 - 1I(j2τrf/K + ltl2 (10-20)

This nonnalized power spectral density is plotted in Fig. 10-16 for various N , where N is the number of repeaters. For 2'Trf/K > I/N, (2可K + l)N>> 1, and <ÞON峙s approach的(K!2'Trfi , as can be seen from Fig. 10-16. For 2'Trf/K < l!N， φON/φOs = NL

• As a result, cumulative jitter tends to be heavy in low-frequency content.

The mean-square cumulative jitter is proportional to the area under the curves III

Fig. 的一16.ByrnC et al.[5Ihave evaluated the integral of Eq.(10-20):

khh (10-21)

where S(N) is a function of N that ranges from 0.5 to 1 as N increases (see Fig. 10-17). Over the range of f for which φ。此丹 is important ， φ0/1) is usually constant enough that

ω2=0 107

106

105

<Þ ON 1Q4 1-一一<ÞOS

1()3

102 ~一

10

1 10-4 10-3 10-2 10- 1

2πf/K 一-J-

FIGURE 10一16 Accumulated jitter power density (的2 = 0)


1.0

0.9 計問: ••- 同•-

~ 戶--

/ j.;'

./

0.8

0.7

/ l三 LI

0.6

0.5 4 6810152030406080100N

Number of regenerators

FrGURE lO一17 Factors for 耐岫ting 前叫H咖

;rγe叮C翎a組na哪p呻proxim純 φ丸fis仍 = φ斟恥何州伽叫圳S正(仰納0). TJ叫le me臼叫翎伽枷a缸組伽n仔1.

前 J~ φfiN df = 0.5N S(N) K <ÞfiS

For the usuaI case of 00 = 0.5 , Eq. (10-13) gives

φfi，(O) 20e02/Ts

and

ON2

= N S(的 K 九見。2

(1 0-22)

(10-23)

(10-24)

where N is the number ofrepeaters.Takin the squammot ofEq.(10-24)shows the

江tlrzzzr此ZZirιAt:e?Zr估計向翩翩tic ji眠Another s。此e of systematic jitter is intersy.叫01 inte社rence (ISI). This is phase

JItter at the PLLInput caused by data pulseseffectIvely shifting the phase of foIIowing data pulses.Duttweiler[6]shows how to calculate the phase spectral density due to ISI

Zι:立izj::f Shape ， a叫叫7] shows 1胸叫lape t伽he晦叫e cha缸組削枷帥nn帥m帥n配仙1旭eTheo昀盯cωoffs鉛蚓阱et品tι-叫u岫ced <Þ屯丸伽以S仄(0) g版g斟iven in Eq. (1 0-仙-13) i臼s on吋 one 叩m叫u脫l

-如e閒帥叫nsi討咐i技t句y 伽伽t c翎al削u脫lses臼sp阱h帥 J戶u帥伽t紀伽E叮r. Th倪 is also 伽 sp脾仰附缸叫ct叫m叫1 d伽e閒n叫 00

due to noise at 伽

;?也出早已iZJt:iizrrL1232s;:TZ;2tZZZZZZ;2;:

『司，


。 282 JN R(的 K吭， where R(N) is a function of N that gr仰row吶s fì加m削rr叫Iincreases (see Fig. 10-17). Then with Eq. (1 0-22) , the total accumulated jitter is

0/ = 0.5N S(的 Kφfi，(O) + 0.282 JN R(的 K0。 (10-25)

where <ÞfiS inc1udes aII systematic jitter-the offsetjitter in Eq. (1 0-13) , and ISIjitter, and pattem-dependent jitter described in section 10-4. Since the random jitter [the second term in Eq. (10-25)] grows more slowly with N , it is usual1y negligible for N > 30.

EXAMPlE 10-3

A transmission line with 30 repeaters carries RZ data at 1.544 Mb/s. Each repeater has an input filter with bandwidth B; = 3 MHz , a signal-to-noise ratio SNR; = 12, and a c1ockrecovery PLL with a bandwidth K = 31 .4 krad/s and ω2 = O. The PD in the PLL has a figure of merit M = 10.6. Find the accumulated jitter at the end of the transmission line.

From Eqs. (3-7) and (4-14) , Oeo = 11M = 0.0942 radians. The data spacing is Ts =

111.544 Mb/s = 648 ns. For random data with 00 = 0.5 , Eq. (1 0-13) gives φfi，(O) =

20e}Ts = 1.15 X 10- 8 rad2/Hz. For N = 30 , Fig. 的一17 gives S(的= 0.9. Then the first term of Eq. (10-25) is 0.00487 rad2.

From Eq. (6-26) the random phase spectral density is 0 0 = 1IB;SNR; = 2.08 x 10- 8 rad2/Hz. From Fig. 10-17，間的= 0.99. Then the second term in Eq. (10-25) is 0.000706 rad2, which is only 14.5% ofthe first term. Th叫哩!且cumulated jitter is ON 2 =

0.00487 + 0.000706 = 0.00558 rad2, or ON rms = )0.00558 = 0.0747 radians.

Accumulated jitter is removed by a c1ock-recovery PLL with a VCXO (see section 5-6) to achieve a very smal1 bandwidth K (< 1 rad/s). The recovered c10ck with no jitter samples the data with accumulated jitter 舟， and the rec10cked data therefore has no jitter (practicaIIy). If the phase ON between the c10ck and the data exceed τ12 for RZ data, errors will occur. For N = 30 , the Central-Limit Theorem [9] makes ON about Gaussian , and it exceeds x ON rms wíth a probability approximated [10] by

P(x) = 0.4 (1 /x - 1Ix3) e( - x212) (10-26)

For the ON rms 0.0747 radians in Example 10-3 , ON τ/2 corresponds to x 1.57/0.0747 = 21. Then ON exceeds 'Tr12 with a probability P(x) = 3 X 10- 98 , and there are essential1y no errors due to rec10cking of the data. If ON were large enough to cause a significant error rate , an elastic store [11] would be necessary in the jitter removal.

Equation (1 0-24) gives the accumulated offset jitter for the case ω2 = O. For the more usual case ofω2 手 0 ， the peak value of H(s) exceeds unity , and theHN in Eq. (10-17)

!'I i!


can be quite large for large N. As shown in Chapter 2, the peak value of H is Hp = 1 + ω2/K for ω2 << K. Then

Hf,=(1 + ωzl的N = exp(N，ωzl的 (10-27)

and the phase transfer function ON/Os grows about exponentially with N. This can lead to much greater jitter accumulation than predicted by Eq. (10-24) ifω2 is not kept sufficiently small. For ω2 手 0 ， the PLL transfer function is

H(s) = Ks + K，ω2

S2 + Ks 十 Kω2

Using this expression for H(s) in Eqs. (10-17) and (1 0-19) leads to the normalized spectral densities in Fig. 的一18. As ω2/K increases , the peaking and the area under the curve for a given N increase.

The area under a curve in Fig. 10-18 gives the normalized mean叫uare jitter:

研/khs(0)=r hNZhs(0)4

lOS

/f、\ N=l00 /、

f 、107

J

ω2IK=0.1 1

f

106 f

J 1 f

r J

/ f 1 t

<f>eN 10"

拉~三p//t、///'Oz〈D\1U\ .U\ 3

、l

\ \

1 千lk i lk

163

1()2

10

2πflK 一一~

FIGURE 10一18 Accumulated jitter power density

可

Sec. 1 。一7 Jitter Accumulation

lOS

107

106

↑耐

<f>eN 10"

163

1()2

10

1

N=1000

10- 4 10-3

235

10-2 10- 1

27rf1K 一~

FIGURE 10-18 (Cont' d)

A computer was used to evaluate the areas by numerical methods , and the results are plotted in Fig. 10-19 as a function of N for several values of ω2/K. A good rule of thumb is to make

ω2/K = l!N (10-28)

so that Hf, = 2 , 7 [see Eq. (10-27)]. It can be seen from Fig. 10-19 that for ω2/K = l!N , 。'N2 is increased by a factor of only 2 , 3 over that given by Eq. (1 0-24) , independent of N. Then for ω2/K = l!N , the accumulated offset jitter is

oi = 2.3 K N S(N) Oeo2TS (10-29)

EXAMPLE 10-4

A transmission line with 30 repeaters carries RZ data at 1.544 Mb/s. Each repeater has a clock-recovery PLL with a bandwidth K = 31 .4 krad/s and a PD with a figure of merit M

10.6. The initial frequency error before acquisition 的 ωeo 1 Mradls. Find the


。品

KPos(O)

0.5

10 100 N

FIGURE 10一19 Nonnalized mean-square cumulative jitter

1000

accumulated offset jitt廷r at the end of the transmission line and the pull-in time for three cases:ω2 = 0.01 K， ω2 0.03K, and ω2 = O.IK.

Forω2 = O. 匠， Fig. 10-19 gives 需/K<ÞOs(O) = 115. As in Example 肘，叫0)=1.15 × l08.Therefore， 0NJ2=O?.:.O415r吋2九， 0叮r ()冉Nrm咖 o.2泊04 ra吋di臼ans昀~. The input 企h巴q伊u叩飢C叮ytωow咐咐hich 伽 PL于 i必s ω lock 昀川ω叫i = 2τ叫品 = 9.7 Mrad/旭s. Fo叮ra組n 缸忱c咖叩恥， t伽he蚓e叫10吐也ω-lll叫吋fre昀叫quen恥tím巳 for a rotational frequency detector is

Tp = (2τ/ω'L)fn(ω/20ω'L) + (40τωeiωi - 2'Tr)/ωL

0.291 ms + 0.135 ms 0 .426 ms

可


加ω2 = O.03K, Fig. 10一19 gives ()N2/K<Þo,(0) = 31. Therefo院研= 31 x 31.4 krad/s x 1. 15 X 10-8 = 0.0112 rad2 or ()N rms = Q.106 radian~. The pull-in time is the same since it doesn't depend on ω2' However, since ω2 - l!R2C, the value of C must be about 仕iple that fl叫 ω2 = O.IK, and the frequency detector must provide about triple the current to charge C during acquisition. 一-

Forω2 = 0.01 K , Fig. 10一19 gives ()N2/K<Þo,(0) = 18. Th的fo間，帶 18 x

31.4 Mrad/s x 1.15 x 10-8 = 0.0065ra針， or ()N rms = Q.081 radian~. The pull-in time is the same. However, the current required ofthe frequency detector is now ten times that forω2 = 0.1 K.

Decreasing ω2 from 0.1 K to 0.03 K reduced ()N rms by 50%. Decreasingω2 further to 0.01 K only reduced ()N rms by another 20%. This is probably not worth the extra current req叫自d of the frequency detector. Therefore, the best choice for ω2 is O.03K, as recommended by Eq. (10-28).

REFERENCES

[1] P. R. Trischitta and E. L. Varma , Jitter in Digital Transmission Systems , Artech House: Norwood, Mass. , 1989.

[2] B. P. Lathi , Modern Digital and Analog Communication Systems , HRW: Philadelphia, 1989, section 2.9.

口] Lathi , Modern Digital and Analog Communication Systems.

[4] S. W. Golomb , Shift Register Sequences , Holden-Day: San Francisco , 1967.

[5] C. J. Bym巴， etal.，'‘ Systematic Jitter in a Chain of Digital Regenerators ," B.S.T.J., vol. 42, no. 6 (November 1963), pp. 2692-2714.

[6] D. L. Duttweiler,“The Jitter Performance of Phase-Locked Loops Extracting Timing from Baseband Data Waveforms," B.S.T.J. vol. 55 , no. 1 (January 1976), pp. 37-58.

[7] E. Rosa,“Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission," IEEE Trans. on Communications , vol. COM-22, no. 9 (September 1974) , pp. 1236--1249

[8] O. E. DeLange,“The Timing ofHigh-Speed Regenerative Repeaters," B.S.T.J. vol. 37, no. 6 (November 1958), pp. 1455-1486.

[9] Lathi , Modern Digital and Analog Communication Systems, section 5.4.

[10] National Bureau of Standards , Handbook 01 Mathematical Functions , U.S. Govemment Printing Office: Washington , D.C., 1964, p. 932

[11] Z. Kitamura, K. Terada, and K. Asada,“Asynchronous Logical Delay Line for E!astic Stores," Electronics and Communications in Japan , vol. 50 (November 1967), pp. 90-99.

『司，

CHAPTER

11

FREQUENCY SYNTHESIZERS

A frequency synthesizer generates any of a number of frequencies by locking a VCO to an accurate frequency source such as a crystal oscillator. Most quality FM radios now use a 企equency synthesizer to generate the 101 different frequencies necessary to tune to the various stations. For proper tuning , the synthesized fr，叫uency should be accurate to within 10 parts per million (ppm)一the accuracy of a crystal oscillator. Since it is impractical to have 101 crystal oscillators , a frequency synthesizer is used to generate any one of the frequencies from just one crystal oscillator.

11-1 SINGLE-LOOP SYNTHESIZER

The simplest form of a frequency synthesizer is shown in Fig. 11-1. It is a PLL with -;- N frequency divider in the feedback path. When the PLL is in lock , the fed-back frequency J)N equals the input frequency-the rφrence Jrequency fr. Therefore , the output frequency IS

Jo=NJr 、、•• /

gi l l Jtk

ttt

螢光標示

ttt

螢光標示

10 MHz

240 Frequency Synthesizers Chap. 11

fo

98.8 to 118.8 MHz

N=約4 to 594 FIGURE 11一 Simple frequency synthesizer

For a fixed 兵， the desired fo is generated by selecting the proper integer N. Circuits that divide a frequency by a value N that is controIled by a signaI are caI1ed programmable dividers orprogrammable counters.Motorola[Ilmanufactures an integrated programIIIable counter-the MC4018. See RohdeI [2] for a complete discussion of programmable counters.

EXAMPLE 11-1

Design a single-loop synthesizerto generate 98.8 MHz , 99.0 MHz , 99.2 MHz, . . . 118.8 MHz. That is,!o is to have a range from 98.8 MHz to 118.8 MHz with a resolution ofO.2 MHz.

AU the frequencies are multiples ofO.2 MHz. Then fromEq. (11-1) ,fr = 0.2 MHz. The lowest tkqliency is98.8MHz=494 × 0.2MHz, and the highest frequency is 118.8 MHz = 594 X 0.2 MHz. Then N must range from 494 to 594.

Since it is difficult to make crystaIs that resonate as Iow as 0.2 MHz , the reference fre~uenc~ here would probably b~ o?tai~_e~ by d~viding down a higher crystaI frequency such asfi = 10 MHz (see Fig. 11-1). If the -:-50 is made a selectable -:-M, the~fr ~ fi!M , and Eq. (1 1-1) becomes

fo = (N/M)fi (1 1-2)

Integrated circuits are available commerciaIly that provide the -:- M and -:-N frequency dividers and the PLL's phase detector in one package. [3]

11-2 CHOOSING THE BANDWIDTH K

The bandwidth K of a PLL in a frequency synthesizer affects four parameters of the performance: the puI1-in time aft巴r a new N is selected, the suppression of phase noise , the suppression of spurious modulation , and the resistance to injection Iocking. The puII-in time, given by Eq. (8-28') , is approximately

Tp = 8feJNK2

可

Sec. 11-3 Synthesizer with Mixer 241

for the choice ω2 = K/4. The phase noise in most cases wiI1 be govemed by Eq. (6-63):

。。2=a/K

where a is a constant. Spurious modulation，個alyzed in section 9-1-2 , is also present in frequency synthesizers. We will show in Eq. (11-14') that the spurious phase modulation IS

!1() =τ8NK2!f，2

where 8 is proportional to the PD offset voltage. Avoidance of injection (section 5-9 and Example 9-2) is usuaI1y not a dominant consideration compared with the three above.

The strategy in designing for N and K is to minimize the maximum N to reduce !1θThen K is chosen as a compromise between a smaII value to reduce !1() and a large value to 削uce 穿If the 耳 for the chosen N max and K is unacceptable , a decrease in Tp wiIl have to be traded off against an increase in !1().

The -:- N frequency divider is still considered part of the phase detector，的 it was in Fig.4一12. For a three-state PD with a -:- N , the phase detector gain is Kd = Vdm!2τN. Therefore , the bandwidth K = KdKhKo is inversely proportional to N. As N is varied in a frequency synthesizer to change the frequency , K also varies. However, the product NK remains constant. In particular ,

NminKmax NmaxKmin (11-3)

This quick discussion provides a rough overview of the factors influencing the choice of the bandwidth K. The foI1owing sections will provide more rigorous anaIysis and some design examples.

11-3 SYNTHESIZER WITH M故ER

It is sometimes possible to reduce N by int叫uci時 a mixer into 伽 PLL ， as in Fig. 11 之This wiU reduce the spurious phase modulation !1() while achieving the same range and resolution as the frequency synthesizer in Fig. 11-l.

ι

FIGURE 11-2 Frequency synthesizer with mlxer


;;fiiiIimiH咐:/o=N j，. 十五 (1 1-4)

Here, ji provides most ofL, and Nprovides the smaller, variable portion ofjL-In Fig.l I-1, jL has a range from 98.8MHz to l18.8MHz and a resolution of 0.2MHz.ThicunmR range IS 叫ized by Eq. (1川 f扣O叫= 0.2MH圳= 1仙

(ωse臼e FH1g.11-2).Compared with the synthesizer in Fig.II-l the largest value ofN is now nly 200 rather than 594.\

A叮 of tl叫hase de叫ors described in Chapter 4 can serve as a mixer. The threestate PD has a pr?pedy thatIs especially usehI-it produces m ouwt only whe叫 ISZZTTIITf叫…ts the也 from岫ng叫 - /0州 = /rra伽伽 (fo 一

In pra月ice ， the mixer p叫uces 酬。的/0 - /2 and/o + 后 but also some sDurious

立ZZZZZdrs iyM叫缸叫叫las叮叫叫it岫伺圳g伊i廿ives臼叫…sa叫a叫t位血伽伽h岫1昀悶O叮r呵ld叫s鉛ssio叫s泣SIOI昀lOIα叫Iw w mllllml犯ze them. In particul缸， the /0 and /2 components a

E立芷江ftzzrι::zrrmLISts啊

/0-/2</2 (1 1-5)

說:JHMNZH研制品:扭曲e additive且“noise component causes phase modulation with an amplitude of I/115

2ZZ心話:心立一立品arrtJEJZZ丸rctmHO)

11-4 SPURIOUS MODULATION

可

If

Sec.11-4 Spurious Modulation 243

spurious modulation will be less. In this section, we will derive the amplitude of /1{} when the input is a fixed reference frequency.

A typical circuit for a single-Ioop synthesizer (with or without a mixer) is shown in Fig. 11-3a. The phase detector is a three-state PD (see Fig. 4-8b). The loop filter is active with essentially infinite gain at dc. Therefore, theaverage of its input Vd must be zero , where

Vd 三 Vu -VD

If there is no offset voltage VdO' then Vd consists of pulses of zero width. In practice there is always some Vdo (shown negative in Fig. 11-3b) , and Vd must have pulses wide enough to make the average be zero. Then the duty cycle 8 must be

8 VdjVdm (11-6)

where Vdm is the maximum value of Vd. For a three-state PD with a -;- N frequency divider, Vdm is related to the PD gain Kd by

Vdm 2τNKd (1 1-7)

The period of the waveform is

Td = l !fr

where /r is the reference frequency at the input to the PLL. It is the pulses in the Vd waveform that cause phase jitter at {}o. The suppression of

these pulses is called rφrence suppression because their frequency is the reference frequency j,.. The Vd waveform experiences a (high-frequency) gain of Kh in the loop filter and a gain of Ko in the VCO to produce a pulse in /1ωo of height

Aω VdmKhKo 2τTNKdK~o = 2τNK (1 1-8)

and width δTd (see Fig. 11-3b). Since {}o is the integral of /1ω0' the change in {}o is the area under this pulse:

/1{} = /1ωδTd = 2τNK8!fr (1 1-9)

Then for a fixed offset Vdo and a fixed bandwidth K , the jitter increases in proportion to N. (The mixer is transparent 的 phase; it doesn't enter into the analysis.)

It is possible to reduce the spurious modulation /1{} still further by adding a low-pass function to the loop filter. One circuit design to do this is shown in Fig. 11-4a. The capacitor C3 together with R] form a low-pass filter with a cutoff at

ω3 = 4/R]C3 、‘... ,

EJ

AV --1i ttz '，'‘‘、

4ω。

VdmKhKo h，.呵__ Area =t;O

4ω。 =KhK戶已

。o

。o=j恥的TMi

(b)

FIGURE 11-3 Phase jitter due to spurious modulation

Vc

凡 '=Khω'3fv<JCit

4ω。 4ω。=Kovc

Area= t;.O

。。。o=ft;ωodt

(b)


The complete loop filter transfer function is then

主主_ V" S +ω2 Ud(s)-Ah35(s+ω3)

The pulse frequency fr of V d is usually much higher than ω312'IT and ω212'IT， so we can approx1mate vc(S)/Vd(S) = KhωÞ (see Fig. 3一12a). In the time domain this corresponds to Vc(t) Khω3JVd(t)dt， and the change in Vc is Khω3 times the area under a V d pulse:

/1vc = Khω3VdmoTd = 2τNKcI<hω30Td (11-11)

(See the Vc waveform in Fig. 11斗的 The corresponding change in 的。 lS

Aω Ko/1vc 2τNKdKhKoω30Td

= 2τNK，ω30Td = 2τNK，ω3哎f，. (1 1-12)

The change /1() in (}o is the area under the positive portion of the /1ωo waveform (see Fig. 11-4b):

/18 = /1ωTi8 τNK，ω30/4f，2 (11- l3)

As noted in section 11-2, the product NK is not dependent on the programmed N. Therefore , Eq. (11- l3) may be evaluated for any consistent pair-Nmin and Km"" for exa呻le. The smallest jitter is realized by mak:ing ω3 as small as possible. For 品abilitvreasons (see section 3-7) , the smallest practical ω3 is 4Kmax. For this choice of ω針，

Aθ=τN mino(Kmax!fr?, ω3 4Km缸 (11-14)

EXAMPLE 11-2

The synthe白er in Fig. 11-1 has a PD with 0 = 0.01. Find the necessary K叫hat /1(} is just 0.05 radian. Look at the cases both with and without a pole atω3 ，

The 叫的n叫叫lency isfr = 0.2 M施， and N max = 594. Then for no pole 泌的，Eq. (1 1-9) gives Kmin = /1(}fr!2'ITN δ= 益主且也~. This is a very small bandwidth that will make for a long pull-in time and a larger phase noise.

For apoltatω3 = 4KmaxandNmin = 494 , Eq. (1 1-14)givesKma/ = /1(}fr2/τN一 δ= l29(krad/8):?nfkmax = lHl.4 釘恤ad仇/旭s. T刮h咒1en臼n fl加romE肉q. (仙11引， K凡叮mm=垃虹鎧坐s. This i的s a more reasonable ba吋wi拙， but it can stiII be improved , as 品next example shows.

司司，

Sec.11-4 Spurious Modulation 247

EXAMPLE 叫一3

The synthesizer in Fig. 11-2 has a PD with δ= 0.01. Find the necessary K with a pole at ω3 so that /1(} is 0.05 radian.

For apole 泌的 = 4Kmax andNmin = 100, Eq. (11-14) gives Kma/ = /1(}jr2/τNmino = 636 (krad!s?, and Kmax = 25.2 krad/s. Then Kmin = (100/200)Kmax =旦巫坐過盔，This is some improvement over the 9.5 krad/s in Example 11-2.

EXAMPLE 11-4

The synthesizer in Fig. 11-5 achieves the same range and resolution oflo as that in Fig. 11-2, but N changes by a factor of 10 1 rather than a factor of 2 over the range. For a PD with δ0.01 ， find the necessary K with a pole atω3 so that /1() is 0.05 radian

For apole 泌的= 4KmaxandNmin = I , Eq. (11-14)givesKmax2 = /1骯2/τNminδ=

6.36 X 10 1日 (rad/s戶， and Kmax 252 krad/s. Then Kmin = (1 /101)Kmax = 2.主主且也s.This is not even as large as the Kmin in Example 11-2.

The three examples above i1lustrate a couple of points. Both the mixer and the divider reduce the output frequency before it is applied to the PD. What share of the job should each have? For a given reference suppression , K is larger if N is kept small. But if N is so small that N majN min is large , then K also varies over a large range. This forces Kmin to be much smaller than Kmax and ω3' It can be shown from Eqs. (1 1-3) and (1 1-14) that for a given 11(}, Kmin is maximized for

NmajNmin 2

ι

1 to 101 FIGURE 11-5' Frequency synthesizer for Examp1e 11-4


11-5 DMDED OUTPUT

掛拓掠;:荒:C∞O叮臼p仰on岫d由s tωot伽he top octave of a p閃m即lan佩1

;謂結t扭3剖古掛叫H♂浩謊:;:引制;l喘告詰引itH!z喘嗨(混謊E且叫肘:ifit肘;認謊咐5古吋)5 i 您吉古i!嚨j2忠;5i:討扣:?T令吋?控世古叮才?T弓:::::苦抗踹♂缸品踹2z泣:;:2到珈f訪!告i2旦:;;苛:借:站盟i詰立立j:許?FG此恥芷缸川:扎況叮;丈芯泣臼iZ立U::立;: :

10' = jν1000 = N(4 Hz) (11-15)

which vaItes from 2092Hz to4184Hz-over the range Of N The high rJC will allow a higher PLL bandwidth K , and 伽 pull-In time will not be jo long

11-6 PULL-IN TIME

zrzri叫~ for a PLL wit

Tp ωedK 一 2τN L )K - N τNω2 (1 1-16) 0.5N，ω2

混合叫:13叮叮?127rrzziLZCil竺;加rJ;4

523 to 1046

2092 to 4184 Hz

九 =65sec

fo

FtGURE 11-6 Audio frequency synthesizer

可

Sec. 11-6 Pul l-ln Time

523 to 1046

fo

2 ,092 to 4.184 MHz

九 =65ms

FIGURE 11一7 Synthesizer with divided output

EXAMPlE 11-5

249

f2

The audio synthesizer in Fig. 11-6 has a PD with (3 = 0.01. Choose K andω2 so the frequency jitter Ô.ωis only 271"(4 Hz). Find the pull-in time when N is changed from 1046 to 523.

For ω3 = 4Kmax , Eq. (1 1-12) gives Ô.ω 871"NminKmax2(3/fr. For Nmin = 523 andlr = 4 Hz , Ô.ω= 8τrad/sec requires Kmax = 0.875 rad/s and Kmin (523!l046)Kmax 0.437 rad/sec. Choose ω2 = Kmin/4 0.109 rad/s-一一位s high as possible for fast pull-in.

The initial frequency is 10 4184 Hz , and the final frequency is 2092 Hz. Then leo 4184 - 2092 Hz 2092 Hz. The final divider value is N Nmin 523 , corresponding to K = Kmax = 0.875 rad/sec. Then from Eq. (1 1-16) , Tp = 525.5 seconds , which is certainly excessive for most applications.

EXAMPlE 甘-6

The audio synthesizer in Fig. 11-7 has a PD with (3 0.0 l. Choose K and ω2 so the frequency jitter Ô.ω ， is only 271"(4 Hz). Find the pull-in time when N is changed from 1046 to 523.

For the synthesizer in Fig. 11-7 , all frequencies to the PLL are scaled up by a factor of 1000 from those in Fig. 11-6. Then if we choose Kmax = 875 rad/s , and ω2 = 109 rad/s (scaled up by a factor of 1000 from those in Example 11-5) , the spurious modulation will be Ô.ω=2τ(4 KHz). After the -7- 1000 frequency divider, the spurious modulation is Ô.ωF = 2τ(4 Hz) , as desired.

For N = 1046, the initial frequency isi, = 4.184 MHz , and the final frequency is 2.092 MHz. Then/co = 4.184 - 2.092 MHz = 2.092 MHz. The final divider value is N

523. Then from Eq. (1 1-16) , the pull-in time is Tp 皇之旦旦， which is barely noticeable in a human time frame.


11一7 MULTIPLEXED OUTPUT

It is difficult to make a VCO based on an L-C osciIlator with a range of much more than a factor of four because of the limited range of a varactor (see section 5-3). At high frequencies , the VCO may have a range of only a factor of two (an octave). Multivibrator VCOs can have a wide range , but they are too noisy for many synthesizer applications. Therefore , a synthesizer with a wide range must often be realized by dividing the output frequency by various amounts. For example , the audio synthesizer in Fig. 11-7 generates the tones in the top octave of a piano. The next lower octave can be obtained by dividing by two , and the next octave below that is obtained by dividing by four, etc. The circuit in Fig. 11-8 shows a binary counter used to divide10 by 2代 where M is 0 to 6 depending on the stage of the counter. Thus , the six stages generate the next six octaves below the top octaveι'. A multiplexer (controIled by the digital number M) selects the desired octave , so from Eq. (1 1-1日 the final output frequency is

此'12M = N(4 Hz)I2M (1 1-17)

For N = 523 to 1046 and M = 0 to 6 , this gives a range from 32.7 Hz to 4184 Hz (about the range of a piano). In the top octave , the resolution is 4 kHz!lOOO 4 Hz. In the bottom octave , the resolution is 4 Hzl64 = 0.06 Hz (this is the same percentage rcsolution as in the top octave).

11-8 MULTIPLE-LOOP SYNTHESIZERS

If a synthesizer with a frequency resolution as fine as 0.01 % is needed , more than one PLL must be used in the design to keep the spurious modulation and pull-in time reasonable. Suppose a frequency synthesizer is to have a l-kHz resolution for a frequency range from 10 MHz to 20 MHz. An attempt at realizing this with a single-loop synthesizer

2ω12 to 4184 Hz

Binary counter

Multiplexer

523 to 1046

FIGURE 11-8 Synthesizer with multiplexed output

花/計，

32.7 Hz to 4184 Hz

一『可

251 Sec. 11-8 Multiple-Loop Synthesizers

10,000 to 20,000

FIGURE 11-9 High-resolution synth巳sizer(impractical realization)

:詰古部?肥i任1E拉i吉i:芯i吉ii叫器古叩:i泣山趴丘缸趴iL[♂叫:;計}H喘j站Ei惦;注浩古慌E吉f巳叫:立茄叫刮:i3i5抗拉:芯引t古叫:甘諒謊: 昀m叫叫叫s叫叫叫u叫山lkt &ι: J品品泣站i立:出t ;泣2泣: J;泣1f咒:心;血?2;;泣江:U;:: J拾;泣f;且i巳r?: :;泣: 1 ll卜凹-一一N叭川1 pr仰仰rov仰州Vreso叫lu叫lti叩on扎1L, geIIeratingh=N2(loo kHZ).The third PLL sums these tw f q

generate

10 = 12 + 11' = (1 00 N2 + N 1)(1 kHz) (1 1-18)

Fore…ple , if j,) = 15.5加Hzi必s d由仰伽巴臼叩s叮i叫伽 prop叮叭紀蚓叫叫et訓叫t缸吋伽ti

l73.Note that d1e maximum valueoflV in any loop is only 200 , andjL is not iess than loo

zgJZJZJZsZ:立川江JJ亂iZZA:1;1bIZrhIT品::1:

4

100 kHz

f2

99 to 198

9.9 to 19.8 MHz

f。一起

fí = N,t,l100

f2 =N2ι

ι =f2 +fí = (N2 +N,/100)fr

FIGURE 11- \0 Multiple-Ioop synthesizer


cost and board space. These ICs include a three-state PD and all necessary frequency dividers.

Which of the three PLLs in Fig. 11-10 is critical in determining the phase jitter? The following example lends some insight.

EXAMPlE 11-7

The bandwidth of each PLL in Fig. 11-10 is Kmax 2'11"(5.0 kHz) 3 l.4 krad/s corresponding to N = 100. This is a compromise between a smaller K , which is better for reference suppression , and a larger K , which is better for phase noise suppression. AIso , for each PLL ， ω3 4K max 126 krad怨， and δ0.0l. Find the peak-to-peak phase jitter ~θat the output due to spurious modulation.

Let the peak-to-伊拉 jitter at 后， 11 " and 12 be represented by ~吭， MJ1' , and M)2.

From Eq. (11-14) , N 1 = 100 gives ~θ1 = 0.31 radian , and N2 = 99 gives MJ2 = 0.30 radian. But fI' = 1/100, so ~81' = ~8/100 = 0.0031 radian.

Let the peak-to-peak jitter at 10 be ~83 when fI' and 12 are jitter-free. Then Eq. (1 1-14) applies to PLL3 with N = 1 (no divider). The minimum reference for PLL3 is fI'

100 kHz , and Eq. (1 1-14) gives ~83 = 0.0031 radians. When fI' and后的 not jitterfree but have jitter ~θl' and ~82 ， then the total phase jitter at the output is

~8 = ~83 + (~81' + ~(2) IH( jωr)1 (1 1-19)

where ωr is the frequency of the phase jitter from PLL1 and PLL2; that 芯， ωr 三 2甘正 = 2τ(1 00 kHz). This makes the approximation that the phase jitter waveform is sinusoid划，which it is not (see 80 in Fig. 11-4b). Therefore , Eq. (1 1-19) is conservatively large in its estimate. For ωr>> ω3 = 4K，的 in our case , then IH( jωr)1 = K，ωiωr2 = 4(KIωr)2 =

(κ/πf，? Then Eq. (11-19) becomes

~8 = ~83 + (~81' + ~(2)(KIπ五? (11-20)

= 0.0031 + (0.0031 + 0.30) 0.01

= 0.0031 + 0.000031 + 0.0030 = 0.006131 radian

The middle term is contributed by PLL1, and this is negligible. The first and last terms are contributed by PLL3 and PLL2, and these are about equal.

11-9 PHASE NOJSE

The principle sources of phase noise in a synthesizer are the VCOs and to a lesser extent the reference frequencies. To find the contribution from each of these sources , we need the phase transfer functions for the PLLs making up the synthesizer.

可

253

Sec.11-9 Phase Noise

bfif:站出11335點HJ抖(Vdml2τN) F(s) K)s__ FJ勻

(Vd,j2'11") F(s) Kol~ 8,+ 80 = + (VdmI2'11".的 F(s) Kols

1 + (Vdml2τ的 F(s) Ko/s -

k d F(s) Kols N Kd F(s) Ko/~ S Or+I+kd F(5)KJSO2

1 + Kd F(s) Kol

= N H(s) (}r + H(s) (}2

so the transfer functions are

8)(}r = N H(s)

。J(}2 = H(s)

(1卜21)

(1 1-22)

hown in Fig. ll-llc. We already have from

lfti;:tzti1321:tZZJ泣ZLgmfonto 伽恥 output:8)8n = He(s)

(11-23)

The frequency response piotted in Fig.316IS repeated here in Fig.ll-llc.The total

spectral density of 80

(s臼 section 6-1) 的 therefore

φfI" = \He12φen + N2\H12φer + IHI2φ的(11-24)

where <Þe鬥丸，叫 φen are the sp吵1 densities of ()" (}2' and 仇 The area underφflo gives the mean square phase noise (}o\

EXAMPlE 11-8

izer in Fig. 11一lO has N2=198and Nl=200SOL=2O MHz.PLLl and

l謊話fifiiyjFEfilt話:i7133233-tzzz;其ig. 11卜叫一spectral density φ0枷昀0- 1胎6 rad2勾1Hz. Find the rrr口ms phasenOlseι

可

(a)

Kd = Vdm/2πN

(b)

IIioI021 =NIHI N

100/8rl = IHI

-一--+--

100/Onl = 1 凡|

ω2 K ω3 w

(c)

FIGURE 11-11 Phase transfer functions {}oLØ,. and Oj02

?~4

Sec. 11-9 Phase Noise

10-6

1 。一7

10-8

6.4 x 10- 9 一一-

10-9

1。一 10

10- 11

4x10- 12 一一槍，

10- 12

(rad2/Hz)

\ \ \ \

\ er= 10- 16 rad2/Hz

|\ /en N=200

| \_______IHe1 1句戶。1 = ez

A A

A c、

c、企、金、是、金、金、是、金、、c、

內12er 、金、心c、是、

500 2.5 k

b、

1M

FIGURE 11-12 Phase spectraI densities for PLL1 and PLL2 iri Example 11-8

255

f (Hz)

If we approximate N = 200 for both PLL, and PLL2, then the analysis is the same for both loops:

φ8'φ82 = IHel12φOn + N2 IHd2φ8r

where Hel and H , are He and H corresponding to bandwidth K,. The third term from Eq. (1 1-24) is not pr的ent because there is no mixer. The two remaining terms are plotted in Fig. 11-12; it is clear that the first term dominates. Therefore , φ0圳 φ0位2 = 1恤H爪此e ， 12φ 0伽n

One reference frequency for PLL3 is];λi' with ()吶" = (},1l 00 and spectràl densityφ。 lF=φ8 ，/(100)2. Therefore , Eq. (1 1-24) for PLL3 becomes

φ。o IHe312φ8n + IH312φ8" + IH312φ82

where He3 個d H3 are He and H corresponding to bandwidth K3. These three terms are plotted in Fig. 11-13; it is clear that the second term is negligible. Then

存 =J hzif==f:|HJhn4+flA|勻。2

可

257

W咐h倪 φ斟0伽叫n(恆K)ρ/甩2'lT甘叫) = (ο2τ可電νrfiμ仄ì，/K)ι釗)f旬@o = 6.4 x 1ω0- 9汽ν， a term involving @o is negligible , and the factor of K3/(K3 + K)) is necessary because of the additional break at K3!2'lT that IH312 causes. Then the to叫哥= 16.3 X 10- 6 + 23.6 X 10- 6 = 39.9 x 10 • 6 rad2, and ()o rms Q.00632 rad.

Prescaling Sec.11-10 Chap.11 Frequency Synthesizers

(rad2JHz)

10-6

10-7

。 10- 86.4 x 10-9 一→』

256

One practical consideration in designing frequency synthesizers is the speed limitation of the components. The programmable -7 N frequency dividers , in particular, are typically limited to a maximum frequency of 25 MHz. 的問， for example , the specifications for the MC40l8 with an "early decode" feature for reprogramming. [5] This restriction has led to some tricks in realizing the -7 N in high-frequency synthesizers.

Consider the single-Ioop synthesizer in Fig. 11一14. It generatesfo = N(l MHz) = 100 MHz to 200 MHz for N = 100 to 200. The -7 N is nottoo large , andfr is not too small a fraction offo' so spurious modulation and pull-in time should not be a problem. But the 200 MHz output frequency appears directly at the input of the -7 N , which can handle only 25 MHz maximum.

One possible solution would be to use a fixed -7 10 prescaler before the -7 N so it sees only 20 MHz , as in Fig. 11-15. Iffr is reduced to 100 kHz , then we again havefo =

ION)(100 kHz) = N) (l MHz) = 100 MHz to 200 MHz for N) 100 to 200. But the overall N = ION) = 1000 to 2000 , andfr is only.ι11000. This willlead to problems with spurious modulation and pull-in time.

It is not such a problem to make a fixed divider, such as the -7 10 in Fig. 11一 15 ， that can handle high frequencies. It is the programmable dividers that are restricted to about 25 MHz. A compromise is to use a divider that can be programmed for only two values. Such two-modulas prescalers can be made to work at frequencies as high as 600 MHz. [6]

The synthesizer in Fig. 11-16 uses a two-modulas prescaler to realize a -7 N that handles high frequencies. The price is that it takes four devices to realize the division: a -7 N) frequency divider , an A counter, a -7 10/ -7 11 prescaler, and a control unit such as the MC12014. Under command of the control unit, the prescaler divides by either 10 or

甘-10 PRESCALlNG

f

(Hz)

函，

-bu

L』'，他

、一

\一、

\1 、、

\?、

\\、、、

心、\、

\一、\\

b、、\

、人Y、-、

11

卜、-、、、

\\、‘、\、

、s、

i、、

信、、、

t、、

1

\\\\l kr、\、

、心而γ\

、、有

心hy

w\

司、

科

/j\\一

\-\\一

\\一

\\F \\情\\司/

、

1

剝/

H -t/

1M

<Þ.肘'=<Þ81 /(1∞)2

Phase spectral densiti的 for PLL3 in Example 11-8

100 k 10 k iknm d5

何

|純肉。l'

、/ /'fa \

5∞ ω2/27r

1 k

FIGURE 11一13

1.6x 10-9 -→』10-9

10- 10

10- 11

10- 12

τT

了 h. @。

The evaluation of the first integral is given by Eq. (6-55):

fa

y + IHe3 12φ叫 <ÞOn(几/2叫[于f

16.3 X 10-6 rad2

where <ÞOn(K312的 = (2τr!iK3)句。= 1.6 X 10-9, andy = JI二函口正= 0.775. The e ILlation ofthe second integral is gmlby a modined fEAm ofEq.(635):

i戶

L y

IH312φ02 df = φOn(K/2τ) I 主L ﹒ K3L 4 K3 + K)

f

FIGURE 11一14 High-frequency synthesizer (impractical realization) 100 to 200

+

= 23.6 X 10 • 6 rad2

258

4 100 kHz

100 to 200

ι

100 to 200 MHz

Frequency Synthesizers Chap. 11

FIGURE 11-15 Synthesizer with fixed presca1er

11. The control unit monitors the outputs of the -:-. N 1 and the A counter to know when to select the -:-. 10 or the -:-. 11.

Suppose we want to divide .t;, by 128 in order to synthesize 128 MHz. Then N 1 is set to 12 , and A is set to 8. The sequence begins with the control loading the A counter with 8 and selecting -:-. 11 for the prescaler. Then after 11 cycles of巴ι ， the A counter decrements to 7. This continues until the A counter reaches zero , signaling the control to select -:-.10 for the prescaler. So far the -:-.N1 (a -:-.12 here) has received 8 pulses from the prescaler, so it needs 4 more before it puts out one pulse itsel f. Each of these next 4 correspond to 10 cycles of 10' Therefore , the total cycles of .t;, required to produce one puIse from the -:-. N 1 is

11 + 11 + 11 + 1 1 + Il + 1 1 + 1 1 + 11 + 10 + 10 + 10 + 10 = 128

When the control senses this pulse , it loads the A counter with 8 , selects -:-.11 for the prescaler, and the sequence starts over. From this example, it should be clear that the circuit realizes a frequency division of ION1 + A. Therefore

10 = (10 N 1 + A}ι (1 1-20)

Note that the operation requires that

A 三 N 1

ι

100 to 200 MHz

ι = (10N, +A)fr

(11-21)

FIGURE 11-16 Synthesizer with two modulas prescaler

可實

References 259

Therefore , the circuit can't divide by 79 , which would require N 1 7 and A 9. However , prescalers are available with -:-. M/ -:-. (M + 1) capabilities , where M is not necessarily 10. Then the generalization of Eq. (1 1-20) is

10 = (MN1 + A);;' (1 1-22)

For example , for M = 6 , the prescaler can divide by either 6 or 7. Then10 = (6 N 1 + A) 1 MHz , and .t;, = 79 MHz requires N 1 = 13 and A = 1, which satisfies Eq. (1 1-21). Note that with M = 6,fo can now go no higher than 150 MHz if the -:-. N 1 is to see no more than 25 MHz. Therefore , there is a tradeoff in selecting M.

REFERENCES

[1] MECL Device Data , Motorola Semiconductor Products Inc. , Phoenix , 1988 , section 6. [2] U. L. Rohde, Digital PLL Frequency Synthesizers, Prentice-Hall: Englewood Cliffs , NJ ,

1983 , section 4-6. [3] CMOS/NMOS Special Functions Data, Motorola Semiconductor Products Inc. , Phoenix ,

1988 , section 6. [4] V. Manassewitsch, Frequency Synthes閏月， Wiley: New York , 1997, sections 2-1 and 6-2.

[5] CMOS/NMOS Special Functions Data.

[6] MECL Device Data.

ttt

底線

ttt

底線

'

LIST OF SVMBOLS h\IDEX

B; Noise bandwidth of input bandpass filter Vo VCO output voltage BL Noise bandwidth of PLL tansfer function H Vo Peak value ofν。Bm Message bandwidth Vp Pull-in voltage from phase detector during CT Varactor capacitance acqms ltIon C, Capacitance in crystal model Vj Oscillation voltage in VCO Cx Externa1 capacitor for multivibrator VCO V j Peak value ofνl F(s) Loop filter transfer function V2 Voltage across R2 in loop filter fa Offset frequency below which f1icker noise V3 Voltage across C in loop filter

dominates 品。 Density of ones in an RZ data signal Forward gain，的 Lock-in frequency , 141, 145, 160,

fb Ha1f-bandwidth of resonant oscillator' s tank ßO Spurious phase modulation (p巴拉-to-peak) Accumulated jitter, 236 Free-running voltage , 11 164

Ic Half-bandwidth of filter following oscillator ßω Spurious frequency modulation (peak-to-peak) Acquisition: Frequency dernudulation , 205 Loop filter , 20 , 25 fm Offset frequency from “ carrier" 4ωz Input 仕equency deviation aided , 174, 177 Frequency detector, rotationa1, 177 actlv巴， 26

L PLL output frequency in Hz Aω。 Output frequency deviation frequency , 155 Frequency divider，的， 240 passlv巴， 20

L Reference frequency for synthesizer φ'x (f) Power spec仕a1 density of x(t) self, 157 , 164 Frequency error, 157 pole , 38

G(s) Forward gain of PLL control loop 。d Phase difference between input and output Aided acquisition , 174, 177

averageω。 158 zero , 27

H(s) PLL phase transfer function signals Bandwidth , 3 dB , 9, 16, 17, 22 initia1, 161 Loop gain, 18

He(s) Transfer function from 8j to 8e {}e Phase error between input and output signa1s Bandwidth , noi間， 111 Frequency rnodulation , 202 Mixer , double-ba\anced , 52

random，的lHp Peak value of transfer fu恥tion IH(j叫i {}em Value of 8e for maximum phase detector Baud, 211 sinusoida1, 148 Mixer in synthesizer, 241 K PLL 3-dB bandwidth voItage Beat note , 159 , 168

Frequency noise , 207 弘10dified phase detector Kd Phase detector gain 院 Phase of PLL input signal Frequency rarnp , 145 characteristic , 75 Kh High-frequency gain of loop fi Iter {}n Oscillator phase noise when not in a closed Clock recovery, 211

Frequency step, 143 Modulation bandwidth , VCO, 82, Control voltage , static , 12 91 Km Multiplier gain loop Control voltage , VCO , 11 Frequency synthesizer (See

Multiple-Ioop synthesize郎， 250Ko VCO gain 。。 Phase of PLL output signal Costas loop , 200

Synthesizer, frequency) Multiplexer in synthesizer, 250 M Phase detector figure of rnerit 。。 Power spectral density of white phase noise Counter, prograrnmable , 240 Multiplier n(t) Noise “)c

A verage frequency e叮or during acquisition Crysta1 VCO , 94 Gilbert multiplier, 50 double-balanced , 52 N Frequency divider ratio 《是)d Detector frequency-fundamental frequency of Cumulative jitter, 232 , 236 four-quadrant , 47，紗， 51No Power spectral density of white noise Vd Cycle slip , 131

Hold-in range, 135 Gilbert, 50 Tp Pull-in time We Frequency error during acquisition overdriven , 54 T, Mean time between cycle slips W eo lnitial 仕equency error during acquisition Damping ratio, 34 Multivibrator, voltage-controlled,

Vc VCO control voltage W; Average (carrier) frequency of input signal Detector frequency , 48 , 68 , 72 E吋ection constant, 99, 101 83 Vd Phase detector output voltage (average) “)L

Lock-in frequency-吋九 for which acquisition is DeviI' s advocate , 261 Injection effects , 102 , 2個Divider, frequency , 68 , 240 Input frequency , average , 14, 136 n-state phase detector, 68

νd Phase detector output voltage (instantaneous) complete Divider, programmable , 240 Input frequency deviation, 136 Natural frequency , 34 Vdm Maxirnurn value of V d Wm Modulation frequency of input signal Intersyrnbol interfer，閃閃， 232 Noise bandwidth , 111 Vdo Phase detector free-running voltag巴， or offset W n OsciIlator frequency noise when not in a closed 凹的tic store, 233 Noise bandwid銜， PLL , 116

vo1tage loop ExcIusive-OR phase detector , 55 Jitter, 211

Noise 10w-frequency cuto缸， 119 VH Logic “ high" voltage “)0

Output 企equency of VCO Extended range phase detec帥， 68accurnulation, 230, 236 Non-retum-to-zero data , 212

νt PLL input voltage 包)p Pull-in frequency-maximum 鈍。 for acquisition offset , 227 NRZ data , 212

V j Peak value of Vi 。)p Peaking frequency of IH(jωm)1 Figure of merit, phase detector , pattem-dependent, 218

V{ I吋ection voltage into VCO Wj Loop filter pole frequency less than K 52, 164 random, 232 Offset frequency, 121

V{ Peak value ofη 。)2 Loop fiIter zerö frequency First-order phase-Iocked loop , 18 systematic , 232 Offset jitter, 227

Flicker noise , 121 VL Logic “ low" voltage 也)3 Loop fiIter pole 企equency greater than K

260

山川心情芳、孔、如前向開可關糊如是聰哥輛輛1至ζ2

262 Index

Offset voltage: Prefilter, 111 Step response: loop filter , 31 Prescaler, two-modul訟， 257 frequency , 143 phase detector, 29 Programmable counter, 240 phase , 36 Ones densi句， 228Pull-in range , 163 , 170, 164 Symbols , list of, 261 Output frequency deviation , l3 Pull-in time:

Synthesizers，台equency ， 239 Overdriven multiplier, 54 aided three-state PD , 177 mixer in , 241 Overshoot, step response , 36 passive loop filter, 166 multiple-Ioop, 250 rotatíonal FD , 181 multiplexer in , 250 Patten叫ependent jitter, 218 self acquisition , 162, 164, 166 phase noise , 252 Peaking frequency , 34 synthesizer, 248 prescaler in , 257 Phase demodulation , 192, 195 three-state PD , 173 pull-in time , 248 Phase detector, 47 Pull-in voltage , 160, 164 single-Ioop , 239 characteristic , 11

Systematic jitter, 232 characterist眩， modified , 75 Q , resonant VCO, 92, 121 figur，且 of merit, 52 Quadricorrelator, 179 Three-state phase detector, 61 , 仕巳e-runmng voltage , 11

78, 171 offset voltage , 29 Range, phase detector, 11, 139 Timing jitter, 211 range , 11 , 139 Range , VCO 11 , 81 Timing margin , 229 exclusive OR , 55 Reference frequency , 239 Transition density , 228 extended range , 68 Remodulator, 200 Two-modulas prescaler, 257 n-state , 68 Return-to-zero data, 212 Two-state phase detector, 59 sample-and-hold，的 Rotational frequency detector, 177

three-state , 61 , 78 RZ data, 212 Varactor diode, 87, 95 two-state , 59 VCO: Z-state , 65

Sample-and-hold phase detector, characteristic , 12 Phase differenc巴， 11 67 control voltage , 11 Phase error respons巴， 43 Second-order phase-locked 100p, 22 crystal , 94 Phase error, 9, 11 SeH、 acquísitíon ， 157, 164 gaín , 13 Phase modulation , 185 Signal-to-noise ratio , 116, 207 linearity, 82 Phase noise Slip detector, 73 , 74 modulation bandwidth , 82 , 91 C叮or， 119 Spectral densi吟， power, 109 range, 11 , 81 mput, II6 Spectral width , oscillator, 104 resonant, 86 output, II7 , 126, 128 Spectrum analyzer, 124 VCXO , 94 synthesizer, 252 Spurious modulation , 187, 189, Voltage-controlled crystal VCO; 120 242

oscillator, 94 Phase spectral density , 125 Squaring loop , 196 Voltage-controlled oscillator且， 81Phase-shift keying , 195 Static control voltage , 12

Power spectral density , 109 Static phase error，的， 14, 23 , 28 Z-state phase detector, 65

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PHASE-LoCKED Loop CIRCUIT DESIGN - pudn.comread.pudn.com/downloads198/ebook/929907/Phase-Locked Loop... · 2009-09-20 · 10cked 100p operation in these app1ications. The approach