PETER KHANH HOANGCell Phone (408) 209 – 0688, Home Phone: (408) 262 – 9173; Email: peterhoang20@gmail.com

Summary:- Validate, Characterize CPLD, FPGA IC and SoC and Release to production.- Use Verilog Simulation and schematic capture to debug to component level in whole chip

environment set-up. - Generate Characterization Plan documents and specification documents. - Design pattern for timing measurement and for functional tests. - Bring up Test Board and new silicon. - Work with cross functional teams to resolve low yield, reliability test fail and customer

issues. Familiar with failure analysis techniques like SEM,FIB, Liquid Crystal, Probes, …- Generate Test Board documents, order and interface with vendors to have good pricing

and services.- Experience in bench set up equipment and high speed IO testing for SERDES, PLL and

DDR. - Write Python codes for bench automation to improve test time by 3x.

PROFESSIONAL EXPERIENCE:09/2012 – 08/2013: Validation engineering position contract at Intel (Santa Clara site) through CompuCom Systems Inc. 7171 Forest Lane, Dallas, TX 75230.

- Experience in platforms/CPU validation across Process, Voltage and Temperatures (PVT).- Experience in Window8, DOS, EFI, TAP/ITP and scripting languages.- Experience in board bring up, system validation and operation, multiple displays (HDMI, DP,

EDP & SDI).- Experience in concurrency tests of CPU performance, Memory stress, IO stress (interface with

PCIE, DDR Memory, Camera, USB2/3, EMC/SSD/SATA drivers).- Experience in changing system configurations and enabling new Hardware Add On.

11/1994 – 12/2011: Lattice Semiconductor Corp., San Jose, California.

06/2006 – 12/2011: Senior Staff Product Engineer- Experience with all phrases of semiconductor chip manufacturing (development, fab, package,

test, reliability and manufacturing).- Experience in validation SoC Device (Power Management IC and FPGA/PLD).- Experience in creating technical documents (characterization report, software timing and

datasheet)- Experience in characterization designs for timing measurements.- Experience in pre-silicon tasks (characterization plan generation, test board design and order,

characterization pattern generation and simulation).- Experience in functional patterns generation, simulation and convert for ATE and bench

verification.- Experience in working with test engineers to develop test flow and test coverage, minimize test

time and complete package for manufacturing transfer.- Experience in working with global cross functional teams.- Collaborated with Reliability to provide burn in pattern/board and to resolve failures.- Good software skills and scripting (Unix, Linux, Perl and Python). Wrote Python codes for

semi-auto control of a bench test set up to improve test time 3 times.

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- Good background in statistics (experience with SAS and JMP tools).- Experience in high pin count and complex packaging.10/2000 – 06/2006: Staff Product Engineer- Experience in new product development tasks such as characterization, yield analysis, test

development and reliability tests.- Experience in characterization pattern generation and simulation.- Experience in SERDES and PLL characterization.- Experience in bench setup equipment (BERT, Logic Analyzer, Oscilloscopes, meters,…).- Good team player: flexible and adaptable (remotely interfaced with multi-cultural groups).11/1994 – 10/2000: Product Engineer II- Experience in new product characterization, yield enhancement, test development for PLD.- Correlated and checked out wafer sort and Final Test programs.- Generated Burn-in patterns and test vectors.- Wrote characterization reports.- Maintained product web pages.

01/1990-11/1994: SUPERTEX Inc., Sunnyvale, California06/1991-11/1994: Product Engineer I- Experience in characterization of CMOS devices and High Voltage (200V) CMOS devices.- Experience in product manufacturing (test specs and work order preparation, support test floor

and QA).- Experience in Failure Analysis techniques (micro/pico-probes, laser cut, liquid crystal and KLA

EMMI system) to improve the yield and to resolve customer issues.- Experience in reliability tests (HTOL, 85% Humidity, ESD, Temp Cycle and Autoclave tests).01/1990-06/1991: Technician III- Collected characterization data.- Supported production in setup and troubleshoot test system for wafer sort and final test.- Built load boards for bench setup and tester.- Verified QA failed, burn-in failed, wafer sort and final test low yield (on bench/tester).

01/1988-12/1989: MASS MICRO SYSTEM Inc., Sunnyvale, CaliforniaElectronic Technician,- Built prototype case for disk drives. Developed test and performed QA disk drives.   Installed

Macintosh OS.

EDUCATION:1992-1994: UC Berkeley Extension, Menlo Park, California

Four pertinent courses: Process, Physic Device, Digital Design and Analog Design

01/1985-12/1987: California State University, Sacramento, CaliforniaBachelor of Science: Computer Science with concentration in Electronics

Background in EEPROM, Static RAM, Structure programming languages, Assembly Language and Script Languages (Perl, Python).

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