Peter W PhillipsAshley Greenall

Matt WarrenBruce Gallop

Rick Shaw08/03/2013

2

Recall: ABCN25 Functional Test

Passive Probe CardBonded Chip Card& Common Driver

“Driver” board was actually just a buffer and MUX, really driven by NI hardware

3

Recall: ABCN25 Wafer TestDigital Test Vectors supplied by Francis Anghinolfi as .vcf files• Block A CV• Block B CI W shunt• Block C CI M shunt1• Block D CI M shunt2DVM measurements• DAC linearity using ABCN internal

MUX• Vout from internal LDOAnalogue Tests• Two Point Gain• Two Point Trim

Wafer A5GJ0HX

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ABC130 Test Proposal

SAMTEC

Standard Probe card ends in 0.1” pitch header: add mezzanine PCB to adapt

to two SAMTEC headers. (RH header is used alone for hybrid R/0)

ABC130

“Baby” Sensor(optional)

HV

Propose companion single chip PCBwith identical SAMTEC pinouts.

This takes one ABC130 and (optionally) a “baby” strip sensor

Driver PCB

SAMTEC

SAMTEC SAMTEC

SAMTEC SAMTEC

Not to scale!

100n

F

Edge Sensor wired to A9, A10 ?

ABC-130

100n

F

100n

F

100n

F

Final Pad Frame is on hold pending betterunderstanding of FE stability concerns

=> concentrate on Driver PCB for time being

Analogue MUX pads here

PRELIMIN

ARYSCAN TEST Pads here

5

6

SAMTEC 40 SAMTEC 50

SAMTEC 40 SAMTEC 40

MO

LEX 12

Spartan3AN

AD7998

AD7998

AD7998

SHUNTCONTROl

BLOCK

TO HSIO

TO DEVICE UNDER TESTUse both headers for ASIC testRH cable only for hybrid test

ASIC POWERUnused forHybrid test

What’s on the Driver PCB?(simplified)

Spartan initially programmed as“passive” SLVS buffer

BUT can be programmed as

HCC for hybrid & module tests

Not to scale!

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ASIC ONLY CONNECTOR1Spare2spare3PadTerm 1.2V CMOS4Addr0 1.2V CMOS5Addr1 1.2V CMOS6Addr2 1.2V CMOS7Addr3 1.2V CMOS8Addr4 1.2V CMOS9VDDD pre LDO

10VDDD pre LDO11DVDD post LDO12GND13DVDD post LDO14GND15VDDA pre LDO16VDDA pre LDO17AVDD post LDO18GND pre LDO19AVDD post LDO20GND post LDO21AVDDMON post LDO22DVDDMON post LDO23VDDD pre LDO24VDDD pre LDO25DVDD post LDO26GND27DVDD post LDO28GND29RSTB_pad 1.2V CMOS30ScanEnable 1.2V CMOS31ScanInBC 1.2V CMOS32ScanOutBC 1.2V CMOS33ScanInClk 1.2V CMOS34ScanOutCLK 1.2V CMOS35GND Analogue36AnaMux Analogue37GND Analogue38TestCom Analogue39Switch Analogue40Switch Analogue

COMMON (HYBRID) CONNECTORHYBRID MODE ASIC MODE

1SHUNTCTL SHUNTCTL2GND GND3Power Power4GND GND5Power Power6GND GND7Power Power8GND GND9XoffR0-

10XoffR0+11DataR0- FCCLK+12DataR0+ FCCLK-13Vmonitor1 VADD14Vmonitor0 VDDD15BCO+ BCO+16BCO- BCO-17DRC+ DRC+18DRC- DRC-19L0/Cmd+ L0/Cmd+20LO/Cmd- LO/Cmd-21R3+ R3+22R3- R3-23Regulator Enable 1 Regulator Enable 124Regulator Enable 0 Regulator Enable 025Data1- DataL+26Data1+ DataL-27Xoff/on1+ Xoff/onL+28Xoff/on1- Xoff/onL-29NTC130NTC031Xoff/onR2+ Xoff/onR+32Xoff/onR2- Xoff/onR-33DataR2+ DataR-34DataR2- DataR+35Data3- FC1-36Data3+ FC1+37Xoff/onR3- FC2-38Xoff/on R3+ FC2+39DGND GND40DGND GND

PRELIMINARY PINOUTS

“COMMON” header- All SLVS- HCC monitoring lines- Power to (real) HCC

“ASIC” header- All CMOS- ASIC Power- DAC characterisation

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What will be Tested?• Currents

– Shunts and LDOs on and off

• Digital Test Vectors• DAC characterisation

– AnaMux and TestCom

• SLVS / Termination check– ADC to measure HI and LO levels in steady state– Also checks probe contact

• Three Point Gain

• Driver needs extra circuitry over that needed for hybrids– Address & Enable lines – ADCs for analogue measurements– Analogue switch and Shunt Control block

• GND or control line

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Same driver board as for ASIC test(but with different firmware)can be used to emulate HCC.

This may possibly include ADCs.Can make smaller driver PCB

better suited to module (stave) tests if required by HCC schedule.

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ABC130 in SCTDAQ• ABC130 appears as a special input stream• HSIO decodes packets to a 64-bit aligned sequence• Send bit data to ABC on one of 4 streams• Recent addition is the option of a timed L0

• For “CAL+L1A”, but tested with BCR + L0•2 “ABC130s” in a chain have been tested

• SCTDAQ sends commands• Mapping old to new• BCR -> BCR• Soft Reset -> L0IDReset (Aim is to know next L0)• L1 -> L0 + L1 + (R3)

• keeps track of L0 since reset• each is a separate command to HSIO so asynchronous

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N-Mask test (one “ABC130”)•Using test mode (put mask into pipeline)•Here collected in 1BC mode, can also use 3BC• Mask is set

by bit• Readout

interleaved

• Also see R3(ignored for

time-being)

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What’s next?

• Driver Schematic under preparation by Rick– Details being fixed as this progresses– Hope to have something for discussion at Berlin– Then proceed to layout

• Single Chip board and Probe Card– On hold until final pad frame released– Four power domains (two ins, two outs) + stability concerns

=> full custom probe card?• Firmware

– Configure a second HSIO as a “mini-hybrid”– Use this to test firmware/software in detail