PERMANENT INTERCONNECTION ELECTRONIC …downloads.hindawi.com/journals/apec/1981/245087.pdf · 140 I.G. LANG Curnutfive 100-Other20. 0 1978 1 BC 1980)85 )90 YEARS Key:-DlP. Du[In-Line

Electrocomponent Science and Technology, 1981, Vol. 9, pp. 139-1450305-3091/81/0902-0139 $06.50/0

(C) 1981 Gordon and Breach Science Publishers, Inc.Printed in Great Britain

PERMANENT INTERCONNECTION TECHNOLOGYELECTRONIC INTERCONNECTIONS- THE PRINTED

WIRING BOARD

I. G. LANGExacta Circuits Limited- Selkirk, Scotland, U.K.

(Received November 21, 1980; in final form June 8, 1981)

Modern manufacturing techniques which have been developed in respect of interconnection and packaging systemsusing printed circuit boards, are outlined. It is shown that these systems are capable of meeting present and futurerequirements for component mounting, including VLSI.

1. INTRODUCTION

Faced with the bewildering proliferation of alternativeinterconnection solutions it might be possible tounderestimate the advantages of the high volume, highyield PCB industry. However, contrary to popularbelief, the PCB Industry is already meeting thechanging requirements of electronic packaging broughtabout by the impact of LSI and VLSI technology.

It is not the intention of this paper to give an in-depthreview of silicon devices, but it is necessary to highlightsome of the significant trends in micro-electronicstechnology in order to relate adequately to themacro-electronics packaging technology of the PCBsubstrate.

2. INTERCONNECTION TRENDS

In 1980 the Dual In-line package (DIP) was thedominant and standard IC Package. A recent survey byMackintosh Consultants on behalf of Exacta, however,has indicated that chip carriers (CC) and spiderbonding (TAB) will rapidly grow in application. Themost likely scenario is as shown in Figure 1.

3. FACTORS INFLUENCING CHANGE

Considerations behind the packaging change shown inFigure 1 include the following factors:

’Paper criginily given in the Technical Papers programmeof Electronica, Munich, November, 1980.

a) Packaging Density, where product or equipmentsize is a major design criteria.

b) Cost Reduction, to be achieved by space and/orsize saving.

c) Performance, as defined in terms of the signalspeed in the circuit system. The over-all length of theinternal wiring is significant in this respect.

d) DIP Packaging Constraints, particularly with

regard to heat dissipation and of the numbers of input/output pins required.

4. IMPACT OF INTEGRATION

The IC is the driving force behind electronicsdevelopment, and integration at chip level will continueto grow. It will become less possible to treat componentand system/equipment design as separate exercises andthere is an increasing realisation that design should notbe partitioned too early and without reference toanticipated technological advances. For example, theoptimum system design for, say, a 1983 product shouldpredict and utilise a 1983 component or systemarchitecture technology.

It might be thought that as integration grows at chiplevel the macro-packaging would become simplified.This has not been the case in the past and it is unlikelyto be the case in the future as human ingenuity andmarket demands continue to encourage products whichcan have higher performance or cost less. A range ofmacro packaging technologies is and will continue to beavailable but the correct combination to be selected willvary with the industry sector and application, e.g.whether it is a consumer product, an aerospace

140 I.G. LANG

Curnutfive

100- Other

20.

01978 1

BC1980 )85 )90

YEARS

Key :- Dl P. Du[ In- Line PackageCC. Chip Carrier.TAB. Tape Auforncfed Bonding.

BC. Bare Chip.

FIGURE 1 Worldwide I.C. Package usage. (Cumulative % for various technologies).

application, a computer mainframe requirement, or anelectronic toy.The impact of integration on the substrate

requirement can be summarized as follows:

a) Increased interconnection density is requiredwith the increase in number of input/output pins perchip.

b) Earth and voltage planes at precisely controlleddistances from conductors may be required to provideimpedance control and reduce cross talk.

c) Tracks will become smaller to minimisecapacitance and maximise density and yet will have toretain high conductivity to minimise any voltage dropin the track.

d) Thermal management will become a majorconsideration.

Given the above considerations, at a recent

interconnection seminar held in conjunction with BPAand Exacta, the following optimum substratespecification shown in Table I was evolved.

Design/modification turnroundThermal dissipationInterconnection densityAssembly yieldSubstrate accessComponent attachment

Substrate testReliabilityEnvironmental performance

Substrate sizeElectrical characteristics

Assembly and testCost

TABLEOptimum substrate specification.

7 days2 watts in -2 (645 mm2)0.25 mm grid90% using electrically pretested components and substratesSpace for hard wired modification during developmentBy solder. Joints to withstand 5 changes. Offer surface mounting as well as

through hole mounting capabilityAccess to 0.25 mm grid10-9 failures/joint/hour-50C to + 125C. Withstand 40 g shock. Withstand 2 g vibration in range 5

to 500 HzDetermined by optimum replacement unit or functional building blockControlled impedance for interconnection lengths greater than 2 inches.Ground plane screening

AutomaticProvide reduction of overall system cost

ELECTRONIC INTERCONNECTIONS PRINTED WIRING BOARDS 141

Can PCB manufacturing develop to meet thedemands given in Table I? In fact many of the largermanufacturers who carry their own R & D teams andwho operate at the higher technology end of the marketcan already fulfill most of this specification.

5. A PCB SUBSTRATE SOLUTION

Generally, a fine line, controlled dielectric, copperconductor substrate can meet the specification of Table

I, and an extensive range of interconnection possi-bilities can be available at typically printed wiring boardcosts. There is a broad relationship between overallsystem packing density and the probability of electricalsuccess. Some existing varieties of PCB systems areshown in Figure 2(a)-(h). The relationship betweenthese existing PCB systems and achievable packingdensities against broad PCB costs is shown in Figure 3and a curve showing the probability of electricalmalfunction vs Packing density has been superimposedon the diagram.

Conductor

0 ietecfric

Pcfed thru’ hole

(a) Double sided plated thru- hole printed circuit board.

Hectf Sink

(b) Thin laminate (0.008") with surface mounted heat sink.

Bonding insulQfion

(c) Double double sided plated thru’ hole printed circuit board.

FIGURE 2 (Continued overleaJ)

142 I.G. LANG

/ .’.--X/ //......(d) Multilayer printed circuit board. (Intermediate layers not shown).

(e) Multilayer printed circuit board with internal heat sink.

(f) Multilayer printed circuit board with surface mounted heat sink.

(g) Buried via hole multilayer printed circuit board.

(h) Double multilayer printed circuit board.

FIGURE 2 Varieties of PCB systems (The dimensions can be appreciated by realising that the closest centre tocentre distance between the holes in the dielectric is 0.1 inch).

ELECTRONIC INTERCONNECTIONS- PRINTED WIRING BOARDS 143

pmtl_ilityett,c:Cicotmalfunction

costs

packing densi fyFIGURE 3 Costs vs Packing density for various PCB techniques. (Probability of electrical malfunction vs Packingdensity super-imposed).

Included in Figure 3 is reference to the substrateknown as a CHIPSTRATEt which is the furtherance ofmethods of placing conductors and a large variety ofinsulators in similar three dimensional orientations tothose shown in Figure 2 to provide a finished substratewhich is suitable for the surface mounting of lead-lesscomponents.The higher technology end of the packaging

spectrum will be covered by fine line pillar plated,sequentially produced multilayer boards using as low apermittivity material as possible. Such a system isshown in Figure 4.

6. PCB DIELECTRICS

From a study of properties, processability and costs alist of the most promising resins and reinforcement canbe made. This is shown in Table II.

Further work in this area will doubtless produceimproved polymers and reinforcements.For fine line, thin boards the characteristics required

are:

a) as low a dielectric constant as possible.

b) as high a continuous service temperature aspossible.

Component Ptctcemenf Pads.

FIGURE 4 Pillar plated printed circuit board (distance between component placement pads > 0.020 inch).

tCHIPSTRATE a trade mark of Exacta Circuits, Ltd

144 I.G. LANG

TABLE IIProperties of useful PCB dielectrics.

Temp. limitMaterial Dielectric constant (C)

Coeff of expansion in x-y plane(ppm/C)

ResinEpoxy 3.5 150Polyimide 5.4 260PTFE 2.1Acrylonitrite butadiene 5.3Polysulphone 3.0 150

60-9040-70130-190120-20054

Resin glassEpoxy 4.6 160 10-15Polyimide 4.6 260 9-13PTFE 2.4-2.6 260 10-15Triazine 4.5 260 9-14

Resin/Kevlar reinforcementPolyimide 4.7 260 0-10

c) a coefficient of expansion as near as possible toceramic (8ppm/C) for leadless chip carrier attachment.

Whilst not critical for leaded components thecoefficient of expansion characteristic should be met asclosely as practical to provide maximum in-servicereliability through thermal cycling. In practice thereliability achieved with epoxy glass when coupled withmodern electroplating practices is satisfactory.

7. CURRENT PCB INDUSTRY EXPERIENCE

The industry has current high volume processingexperience with epoxy, polyimide, PTFE andacrylonitrile butadiene and it is significant that it is onlyin the wet chemical processing area where slightvariations occur, whereas mechanical,photolithographic and handling processes are commonregardless of substrate material.

Generally with current products, mixtures ofpolymers are encountered within one subsrate, e.g.with a flexirigid multilayer board there can be foundpolyimide, acrylic adhesive, modified epoxy adhesiveand epoxy, or with a high frequency microwavemultilayer circuit board there can be PTFE, FEP,modified epoxy and epoxy. These polymer mixtureswitin one substrate have provided the impetus toestablish processing methods which can accommodate arange of dielectric materials.The PCB industry already has available a wide range

of processing methods such as photolithography;plasma etching systems; electroless deposition;

precision mechanical feature generation andelectroplating. There are also capabilities innumerically controlled lasers to provide features suchas edges, and through blind holes in non-reinforceddielectrics. Also wet polymer application and curingmethods are used so that all the necessary ingredientscan be available for the economic production of fineline, controlled dielectric, polymer substrates.

7.1 DESIGN/MODIFICATION TURNROUND

Using currently available computer aided design andmanufacturing techniques it is quite possible totransmit a design change digitally along with other keydata to the manufacturer who then uses the datadirectly in key processes such as: Photoplotting, NCdrilling, profiling and laser scribing and automaticelectrical test; i.e. those areas in substrate manufacturewhich are unique to the type and which traditionallytake most of the time in the manufacturing cycle.

8. PCB INTERCONNECTION DENSITY

One of the important requirements given in thespecification of Table 1 was that of PCBInterconnection Density. Currently a 0.50 mm grid iscommon with an increasing use of a 0.35 mm grid.Many larger manufacturers produce high volumes ofwork on a 0.25 mm grid, i.e. 4 tracks between aconventional 0.254 mm grid encompassing thestandard DIP. This demands a satisfactory

ELECTRONIC INTERCONNECTIONS- PRINTED WIRING BOARDS 145

photoprinting process with adequate resolution and ahigh standard of maintained cleanliness, i.e. managerialand process controls coupled with the operationaltechniques required to provide the high yield. Thephotoprinting processes used already typically takesplace in a class 100 clean room with controlledtemperature/humidity, and the refinement ofoperational/management/process controls in such areaswill be required in order to maintain the existing highyields as line widths become smaller. Current dry resistsare used to provide a 0.2 mm grid whereas wet resistsare certainly capable of much finer work.

9. PCB CONDUCTOR/FINISHES

published work indicating that leadless chip carriers canbe attached to epoxy glass, polyimide or triazine PCB’sand that this approach is adequate for benign tomoderately severe environments and that the reliabilityof such a system is at least equal to that of conventionalPCB packaging. Much more published work is requiredhere to increase the acceptance of such a system andthere are many in the industry who are evaluating therelative performances. It is probable that the currentlyused resin systems will prove to be satisfactory butwork will continue on types such as Kevlar reinforcedpolymers following the published work of StewartGreer of IBM defining which low expansivity organicsubstrates can be fabricated and used.

Currently copper, tin, nickel, gold, tin/lead are ingeneral use, deposited by ele6troplating, electroless orvacuum techniques. These have the appropriatesatisfactory properties of high conductivity, highthermal distribution and easy component attachment.

10. COMPONENT ATTACHMENT

As stated earlier, the coefficient of expanasion of thesubstrate should be in the range 5-10 ppm to match thepossible use of ceramic leadless chip carriers. (This isnot an important consideration with plastic orcompliant leaded chip carriers and TAB, where thebare but hermetically passivated chip is used directly orwhen leadless chip carriers are used withsockets.) There are mixed feeling concerning theattachment of leadless chip carriers to PCB’s with themore conservative companies pointing to the thermalmismatch as a potential problem. However, others haveappreciated the potential yielding plasticity of thesubstrate dielectric and of the solder joint. As anexample, Martin Marietta and the USAF 2 have

11. CONCLUSIONS

An optimised packaging solution for many systemapplications using modern components such as LSI andVLSI chips, will remain with printed circuit boards.PCBs have already been modified to provide finerlines, reduced dielectric, reduced dielectric constantsand increased interconnection chemistry, and can bemanufactured using existing technology. The longestablished technology of pillar plating will increase inimportance. Perhaps in future the PCB initials maystand for Polymeric Chipstrate Build.

REFERENCES

1. C. L. Lassen, "Wanted: A New InterconnectionTechnology"-Electronics, 27 September, 1979.

2. R. E. Settle, "New Family of Microelectronics Packagesfor Avionics"-Solid State Technology, June 1978.

3. S. E. Greer, "Low Expansivity Organic Substrate forFlip-Chip Bonding"-IEEE Trans. Components, Hybridsand Manufacturing Technology. CHMT 2. pp 140-144,1979.

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PERMANENT INTERCONNECTION ELECTRONIC …downloads.hindawi.com/journals/apec/1981/245087.pdf · 140 I.G. LANG Curnutfive 100-Other20. 0 1978 1 BC 1980)85 )90 YEARS Key:-DlP. Du[In-Line