Performance Analysis Of Mux Based

Convolutional Encoder

P.Mano1*

M.Krishnamurthy2

Depatment of Electronics and Communications Engineering

Depatment of Electronics and Communications Engineering

PSNA College of Engineering and Technology PSNA College of Engineering and Technology

Dindigul,India Dindigul,India

Abstract---Digital communication is used to transform the information between senders to receiver. Various errors can affect the transmitted signals hence it is mandatory by using error control coding techniques. Then the errors can control by using convolutional technique. Covolutional code can do both error detection and correction. The main operation in convolutional encoder is XOR operation, which consume high power. The main objective of this work is to reduce the encoder architecture complexity, power consumption and time level, by remove the XOR operation. Thereby apply the MUX based Encoder technique. This encoder consists of MUX and registers which reduces the circuit complexity and critical path section. Finally to get the encoder output data bits using MUX based architecture Keywords---Automatic Repeat Request (ARQ), Forward Error Correction (FEC), Convolutional Code (CC)

I. INTRODUCTION

In a communication system, error detection and correction mechanisms are vital and numerous techniques exist for reducing the consequence of bit-errors and trying to make sure that the receiver eventually gets an error free version of the packet. In error detect and retransmission method, the receivers detect the error and request the transmitter for retransmission. In this method the receiver can detect the error only. This method applicable for point to point communication links. In error detection and correction, the receiver can used detect the error and also to rectify the error, it also known as the forward acting error correction. Since it consist of more ARQ for the overall operation. Error correction code (ECC) can do both error detection and correction. In block codes technique, each block contains blocks of ‘k ‘information bits is encoded into a block of n bits (n>k) [14]. It is a one-to-one correspondence between the information and codeword .It takes large time for small high rate applications. In convolution code, the encoder accepts a k-bits message comes from in serially rather than in large blocks. The encoder operates on the incoming message sequence continuously in serial manner [9]. The buffer is not needed. The code words generated are non-systematic codes. In convolutional encoder mainly depends on XOR operation [15]. It consumes more dynamic power through entire

operation [7] & [8] and then using of common subexpressions element (CSE) [13] & [10]. The convolutional codes are defined by three parameters which are as follow: (a) Rate: Ratio of the number of input bits to the number of production bits. In this example, rate is 1/2 which means there are two production bits for each input bit. (b) Constraint length: The number of stoppage elements in the convolution coding for example with k = 3, there are two delaying elements. (c) Generator polynomial: Wiring of the input sequence with the stoppage elements to form the output. For example, generator polynomial is [7, 5]8 = [111,101]2

II. DESIGN AND IMPLEMENTATION

The implementation of MUX based convolutional architecture is depends on the following few step of process.

Figure1.Block diagram of convolution

encoder architecture

The above block diagram figure1 explained about

MUX based convolutional encoder. First block of the architecture is based on the information bit. It combined with the possible combinations of the input data. Based on the

different parameter like code rate, constraint length and generator polynomial, the given input can be encoded. After that process the encoded output will be grouping, then it split into two part row tag (RT) and column tag (CT). The decomposed outputs, the ROM is prepared by merging the common rows and assigning new reduced RT with same CT. The process of convolution encoder is explained in detailed below. Here the algorithm can be tested at a code rate (r= 1/3) with the generator polynomials g0(x) = (557), g1(x) = (663) and g2(x) = (711) and constraint length K=9. The conventional convolutional encoder for CDMA-2000 shown in a figure

Figure 2. conventional convolutional encoder.

The MSB bits of the input are given in to selection line of 32:1 MUX. Based on the selection bit it will produce the output. From the decomposition process, to form a new row tag and column tag bit and then to restoring bits into a certain memory location.

TABLE 1.CONVOLVED OUTPUT a.

Assignment and encoding;

By assuming information bit as logic‘0’, for all possible combination of the input state. Then, it will be encoded similar to the basic convolution process. The number of output bits depends on the code rate value. (i.e) r= l/n.

b. Grouping;

The similar encoded output bits are grouping together to form a new table2.

c. Decomposition;

Here the possible combination of encoded states are split into two subparts RT and CT. RT= [K-{(1/k) + 1}] Bits CT= (1/k) Bits.

Based on the above two equations, the row tag and column tag are framed. The uniformity output of row tag with respect to column tag is known as Isomorph states. TABLE 2.REARRANGE OF CONVOLUTION OUTPUT

TABLE 3.ISOMORPH STATES FOR RT

d. Restoring; Get Mealy back from Moore mechanism i.e. again consider the logic ‗1‘ while applying uniformity bit check concept of XOR, the system get back its full-performance

TABLE 4: NEW RT ASSIGNMENT BASED ON ISOMORPHS

Figure 3.Reduced ROM XOR-Free Architecture for CDMA-2000

Then the algorithm can further tested at same

parameter like code rate, constraint length and generator polynomial. Here the 4:1 MUX can be replaced by 8:1 multiplexer. The MUX based convolutional encoder architecture shown in a figure4.The concordinate operation can be performed between 32:1 MUX output data and given 8-bit input data. That operation can be used to form eight input value. The output of 8:1MUX is 3 bit since, code rate r= (1/3). Then the encoder output will be stored in the ROM, based on the new RT and CT. finally to get a encoder output.

III. RESULT

The MUX based convolutional encoder architecture is implemented on Xilinx using VHDL code. This architecture encoded at a code rate r=1/3 and constraint length K=9

Figure 4:MUX based Convolutional Encoder for

CDMA-2000. TABLE 5.COMPARISON

.

The comparison of various parameters like number of IOB’s, LUT’s and frequencies shown in table 5. The Xilinx XPower analyzer tool used to find the dynamic power consumption of the MUX based convolutional encoder architecture at a clocking rate of 1000ns. The overall parameter comparison graph and power consumption showed in figure 5 & 6.

Figure 5.MUX based convolutional encoder comparison

Figure 6.power calculation

IV. CONCLUSION

From the above discussion it is concluded, there are

different types of operation can be used for error correction and detection. Then the way of approach the convolutional code operation also various from one to another. Here we discuses about the convolutional code, XOR based circuit operation even though they have few drawbacks. A new MUX based encoder is identified to improve the overall performance which includes less circuit complexity, low power consumption through process. This MUX based convolutional encoder architecture can be discussed in my future.

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