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K. J. Somaiya College of Engineering, Mumbai-77

Batch No._____ Roll No. ____

Experiment / Assignment/ Tutorial No. 1

Grade : AA/BB/BC/CC/CD/DD

Signature of the Staff In-charge with date

Title: DIAC CHARACTERISTICS.

___________________________________________________________________

___ Aim and Objectives of the Experiment..

1) To study V/I characteristics of DIAC DB3 and find its resistance in 3operating regions.

2) To identify negative resistance region in the characteristic. ___________________________________________________________________ CEOs to be achieved: CEO 1:To learn the basic concepts of Power Electronics devices

Theory: (Attach theory in a separate sheet). Mention cross-sectional view,

operating principle, circuit symbol. Attach data sheet of DB3 DIAC

1

Department of Electronics Engineering

Power Electronics VI Sem./Jan - Apr 14

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Stepwise-Procedure: 1. Connect the circuit as shown in figure.2. Initially set current measuring multimeter in scale of microampere.

3. Apply variable supply voltage from 0 V to 60 V. in steps of 5V andmeasure voltage across DIAC (VDIAC) and current flowing through it

(IDIAC).

4. Once the current increases sufficiently it will be indicated on the ammeter asout of range, change the scale to milliampere range .

5. Increase supply voltage in small steps near curve to get accurate reading and

continue measuring VDIAC and IDIAC.

6. Now reversing the polarities of the supply, repeat the steps from 2 to 5

7. Plot IDIAC versus VDIAC and note down forward and reverse turn onvoltage of DIAC. Also note the voltage when device comes out fromnegative resistance region.

Circuit Diagram:

2



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Observation Table: At least 20 readings

Forward characteristics Reverse characteristics

Vsupply (V) VDIAC IDIAC Vsupply (V) VDIAC (V) IDIAC

Graphs: (Draw and attach relevant graph )

3 Department of Electronics Engineering


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Calculation:- 1) Resistance in non-conducting region:-

2) Resistance in – ve resistance region:-

3) Resistance in conducting region:

Results:

1. VBOF =

2. VBOR =

3. IBO =

4. IF =5. V =

Post Lab Questions

1. What do you mean by breakover voltage symmetry and dynamic breakover

voltage ? Specify its value from experiment and datasheet.

2. How the term DIAC is obtained?

3. What is the significance of – ve resistance region?

Conclusion--

4Department of Electronics Engineering


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Title: R & R-C Gate triggering circuits for Thyristor

___________________________________________________________

___________ Aim and Objectives of the Experiment.. — 1) To find out R and corresponding triggering angle ‘α’ in both

circuits

2) Comparison of both methods. ___________________________________________________________

___________ CEOs to be achieved:

CEO 4 To study Turn ON and OFF Circuits of SCR and use themin applications of Thyristors.

Theory: (Attach theory in a separate sheet). Mention circuit

operation of R and R_C triggering with waveforms. ___________________________________________________________

___________ Stepwise-Procedure for R and RC Triggering

1) Connect the circuit as shown in the diagram for R triggering2) Connect the oscilloscope plug pin to unearthed socket provided

in the kit .3) Switch 230V ac supply and keep POT at its extreme position4) Observe and measure peak supply voltage and load voltage

waveform and calculate α.

5) Repeat the above step for various positions of the POT

6) Disconnect the supply and the connections and measure theresistance for the same positions of the POT.

7) Connect the circuit as shown in the diagram for RC triggering8) Repeat the steps from 2 to 6

5

Department of Electronics Engineering Power Electronics VI Sem./Jan – Apr 14

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Circuit Diagram: RC Triggering

Observation Table :

R triggering circuit:-

R in

K Ω

t

in msec

T

in msec

Triggering

Angle α.In degrees

Vm

volts

Vdc

volts

Triggering

Angle α.In degrees

6

Department of Electronics Engineering Power Electronics VI Sem./Jan – April 14

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R_C triggering circuit:-

R in

K Ω

t

in msec

T

in msec

Triggering

Angle α.

In degrees

Vm

volts

Vdc

volts

Triggering

Angle α.

In degrees



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sdr






Title: Study of Semi converter

Aim and Objectives of the Experiment..-- 1) To study the full wave half controlled rectifier(Semiconverter) with R and RL

load.

2) To study the effect of free-wheeling diode on the same.

______________________________________________________________________

CEOs to be achieved:

CEO 4 To study Turn ON and OFF Circuits of SCR and use them inapplications of Thyristors.

Theory: (Attach theory in a separate sheet). Mention types of converters and

circuit operation of full wave half controlled rectifier(Semiconverter) with R and

R-L load. _____________________________________________________________________

Stepwise-Procedure: 1) Connect the circuit as shown in the diagram with load resistance R = 500Ω. 2) Connect the oscilloscope plug pin to unearthed socket provided in the kit.3) Switch on 230V ac supply and adjust ‘α’ to minimum value by controlling

resistance in UJT triggering circuit. 32 V. peak voltage will be available at theinput of bridge.

4) Observe and draw the load voltage waveform and measure average loadvoltage.

5) Change the ‘α’ and repeat step 4.

6) Now connect load resistance 500 Ω in series with L1, L1+L2 and

L1+L2+L3 and repeat steps 3,4,5 with and without free-wheeling diodein the circuit.7) Measure accurate voltage from 0 to ‘α’ with and without free-wheeling

diode.

9



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Circuit Diagram:

Date: _____________ Signature of faculty in-charge



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K. J. Somaiya College of Engineering, Mumbai

Observation Table :

R Load :-

Vm = ________Volts.

tin msec

Tin

msec

Triggering

Angle α.

In degrees

Load VoltageMeasured.

volts

Load VoltageCalculated

volts

R+L1 Load:-

Vm = ________Volts.

t

in msec

T

in msec

Triggering

Angle α.

In degrees

Load Voltage

Without FWD

volts

Load Voltage

With FWD

volts

R+L1 +L2 Load:-

Vm = ________Volts.

tin msec Tin msec TriggeringAngle α.

In degrees

Load VoltageWithout FWD

volts

Load VoltageWith FWD

volts

R+L1+L2+L3 Load:-

Vm = ________Volts.

tin msec

Tin msec

Triggering

Angle α.

In degrees

Load VoltageWithout FWD

volts

Load VoltageWith FWD

volts

11



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Voltage from 0 to ‘α’ for R+L1+L2+L3 Load with and without free-

wheeling diode for minimum ‘α’ set.

Draw waveforms for all types of loads for any one value of ‘α’ .

Calculation :

Average load voltage calculation theoretical:- Vdc = Vm ( 1+cos α )/ π




Load Voltage from 0 to ‘α’

Without FWDvolts

Load Voltage from 0 to ‘α’ With

FWDvolts

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Post Lab Questions

1. What is the effect of the load inductance on the average load voltage? Why?

2. Prove that semiconverter has buit-in free wheeling diode effect for R-L load. 3. What will happen to Vdc if FWD is connected for R-L load.

Conclusion---


13



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Title: Study of Full converter and comparison with Semi Converter.

______________________________________________________________________ Aim and Objectives of the Experiment..-- 1) To study the full wave fully controlled rectifier with R and RL load

2) To study the effect of free-wheeling diode with R-L load.

3) Comparison with semi converter

______________________________________________________________________

CEOs to be achieved:

CEO 4 To study Turn ON and OFF Circuits of SCR and use them inapplications of Thyristors.

Theory: : (Attach theory in a separate sheet). Mention circuit operation of fullwave full controlled rectifier(Fullconverter) with R and R-L load.

______________________________________________________________________ Stepwise-Procedure:

Connect the circuit as shown in the diagram with load resistance R = 500Ω. 1) Connect the oscilloscope plug pin to unearthed socket provided in the kit.2) Switch on 230V ac supply and adjust ‘α’ to minimum value by controlling

resistance in UJT triggering circuit. 32 V. peak voltage will be available at theinput of bridge.

3) Observe and draw the load voltage waveform and measure average loadvoltage.

4) Change the ‘α’ and repeat step 4.5) Now connect load resistance 500 Ω in series with L1, L1+L2 and

L1+L2+L3 and repeat steps 3,4,5 with and without free-wheeling diodein the circuit.

6) Measure accurate voltage from 0 to ‘α’ with free-wheeling diode.



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Circuit Diagram:


15



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Observation Table :

R Load :-

Vm = ________Volts.

t

in msec

T

in

msec

Triggering

Angle α.

In degrees

Load Voltage

Measured.

volts

Load Voltage

Calculated

volts

R+L1 Load:-

Vm = ________Volts.

t

in msec

T

in msec

Triggering

Angle α.

In degrees

Load Voltage

Without FWD

volts

Load Voltage

With FWD

volts

R+L1 +L2 Load:-Vm = ________Volts.

t

in msec

T

in msec

Triggering

Angle α.

In degrees

Load Voltage

Without FWD

volts

Load Voltage

With FWD

volts

R+L1+L2+L3 Load:-

Vm = ________Volts.t

in msec

T

in msec

Triggering

Angle α.

In degrees

Load Voltage

Without FWD

volts

Load Voltage

With FWD

volts

Date: _____________ Signature of faculty in-charg

16


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Voltage from 0 to ‘α’ for R+L1+L2+L3 Load with free-wheeling diode forminimum ‘α’ set.

Draw waveforms for all types of loads for any one value of ‘α’ .

Post Lab Questions

1. What is the effect of the load inductance on the average load voltage? Why?2. What is the effect of the free-wheeling diode with RL load?3. Compare the results with semi converter and comment on the same?

Conclusion---


17



Load Voltage from 0 to ‘α’

Without FWD

volts

Load Voltage from 0 to ‘α’ With

FWD

volts

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® DB3 DB4 SMDB3

DIAC

FEATURES

3) VBO : 32V and 40V

4) LOW BREAKOVER CURRENT

DESCRIPTION

Functioning as a trigger diode with a fixedvoltage reference, the DB3/DB4 series can beused in conjunction with triacs for simplified gate

control circuits or as a starting element influorenscent lamp ballasts.

A new surface mount version is now available inSOT-23 package, providing reduced space andcompatibility with automatic pick and placeequipment.

ABSOLUTE MAXIMUM RATINGS (limiting values)

DO-35 (DB3 and DB4)

2 3

1

SOT-23(SMDB3)*

Pin 1 and 3 must beshorted together

Symbol Parameter Value Unit

ITRM Repetitive peak on-state current SMDB3 1.00 A tp = 20 s F= 120 Hz

DB3 / DB4 2.00

Tstg Storage temperature range - 40 to + 125 C Tj Operating junction temperature range

Note: * SMDB3 indicated as Preliminary spec as product is still in development stage.

October 2001 - Ed: 2B 1/5

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DB3 DB4 SMDB3

ELECTRICAL CHARACTERISTICS (Tj = 25°C unless otherwise specified)

Symbol Parameter Test Conditions SMDB3 DB3 DB4 Unit

VBO Breakover voltage * C = 22nF ** MIN. 28 28 35 V

TYP. 32 32 40

MAX. 36 36 45

I VBO1 - VBO2 I Breakover voltage C = 22nF ** MAX. 3 V symmetry

V Dynamic breakover VBO and VF at 10mA MIN. 10 5 V voltage *

VO Output voltage * see diagram 2 MIN. 10 5 V (R=20)

IBO Breakover current * C = 22nF ** MAX. 10 50 A

tr Rise time * see diagram 3 MAX. 0.50 2 s

IR Leakage current * VR = 0.5 VBO max MAX. 1 10 A

IP Peak current * see diagram 2 (Gate) MIN. 1 0.30 A

8. Applicable to both forward and reverse directions.

6. Connected in parallel to the device.

PRODUCT SELECTOR

Part Number VBO Package

SMDB3 28 - 36 SOT-23

DB3 28 - 36 DO-35

DB4 35 - 45 DO-35

ORDERING INFORMATION

SM DB 3

Surface

MountVersion

Diac Series

Breakover voltage

4. VBO typ = 32V5. VBO typ = 40V

2/5

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DISCRETE SEMICONDUCTORS

DATA SHEET

C106D

Thyristors logic level

Product specification July 2001

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Philips Semiconductors Product specification

Thyristors logic level C106D

GENERAL DESCRIPTION QUICK REFERENCE DATA Passivated, sensitive gate thyristor in a SYMBOL PARAMETER MAX. UNIT plastic envelope, intended for use in general purpose switching and phase control

Repetitive peak off-state 400 V applications. This device is intended to be DRM interfaced directly to microcontrollers, logic RRM voltages integrated circuits and other low power gate T(AV) Average on-state current 2.5 A trigger circuits. T(RMS) RMS on-state current 4 A

TSM Non-repetitive peak on-state 38 A current

PINNING - SOT32 PIN CONFIGURATION SYMBOL

PIN DESCRIPTION

1 cathode a k

2 anode

3 gate

g Top view 2 3MBC077 - 1

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDRM, VRRM Repetitive peak off-state voltages

T(AV) Average on-state current T(RMS) RMS on-state current TSM Non-repetitive peak

on-state current

I2t I

2t for fusing

dIT /dt Repetitive rate of rise of on-state current after triggering

GM Peak gate current GM Peak gate voltage RGM

Peak reverse gate voltage GM Peak gate power G(AV) Average gate power

stg Storage temperature j Operating junction

temperature

- 4001 V

half sine wave; Tmb ≤ 113 ˚C - 2.5 A all conduction angles - 4 A half sine wave; T j = 25 ˚C prior to surge t = 10 ms - 35 A t = 8.3 ms - 38 A t = 10 ms - 6.1 A s ITM = 10 A; IG = 50 mA; - 50 A/ s dIG /dt = 50 mA/ s

- 2 A - 5 V

- 5 V - 5 W over any 20 ms period - 0.5 W

-40 150 ˚C - 125

2 ˚C

1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor

may switch to the on-state. The rate of rise of current should not exceed 15 A/ s. 2 Note: Operation above 110˚C may require the use of a gate to cathode resistor of 1kΩ or less.

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Thyristors logic level C106D

THERMAL RESISTANCES

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

th j-mb Thermal resistance - - 2.5 K/W junction to mounting base

th j-a Thermal resistance in free air - - 95 K/W junction to ambient

STATIC CHARACTERISTICS

25 ˚C unless otherwise stated T j =


GT A Gate trigger current VD = 12 V; IT = 0.1 A - 15 200

IL Latching current VD = 12 V; IGT = 0.1 A - 0.17 10 mA H Holding current VD = 12 V; IGT = 0.1 A - 0.10 6 mA T On-state voltage IT = 5 A - 1.23 1.8 V GT Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.4 1.5 V

VD = VDRM(max); IT = 0.1 A; T j = 110 ˚C 0.1 0.2 - V ID, IR Off-state leakage current D

=DRM(max)

R

=RRM(max)

j=

- 0.1 0.5 mA

DYNAMIC CHARACTERISTICS

T j = 25 ˚C unless otherwise stated

PARAMETER CONDITIONS MIN. TYP. MAX. UNIT SYMBOL

dVD /dt Critical rate of rise of VDM = 67% VDRM(max); T j = 125 ˚C;

gt o -s a e vo age exponential waveform; RGK = 100 Ω Gate controlled turn-on ITM = 10 A; VD = VDRM(max); IG = 5 mA;

time dIG /dt = 0.2 A/ s q Circuit commutated VD = 67% VDRM(max); T j = 125 ˚C; ITM = 8 A;

turn-off time VR = 10 V; dITM /dt = 10 A/ s; dVD /dt = 2 V/ s; RGK = 1 kΩ

- 50 - V/ s

- 2 - s

- 100 - s

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Title: Measurement of Latching & Holding current of SCR 106 D.

___________________________________________________________________ Aim and Objectives of the Experiment.. —

1) To measure Latching (IL) and Holding (IH) current of SCR 106 D. ______________________________________________________________________ CEOs to be achieved: CEO 1 To learn the basic concepts of Power Electronics devices

Theory: (Attach theory in a separate sheet). Mention cross-sectional view,

operating principle, circuit symbol of thyrister. Define Latching Current and

Holding Current of a Thyrister. Attach data sheet of Thyrister 106 D. ____________________________________________________________________

Stepwise-Procedure:A) Measurement of Latching Current 1. Connect the circuit as shown in the diagram and apply 30 V.2. Measure IAK and VAK .3. Put switch in the gate circuit S1 ON and measure IAK and VAK . If SCR is not triggered

then reduce the pre- set resistance in gate circuit such that SCR triggers. Don’t changethis resistance then. Adjust Rs to minimum value so to get maximum IAK.

4. Switch OFF S1 ( Gate drive removed) and check whether SCR remains in turn oncondition or not. If it remains ON then SCR is latched on now and measure IAK andVAK . IAK ≥ IL . If it remains OFF then IAK < IL .

5. Switch on S1 and increase or decrease resistance in A-K circuit Rs (based on theabove condition) such that IAK comes closer to IL

6. Switch off S1 and check the condition mentioned in step 4. Repeat step 5 till you getthe latching conditon.

B) Measurement of Holding Current 1. Reduce Rs to minimum value, apply 30 V. supply and switch on S1. Measure IAK

and VAK . IAK will be maximum.

2. Switch off S1 and increase Rs slowly and observe IAK . Measure that minimum

value of IAK at which device suddenly goes into blocking state. At this point weget the holding current.

1823Department of Electronics Engineering


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Circuit Diagram:

Observation Table:-

Latching Current

Va ue o Rs Sw tc Po t on(Gate Drive)

VAK IAK Comment

19



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Holding CurrentVa ue o Rs Sw tc Po t on

(Gate Drive)VAK IAK Comment



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Title: Light dimmer circuit

______________________________________________________________________

Aim and Objectives of the Experiment..-- 1) To study light dimmer circuit using Diac DB3 &Triac BT136 __________________________________________________________________ CEOs to be achieved: CEO 1:To learn the basic concepts of Power Electronics devices

CEO 2 :To get skill of developing and design related power electronic circuits

Theory: (Attach separate sheets for theory) ). Mention the principle of operation

of light dimmer. Attach data sheet of DIAC DB3 & TRIAC BT 136 ______________________________________________________________________ Stepwise-Procedure: 1. Connect the circuit as shown in figure.

2. Observe the waveform across load, capacitor and Triac for two triggeringangles which gives extreme brightness of the lamp load.

Circuit Diagram:



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Draw the above mentioned waveforms directly

fromCRO.

Calculation:

Use Breakover voltage of Diac as in experiment No.1 and calculate ‘α’

Voltage across the capacitor connected to Diac Vc(t) = Vsupply * Xc/|Z|

Vsupply = Vmsintωt

Post Lab Questions

1. Which mode of operation of Triac is used in the above application?Why?

Conclusion:




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Title: To study the working of SCR Driver circuit

______________________________________________________________________ Aim and Objectives of the Experiment..-- 1) To study Ramp and Pedestal Driver circuit2) To plot graph of triggering angle ‘α’ v/s Vc

______________________________________________________________________ CEOs to be achieved: CEO 2 To get skill of developing and design related power electronic circuits

CEO 4 To study Turn ON and OFF Circuits of SCR and use them in applications ofThyristors.

Theory: (Attach separate sheets for theory) Mention working of Ramp and pedestal

driver circuit

______________________________________________________________________ Stepwise-Procedure:

a. Connect the circuit as shown in the diagramb. Connect channel 1 of CRO to the secondary voltage of transformer to havec. reference voltage waveform on CRO. Switch on supply to control circuitd. Keep Vc=0V and adjust the ‘α’ to 180 degrees by varying the POT

e. Observe waveform at various test points in the circuit by giving them tochannel 2 of CRO.

f. Now connect channel 2 to output of any one pulse transformer toobserve firing pulses on CRO.

g. Note down firing angles at different control voltage Vc and plot ‘α’ v/s VcCircuit Diagram: (Attach circuit diagram in a separate sheet)



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Observation Table

Vc ‘α’

Volts degrees

Draw waveforms at each test point directly from CRO

Graphs (Attach graph ‘α’ v/s Vc)

Post Lab Questions

1. Comment advantages and disadvantages of this control circuit

2. What is the need driver circuit and how the above circuit satisfies the same?

Conclusion---




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Title: Forced commutation circuits of SCR (106 D)

______________________________________________________________________ Aim and Objectives of the Experiment..-- 1) To study Class B commutation by an LC circuit

2) To study Class C commutation by triggering charged capacitor withauxiliary SCR

______________________________________________________________________ CEOs to be achieved: CEO 4 To study Turn ON and OFF Circuits of SCR and use them inapplications of Thyristors.

Theory: (Attach separate sheets for theory) Mention working of class B and class

C method of commutation ______________________________________________________________________

Stepwise-Procedure: Class B

1. Connect the circuit as shown and put on the supply2. Measure capacitor voltage

3. Trigger SCR and observe whether SCR turns off or not

4. Progressively change the value of capacitor and inductor and observe thecommutating effect

5. Find the condition for successful commutation

Class C 1. Connect the circuit as shown and put on the supply

2. Measure capacitor voltage and load current3. Trigger auxiliary SCR and observe whether main SCR turns off or not

4. Progressively change the value of capacitor and observe the commutatingeffect

5. Find the condition for successful commutation6. Calculate circuit turn off time for the given circuit



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Circuit Diagram: Class B

Circuit Diagram: Class C

26



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Calculation

Post Lab Questions

Explain the reason for commutation failure in Class B and Class C circuits

Conclusio




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Triacs BT136 series

GENERAL DESCRIPTION QUICK REFERENCE DATA Passivated triacs in a plastic envelope, SYMBOL PARAMETER MAX. UNIT intended for use in applications requiring

BT136- 600 high bidirectional transient and blocking voltage capability and high thermal cycling BT136- 600F performance. Typical applications include motor control, industrial and domestic DRM Repetitive peak off-state 600 V lighting, heating and static switching. voltages

T(RMS) RMS on-state current 4 A TSM on-repet t ve pea on-state

current

PINNING - TO220AB PIN CONFIGURATION SYMBOL

PIN DESCRIPTION 1) main terminal

1

2) main terminal 2

3) gate

tab main terminal 2

tab

T2 T1

1 2 3 G

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V Repetitive peak off-state - 6001 V

DRM voltages

T(RMS) RMS on- state current full sine wave; Tmb ≤ 107 ˚C - 4 A TSM on- repet t ve pea full sine wave; T = 25 ˚C prior to

on-state current surge t = 20 ms - 25 A t = 16.7 ms - 27 A

I t I t for fusing t = 10 ms - 3.1 A s dIT /dt Repetitive rate of rise of ITM = 6 A; IG = 0.2 A;

on-state current after dIG /dt = 0.2 A/ s A/ triggering T2+ G+ - 50 s

T2+ G- - 50 A/ s T2- G- - 50 A/ s

T2- G+ - 10 A/ s GM Peak gate current - 2 A GM Peak gate voltage - 5 V GM Peak gate power - 5 W G(AV) Average gate power over any 20 ms period - 0.5 W

stg torage temperature - T j Operating junction - 125 ˚C

temperature

1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the triacmay switch to the on-state. The rate of rise of current should not exceed 3 A/ s.

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June 2001 1 Rev 1.400

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Triacs BT136 series

THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

th j-mb Thermal resistance full cycle - - 3.0 K/W junction to mounting base half cycle - - 3.7 K/W

th j-a Thermal resistance in free air - 60 - K/W junction to ambient

STATIC CHARACTERISTICS



BT136- ... ...F GT Gate trigger current VD = 12 V; IT = 0.1 A

T2+ G+

-

5

35

25

mA T2+ G- - 8 35 25 mA

T2- G- - 11 35 25 mA T2- G+ - 30 70 70 mA

IL Latching current VD = 12 V; IGT = 0.1 A T2+ G+ - 7 20 20 mA T2+ G- - 16 30 30 mA T2- G- - 5 20 20 mA T2- G+ - 7 30 30 mA

H Holding current VD = 12 V; IGT = 0.1 A - 5 15 15 mA VT On-state voltage IT = 5 A - 1.4 1.70 V

GT Gate trigger voltage VD = 12 V; IT = 0.1 A - 0.7 1.5 V VD = 400 V; IT = 0.1 A; 0.25 0.4 - V T j = 125 ˚C

D Off-state leakage current D=

DRM(max) - 0.1 0.5 mA

T = 125 ˚C

DYNAMIC CHARACTERISTICS


SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT BT136- ... ...F

V/ s dVD /dt Critical rate of rise of DM

=DRM(max) 100 50 250 -

o -state vo tage T = 125 ˚C; exponential waveform; gate open circuit

V/ s dVcom /dt Critical rate of change of VDM = 400 V; T = 95 ˚C; - - 50 - commutat ng vo tage T(RMS)

dIcom /dt = 1.8 A/ms; gate

open c rcu t s gt Gate controlled turn-on TM

=D

=DRM(max) - - 2 -

time IG = 0.1 A; dIG /dt = 5 A/ s

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June 2001 2 Rev 1.400

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Triacs BT136 series

Ptot / W Tmb(max) / C 8 101

7 104

6 1 = 180 107

120 5

90 110

4 60 113

3 30

116

2 119

1 122

0 125 0 1 2 3 4 5

IT(RMS) / A Fig.1. Maximum on-state dissipation, P tot , versus rms

on-state current, I T(RMS), where α = conduction angle.

1000 ITSM / A

IT ITSM

T time

Tj initial = 25 C max

100 dIT /dt limit

T2- G+ quadrant

10 1 us 1 us 1ms 1 ms 1 ms

T / s

Fig.2. Maximum permissible non-repetitive peakon-state current I TSM , versus pulse width t p, for

sinusoidal currents, t p ≤ 20ms.

30 ITSM / A

25 IT

ITSM

T time 20 Tj initial = 25 C max

15

10

5

0 1 10 100 1000 Number of cycles at 50Hz

Fig.3. Maximum permissible non-repetitive peakon-state current I TSM , versus number of cycles,

for sinusoidal currents, f = 50 Hz.

IT(RMS) / A 5

4 107 C

3

2

1

0 -50 0 50 100 150

Tmb / C Fig.4. Maximum permissible rms current I T(RMS) ,

versus mounting base temperature T mb.

12 IT(RMS) / A

10

8

6

4

2

0 0.01 0.1 1 10

surge duration / s

Fig.5. Maximum permissible repetitive rms on-state current I T(RMS), versus surge duration, for sinusoidal

currents, f = 50 Hz; T mb ≤ 107˚C.

VGT(Tj) 1.6 VGT(25 C)

1.4

1.2

1

0.8

0.6

0.4 -50 0 50 100 150

Tj / C Fig.6. Normalised gate trigger voltage V GT (T j )/

V GT (25˚C), versus junction temperature T j .

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