1. 2011 ANSYS, Inc. March 30, 20151 Pre-layout PCIe Channel
optimization for enabling PCI Gen4 with baseline Gen3 CEM connector
on a client topology in HFSS v16 Fisayo Adepetun SI/PI Application
Engineer
2. 2011 ANSYS, Inc. March 30, 20152 As data rates increase on
high-speed differential buses, efforts must be made to guarantee
that crosstalk and impedance discontinuities are minimized to keep
channels from being dominated by undesirable SI effects . One
source of impedance mismatch on a high-speed channel is the PCB via
which allows traces to transverse from one layer to the next. These
can be simulated in a channel in HFSS and tuned for best
performance to achieve a desired channel solution space.
Introduction
3. 2011 ANSYS, Inc. March 30, 20153 Why HFSS? HFSS R16 offers a
unified desktop consisting of HFSS 3D, HFSS 3D Layout, Linear
Circuit Simulator & SI Option. Offers the convenience of making
individual models and doing a full channel analysis in one user
interface*.
4. 2011 ANSYS, Inc. March 30, 20154 Niquist Frequency: Is
defined as half the sampling rate of a discrete signal processing
system. e.g. for a signal with a data rate of 5Gbps; the niquist
frequency is 2.5GHz. PCIe CEM Spec: PCIe Card Electromechanical
Specification FFE: Feed forward Equalizer CTLE: Continuous time
linear equalizer PRBS: Pseudo random bit sequence FEXT: Far end
crosstalk ISI: Inter-symbol Interference Terms
5. 2011 ANSYS, Inc. March 30, 20155 Case Study: PCIe Client
Channel Design Tx RxPkg Skt Via Routing Via Conn Add-in Card + Pkg
Rx TxPkg Skt Via Routing Via Conn Add-in Card + Pkg Channel
performance at 8GHz is impacted by a number of features in the
channel. Via transitions and Routing will be optimized in HFSS to
enable the gen 4 data rate at 14. Focus of this presentation will
be on optimizing the Tx path only.
6. 2011 ANSYS, Inc. March 30, 20156 Topology: 1 connector 14
Channel (10 on Base board, 4 on Plugin Card) Models: Assumptions:
Crosstalk treatment is A-V-A; tand=0.015 used on pcb as recommended
by PCI SIG Simulation Assumptions Comments Solver HFSS 3D Q3D Via
PCIe Connector, board and Socket x Connector Standard PCIe CEM
connector x Microstrip Routing x Stripline Routing Asymmetric
Stripline (4h15) x Tx Rx EQ: Adaptive 3 tap FFE EQ: First order
CTLE, 1 tap DFE DR: 8GBps & 16GBps UI: 125ps/62.5ps Vswing:
800mVpp Pattern: PRBS 18 (seeds 0,1,2 on pair 1,2,3)
7. 2011 ANSYS, Inc. March 30, 20157 HFSS Channel Schematic
Solved 3D vertical and 2D models inserted directly into the
schematic TX RX
8. 2011 ANSYS, Inc. March 30, 20158 PCIe Client Channel
Topology Original design Stripline routing on Layer 3 Introduces 3
stubs. - Target length works great at PCIe gen 3 (8Gbps) but can be
a show stopper at gen 4 (16Gbps) 9.5 0.5 4 Baseboard Plugin
Card
9. 2011 ANSYS, Inc. March 30, 20159 PCIe Client Channel
Topology Improved design Microstrip routing on Bottom Layer No
stubs 9 1 4 Trade-offs: More FEXT for less ISI. Baseboard Plugin
Card
10. 2011 ANSYS, Inc. March 30, 201510 Frequency Domain Analysis
Shows large divergence in loss at 8GHz between the original (red)
and redesigned channel (green). Crosstalk is also more with after
re-design with Microstrip on bottom(green). 3 60mil stub vias are
clearly a problem at 8GHz
11. 2011 ANSYS, Inc. March 30, 201511 Time Domain Analysis
Shows closed eye at reference receiver on the Stripline topology.
EYE open on re-designed Microstrip topology. EYE at reference
receiver on Stripline topology EYE at reference receiver on
improved Microstrip topology EH: 62mV
12. 2011 ANSYS, Inc. March 30, 201512 A closer look at the
Stripline topology design Stripline routing on same layer but
placing cap and connector break in on bottom eliminates 2 stubs 9.5
0.5 4 10dB better loss at 8GHz ~9dB more xtalk at 8GHz but overall,
its still acceptable EH: 13mV
13. 2011 ANSYS, Inc. March 30, 201513 A closer look at the
Stripline topology design (contd.) Stripline routing on same layer
but placing cap and connector break in on bottom eliminates 2 stubs
7.5- 9.5 0.5 4 ~2.2dB better loss at 8GHz with 2 reduction EH: 13mV
EH: 28mV 14 12
14. 2011 ANSYS, Inc. March 30, 201514 Simply put, the via poses
a serious impedance discontinuity. There are 2 important via
features: Thru part Stub part To minimize ISI due to reflections in
the channel, the Stubs should be mitigated. Stubs will continue to
be of serious concern as data rates increase. Why are vias the
problem? Stub resonance should be far from the Nyquist frequency
Push via resonance as high a frequency as possible.
15. 2011 ANSYS, Inc. March 30, 201515 Why are vias the problem?
60mil Stub 10mil Stub 0mil Stub The longer the stub the larger the
discontinuity. The via with 60mil stub drops as low as ~53ohms in
an ~85 ohm channel
16. 2011 ANSYS, Inc. March 30, 201516 For best performance,
vias should be designed to be as transparent as possible. Some
practical design guidelines to make vias: Minimize length of via
stubs Ensure there is at least one return via adjacent to every
differential via pair Use as tight a pitch between the two vias as
practical Remove all non-functional pads Use as large an antipad as
practical Via Optimization
17. 2011 ANSYS, Inc. March 30, 201517 Antipad Size vs. Resonant
Frequency By increasing the antipad diameter, the resonant
frequency was increased from 15GHz to 18.2GHz
18. 2011 ANSYS, Inc. March 30, 201518 Optimizing the Socket via
By using a larger antipad within allowable limits, the via
capacitance reduces and thus, the impedance increased +10ohms thus
improving Channel ISI.
19. 2011 ANSYS, Inc. March 30, 201519 Optimizing the Board via
By using a larger antipad within allowable limits, the via
impedance increased +17ohms thus improving Channel ISI.
20. 2011 ANSYS, Inc. March 30, 201520 Insertion loss comparison
Optimized socket via Original socket via Better insertion loss at
Niquist with joined antipad.
21. 2011 ANSYS, Inc. March 30, 201521 FEXT Comparison Optimized
socket via Original socket via ~17dB less crosstalk at Niquist with
joined antipad.
22. 2011 ANSYS, Inc. March 30, 201522 How does this impact
Channel performance?
23. 2011 ANSYS, Inc. March 30, 201523 Impact of optimized
Socket and board Via EH: 13mV We gain back 10mV of EH! +2mV still
needed to meet Tx CEM spec EH requirement EH: 23mV
24. 2011 ANSYS, Inc. March 30, 201524 Impact of optimized
Socket & board Via and 1inch length reduction With 1nch
reduction (so channel length now 13inches); EH = 28mV EH: 28mV
25. 2011 ANSYS, Inc. March 30, 201525 Signal integrity
simulation requires accurate models to ensure reliable designs
Pre-layout simulation is a powerful tool that can help set robust
platform design guidelines The ANSYS HFSS unified desktop provides
full coverage for SI analysis needs for pre-layout analysis: Time
domain analysis via QuickEye or VerifEye Frequency domain analysis
via LNA and NDE 3D vertical models can be made and inserted
directly into simulation channel deck Conclusion
