Paul Barbee, Brian Lewis, & Alex Mrozack ECE262 – Analog Design May 8, 2010

Input Clock PLL Digital Clock Generation/Multiplication

Output Clocks

Phase Detector Charge

Pump Low Pass

Filter Voltage Controlled

Oscillator (11 Stage CSI)

D Flip Flop Edge Triggered 64x Divider

Feedback

 Locking Frequency Range – 1-5MHz  Typical Supply Voltage – 5VDC  Lock Time – 10us  Max Jitter – 38ns (at rough lock…could

still meet 100ps desired spec after settling)

 Max Wander - +/-50 ppm??????  Power – 1W Peak

 66 Devices for Analog Logic ◦ Major devices – Charge Pump, VCO

 242 Devices for Digital Logic ◦ Clock multiplication, PFD

  Size – 1mm * .5mm (working area not actual) ◦ Taking our loop filter off chip

 Best, Roland E.:  Phase-locked loops : theory, design, and applications

 Razavi, “Design of High-Speed, Low-Power Frequency Dividers and Phase-Locked Loops in Deep Submicron CMOS” (IEEE Journal of Solid State Circuits, February 1995)

 Razavi, “Design of Analog CMOS Integrated Circuits”