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Patrick Coleman-Smith CCLRC Daresbury1
AGATA Digitiser Summary February 2005
Patrick J. Coleman-SmithFor the Digitiser Technical
Group I.Lazarus Daresbury
P.Medina IReS
R.Baumann IReS
C.Santos IReS
M.Chambit IReS
J.Thornhill Liverpool
D.Wells Liverpool
Patrick Coleman-Smith CCLRC Daresbury2
• Revised Mechanical Structure• Global Clock internal delivery• Laser link trial report• TNT2 tests• Slow Control• Cost• Schedule• Some Remaining Questions
Patrick Coleman-Smith CCLRC Daresbury3
Previous Mechanical Structure
Patrick Coleman-Smith CCLRC Daresbury4
New Mechanical Assembly
Mechanical Constraints
•Distance to the Detector 5 Metres
•Power Dissipation around 400W
•Mechanically dependant on the detector array.
Use Water Cooling
New arrangement of PCBs
Patrick Coleman-Smith CCLRC Daresbury5
co n n ecto rsM o d u le
C o o led p la te
C o o led p la te
Bac k p lan ec o n n ec to r
C en tr a l F I X E Dc o o lin g p la te .
F r o n tp an e l
R earp an e l
B2 B c o n n ec to r s
co n n ecto rs
2 E lec tr o n ic s m o d u les in s er ted in c o o lin g r ac k
P C B c o m p o n en ts
Bac kP lan e
T h er m al F o am
P o w er s u p p lyan d c o n tr o l P C B
Structure of the Digitiser: Cooling, and mechanics
Patrick Coleman-Smith CCLRC Daresbury6
Internal Global Clock Distribution
•Clock reference input from the Pre-Processor core board using Laser link.
•The idea is to use Sinusoidal clock through a Jitter smoother and a Mini-circuit splitter
•Distribute to the Flash ADCs via cable.
•Passive Filter to transform the square wave input to a sinusoidal signal
Patrick Coleman-Smith CCLRC Daresbury7
C lo c k s e lec t
1 0 0 M HzC lo c k f ro mL as er o u t
N B6 L 1 6 o r 1 0 0 E P 1 6S Y8 9 8 3 0 U
1 0 0 M Hz f o r in te r n a ls y s tem s u s e ( s y n c , C F D e tc )
S Y8 9 2 9 5 UT I
1 0 0 M HzD if f O s c .
S 1
S 2
S 3
S 4
S 5
S 6
C o re 1
TR A NS M I S S I O N S EC TI O N
R EC EI V E S EC TI O N S EG M ENTS
N B6 L 1 6 o r 1 0 0 E P 1 6AD C 1 C L O C K
AD C 3 C L O C K
AD C 6 C L O C KAD C 5 C L O C KAD C 4 C L O C K
AD C 2 C L O C K
AD C 7 C L O C KVI R T E X C L O C K 1VI R T E X C L O C K 2S P AR E
C o re 2
C o re 1 an d C o r e 2ar e in te r n a l c o ax ia l lin k sto th e AD C c lo c k s
N B6 L 1 6 o r 1 0 0 E P 1 6
R EC EI V E S EC TI O N C O R E
AD CC lo c kin p u t
T C 1 -1 T
AD T 4 - 1 T
C L KS E L E C T
X T AL
D E S KE W
C S - 3 0 0An alo g u e
P L LJ itte rF ilte r
D is c r e te 1 0 0 M HzBan d P as s F ilte r
0 /3 d bAtten
G AL I - 5 1P o w erAm p
P o s tam pF ilte r P O W E R
S P L I T T E R
( O u tp u tsm u s t a lw ay sb e te rm in atedin to 5 0 o h m s )
C lo c kD is tr ib u tio n
S I N EI n p u t
S I N EO u tp u ts
R E C
R E C R E CAD T 4 - 1 T
S I N EI n p u t
Internal Global Clock distribution schematicUnder Development at Liverpool University
Patrick Coleman-Smith CCLRC Daresbury8
Laser Trial Test and Results
•Designed the Laser Trial board with four Laser modules.
•Used Xilinx recommended PCB connection parameters for the 2Gbit/sec connections from the Virtex2Pro BGA to the Laser modules.
•Test connection to a Xilinx Development board:16 bit data from counter incrementing at 100MhzThree channels operating independently.Receiver tracks the data, checking each value received.Transmitter and receiver share the same clock.
•Ran for 8 days with no errors. 6.9 x 1013 Transfers per link
Patrick Coleman-Smith CCLRC Daresbury9
R o hd e a nd S c hw a rz P u ls e G e ne ra to r 1 0 0 M hz
Le C ro y P u ls e ge ne ra to r - s ingle to d iffe re ntia lc o nv e rs io n
P ic o lightd evelo p m entb o ard fo r 12
C hannel Las er
R eceiv er
Las er T rial V M Ec ard
X ilinx V irtex2P ro
Zarlink V C S ELLas er 12 c hannel
T ran s m itter
X ilinxV irte x 2 P ro
d e v e lo p m e ntb o a rd
3 0 M e te rs o f1 2 F ib e r rib b o n
X ilinx P arallelp ro gram m ing L inks
Se r ial L ink
Laser Trial Test Block Diagram
Patrick Coleman-Smith CCLRC Daresbury10
Laser Trial BoardLaser Transmitter
Virtex2Pro
100Mhz clock input
Analog Inspection
Patrick Coleman-Smith CCLRC Daresbury11
Laser Trial Setup
Patrick Coleman-Smith CCLRC Daresbury12
TNT2 Tests 1
Patrick Coleman-Smith CCLRC Daresbury13
TNT2 Tests 2
Patrick Coleman-Smith CCLRC Daresbury14
Slow Control
External interfaces: Xport module• Galvanically isolated serial link over 10/100baseT physical layer.
• Experiment control for the digitiser.
• Laboratory and diagnostic access.
Internal interfaces : Serial link• Link is Clock, Data, Frame signals
• Simple protocol developed at Liverpool. Connects all FPGAs using Star topology.
Requests all generate an Acknowledge.
Timeout with reset of link.
Long write to allow re-program of FPGA.
'C O R E 'C O N T R O LS P AR T AN
'S EG M EN T 'C O N T R O LS P AR T AN
S E G M E N T 1AD C VI R T EX
X P O R T
S E G M E N T 4AD C VI R T EX
S E G M E N T 3AD C VI R T EX
S E G M E N T 1AD C VI R T EX
S E G M E N T 2AD C VI R T EX
C O R E AD CVIR T E X
S E G M E N T 2AD C VI R T EX
X P O R T
LO C AL C O N T R O LR EG IS T E R S
S R AM
LO C AL C O N T R O LR EG IS T E R S
S R AMF L AS H
R AM
F L AS HR AM
P r o g ram c o d e
P r o g ram c o d e
C O R E/S E G M E N TM O D ULE
S E G M E N TM O D ULE
c o r es eg m en tlin k v iab ac k p lan e
T x /R x C L K/D AT A/F R AM Eb o th d ir ec tio n s
T x /R xC LK/D AT A/F R AM E b o th d ir ec tio n s
Patrick Coleman-Smith CCLRC Daresbury15
Prototype Digitiser : 45,000 Euros
Further Digitisers : 30,000 Euros
Cost Estimates
Patrick Coleman-Smith CCLRC Daresbury16
Schedule
Patrick Coleman-Smith CCLRC Daresbury17
Some Remaining Questions
1. Offset Control link protocol
2. Segment and Core data link start-up protocol, and how to respond to failures.
3. Global clock link start-up and calibration
4. Pre-Amp Interface - Pulser Control
5. Slow Control External interface protocol
6. Mechanical mounting on the Apparatus
Patrick Coleman-Smith CCLRC Daresbury18
2 4 S eg m en tBac k p lan e
Las er
Las er
Las er
Las er
An alo g u eS ig n als in
An alo g u eS ig n als in
C lo c ks ig n als
E th er n e t p o r t
Bac k p lan e
Las er( F AD C an dC lo c k )
Las er
Las er
An alo g u eS ig n als in
An alo g u eS ig n als in
P O W ER I N 4 8 V
C lo c k s ig n als o u t
C lo c k s ig n als
C lo c k s ig n als
E th er n e t p o r tC o r ean d
1 2 s eg m en t
I n s p ec tio n lin esth is s id e a ls o
Signal interconnections
Patrick Coleman-Smith CCLRC Daresbury19
C L O C KC o n n ec tio n s
D etec to r in p u ts
S M A an d c o ax
C o r e
S eg m en t 1
S eg m en t 2
S eg m en t 3
S eg m en t 4
S eg m en t 5
S eg m en t 6
FR O NT PA NEL I NTER C O NNEC TS
Front panel clock interconnects
Patrick Coleman-Smith CCLRC Daresbury20
W ar m W ater o u t
C o o l W ater I n
O v er v iew o f m ain s tr u c tu r e w h ic h tak es 2 e lec tr o n ic s m o d u les( C o r e an d s eg m en t m o d u les - ( 1 + 1 2 ) an d ( 2 4 ) = 3 7 c h an n els ) .E ac h e lec tr o n ic m o d u le c an b e r em o v ed f r o m th is f r am e w ith o u th av in g to d is tu r b th e w ater s u p p ly , r ed u c in g a tten d an t r is k s .
Main Structure of the digitiser housing
Patrick Coleman-Smith CCLRC Daresbury21
Block Diagram of the Digitiser
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Segment board block diagram
Patrick Coleman-Smith CCLRC Daresbury23
DC-DC graphs
Patrick Coleman-Smith CCLRC Daresbury24
Clock Test boards
Patrick Coleman-Smith CCLRC Daresbury25
Slow control test board
