Energy Procedia 38 ( 2013 ) 881 – 889

1876-6102 © 2013 The Authors. Published by Elsevier Ltd.Selection and/or peer-review under responsibility of the scientifi c committee of the SiliconPV 2013 conferencedoi: 10.1016/j.egypro.2013.07.360

ScienceDirect

SiliconPV: March 25-27, 2013, Hamelin, Germany

Passivation of textured silicon wafers: Influence of pyramid size distribution, a-Si:H deposition

temperature, and post-treatment Bert Stegemanna,*, Jan Kegela,b, Mathias Mewsb, Erhard Conradbd , Lars Korteb,

Uta Stürzebecherc, Heike Angermannb

aHTW Berlin a - University of Applied Sciences Berlin, Wilhelminenhofstr. 75a, D-12459 Berlin, GermanybHelmholtzb -Zentrum Berlin für Materialien und Energie, Institut für Silizium-Photovoltaik, Kekuléstraße 5, D-12489 Berlin,

GermanycCiS Institut für Mikrosensorik und Photovoltaik, Konrad-Zuse-Str. 14, D-99099 Erfurt, Germany

Abstract

In this study we focus on optimizing the passivation of pyramid textured n-type crystalline silicon (c-Si) wafers by deposition of intrinsic amorphous Si (a-Si:H(i)) layers. By statistical analysis of the pyramid size distribution it is revealed that a decreased fraction of small pyramids leads to longer minority charge carrier lifetimes and, thus, a higher Voc potential for solar cells. Further, we demonstrate that optimized parameters for the deposition of a-Si:H(i)layers on planar Si(111) wafers can be transferred to the a-Si:H deposition on random pyramid textured Si(100)wafers exhibiting facets with {111} orientation. In particular the influence of the deposition temperature on theoptical layer properties is elucidated. Furthermore, the favorable impact of post-deposition plasma-hydrogenation and annealing on the charge carrier lifetime (> 5 ms) and the implied open-circuit voltage (up to 738 mV) aredemonstrated.

© 2013 The Authors. Published by Elsevier Ltd.Selection and/or peer-review under responsibility of the scientific committee of the SiliconPV 2013 conference

Keywords: c-Si; a-Si:H; Defect Density; Etching, Heterojunction; Interfaces; Lifetime; n-type; Optical Losses; Texture.

* Corresponding author. Tel.: +49-30-5019-3237; fax: +49-30-5019-2115.E-mail address: bert.stegemann@htw-berlin.de.

Available online at www.sciencedirect.com

© 2013 The Authors. Published by Elsevier Ltd.Selection and/or peer-review under responsibility of the scientifi c committee of the SiliconPV 2013 conference

Open access under CC BY-NC-ND license.

Open access under CC BY-NC-ND license.

882 Bert Stegemann et al. / Energy Procedia 38 ( 2013 ) 881 – 889

1. Introduction

Due to the resulting very low interface defect densities, excellent hetero-interface passivation can be achieved by deposition of intrinsic amorphous Si (a-Si:H(i)) layers onto planar crystalline silicon (c-Si) wafers. Subsequent deposition of doped a-Si:H layers allows the fabrication of heterojunction solar cells with high open circuit voltages and high efficiencies > 23 % [1]. A significant solar cell efficiency improvement can be achieved by wet-chemical texturing of the Si(100) wafers to produce pyramids with {111} oriented facets and a size of a few microns. This random pyramid texture minimizes reflection losses and increases the absorption probability by light trapping [2]. However, adequate passivation of pyramid textured Si wafers is more difficult to achieve due to the increased effective surface area and a higher number of crystallographic imperfections [3].

In this study, the particular influence of variations in the fraction of small pyramids on interface recombination is systematically investigated by statistical analysis of the preparation-induced pyramid size distribution. The consequential effect of these morphological properties on the charge carrier lifetimes and the implied open circuit voltages for a-Si:H(i)/c-Si interfaces are analyzed. Since a-Si:H(i) deposition parameters for optimal passivation are well established on planar c-Si wafers, it is a further goal of this study to correlate results on the passivation of planar Si(111) wafers by a-Si:H(i) layers to the passivation of random pyramid textured Si(100) wafers with a surface consisting of {111} facets. Applying textured substrates with lower fraction of small pyramids we focus here on the optimization of the a-Si:H(i) deposition temperature and subsequent thermal treatment for achieving long charge carrier lifetimes. For additional passivation a hydrogen plasma treatment was applied as described in [4].

2. Experimental

Random pyramid textured substrate surfaces on initially as-cut c-Si(100) wafers (n-type, float zone grown, 1-5 - 300 μm) were prepared by wet-chemical treatment in potassium hydroxide (KOH) containing solutions. Conventionally, random pyramid textures are fabricated by wet-chemical etching of the wafer in alkaline solutions containing isopropyl alcohol (IPA) as an additive. Due to its high volatility and environmental impact IPA was replaced by GP Alkatex ZeroTM (GP Solar GmbH). By systematic variation of the etching time, randomly distributed pyramids with different size distributions were prepared. The pyramid size distribution and particularly the fraction of small pyramids were determined by statistical analysis of scanning electron micrographs (SEM).

Immediately before a-Si:H(i) deposition, both pyramid textured substrates and polished Si(111) reference samples were pre-treated applying a standard RCA cleaning process [5] and a subsequent etching step in HF (1%) with optimized durations of 180 s or 60 s [6]. Amorphous Si layers were deposited by standard plasma-enhanced chemical vapor deposition (PECVD) at temperatures ranging from 170 to 230°C with a nominal thickness of 17 nm corresponding to about a 10 nm thick layer on textured c-Si wafers. After a-Si:H(i) layer deposition the samples were annealed at 200°C for 20 min. Selected samples were treated after deposition with hydrogen plasma (190°C, 4 min.) to elucidate a possible additional passivation effect. Optical layer properties were determined by spectral ellipsometry (SE).

The effect of interface passivation on the minority charge carrier lifetime was investigated by transient photoconductance decay measurements (TrPCD) after a-Si:H(i) layer deposition and post-deposition treatment. The time-dependent photoconductance as well as the light intensity were simultaneously measured contact-less via an RF bridge and a calibrated reference solar cell, respectively, using a commercial set-up (Sinton WCT-100). Thereby, the effective minority carrier lifetime ( eff) and the implied open-circuit voltage (impl. Voc) were determined [7].

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3. Results and discussion

3.1. Influence of the pyramid size distribution on carrier lifetimes and implied open circuit voltages

As recently reported, both the depth of saw damage removal and the duration of the texture etching in IPA-free KOH containing solution influences the pyramid morphology [8,9]. Largest pyramids are obtained at intermediate saw damage removal (ca. 10 μm/side) and intermediate texture etching times of ca. 20 min. An increasing number of small pyramids can be observed for short (5 min) and for long (40 min) texture etching times as well as for incomplete saw damage removal of <5 μm/side. Moreover, in case of long etching times of 40 min even pyramid-free substrate areas can be found on the sample in addition to many small pyramids [8,9]. Typical examples are shown in the SEM images in Fig. 1. Fig. 1a shows a sample with mainly small pyramids where the surface morphology is dominated by incomplete saw damage etch removal, while in Fig. 1b a larger fraction of large pyramids appears due to the optimized texture etching time at complete saw damage etch removal.

The statistical analysis of these SEM images leads to the histograms given in Fig. 1c/d and allows for an estimation of the pyramid sizes and their size-distribution on the textured silicon wafers. For quantitative description of the surface morphologies and to obtain a meaningful measure for comparison of different samples two characteristic parameters are derived from this statistical analysis and provided in the histograms, (i) the average size of the pyramid base area (see Fig. 1c/d) and (ii) the fraction of small pyramids (i.e. the fraction of the first three size-classes (up to 6 μm2 for all samples under investigation) relative to the total area).

(a) (b)

(c) (d)

Fig. 1. SEM images of textured Si wafers: (a) after 5 μm/side damage etch removal and 20 min texture etching time, (b) after 10 μm/side damage etch removal and 10 min texture etching time. Scanning size of both images: 25 μm × 19 μm, tilt: 30°. (c,d)

Histograms of the statistical analysis of the corresponding pyramid sizes in the SEM images above. Data is obtained from at least 3 measurements at different positions on the sample.

average pyramid size: 2.9 μm2 fraction of small pyramids: 72.5 %

average pyramid size: 8.4 μm2 fraction of small pyramids: 18.9 %

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In order to further evaluate the influence of the pyramid size distribution on the electronic interface properties, a series of textured samples with a systematic increase of the fraction of smaller pyramids was prepared [9]. On these differently prepared surfaces identical a-Si:H(i) layers were deposited by PECVD applying the same process parameters for all samples (TSub = 170 °C, layer thickness = 6 nm).

The analysis of the influence of the pyramid size distribution on eff is summarized in Fig. 2. This graph shows the dependence of the carrier lifetime on the fraction of small pyramids and can be roughly divided into two parts. Whereas samples with a large fraction (>50%) of small pyramids show lower carrier lifetimes of eff 2.5 ms, samples with a fraction of small pyramids <50 % reach higher values, up to 4.2 ms. eff rises with increasing fraction of bigger pyramids due to the lower density of pyramid valleys which are known to be centers for epitaxial growth as well as for local cracks of the a-Si:H(i) layer [10]. In addition it was found was found that above a certain threshold, a further increase in pyramid size does not lead to a further increase in charge carrier lifetime. It is suggested that on textures with large pyramids the recombination processes at defects on the pyramid facets dominate the overall recombination at the interface [11]. This behavior is well described by the fraction of small pyramids, which is thus recommended to be considered as the relevant parameter, rather than the average pyramid size [8].

Fig. 2. Dependence of the effective carrier lifetime on the fraction of small pyramids.

3.2. Influence of the a-Si:H deposition temperature

While in section 3.1 we demonstrated the influence of pyramid surface morphology, in this section the focus is put on the optimization of a-Si:H(i) layer deposition parameters for textured solar cell substrates. For these investigations samples with lower fractions of small pyramids (cf. Fig. 2) and, thus, a potentially higher minority charge carrier lifetime, thus Voc potential, were selected.

The deposition of a-Si:H(i) layers on planar c-Si wafers is an established process [12] and the influence of substrate temperature Tsub during deposition and post-deposition treatments on the resulting layer properties is well understood. In order to get insights into the transferability of these recipes to the

Bert Stegemann et al. / Energy Procedia 38 ( 2013 ) 881 – 889 885

controlled deposition of a-Si:H(i) layers on textured c-Si wafers parallel deposition experiments were carried out on polished Si(111) wafers and on textured Si(100) wafers exhibiting {111} oriented facets. All process steps (i.e., RCA cleaning, a-Si:H(i) layer deposition, post-treatment) were applied in parallel on both polished and textured Si substrates with the same process parameters. In this study a nominal a-Si:H(i) layer thickness of 17 nm was chosen, corresponding to an effective layer thickness of about 10 nm on textured substrates, as estimated from the effective surface enlargement by a factor of 1.73.

In a first step, the influence of the substrate temperature TSub during a-Si:H(i) deposition on the optical layer properties on planar substrates was determined by SE. The results (see Fig. 3) show that with increasing substrate temperature (from 170 to 230°C) the bandgap is narrowed from 1.72 to 1.64 eV and the refractive index, and thereby the absorption, is increased. This can be explained with a lower incorporation of hydrogen and the more compact layer structure [13]. Accordingly, the variation of the substrate temperature TSub during a-Si:H(i) deposition allows to tune precisely the optical properties of the a-Si:H layer.

eff and implied Voc on polished and textured Si wafers after subsequent annealing is shown in Fig. 4. For the planar wafer it is found, that increasing the temperature up to 190°C leads to an increase of the charge carrier lifetime up to 9.5 ms, which is due to the excellent interface passivation created by the highly mobile hydrogen. At 190°C a trade-off between hydrogen concentration and mobility is reached. As observed in the optical measurements (cf. Fig. 3), at lower substrate temperatures the layer contain larger amounts of hydrogen. However, at lower temperatures diffusion is limited and accordingly interface passivation is suppressed, which results in low charge carrier lifetimes. Beyond 190°C there i eff, possibly due to the lower hydrogen concentration or to increased interface recombination caused by local epitaxial growth, which is known as being detrimental for passivation [14]. On the textured wafer, the same qualitative behavior is observed. The maximum lifetime of 3.3 ms is - as expected - lower than in the planar case, but found at the same temperature of 190°C. An analogous behavior for the implied Voc is found, indicating efficient interface passivation. Apparently, at Tsub = 190°C a high-quality layer and a well passivated interface are obtained.

(a) (b) Fig. 3. Optical properties of a-Si:H(i) layer (thickness 17 nm) as a function of the substrate temperature during deposition and after

thermal annealing: (a) optical bandgap energy EG0, (b) spectral dependence of the refraction index n.

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Fig. 4. Dependence of the carrier lifetime (left) and implied Voc (right) on the a-Si:H(i) deposition temperature for planar and

textured Si wafers (after thermal annealing)

3.3. Influence of the post-deposition treatment

The effect of the thermal annealing step on the lifetime and the implied Voc is shown in Fig. 5 for different deposition temperatures. In both cases the ratio of the lifetimes and implied Voc after and before annealing at 200°C for 20 min is depicted. These gain / loss charts visualize the impact of the thermal annealing. Values >1 generally indicate an improvement upon thermal annealing. Accordingly, it is concluded from these graphs that thermally annealing the textured samples results in even higher gains as compared to the planar samples. Moreover, at low substrate temperatures (ranging from 170 to 200 °C) a clear improvement of eff and the implied Voc upon annealing is found. This is due to the initially (i.e., after a-Si:H(i) deposition) rather high defect concentration at the hetero interface as well as in the a-Si:H(i) bulk which can be efficiently saturated by the mobile hydrogen after thermal annealing. At deposition temperatures >200°C no improvement is found due to partial deterioration of the a-Si:H interface. In this case, in the initial state, i.e. after deposition, many defects states are already passivated and less hydrogen atoms remain available for temperature-induced passivation. These findings imply that for random pyramid textured Si substrate surfaces with (111) termination the deposition temperature should not exceed 200°C during fabrication of heterostructure solar cells.

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Fig. 5. Dependence of the carrier lifetime (left) and the implied Voc (right) on the a-Si:H(i) deposition temperature for a planar, polished Si(111) and a textured Si wafer after thermal annealing. Shown are the ratios of the lifetimes and the implied Voc after and

before annealing.

Proper post-treatment clearly improves the electronic properties of the a-Si:H(i)/c-Si(n) stacks, which

is mainly due to the interface passivation by hydrogen. A further improvement is achieved by hydrogen plasma treatment. This additional post-deposition hydrogen supply leads to a higher saturation of dangling bonds and thus to an improvement of the interface [2]. Fig. 6 compares the influence of thermal annealing (at 200°C) and hydrogen plasma treatment (at 190°C) eff and impl. Voc. In addition sequential plasma hydrogenation and thermal annealing is investigated, which is motivated by the technological requirement of successive layer deposition (i.e., doped a-Si:H layers, transparent conductive layers) at substrate temper 200°C for complete solar cell fabrication. Therefore it must be ensured that the interface properties of hydrogenated a-Si:H(i)/c-Si stacks do not deteriorate.

Both on the polished and the random pyramid textured substrates plasma hydrogenation with subsequent thermal annealing lead to a distinct increase of the carrier lifetime and implied Voc compared to thermal annealing or plasma hydrogenation, although the increase is more pronounced for the polished samples. Hydrogen plasma treatment is even superior to thermal annealing and of particular benefit for interfaces with high defect densities. In case of the polished wafer, eff increases by a factor of about 2

eff = 17.7 ms) and a further improvement to values of 21 ms is achieved by additional thermal annealing. Charge carrier lifetimes are as expected - lower on the textured substrates, but show the same qualitative behavior. In this case lifetimes of nearly 5 ms are achieved. Thus, it is concluded that hydrogen plasma treatment and thermal annealing are clearly beneficial for saturating interface defects on the textured wafers and result eff and higher implied Voc.

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Fig. 6. Influence of post-deposition treatments on charge carrier lifetimes (left) and implied open circuit voltages (right) on a-Si:H(i)/c-Si hetero-interfaces deposited at TSub = 190 °C.

4. Conclusions

We investigated the influences of the pyramid size distribution, the a-Si:H(i) layer deposition temperature and the post-deposition treatments on the passivation of textured Si wafers. From the results it is concluded that the minimization of recombination losses at textured a-Si:H(i)/c-Si interfaces requires the optimization of the wet-chemical etching process to avoid large fractions of small pyramids and the optimization of the a-Si:H(i) deposition and post-treatment parameters.

Knowledge from a-Si:H(i) layer deposition on planar substrates was successfully transferred to a-Si:H(i) deposition on random pyramid textured substrates, yielding high minority charge carrier lifetimes of > 5 ms and implied open-circuit voltages of up to 738 mV using a combination of hydrogen plasma treatment and thermal annealing, on (n)c-Si wafers passivated with ~10 nm a-Si:H.

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Acknowledgements

The authors thank C. Klimm (Helmholtz-Zentrum Berlin) and K.-D. Wustig (HTW Berlin) for SEM image acquisition and A. Lawerenz (CiS Erfurt) for fruitful discussions. This work is part of the project

- is supported by the HTW Berlin.

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