September 09 1

PaSiVe: Tool for Matlab/Simulink Design Flow for Fast Prototyping Signal Processing Systems on FPGA

Zhongren Cao Joshua NgSenior Research Engineer California Institute for Telecommunications & Information TechnologyUniversity of California, San Diegozcao@soe.ucsd.edu

Bhaskar RaoProfessorElectrical and Computer DepartmentUniversity of California, San Diego

Outline

Motivation

Fast Prototyping Design Flow

PaSiVe: Tool for Matlab/Simulink Flow

Example Project

September 09 2

EXperimental reConfigurable radIo TEstbedA joint project between Ericsson Research and Calit2@UCSD

Sponsor: Ericsson Research

Motivation

Fast PrototypingImplement new ideas in a real scenario quicklyVerify innovations and identify problems early in the design phaseFPGA is widely adopted for fast prototyping projects

ProgrammabilityComputing parallelism

Limitation of the Tradition FPGA Design FlowTeam is separated into system/algorithm and hardware groups.

Use different languages Communication problem within the teamDifferent expertise require different development environments

Time consuming and error-prone for translationVery difficult for joint algorithm-architecture-circuit optimizationUnsuitable for fast prototyping projects

September 09 3

Motivation

Matlab – The De Facto Tool for Signal ProcessingWidely adopted by signal processing system and algorithm designers Providing abstractions for

Complex numbers, matrices and vectorsSupporting arithmetic operation with multi-dimension data structurePreserving parallelism of the algorithmAgnostic to hardware implement architecture

SimulinkSmoothly integrated with MatlabGraphic Interface that captures addition system aspects information

Implementation architectureTimed data flow

Ideal for fast system prototyping

September 09 4

Design/Implementation Workflow

Matlab/C

Real-world signal

VHDL/Verilog

FPGA

Written Spec

Measurement

Matlab/Simulink

Real-world signal

FPGA

Measurement

Traditional Design Flow

Matlab / Simulink Design Flow

Simulink – Unified Design InterfaceHierarchy layered abstraction for a signal processing systemIntuitive for both system engineers and hardware designers

Algorithm development and modelingArchitecture and circuit optimization

A golden reference is still needed – Matlab descriptionGenerate verification data setsVerify operation accuracy

Three Major Phases in the Matlab/Simulink Flow1. Executable Matlab system description2. Bit-true and cycle-true Simulink model3. Real-time hardware execution

Fast Prototyping Design Flow

September 09 6

September 09 7

Matlab and Simulink Design Flow

System and Algorithm Description in Matlab

Bit True and Cycle TrueSimulink Model

Real-Time FPGAExecution

Executable System Description in Matlab

System SpecificationHierarchy system partitioning Algorithms used by each system module

Generates Test Data Set for Verification

System PartitioningBased on data flow and functionalitiesConsidering the expertise and skills of designersLooking for reasonable hierarchy levelsFrequent modification

Typical for prototyping projectsGood system partitioning

Localize modification within the hierarchy structure

September 09 8

Bit-True And Cycle-True Simulink Model

Magic of Hardware Equivalent BlocksSupport fixed point simulation in SimulinkImplanted with verified and optimized technology-specific HDL

Xilinx FPGA – System GeneratorAltera FPGA – DSP BuilderASIC – Synplify DSP or UC Berkeley INSECTAUser customized blocks

Early stage power and area estimation

Simulink Model vs. Matlab DescriptionData in Simulink is timed with explicit sample rate information

Matlab’s data are untimed.Simulink has control logic and delay pipelining

No need to consider in MatlabFixed point arithmetic in Simulink

September 09 9

Real-time Hardware Execution

Verification With Real DataAdditional data save scheme is built into the FPGA design.

September 09 10

PaSiVe Overview

Collaborative Prototyping is NecessaryDesign becomes more and more complexFPGA capacity grows significantly

PaSiVe – Parameterization, Simulation and VerificationA tool for facilitate collaborative fast prototypingUsing the Matlab / Simulink design flowPaSiVe manages multiple design filesPaSiVe supports modular designPaSiVe organize simulationsPaSiVe streamlines verifications

September 09 11

Design File Organization in PaSiVe

September 09 12

Modular Design in PaSiVe

September 09 13

Modular Design in Fast PrototypingEnable parallel development on multiple modulesSimplify verification, debug and correctionFlexible to add, delete and change module functionalities

Realize Modular Design in MatlabStraightforward with Matlab functionsEach module is implemented in a separate Matlab function fileEach module has its own parameter files and verification filesHierarchy among modules is reflected in nested function calls

Implement Modular Design in SimulinkNot obviousSimulink simulation requires one file to contain the full system

Modular Design in PaSiVe

Using Simulink Library Link for Modular DesignEach module is implemented as a Simulink library blockA library block can include links to other library blocks

Reflecting modular hierarchyThe full system Simulink model includes links to all modules’ libraries

September 09 14

Simulation in PaSiVe

Modes of Simulation in PaSiVeBased on prototyping phases

Matlab only simulationSimulink only simulationMatlab-Simulink joint simulation

Based on simulated system scopeFull system simulationPartial system simulationSingle module simulation

PaSiVe Simulation MechanismOverlay on top of vender’s simulationUse ‘Simulation Configuration file’

psvset.mSupport Monte Carlo simulation

September 09 15

Simulation in PaSiVe

September 09 16

Verification in PaSiVe

Pre-Generation VerificationHappen before generating the hardware bitstreamVerify bit-true cycle-true Simulink model against the Matlab descriptionUse Matlab and Simulink joint simulation

Same parameter setSame initial inputs and conditions

Post-Generation VerificationHappen after real-time FPGA executionCheck the FPGA operation accuracyRely on real data collected from FPGA operationUse Matlab simulation to speed up verification

Simulink simulation is slowSimulink is invoked when Matlab simulation shows errors

September 09 17

Verification in PaSiVe

September 09 18

Verification in PaSiVe

Verification FilesDesigned by developersCalled by PaSiVe after simulationData translation is needed

From multi-dimensional matrices to sequential arraysFrom untimed to timesFrom floating point to fixed point

Data translation canVerify control logic designMatch delay pipelining

September 09 19

Example Project

Over-the-air SISO-OFDM packet transmission

September 09 20

Example Project

September 09 21