Part IIA Third Year Projects Computer-Based Project in ...dmh/ptiiavlsi/pdf/C6-2007.pdf · Part IIA Third Year Projects Computer-Based Project ... chip’ may contain digital, analog,

Computer-based project in VLSI Design

D M Holburn EN2002 and ICFlow2003.3 April 2007

Part IIA Third Year Projects

Computer-Based Project in VLSI Design

Co 3/6

May 2007

This Lab guide is supplemented by material on the project’s CamTools worksite, for which all participants will receive a login.

Worksite: http://camtools.caret.cam.ac.uk/portal Email support: [email protected]

Computer-based project in VLSI Design Introduction

D M Holburn May 2007 EN2002.1 1 C6intro.doc


Computer-Based Project in VLSI Design Co 3/6

Introduction

The aims of this project are to provide a degree of familiarity with the following:

• The potential of computer-aided design for crafting a System-on-a-Chip • The tools available for key activities in electronic system design • The value of hardware description languages (HDL) • The importance of hierarchy and design re-use in IC design • The structure and detailed design of MOS transistors • Development of simple digital circuits based on MOS transistors • Numerical simulation of digital systems and MOS transistor circuits • The importance of parasitic capacitance in determining operating speed • The relationship between simulated results and measured performance

We wil achieve all this through the design of a small ‘System-on-a-Chip’, with a combination of structured practical computer-based exercises, carried out under the supervision of a demonstrator; short 'mini-lectures' to introduce key issues and to provide direction; demonstrations of important techniques and opportunities to measure the actual performance of a real chip.

Format

In this project, students will work in pairs, and will share the work at the computer terminal. Each student should undertake supporting work away from the terminal (reading, researching, planning and so on), and each student will be expected to write two interim reports and a final report.

Schedule

Week 1: Introduction to project objectives and tools. Use of VHDL for modelling design concept and system design. Examination and adaptation of transistor-level schematics for a simple 2 input logic gate. Exercises on design of 2 input logic gate. First interim report.

Week 2: Schematic capture of ring oscillator and programmable divider design. Creating symbol and schematic diagram for ring oscillator element. Introduction to simulation of schematic design. Estimating system performance. Identification of design errors. Comparing results with measured performance of CMOS ring oscillator circuit. Second interim report.

Week 3: Layout and design rule verification of NOR gate structure. Layout vs Schematic verification. Estimating parasitics. Netlist and parasitic extraction. Simulating NOR gate performance using Accusim. Comparing results with measured performance of CMOS ring oscillator circuit.

Week 4: Further simulation using Accusim. Investigating techniques for semi-custom design. Floor-planning, placement of logic blocks, pads and primitive cells, automatic routing and optimisation. Final report.



Mini-lectures

(i) Introduction to VLSI Design & VHDL. Schematic capture. Ring oscillators. (ii) Design verification by simulation. Integrated Circuit Layout. Design rule

checks. Semi-custom layout. Project Organisation

Some important dates and deadlines are as follows:

Tuesday 15th May 2007 (Week 3) Project begins Monday 21st May 2007 (Week 4) Hand in date for first interim report Monday 28th May 2007 (Week 5) Hand in date for second interim report 5 pm Saturday 9th June 2006 (Week 7) Hand in date for final project reports No reports will be accepted after this date.

During the project period, approximately 8 hours per week will be time-tabled for each project as sessions when one or more demonstrators will be available, to give introductory talks, guidance and help. Students are expected to attend all sessions. On the directions of the Teaching Office, a record will be kept by the demonstrators in charge.

Students will need to spend some additional 12 hours per week per project working on their own (including report writing). For computer-based projects, some of this time will need to be spent working at spare computer terminals, subject to availability.

Students will be issued with a Laboratory Notebook. This is to be used to record all day-to-day activities, as a sketch book for any draft design work, to record calculations, results, etc. Demonstrators may ask to see notebooks when marking reports to check that books are used correctly with entries properly laid out and dated.

This project requires 3 reports to be submitted, i.e. 2 short interim reports and a final report. The maximum total length taken together (typed or hand-written A4 pages) must not exceed 14 sides, plus calculations, and drawings.

Reports should be posted in the box used for Part II experiments on the landing outside the E & IE Teaching Lab (accessible whenever the Department is open).

In preparing reports, students are expected to adhere to the page limits, and to keep the volume of appendices to a minimum. The format will be as follows:

Interim Reports: 2 sides each, excluding appendices. Final Report: Not greater than 10 sides of A4, excluding appendices. Further details are provided elsewhere in this sheet and in the document Third Year Project Guide.

References

Analysis and Design of Digital Integrated Circuits, (Second Edition), D A Hodges & H G Jackson, McGraw Hill.

Principles of CMOS VLSI Design, (Second Edition), N Weste & K Eshraghian, Addison Wesley.

Both books are available in CUED Library and in many Colleges.



Introduction to IC Design

Present day semiconductor technology allows designers to build integrated circuits with millions of transistors or logic gates. This has come about largely as a result of the steady refinement of the processes used to manufacture memories, microprocessors and peripheral interfaces, which has made sub-micron device dimensions an accepted fact. This progressive evolution in microelectronics was predicted by Gordon Moore in the sixties, and appears to be continuing. It was realised early in the evolution of microelectronics that design was a limiting factor, and that the unaided human designer simply cannot cope with the complexity of even a few thousand devices, let alone microprocessors or other circuits comprising millions of transistors. Future developments in technology promise to increase this number progressively.

System-on-a-Chip (SoC) is a revolutionary new approach in microelectronics which aims to integrate all the components of an entire electronic system into a single integrated circuit. The resultant circuit or ‘chip’ may contain digital, analog, mixed-signal or radio-frequency functions, and even micro-mechanical systems – all on one chip. This approach is cost-effective, since it enhances compactness and marketability, and it may also increase the yield or efficiency of the manufacturing process compared with a design involving a circuit board with several chips. However, developments such as these call for new methodologies and tools to address the more challenging design, verification and test problems presented by SoCs in this rapidly evolving area.

Moore's Law describes a doubling of IC complexity every eighteen months, and design productivity has lagged significantly behind this explosive growth. At the same time, competitive forces in the market place are shortening product lifetimes and compelling manufacturers to enhance productivity while coping with an increasing number of products and telescoping the design cycle into a fraction of the time. In these circumstances, designers are increasingly unable to take advantage of available technology in time to meet inexorable market demands. In order to cope with the burgeoning complexity, designers have adopted a number of strategies, several of which we shall meet during this project.

Design Automation First of all, designers make heavy use of EDA (electronic design automation) - the use of computer-based workstations to store, display and manipulate electronic design data. Elaborate suites of software have emerged to support the activity of IC design, and any designer must acquire proficiency with these in order to be productive. This is a key theme in the VLSI Design project.

Hierarchical Design Secondly, virtually all designs make use of hierarchy. A popular approach - top-down design - involves decomposing the design into a top-level block and defining the sub-blocks required to build it. Each sub-block is then progressively decomposed until the design has been reduced to the level of the most primitive leaf cells available. At each stage of the hierarchy, the complexity is maintained at a level that can be handled efficiently. By splitting the design task in this way into smaller, more manageable items which can be systematically designed, the overall design process becomes less daunting. We shall make full use of the hierarchical design approach in this project.



Design reuse Each block created using the hierarchical approach can be regarded as a resource that can potentially be incorporated in future designs. The re-use of such intellectual property (IP) is a key feature of the modern approach to IC design and is regarded as the only way to take advantage of the multi-million device capability of the silicon process. Its implementation across the industry is making formidable demands both of designers and of EDA tool developers. Several of the elements we shall work with in the VLSI project are examples of re-usable IP.

Project Activities

The project will begin with an introduction to the role of VLSI design, followed by a brief explanation of the operation and significance of the target System-on-a-Chip, forming the design to be undertaken. This is a programmable digital divider, a key element in a digital frequency synthesiser, which you will find in any mobile phone, walkie-talkie or other modern communication device. The key parts of this are covered in more detail below.

To summarise, a frequency synthesiser produces an output at one of a selection or pre-programmed frequencies, for use in a receiver or transmitter, to determine the frequency of operation. An oscillator is needed to make this work, and we will use a design known as a ring oscillator to provide a regular system clock. There will be a short discussion of how we go about making digital ICs from MOS transistors (covered in detail in module 3B2). The logic inverter will be used as an elementary example to introduce the concepts of schematic representation, net-lists and parasitic components, and to develop the basic concepts of transistor layout, in which the precise geometrical shape and size of the devices are specified.

In order to investigate and predict the behaviour of the target design, we shall explore the use of a hardware description language (HDL) for abstract modelling. This will make use of the Mentor ModelSim simulator. This approach is intentionally abstract, i.e. it is quite independent of the means by which the design is implemented. While this kind of modelling on its own cannot guarantee that a particular implementation will meet all the demands made of it, it gives a means of better understanding the operation of the design in purely functional terms. Most modern IC designs now commence with a preliminary study based on a hardware description language.

Schematic Capture Next, the Mentor Design Architect tool will be used to capture a simple circuit representation of the target System-On-A-Chip, which might be described as the key parts of a frequency synthesiser. It comprises four key modules:

• A ring oscillator module. This element provides an oscillatory signal which can be used as a clock waveform to control the timing of other circuit elements. Its operation will be studied and its design investigated at progressively greater depth as the project proceeds.

• A programmable divider. This element comprises a number of sub-circuits, listed below, and its purpose is to receive an input signal at a high frequency and to generate an output at a frequency which is at a specified sub-multiple of the input. A much fuller description of the rôle of programmable dividers in frequency synthesis is given below, where it is also explained that a complete



synthesiser requires some additional components that we won’t have time to design.

• The divider module. This element performs a division using bistables connected in cascade to count the input pulses supplied. To make it programmable requires that we can reset it to zero periodically. The counter specified for this design will require 6 or more bits

• A comparator is used to compare the outputs from the counter with fixed inputs to determine when the reset occurs. This is implemented using combinational gates which may include a 2-input XOR.

For convenience, the divider, comparator and other key components are derived from a library of standard parts; however, these are themselves made up of lower level parts (for example, bistables and combinational gates) and their construction can be explored and even altered if necessary.

In addition, the design will make use of pad cells, which provide the physical means in a real integrated circuit for introducing input and output signals as well as power supplies. The design of these is beyond the scope of this project, and standard library cells will be used as supplied.

Note that we shall take largely for granted the method of operation of the digital circuits used, though, as mentioned below, it is important to verify that they are correctly translated into valid physical representations.

These activities will introduce the use of the workstation for describing electronic systems in a hierarchical and symbolic way. The use of symbols to represent standard library parts (e.g. logic gates), or to denote sub-circuits, power supplies, inputs, outputs etc will be illustrated. The importance of properties as a means of conveying information about these entities to other 'down-stream' design tools will be stressed.

Design Architect's facilities for checking the electrical correctness of the circuit will then be explored. Although it cannot be established at this stage that the circuit will work in the way anticipated by the designer, it is possible to identify elementary mistakes, such as missing connections, short-circuits, and so on. Design Architect will then be used to examine the detailed, transistor-level structure of the key element within the ring oscillator, a 2-input NOR gate.

Simulation Because IC fabrication is a costly and time-consuming activity, it is vital that a design be verified as functionally correct before the fabrication process is begun. Numerical modelling plays a vital role in this, through the use of simulators, which attempt to describe the characteristics of an electronic system in terms of numerical models. This procedure is nowadays an accepted phase of any non-trivial electronic design project (even if it does not involve the design of ICs), and a wide range of simulation tools exist. In some, the level of modelling employed is incredibly detailed; as a result, only moderately complex circuits can be investigated without unacceptable penalty in terms of computing time. With others, the models used are simpler, but give less accurate results. They can be used to check for correct operation in much larger designs. In practice, a number of different approaches to simulation may be required, even within the compass of a single design. In this project we shall use three different simulation packages: ModelSim, QuickSim II, and Accusim.



A recognised approach to verifying the correct operation of a design involves capturing a schematic representation of the design, which can then be modelled using a selection of simulators, to confirm that it responds, electrically, as well as in other functional ways, as the designer intended. In most approaches to design, as here, the schematic is created at an early stage as it allows conceptual problems to be resolved before any effort is wasted on layout.

The QuickSim II logic simulator uses simple logical models to describe the behaviour of standard logic gates, and can readily be applied to systems containing thousands of gates. It will be used to check for correct operation of the entire design, and to give an estimate of its anticipated performance, in terms of oscillation frequency and the various output waveforms to be expected.

The Accusim simulator is used to model in a very accurate way the behaviour of a single 2-input NOR gate (of which there are several within the ring oscillator module). Accusim cannot realistically be applied to problems involving more than a few transistors, and could never be used to verify the correctness of the entire design. The creation of a design viewpoint is an essential precursor to numerical modelling of the circuit in order to explore its expected performance.

Circuit Layout The detailed design of the ring oscillator continues with the specification in terms of mask layers for the 2-input NOR gate. A mask specification comprises the set of plans by which a manufacturer creates the physical representation of an integrated circuit, and determines in the most minute way the performance of the system. We shall gain familiarity with the layout tools (ICgraph) available in the Mentor ICstation suite by completing the design of a partly-constructed gate - a 2-input NOR gate - which will serve also to introduce the key mask layers and the tools available for modifying them. Techniques for interconnecting complex structures using metal and polysilicon layers will be explored. The importance of design rules as a fundamental constraint in the design process will be illustrated, using directed exercises to introduce the tools available (ICrules) for detecting design rule violations.

The schematic can be compared, almost literally wire by wire, and device by device, with the corresponding layout, in a procedure known as LVS (Layout versus Schematic), in order to confirm that the layout is actually an accurate representation of the schematic. This uses the Mentor package ICtrace.

Methods for functional verification of the circuit will also be explored, using available tools (ICextract) for extracting netlists and parametric values (for example, transistor dimensions, parasitic capacitances, etc) from layout.

Semi Custom Design After successfully completing the introductory exercises, participants will design a gated ring oscillator, using a chain of 2-input NOR gates connected as logic inverters.

A compact layout, free from design rule violations and with the highest possible oscillation frequency will be the primary objectives. The final phase of the project involves the use of the semi-custom design tools available with the Mentor Graphics suite to prepare the design to the standard required for fabrication (although it will not be possible to fabricate any designs for this project). This will include floor-planning, automated cell placement and automatic routing, and will result in a layout containing



input and output pads, power supply pads and power frame, and all wiring. A full-colour check plot will be generated for incorporation in the final report.

Measurement of performance Although as already explained it will not possible to fabricate the designs created during this project, it is still important to explore how well the performance of manufactured devices matches that predicted by the numerical simulation techniques used to verify the designs. We shall achieve this by comparing the measured performance of a ring oscillator circuit designed in a previous project and fabricated commercially. A special breadboard will facilitate the provision of power supplies and test waveforms, and we shall use standard laboratory equipment (voltmeter, oscilloscope, counter) to carry out the measurements.

Schedule The schedule of activities outlined on page 1 of this document indicates a natural sequence of operations for this work. There are also a number of paper design exercises that need to be carried out in advance of the corresponding workstation sessions. Apart from this, there is a certain amount of flexibility over the order in which the various activities can be carried out, and it is also possible for groups to vary the amount of time spent on certain parts of the project.

Certain parts of the project make particularly heavy demands on computing resources - in particular, QuickSim II and AccuSim - and it will actually be advantageous for there to be some variety over the class in the activities being pursued at any instant.

In addition, a session of experimental measurement forms a key part of the project, and requires about 2-3 hours. Four sets of equipment will be provided, and all groups are expected to take part. The experiment can be carried out at any time during the second, third or fourth week since it does not depend explicitly on the development of the design, and does not require the use of the workstation, and the measured results are required in the final report only.


D M Holburn May 2007 EN2002.1 8 c7intro.doc

Computer-based project in VLSI Design Getting Started

D M Holburn May 2007 EN2002.2 9 C7start.doc


Computer-Based Project in VLSI Design Co 3/6 Getting Started

This pamphlet provides information on getting started (logging in, setting up to run Mentor Graphics tools and executing Design Manager). It also covers issues such as the Falcon Framework, on which the tools are based, the Acrobat Browser (on-line manual system) and generating printed hard copy of designs.

Logging in

During scheduled sessions, the workstations to be used are Intel Pentium PCs with large TFT monitors (the 12 twnxx CAD workstations at the east end of the DPO). These are set up to run Windows XP. Since Mentor runs on a Unix platform, we shall make use of a Windows-hosted X-emulator package Xwin32 to provide a suitable graphical environment in which to work.

Logging in using the hybrid XP/Unix configuration provided involves three stages:

• Logging in to the Windows XP environment • Starting up the Windows-hosted X environment • Logging in to the Teaching System Special ‘mentorxx’ work spaces have been set up and are dedicated to this project, for use by the pairs of students involved. You access these using your own user IDs.

Logging in to the Windows environment involves the following steps:

• Press Ctrl+Alt+Del to bring up the login dialogue. Use your normal CUED login and password.

• Once this has been completed, you may (optionally) use the desktop icons to start up the Netscape Navigator browser to view the project Web Page (see below for details).

• Select the Xwin32 Mentor icon to start up the X environment, and respond to Teaching System login prompts.

The twnxx workstations will normally be used on one of two servers, in order to distribute the load. To allow this, each of these workstations is provided with a menu similar in form to the diagram below. This menu requires you to select which of the available servers should be used before you login. The actual servers available may differ from the example below. XDMCP Host Menu from twn03 lancaster.eng.cam.ac.uk 6 users; Load 1.1, 2.5, 1.8 nimrod.eng.cam.ac.uk

11 users; Load 2.8, 2.6, 2.3

Cancel Accept



In the first lecture you will be assigned a default server, which you should note. The Mentor Graphics software is automatically available on this server. In normal circumstances, use the menu to select the server to which you have been assigned, then click the Accept button. If the load on the designated server is very high, and expected to remain so, you may wish to consider using an alternative server. Bear in mind that some operations - for example, printing deferred to a later session - need you to be on the same server as before. Also, conditions may change during your login period, particularly if another project session is coming to an end as yours starts.

As mentioned, special mentorxx workspaces have been set up and are dedicated to this project, for use by the pairs of students involved. They are provided for this work only, and should not be used for any other activity. Unlike previous years, you will access these workspaces using your own user ID and password. Either member of the team may login, as files created in these work areas will be readable/writable by both. Please note that your own personal login directories are not shared, and you are expected to maintain normal security measures, such as keeping your personal password private, etc. A Project Worksite (including a bulletin board and other facilities) will be available to allow participants, demonstrators and staff to communicate and exchange information in various ways. You will need to monitor this from time to time, as it will be used to publish information not in the Lab Guides and not easily obtained anywhere else.

Your shared mentorxx workspace is provided with a number of initial design files in the cbt directory and elsewhere. A bin directory is provided, and contains a selection of specially written startup scripts, one entitled mentor. You should normally use this to begin your Mentor Graphics session, using the procedure described below. We strongly recommend you use the fvwm window manager. The Mentor tools make heavy demands on the windowing environment and problems may arise if a different window manager is used. If you are accustomed to using a different manager, it will be necessary to modify your setup for the duration of the project so that fvwm can be run instead. This manager is started by default when you start Mentor using the recommended procedure.

Before you can start Mentor, you must change to the directory tree where your shared designs are kept. The command required is: cd /usersG/ptiivlsi/mentorxx

where xx is the suffix for the workspace you and your partner have been allocated. A dedicated startup script has been provided to carry out necessary housekeeping chores at the start of your session. This sets up important system parameters and initialises menus and other features that assist the Mentor Graphics environment. Other scripts depend on these parameters and will fail if the startup utility is not run. The script is found at the top level in your shared workspace. To invoke this, give the command:

. mentor_start_env, followed by Enter.

Please note the dot followed by a space in the above; these must not be omitted.

Then cd to the directory in which your design work will be accomplished. Normally this will be cbt. It is possible to change directories from within any Mentor Graphics application, but file access problems will be reduced if you adhere to this advice.



Please bear in mind that you are expected to carry out the project during the scheduled periods in the DPO, which is the base for all project resources. Outside scheduled Mentor project times cluster twnxx is liable to be in use for other projects. It will normally be possible, subject to availability of a suitable terminal, to login from other DPO workstations. A slightly different procedure is then required because the server-select menu is available only on twnxx; it is thus necessary to rlogin (remote login) to an appropriate server before the tools can be accessed. Virtually all the HP terminals in the DPO and elsewhere are suitable for this work. A sample set of commands for logging in from elsewhere is given at the end of this document. The demonstrators may be able to advise on the procedure for logging in from other terminals, but note that they will only be available during scheduled sessions.

It is also possible (though it may not be a trivial exercise) to access the Mentor software from a remote (non-CUED) terminal - for example, a networked College PC running a suitable Windows-based X client. Such an arrangement could offer potential for access at times when the DPO may not be accessible. However, note that you are expected to attend the scheduled sessions in the DPO in real and not virtual form! We will give what help we can to those who wish to try remote access, and we will post what information we gather on this topic on the project WorkSite (see below), but there are no guarantees of success.

Starting Mentor Design Manager

The Design Manager application is provided to assist in the administration of designs. Although designs are essentially collections of Unix files and directories, you should never use the standard Unix commands (like cp, mv) to manipulate design files. If you do, you are likely to encounter problems with broken or unresolved references, which may mean the loss of your work. Instead, use the facilities provided in Design Manager for copying or moving designs. Handy methods are also provided within Design Manager for exploring designs and starting other tools (for example, Design Architect, QuickSim II, and ICstation). You will find it useful to keep Design Manager available whenever you are running the Mentor tools, either as a normal sized window, or iconised. The fvwm window manager offers up to nine virtual screens in which you can place running applications and switch at will from one to the other.

A shell script has been provided to automate the procedure for starting Design Manager. Unless you are advised otherwise, give the command: mentor to run it. When the graphics window is presented, use the mouse to resize it to a convenient format. A separate pamphlet (Lab Session 1) is provided to introduce you to the features available in Design Manager, and demonstrators will normally be available to assist in the event of queries.

Acrobat Browser (On-line Manual Facility)

The Mentor Graphics System does not include printed manuals. Instead, a comprehensive on-line manual system is provided, based upon a CD-ROM which should be continuously available to the project. It contains facilities for display of detailed information on a very wide range of Mentor-related topics, many of which are not relevant to this project. In addition it offers powerful search facilities that let you identify all on-line manuals containing a reference of interest. You can start the Acrobat Browser from Design Manager, or from any of the other tools. A separate



pamphlet (Lab Session 1) briefly describes the use of the Acrobat Browser, and an introductory laboratory session demonstrates its use.

There will be demonstrations and screenshots of the tools shown during the accompanying mini-lectures.

Generating hardcopy

Most of the Mentor tools provide facilities for printing out schematics, symbols, layouts and simulation results. You will probably wish to include printouts of this kind in your interim and final reports. Note that most of the tools generate output in the form of Postscript files, and special post-processors are provided where required to prepare these for transmission to the printer. In most cases it is possible to preview output on the screen, and decide at that stage whether or not to commit it to paper. Although it is possible to route copies of Postscript outputs to your own home directory, for easier inclusion in reports, it may not be straightforward to route printouts to other printers - e.g. facilities in College or elsewhere.

Printing procedures have changed considerably since previous years, and there may be further changes during this project. Be sure to monitor the Project WorkSite on the Web for late-breaking news.

The printing facilities available to most of the Mentor tools are listed below. Note that these are not the standard CUED printers.

Mentor Name Characteristics

mgcps_a4 This produces monochrome output formatted for A4 paper. mgcpsa4_colour A4-size high quality Colour Laser Printer (DPO)

Note that the colour printing facility will be made available through the computer operators for the closing stages of the project only, involving the design of mask layouts, and this year (2007) a non-standard procedure is needed. Please do not attempt to create colour plots before you have been advised that the facility is available.

Some general instructions about preparing to print from Mentor applications are given in Lab Guides 2, 3 and 4, which describe the use of Design Architect for entry of your designs. You will need to carry out these instructions prior to printing each time you login, and for each new application you start up. Slightly modified procedures are called for with ModelSim, and with ICgraph (the IC layout tool); these are described in the corresponding Lab Guides - Lab Guide 2 - Functional Simulation with ModelSim, and Lab Guide 8 - Semi Custom Design.

With Mentor applications, printed output is passed through a number of special filters and placed in a temporary file ready for transmission to the printer. A script utility mgcplot is provided which lists the Postscript files corresponding to any Mentor printed output you may have created, and asks you to select one. Mgcplot then allows you to select a suitable output device from a list, which includes a screen Print Preview facility using the program ghostview. Note: temporary files are held on the server on which your Mentor application was run. If you wish to print output that was created in an earlier session, you must run mgcplot on that same server.



You are recommended to make use of mgcplot to check that printed output is correctly formatted before committing it to paper. This is especially important for colour plots which are costly to produce. Note that mgcplot must be run from a separate xterm shell. The easiest way to achieve this is to click with the right mouse-button with the cursor over the stippled desktop, then select the Mgcplot item.

We expect the following output devices will initially be available via mgcplot:

Preview to screen (using ghostview) DPO Laserjet printer (normally ljmr1 or ljmr2)

Other print devices may possibly be listed, but you should not attempt to use them unless a demonstrator advises you to do so. Output to the DPO Laserjet printers will be gathered by the operators and placed on shelves for collection in the normal way. Note: The newly introduced printer charging procedures are likely to have some impact on the minor details of obtaining printed output, but this should not affect the way you generate hardcopy from within Mentor applications. If you have any difficulties arising from printing and the need to generate hardcopy output, please consult one of the demonstrators; they may refer you to the Computer Operators.

Exiting from Mentor Applications and logging out

When you finish using any Mentor application, you should exit from it, in order to avoid its presence slowing down the system for others and for yourself as you run other applications. It is especially important to close down the Mentor Graphics system in an orderly way when you logout, for similar reasons. Of course, it is possible to minimise a tool while you temporarily work with a different one, then return to the original application. You may find this style of operation very useful.

Most of the Mentor tools now provide a convenient way of exiting, via the MGC > Exit command. (There are one or two exceptions). The recommended way to leave a tool is to close down all its design child windows (first saving any important data) by double-clicking the Select (left) mouse button on their system icon (top left). To quit the tool completely, use the Exit command provided in the MGC menu. If this is not available, use the Exit option under the window's system icon (top left). Important note: you will also need to quit the transcript window, a text-based window normally lying behind almost every tool's graphic window. You should close down all other Mentor applications before you close down Design Manager.

Warning: If you do not exit from tools in the approved way, you are liable to leave behind a collection of unwanted processes which will ultimately slow down the system. If you think this has happened, consult a demonstrator for advice on how to proceed.

Once you have exited from all Mentor and other applications and closed all shell windows, you will be left with a blank Xwin32 login screen. Close the Xwin32 application on the PC by clicking the X button at top right.

Finally, log out from the Window XP session by selecting:

Start > Shut Down … > Close all applications and log in as another user.



Project Worksite and Electronic Mail

This year a dedicated Project Worksite hosted locally by CARET has been developed to support this project. This is accessible at any time and from any workstation or networked PC with a suitable browser. It is open to all participants, demonstrators and staff, and offers a convenient way of sharing information among participants. It offers a Wiki, available to all, so that if you wish to document a particular feature not otherwise covered, you are welcome. There are discussions boards and live chat facilities, as well as a handy calendar and schedule. We will appreciate feedback o the effectiveness of these tools, and any suggestions you may have to enhance their usefulness.

Information will also be posted here in the form of advice on the following topics:

• First Interim Report • Second Interim Report • Experiment on Electrical Testing of the Ring Oscillator • Accessing Mentor from outside CUED • Hints and Tips

The extent of the information provided is expected to grow as the project progresses.

We recommend you start up the Netscape Navigator application on the workstation under Windows XP; that is, before logging in to the Teaching System. This is because some browsers on the Teaching System interact adversely with some of the Mentor tools. Please note that you are welcome to access the WorkSite from your own account at any time and from anywhere you have web access. The URL is as follows:

WorkSite: http://camtools.caret.cam.ac.uk/portal

While engaged in the project, you should get into the habit of checking the WorkSite on a regular basis, since these modes of communication will be used for speedy distribution of information e.g. reminders about deadlines, minor amendments to the lab sheets, etc. You can also send electronic mail while logged in on your mentorxx account. This may be useful if you wish to email a query or problem report to a demonstrator and wish to include text cut from one of the Mentor windows. If a problem arises when you are working outside scheduled project hours, you are welcome to email to [email protected]. Mail sent to this address is forwarded to all the demonstrators. We cannot guarantee turn-around on solutions for problems reported in this way, but we will do our best.

Scripts to assist with startup

Users who wish to minimise the amount of typing at startup may wish to experiment with the following template. If you are not familiar with the terms and commands described below, you are recommended not to waste time with this.

It is assumed that your execution path ($PATH) includes your ~/bin directory, and that on login, no window manager is started up. Use your favourite text editor to create a file (e.g., my_mentor) in your ~/bin directory, with contents as below: #!/usr/bin/sh cd /usersG/ptiivlsi/mentorxx . mentor_start_env



You will have to change the suffix xx to match the workspace ID you were allocated. Set the access permissions to make the file executable, using for example:

chmod 700 my_mentor When you login, give the command . my_mentor This should place you in your shared workspace with your Mentor environment set up ready for you to start up with the mentor command.

Suggested commands for logging in from other workstations (DPO)

The following assumes you propose to log in to your Part IIA Mentor account mentor6 via workstation tw212 in the DPO. If your Mentor account or the workstation from which you log in are different, change the corresponding items in the dialogue below accordingly.

Login in the normal way to tw212 using your normal user ID and password. The window manager should start up and an xterm window should appear.

In the xterm window give the command:

xon tw300 or xon tw600 (according to the server required)

You may be required to give your password.

Change to your allocated mentorxx workspace, then start up:

cd /usersG/ptiivlsi/mentorxx (replace xx with allocated suffix) . mentor_start_env

To initiate Design Manager use the special mentor startup script.

mentor

Work as normal, ignoring the first (login) window until you actually want to log out.

Please note that the steps necessary to log in from other sites may differ from those above. There are additional scripts that might be preferable according to the exact specification of the terminal from which you log in. You will find additional information about logging in from remote sites on the Project WorkSite.



Computer-based project in VLSI Design Logic gates in CMOS

D M Holburn Apr 2007 EN2002 17 C6cmos.doc


Design of logic gates in CMOS

This pamphlet gives a simple introduction to the principles of operation of CMOS logic gates, and attempts to point out some of the performance trade-offs that have to be addressed in their design. It also introduces the ring oscillator, which forms the heart of the design element of this project. The CMOS inverter

The CMOS inverter or NOT gate is the simplest of the many boolean function that can be implemented using MOS transistors, but it serves to establish the fundamental principles which are common to all types. Our aim is to represent the logical values 1 and 0 by some electrical quantity and devise circuits that will allow us to manipulate these in the same way that boolean functions transform the logical values. It is conventional to represent logic 1 with a high voltage, and logic 0 with a low voltage. Over some forty years of evolution of transistorised logic, the industry has settled on standard values of 5 volts and 0 volts for this purpose. But there is nothing particularly magical about these values, and indeed, within the last few years there has been a progressive shift to lower voltages: 3.3 V, 3 V, 1.8 V …

In CMOS we use enhancement mode MOS (metal-oxide-silicon) FETs. These devices have no conductive channel (i.e. they are OFF) until the gate-source potential exceeds a specific value, the threshold voltage VT. When the channel is fully formed, the device is said to be ON. The table below summarises the dependence of these devices on the gate-source voltage Vgs. The threshold voltages given are typical.

Type VT Vgs = 0 Vgs = 5 Vgs = −5

n-type +1v OFF ON OFF

p-type −1v OFF OFF ON The availability of complementary devices - that is, p-type and n-type - is one of the distinctive features of this technology. It is important to remember that the current equations for the p-type device involve inequalities of the opposite sign to those for the n-type device. In the n-type device, conduction occurs when p-type majority carriers are repelled from the vicinity of the channel, requiring that the gate be positive with respect to the source in order to switch the device ON. In the conductive p-type device, n-type carriers are repelled, requiring that the gate be negative relative to the source to turn the device ON. Thus a p-type device is turned OFF by a high gate voltage which turns an n-type device ON, and the converse holds for a low gate voltage. This complementary operation is of course the key to CMOS circuit design.



A simple model The static characteristics of the CMOS inverter have been covered in Part IA and in third-year courses, and their derivation will not be repeated here. The theory of the devices themselves, and the approaches to fabrication required to make them work as fast as possible have already been covered in a Part IB Elective course, which many of you will have attended. In this project we shall use industry-standard simulation tools to model the behaviour of the devices and the circuits in which they operate. However, in order to be able to have an understanding of the results we observe, we shall develop a very simple approximate model for the conductance G of the MOS transistor channel, from which we can deduce many aspects of logic gate performance. Consider the simple rectangular MOS transistor channel of length and width L and W respectively, shown in Fig. 8 below. Suppose the mobility of carriers within the material is µ.

L

Source Drain W

V=0 V=Vds

Figure 8 – Model MOS transistor channel

Assume that the gate voltage Vg = Vdd, so that the device is conductive.

Let the charge density in the shaded element near the source be Q per unit length.

Then Q = Cox V W where V is the excess voltage on the gate, and is given by V = Vdd − VT. If VT is much smaller than Vdd, we can approximate this: Q = Cox Vdd W The current in the channel, I is given by: I = µ Q E If we may assume that E is invariant along the device, we can write: I ≈ µ Q Vds / L = µ Cox Vds Vdd W/L Hence the conductance G = I/Vds is given by: G = µCox Vdd W/L .



The result just obtained can be interpreted as follows. The channel conductance G (with the gate potential above threshold) is proportional to the factor µCox , often referred to as the process gain factor, and denoted by K. This is determined by material and manufacturing considerations, and is not under the direct control of the circuit designer. G is also proportional to the supply voltage Vdd , within the limits of the approximation, and - most importantly from the perspective of the designer - to a purely geometric factor W/L, often known as the aspect ratio of the MOS transistor. Layout and performance of logic gates We shall now use the simple result deduced above to predict some of the characteristics of the logic inverter, and shall then explore how this treatment can be extended to more complicated gates. The circuit schematic and layout of a CMOS inverter are shown in Figure 9 below.

Figure 9 – The CMOS inverter



The transistor channel is formed by the superposition of the polysilicon gate electrode over the thin gate oxide which is grown on the surface of the lightly doped semiconductor itself. The source and drain are formed from highly doped p- or n-type material created using ion implantation.

It can be seen that the channel width W is determined by the width of the thin oxide region (that is, the distance it extends into the plane of the paper), while the channel length L is actually defined by the width of the stripe of polysilicon which extends across the channel. Both these quantities are directly under the control of the designer, and are in fact the primary means by which the designer determines the performance of each element of the system.

A logic circuit may be characterised by three key parameters:

• Physical size • Power consumption • Speed of operation

An ideal circuit will have minimum size, fastest speed and the lowest power demand. It turns out, however, that it is not possible to optimise all characteristics simultaneously, and the designer must weigh his requirements characteristics and balance the competing constraints to suit the application.

Physical size

This is proportional to the product of W and L. Minimising the values of W and L clearly give the smallest size. However, this approach is limited by the ability of the manufacturing process to produce reliable devices at the smallest dimensions. Like any manufacturing process, it is subject to tolerances which set a lower limit to the size that can be achieved. For example, the current minimum channel length presently available from commercial fabrication facilities is about 0.4 - 0.8 µm (though many designs require greater channel lengths). The designer is thus constrained by a set of rules (Design Rules) which govern the dimensions of the various structures he specifies.

Speed

When the input to the inverter switches between 0 and 1 or vice versa, the output terminal is expected to change state correspondingly. The metal and semiconductor elements connected to the output all possess capacitance to the substrate (and to all other conductors, to be pedantic). We shall regard these separate contributions as a single lumped capacitance C connected between the output and ground. This capacitance must be charged and discharged through the conductive channel of one or other transistor: the discharge to 0V via the n-type channel, and the charge-up to Vdd via the p-type channel. Although there are other factors that determine the delay experienced by a signal in travelling between the input of a logic gate and its output, under most circumstances it is the processes just outlined that dominate. It is possible to develop accurate equations relating the drain current to gate and drain potentials. These can be integrated to determine how long the charge or discharge processes take. However, in the interests of simplicity we shall regard the system as a set of switched conductances which control the charge/discharge dynamics, and we shall assume that



the conductances are constant, and defined by the simple conductance model given earlier.

Using classical RC network theory, we can now write down expressions for the delay for rising and falling edges at the output terminal. We may also assume that the gate potential changes abruptly, so that the channels also change state abruptly between conductive and non-conductive. A convenient pair of expressions, which are well borne out by experiment, are as follows:

Delay time for rising edge ≈ 3 C / Gp Delay time for falling edge ≈ 3 C / Gn

As expected, the smaller the value of C, the shorter the delays and the faster the circuit. Considering the expressions for G, it is clear that the higher the supply voltage Vdd, the more rapidly it will switch.

From the IC designer's point of view, the larger the value of W, the higher the conductance and hence also the faster the circuit. There is a subtlety here which we must not overlook. The capacitance C is to some extent dependent on the values of L and W, since the gate itself and the depletion regions forming the drains of the transistors may make a sizable contribution to the total parasitic capacitance at the output terminal. Increasing W may not necessarily produce the speedup that the simple expression suggests.

There is yet a further complication. Although the values of Vdd and Cox are usually the same for both n- and p-type transistors, the mobility µ differs significantly between the types. Typically, the ratio µn / µp may be two or more. This means that for given values of W and L, the conductances of n- and p-channel devices will be different by the same factor. An inverter using identically-sized transistors would therefore have different delays for rising and falling edges. In real logic circuits, asymmetric delays of this kind are a disadvantage, and measures must be taken to equalise them. For the inverter this is easily achieved by adjusting the ratio W/L for each device such that µW/L is constant. To keep the devices compact, we may use the minimum permissible value of L, and scale W. This results in the value of W for the p-channel being greater than that for the n-channel device by a factor µn / µp . Power

Power is the rate of consumption of energy. One of the great virtues of the CMOS inverter, is that provided the input terminal is held either at logic 0 or logic 1, only one transistor is conductive, the other being non-conductive. As a result there is never under these circumstances a direct pathway for current to flow from Vdd to ground. This means in its turn that the power consumed is negligible. These considerations have led to the use the use of CMOS in many applications where lower power operation is essential.

This convenient model for power dissipation in CMOS is in fact too simple. Charge does actually flow from Vdd to ground every time the output terminal switches from logic 1 to logic 0. While the output terminal is high, the parasitic capacitance charges up to a potential Vdd, and holds a charge C Vdd . When the output terminal changes state, this charge is conducted to ground through the n-channel transistor. A fixed packet of charge C Vdd is thus transferred from power supply to ground each time the input of the gate changes state from 1 to 0 and back again. If the gate is driven by a



periodic waveform of frequency f, we can identify a flow of current from Vdd to ground, via the parasitic capacitance, whose average value Iav is given by:

Iav = f C Vdd

Hence the average power consumption by this single gate is VIav , or f C V 2. We can apply this kind of reasoning to entire CMOS integrated circuits, provided we know the parasitic capacitances associated with each gate output. Estimating the frequency of operation of every individual gate may be rather more difficult. As a first approximation it may be satisfactory to assume that each gate is driven at some fraction (say, about one half) of the externally-supplied clock signal connected to the circuit, on the basis that gates will be clocked at frequencies ranging from DC right up to the clock frequency, and in roughly equal quantities. Where more information is available about signal frequencies, a more accurate dissipation figure can be determined.

This form of dynamic loss is the principal mechanism by which dissipation of power occurs in CMOS. At sufficiently high frequencies, the amount of heat produced can be enough to require special measures to disperse it (the Pentium and DEC Alpha chip are well known illustrations, and dissipate several watts because they run at 100MHz+). This is a further reason to try and minimise the parasitic capacitances. Note that the power dissipation is also proportional to V 2. Hence increasing Vdd in an attempt to improve switching speed has the disadvantage of significantly increasing the dynamic power dissipation. Many new, high speed devices are designed to run at 3 V or even less for this very reason.

More complicated gates

The arguments just developed for the CMOS inverter can be extended to other more complicated combinational gates. Any arbitrary combinational gate in CMOS can be expressed as a pull-up network (consisting of p-channel MOS transistors, and connected to Vdd) and a pull-down network (consisting of n-channel transistors, and connected to ground), as in the diagram below.

Figure 10 – More complex gates



In CMOS each input signal controls a device in the pull-up network and another in the pull-down network. The networks are designed in such a way that either the pull-up network connects the output to Vdd, or the pull-down connects the output terminal to ground. The networks must never be simultaneously conductive.

For example, the transistor schematic for a two-input NAND gate is also shown in the diagram, comprising two n-channel transistors in series (pull-down) and two p-channel transistors in parallel (pull-up).

Let us consider now the issue of delay in more complicated gates. Firstly, the existence of additional MOS transistors connected to the output terminal increases the parasitic capacitance observed there. This is an inescapable fact. Secondly, we see that our simple model for charge/discharge of this capacitance through a single p-type or n-type device has to be extended. In the NAND gate, the discharge takes place through two n-type devices Q3 and Q4 in series. Of course, both devices must be conductive to allow this to take place. However, the charging current may flow through Q1, Q2, or Q1 and Q2, since these devices are parallel-connected. We need to reconsider how to determine the overall conductance of the pull-up and pull-down networks when these may consist of arbitrarily complicated groupings of transistors in series/parallel. A reasonable way of calculating effective conductances for series-connected devices is to use Ohm's Law. Since the 'resistance' of a transistor is 1/G and is therefore proportional to L/W, we can argue that for a string of n series-connected transistors:

effective n

LW

LW

LW

= + +1

...

This is actually not such a good approximation as one might expect, because it fails to take account of the observed non-linear nature of channel conductance, which is dependent on the source and drain voltages as well as on the gate potential. In other words, the conductance of each of two (physically identical) transistors with identical gate voltages, connected in series, may not be identical, since they are quite likely to have different source and drain voltages. This is a fairly fundamental limitation of our simple conductance model. However, we shall ignore this problem for now, as to do otherwise would tend to obscure the important fundamental principles we wish to emphasise.

With parallel-connected transistors, we have observed that the conduction may take place through one or more devices, according to the state of the inputs. When estimating the delay times for a gate, it is normal to use worst-case assumptions. These may then be used to determine worst-case figures for the delay through an entire system, a conservative approach to design. Hence the effective conductance for a parallel set of devices may reasonably be taken as the conductance of just one of those devices, representing the worst case.

Applying this rationale to the 2-input NAND gate, we see that the worst-case pull-up conductance is given by:

p oxC ddV pW pLµ

with only one p-channel device conducting, while the pull-down conductance is:



0 5. n oxC ddV nW nLµ

since two n-channel devices are in series. In order to equalise the worst-case rising and falling delays, we must set these equal. It follows from this that:

pW pL np

nW nL= 0 5.µµ

A further issue which we shall mention but not develop fully, is how we might attempt to normalise the rising and falling delays of gates with multiple inputs to those of the inverter. There may be worthwhile advantages in a family of logic gates with roughly uniform delay, and it is apparent that we can at least improve the situation by choosing nW nL for multi-input gates so that the worst-case

conductance in the pull-down network is similar in magnitude to that for the inverter. This in its turn affects the aspect ratio chosen for the p-channel devices.

We should note that selecting the transistor dimensions in this way cannot in general match rising and falling delay times for every possible input transition. For the 2-input NAND, the delay for a rising input will be a factor of two faster than the worst case if both inputs are switched simultaneously from logic 1 to logic 0 rather than just one.



The Ring Oscillator

The ring oscillator is at least conceptually one of the simplest forms of oscillating circuit. It has a number of technical limitations that render it less than ideal for general-purpose oscillatory circuits, but it has some fascinating features which are of great value to the integrated circuit design engineer.

An ideal ring oscillator consists of a homogeneous chain of identical inverting gates connected in cascade - that is, with the output of each stage connected to the input of the next. The output of the final gate is connected back to the input of the first, giving a closed ring-like structure. See the diagram below.

Figure 12 – Ring oscillator: the simple implementation Note that the circuit shows an odd total number of gates. The simplest way to understand how such an oscillator works is to imagine that any convenient point - say, the input to gate number 1 - attains the value logic 0 at time 0. Since each gate inverts, the output from gate 1 will become logic 1 a short time after (dependent on the delay imposed on the signal as it passes through gate 1. The output from gate 2 will become logic 0 a further gate delay later, and so on. It is possible to visualise a transition (logic 1 to logic 0) racing around the ring, being inverted and delayed as it progresses. When the transition reaches the output from the nth gate (that is, the input to gate 1), it has undergone an odd number of inversions, and therefore is of the opposite polarity, i.e. logic 0 to logic 1, and arrives at time t1 determined by the delay through n gates. The inverted transition races around the ring and reaches the starting point after a further delay t2, and is now of the same polarity as the initial transition. It is clear that so long as the signals assume regular logic levels, the circuit has no stable state, and will continue to oscillate.

To determine the oscillation period, it is necessary to know the delay through each stage. From above we see that during a complete cycle of oscillation a transition must travel round the ring two complete times. If all stages have identical delay τ both for rising and falling edges, it follows that the period of oscillation is 2nτ. Hence the frequency of oscillation is:

f = 1 / 2nτ



Since there is such a close link between τ and the frequency of oscillation, the ring oscillator has considerable value in the design of integrated circuits. It provides a convenient way in which the delay of a simple gate can be measured to a high degree of accuracy with comparatively simple instrumentation. This information is vital in order to provide a check on the fabrication process, and also to determine proper numerical models for the devices. The highest speed gates currently available have delays of a few tens of picoseconds. To measure this kind of delay directly is extremely difficult. Moreover, even if instrumention were available with a suitable response, the capacitive load it would impose on the gate under test would grossly distort the measurement.

The solution is to build a ring oscillator comprising a suitably large number of identical gates. With the ring oscillating, the period of oscillation may be measured and the expression above used to determine the individual gate delay. Any combinational gate capable of performing an inversion may be used in place of the inverter shown. Hence this technique can be applied to NAND, NOR or even XOR and XNOR gates to measure their performance. Virtually all integrated circuits nowadays have a small area set aside for a parametric 'drop-in' - manufacturers' jargon for a small piece of circuitry - typically including a ring oscillator - inserted specifically to allow verification that the processing has complied with expectations. Examples - solutions should be included in your First Interim Report 1. Referring to the section above: Design of Logic Gates in CMOS, show how to

draw the pull-up and pull-down networks in such a way as to produce CMOS gates which perform following logic functions

(a) Y A.(B + C + D)=

(b) Y A + (B.C.D)=

2. How must the transistors be dimensioned to achieve equal worst-case delays for rising and falling edges with the gates (a) and (b) considered above. Assume that µn / µp is 2.5, and that minimum allowed values for L and W are 2µm and 4µm respectively.

3. Comment on the ring oscillator method for determining the delay through a gate. What, if any, are the advantages and disadvantages of this approach to delay measurement compared with a more direct technique?

4. Determine the frequency of oscillation of a ring oscillator if each of the gates used has delay τr for rising edges and τf for falling edges.

5. How might you vary the frequency of a ring oscillator? Hint: consider the simple expressions for delay and transistor conductance developed earlier in this sheet.

6. Is it possible for a ring oscillator to oscillate at any other basic frequency than that given by the expression: f = 1 / 2nτ ? Explain your reasoning.

7. Should it be possible for a ring oscillator with an even number of gates oscillate? Under what limited conditions might oscillation be detectable?



A practical ring oscillator circuit

The simple ring oscillator circuit outlined above well illustrates the principles of operation, but it is not a particularly practical arrangement. For convenience, we shall wish to have some way of switching on or off the train of oscillations, and we shall require more than one output so we can observe the phase relationships between them. To achieve this we require at least one gate to have a second input (i.e. NAND or NOR) so that an external signal can be applied, as in the improved circuit below.

Figure 13 – Ring oscillator: a more practical design To maintain homogeneity in the ring, and for convenience, we shall use 2-input NOR gates for every stage of the ring; where only a single input is required, we shall simply wire together the two inputs A and B, giving the functionality of an inverter. A library part - NOR2 - will be used in the first instance to provide us with a feel for the way the circuit behaves, but in the final design we shall create a mask layout to implement our own version of the 2 input NOR gate, and investigate how its performance compares with that of Mietec's design.

The required specification for the ring oscillator part of the design is provided in the following section.



Computer-based project in VLSI Design Design Specification

D M Holburn May 2007 EN2002.2 29 C6ring.doc

Computer-Based Project in VLSI Design Co 3/6 Design Specification

As outlined in an earlier section, the target design is a complete digital system-on-a-chip for a frequency synthesiser. A fuller explanation of frequency synthesis methods is given later, and there may be opportunities for some designers to incorporate more elaborate features, provided the basic operating principles have been understood. The basic design contains the following elements:

• A single 2-input NOR gate is provided for introductory experiments. • A ring oscillator module, which provides a master clock. • A counter module. This element comprises a binary counter which counts clock

pulses input via the clock terminal. A basic design requires a 6-bit counter. • A comparator module, which compares the outputs of the counter with a pre-

programmed number, applied by means of a set of input pins on the chip, and generates an output when these match.

• Additional logic to respond to the comparator’s output and reset the counter; a further element is included so the output waveform is symmetric.

There is considerable scope for individual creativity within the above specification, but each element is dealt with in more detail below. You can read about the architecture of frequency synthesisers later in this chapter.

The first stage of development involves creating a representation of the entire system using a hardware description language (HDL) to explore and verify its operation. Figure 1 presents a block diagram showing the organisation of the main elements.

Figure 1 Block Diagram of complete top_level system-on-a-chip

Ring oscillator

Counter

Comparator

Control



Ring Oscillator

A key element of this project is the ring oscillator, ring_oscillator, whose development is intended to highlight all the various activities involved in integrated circuit design. During the project you will construct a definition in a hardware description language for it. You will develop a schematic representation of its constituent gates and a graphical symbol; you will have a chance to predict its performance using digital and analogue simulation techniques. You will design and verify the mask layout for the 2 input NOR gate used in its construction, and finally, you will use the ring_oscillator module as a signal source in a programmable divider design which includes counters and other sequential logic devices.

The following section describes the specification to which we shall work for the ring_oscillator part of the design. Ring Oscillator Specification

The simple theory of the ring oscillator is given in the Design of Logic Gates in CMOS pamphlet, and the relation between gate delay and oscillation frequency is derived. The initial design for ring_oscillator will use the NOR2 part whose detailed specification is provided by Mietec; the salient details are given overleaf. We shall aim to produce a ring oscillator with a single Enable input ENB, and two outputs OUT1 and OUT2 taken direct from the ring_oscillator module, with a stated oscillation frequency and phase difference between them. In order to specify the basic characteristics of the ring oscillator portion of the design, we shall use the criteria detailed opposite.

A single instance of the NOR2 gate is also shown in the block diagram in Figure 1. This gate is entirely separate from the ring oscillator and all other parts of the design. It is included to provide a straightforward means of introducing some of the major concepts related to schematic design and simulation.

Later on we shall develop our own NOR2 gate at the most detailed level possible, using individual MOS transistors. The result will be a gate which is broadly similar to the Mietec part, but whose delay characteristics will likely be quite different. With a little reflection and research, and with not too much effort you should be able to design a part which works significantly faster than the original library part, and you should be able to identify ways of making the design more compact (and hence cheaper).



Ring Oscillator Specification Worst-case operating frequency ~6 MHz, based on Mietec NOR2 part with Vdd = 5 volts and nominal loading capacitances (see overleaf for specification). Input ENB = 1 Oscillator disabled Input ENB = 0 Oscillator enabled Typical input/output waveforms

Figure 2 Input and output waveforms

Worst-case timing specifications (see waveforms)

Parameter Description Lower limit (ns)

Upper limit (ns)

T Oscillation period 145 185

t1 Delay from ENB to OUT1 17 21

t2 Delay from OUT1 to OUT2 40 60



Figure 3a – Mietec NOR2 gate characteristics



Figure 3b – Mietec NOR2 gate characteristics

ELECTRICAL CHARACTERISTICS CAPACITANCES

INPUT CAPACITANCE UNIT

A,B 0.104 pF

TYPICAL PROPAGATION DELAYS

(T = 27° Celsius, Vdd = 5V, Cload = 0.2 pF)

OUTPUT INTRINSIC DELAY

UNIT

A,B to Y Rising

Falling

2.7

2.8

nS

nS



Digital sub-systems

In addition to the ring oscillator core, we shall design and explore various additional digital sub-systems. The theme chosen for this year’s project is a frequency synthesiser, a key building block in communications systems and other applications. Design of an entire frequency synthesiser is beyond the scope of a short project like this, unfortunately, so we shall confine ourselves to developing the digital parts only.

As for the ring oscillator, we shall initially investigate and verify the design using HDL. We shall then consider its implementation. Unlike the ring oscillator, which we shall design and model at the most detailed level possible (creating it from individual MOS transistors), the frequency synthesiser design will wherever possible take advantage of pre-defined library components. These will include:

• A digital counter constructed from components taken from the Mietec library (combinational gates and D-type bistables). The counter’s Clock input may be driven by one of the ring oscillator outputs, and the outputs are used to supply clock waveforms needed in other parts of the design. This will emphasise the value of the hierarchical approach to design.

• A programmable divider, which will be developed to fulfil the requirements for the frequency synthesiser case study being targeted in this project. There is a degree of individual choice available in the specification of this part. The programmable divider can itself be divided into two parts: a counter, and a comparator to allow detection of when the counter enters a pre-programmed state. Additional counters will also be needed to meet the specification.

• The ring oscillator already described fulfils the role of a variable voltage-controlled oscillator (VCO). Other elements not being designed here include:

• a phase-sensitive detector (PSD) In most frequency synthesisers, this is a

critically designed analogue multiplier whose detailed design alone would take more time than available for the entire project! It is possible to implement a PSD using an XOR gate, however, and groups making good progress and wishing to push the limits are free to experiment with this idea.

• a master oscillator. Such a device is normally implemented using an off-chip circuit including a high-stability quartz crystal, typically operating at 1MHz or some other convenient frequency. Where necessary, we will be able to use simulated signals for this purpose.

• a low pass filter – another critical element normally calling for off-chip components, and an elaborate and time-consuming design procedure.



Frequency synthesisers A frequency synthesiser is an electronic system for generating any of a range of frequencies from a single fixed-frequency timebase or oscillator. They are found in many modern communications devices, including radio receivers, mobile telephones, Bluetooth accessories, radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS systems, etc. A typical application is illustrated in Fig. 4 below, where it is seen that a frequency synthesiser is used as a Local Oscillator in a two-way radio system, providing channel selection by digital control. However, the list of possible applications extends far beyond communications.

Figure 4 A communications application for a frequency

synthesiser

Evolution Prior to widespread use of synthesisers, radio and television receivers relied on manual tuning of a local oscillator, usually by means of a variable capacitor. The availability of varactor diodes, in which a reverse biased p-n junction exhibits a capacitance dependent upon the applied bias, made it possible to miniaturise such systems. However, variations in temperature and aging of components caused frequency drift. Automatic frequency control (AFC) solved some of the drift problem, but manual retuning was stilll often necessary. Since transmitter frequencies are well known and very stable, an accurate means of generating fixed, stable frequencies in the receiver was desirable to solve the problem.

A simple and effective solutions employs the use of many stable resonators or oscillators for each tuning frequency. Quartz crystals offer good stability and have often been used for this purpose. However, this approach is practical when only a handful of frequencies are required. It quickly becomes costly and impractical in applications where many frequency channels are required. For example, the FM radio band in many countries supports 100 individual frequencies from about 88 MHz to 108 MHz. Cable television can support even more frequencies or channels over a much wider band. A large number of crystals increases cost and requires more space.

Many coherent and incoherent techniques have been devised over the years. Some approaches include phase locked loops, double mix, triple mix, harmonic, double mix divide, and direct digital synthesis (DDS). The choice of approach depends on a



number of factors, including cost, complexity, frequency-step size, switching rate, phase noise, and permissible spurious output levels.

Coherent techniques generate frequencies derived from a single, stable master oscillator. In most applications, the use of a crystal oscillator is widespread, but other forms of resonator and frequency source can be used. Incoherent techniques derive frequencies from a set of several stable oscillators, typically through frequency multiplication, division, and summing/differencing (mixing). The vast majority of synthesizers in commercial applications use coherent techniques because they offer much greater flexibility and can readily be implemented as integrated circuits to give a compact, low-cost solution.

Synthesisers used in commercial radio receivers are almost invariably based on phase-locked loops or PLLs. Many types of frequency synthesiser are available as integrated circuits, reducing cost and size. High end receivers and electronic test equipment use more sophisticated techniques still, often in combination.

Principle of PLL synthesisers The block diagram in Fig. 5 below shows the basic elements and arrangement of a PLL-based frequency synthesiser.

A phase-locked loop does for frequency what the Automatic Gain Control does for stabilisation of voltage or power output in a radio receiver. It compares the frequencies of two signals and produces an error signal which is proportional to the difference between the input frequencies. The error signal is used to drive a voltage-controlled oscillator (VCO) which generates the required output frequency. The output signal is fed through a frequency divider where it is divided down in a known ratio, and fed as one input (the comparison frequency) to a phase-comparator, which compares the phase of the divided signal with the fixed comparison frequency from the master oscillator. The phase-comparator output, in effect an error signal, is passed through a carefully designed low-pass filter, and fed back to the input of the system to control the operating frequency of the VCO. This arrangement constitutes a negative feedback loop. If the output frequency drifts, the error signal will increase, driving the frequency in the opposite direction so as to reduce the error.

Figure 5 Classic phase-locked-loop (PLL) frequency synthesiser



Thus the output becomes locked to the frequency at the other input. This input is derived from a crystal oscillator or similar, which is very stable in frequency, and referred to as the reference frequency. Phase-locked loops have many applications both in communications and other branches of electronics; for example:

• Frequency synthesisers for digitally-tuned radio receivers and transmitters • Demodulation of both FM and AM signals • Recovery of small signals that otherwise would be lost in noise (lock-in amplifier) • Recovery of clock timing information from a data stream such as from a disk drive • Clock multipliers in microprocessors that allow internal processor elements to run

faster than external connections, while maintaining precise timing relationships • DTMF decoders, modems, and other tone decoders, for remote control and

telecommunications

The key to the ability of a frequency synthesiser to generate multiple frequencies is the divider (÷N) placed between the output and the phase comparator, as shown in the simplified sketch below. This usually takes the form of a digital counter, with the VCO output signal acting as a clock. The counter is preset to some initial count value, and counts down at each cycle of the clock signal. When it reaches zero, the counter output changes state and the count value is reloaded. Figure 5 below illustrates the waveforms expected in a simplified design with the single divider N set to divide by 4.

Figure 5 Waveforms with N set to ÷4

This circuit is straightforward to implement using bistable devices (e.g. J-K or D-type flip-flops), and because it is digital in nature, is very easy to interface to other digital components or a microprocessor. This allows the frequency generated by the synthesiser to be easily controlled by a digital system.

Example Suppose the reference signal is fixed at 1 MHz, and the fixed divider R is set to divide by 10; its output frequency is thus 100 kHz. Assume also that the divider N can be preset to any value between 1 and 100. The error signal produced by the comparator will only be zero when the output of the divider is also 100 kHz. For this to be the case, the VCO must run at a frequency which is 100 kHz × the divider count value, N, or RNfr × . Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count of 2, 1 MHz for a count of 10 and so on. Note that only whole multiples of the comparison frequency (which is the divided reference frequency) can be obtained.

Practical considerations In practice this type of frequency synthesiser cannot operate over a very wide range of frequencies, because practical comparators have a relatively limited bandwidth and



may also suffer from aliasing problems. This would lead to false locking situations, or an inability to lock at all. Furthermore, it is hard to make a high frequency VCO that operates over a very wide range. However, in most systems where a synthesiser is used, we do not seek a huge range, but rather a finite number of channels over some defined range, such as a number of radio channels in a specific band.

Many radio applications require frequencies higher than can be directly input to the digital counter N. To overcome this, the entire counter could be contructed using very high-speed logic such as Emitter-Coupled Logic (ECL), or more commonly, using a fast initial division stage called a prescaler which reduces the frequency to a manageable level. Since the prescaler is part of the overall division ratio, a fixed prescaler can cause problems designing a system with narrow channel spacings which are often essential in radio communication or broadcast applications. This difficulty can be overcome using a dual-modulus prescaler, discussed below.

Further practical aspects concern the amount of time taken for the system to switch from channel to channel, the time to achieve lock when first switched on, and how much noise – random fluctuations in the amplitude, frequency or phase - there is in the output. All of these are a function of the loop filter of the system, which is a low-pass filter placed between the output of the frequency comparator and the input of the VCO. Typically, the output of a frequency comparator is in the form of short error pulses, but the input to the VCO must be a smooth, noise-free DC voltage. Any noise on this signal naturally causes unwanted frequency modulation of the VCO. Heavy filtering will reduce this effect, but will lead to a VCO which is unacceptably slow to respond to changes, causing drift and slow response time ; on the other hand, insufficient filtering will produce noise and other problems with harmonics. Thus the design of the filter is crucial to the performance of the system and is, in fact, the main challenge facing the designer of such a system.

A more versatile approach to frequency division The use of a prescaler in a frequency synthesiser can alleviate many of the problems of frequency selection mentioned. A Prescaler is an electronic divider circuit used in high-frequency synthesiser designs to overcome the problem of generating signals at frequencies too high to be passed directly through the feedback loop of the system.

A basic frequency synthesiser as described above generates an output frequency of , given by the reference frequency rf multiplied by the division ratio N/R such that :

RNff ro ×=

Since N is an integer, the output frequency is necessarily restricted to whole multiples of the divided reference frequency Rfr . Typically, these will be the channels for which the radio equipment is designed for, so rf and R will usually be equal chosen so that Rfr is equal to the channel spacing. For example, for narrow-band radiotelephones, a channel spacing of 12.5 kHz is typical. This is achieved by an appropriate choice of the master oscillator frequency, and the divider R, for example 1MHz and 80, respectively.

Suppose that the divider N is only able to operate at a maximum clock frequency of 10 MHz, but the output of is required to be in the range of hundreds of MHz range.

If we were to interpose a fixed prescaler with a value, M, of say, 40, we may now lower the output frequency easily into the operating range of the divider N. However,



this has introduced an additional factor of 40 into the equation, so the output frequency is now:

RfNf ro ××= 40

If the comparison frequency Rfr were to remain at 12.5 kHz, we would obtain channels at a spacing of 40 × 12.5 kHz or 500 kHz, in effect only every 40th channel. Alternatively, if we were to reduce rf by a further factor of 40 to compensate, using an additional divider, the comparison frequency would become 312.5 Hz, which is much too low to allow satisfactory filtering and lock performance characteristics. It would also mean greater complexity in the programming of the divider, as only those ratios giving true channels must be selected, not those increments of 1/40th of a channel that become available with the extra divider stage

An enhanced frequency synthesiser It is relatively straightforward to incorporate a prescaler in an enhanced form of frequency synthesiser. A dual-modulus counter is one which is designed such that it can divide by one of two different factors, usually M and M+1 – for example, 2 and 3; 8 and 9, etc. The division factor actually applied is determined by means of a control input.

Figure 6 Frequency synthesiser with integer dual-modulus

prescaler

In the enhanced design, shown in Fig. 6, the main divider is split into two parts, the primary part N, and an additional divider A, which has a lower count range than N. Both parts of the main divider are clocked from the output of the dual-modulus prescaler, but only the output of the N divider is fed back to the comparator. This arrangement is sometimes known as a pulse-swallow architecture.

Initially, the prescaler is set to divide by 1+M . Both N and A count down until A reaches zero, at which point the prescaler is switched to give a division ratio of M. At this point, the divider N has completed A counts. Counting continues until N reaches zero, which represents a further AN − counts. At this point the cycle repeats. Thus:

R))A(MA)(M(Nff ro 1++−=

which reduces to



RAMNff ro )( +=

Hence, while the output frequency of is still related to rf by a factor which depends on MN/R, a further term A is now added. Only the dual-modulus prescaler needs to be constructed from high-speed parts; and the output frequency channel spacing remains the same as the comparison frequency Rfr .

The diagram below shows the elements and arrangement of a frequency synthesiser with dual-modulus prescaler.

A and N can be computed from the following formulae, which relates them to the required division ratio V:

)(div

mod

AMNVMVNMVA

RVff ro

+====

For this arrangement to work satisfactorily, A must be strictly less than M, as well as being less than or equal to N. These restrictions on the value of A imply that not every imaginable division ratio V is in fact possible unless the counter settings are carefully chosen. For example, V may not fall below )1( −MM ; and with some choices for M, N and A, certain channels will be unavailable.

It is possible to take this idea still further and develop from it a design that is capable of achieving outputs at frequencies that are fractional multiples of the comparison frequency. This may be achieved by passing the VCO signal through the ÷(N+1) counter for a part of the counting period, and through the ÷N counter for the remainder. In this way an average division ratio of somewhere between N and N+1 is obtained, and hence there is a fractional relationship between the input and output frequencies. This can be achieved with only relatively minor changes to the integer pulse-swallow architecture described, and represents a significant improvement to the basic design, as it means that frequency synthesisers can be used to generate accurately specified, closely-spaced channels at very high operating frequencies in the GHz region. This is beyond the scope of the project, however.

A demanding real-life application Modern communication protocols tend to allocate closely located channels at very high frequencies. This poses difficult challenges for the system designer. For example, the Bluetooth short-range wireless protocol allocates 79 channels between 2.402 GHz to 2.480 GHz resulting in a channel spacing of 1MHz. The phase noise (and other distortions from the local oscillator used) must be low enough not to cause interference with transmissions on adjacent channels. However, a stand-alone oscillator with sufficiently high stability would not be tunable over a 79 MHz band. Moreover, quartz crystals, regarded as essential in applications where frequency must be accurately determined, do not have resonance frequencies as high as 2.4 GHz. The frequency synthesiser architecture allows these challenges to be met, and integrated solutions are now readily available with chip costs of only a pound or so.



Notes on other circuit elements The Phase Comparator As seen, a key element in a frequency synthesizer phase-locked loop is the phase comparator. This compares the phase of the divided VCO to that of the divided reference signal. There are several types of phase detector.

The simplest is an exclusive OR gate, which maintains a 90° phase difference, but it is limited in its effectiveness unless the inputs are already at nearly the same frequency. A more complex approach uses a simple state machine to determine which of the two signals has a zero-crossing earlier or more often. This brings the PLL into lock even when it is off frequency. This type is known as a phase-frequency detector.

An analogue four-quadrant multiplier, also known as a mixer, can be used as a phase detector. Multiplying the VCO and comparison signals generates an output consisting of a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the VCO and the comparison, plus a second (unwanted) signal at twice the oscillator frequency that can be eliminated by means of a low-pass filter.

The Voltage-controlled Oscillator (VCO) The VCO must be capable of generating a signal of variable frequency, governed by the value of an external control voltage. A common way to achieve this is by use of an LC oscillator, comprising an LC "tank" circuit, which oscillates by charging and discharging a capacitor through an inductor. Most LC oscillators use off-chip inductors, since on-chip inductors suffer large resistive losses, and are of low Q. A voltage-controlled capacitor is one method of making an LC oscillator vary its frequency in response to a control voltage. Any reverse-biased semiconductor diode displays a measure of voltage-dependent capacitance and can be used to change the frequency of an oscillator by varying a control voltage applied to the diode. Special-purpose variable capacitance varactor diodes are available with well-characterised wide-ranging values of capacitance.

A ring oscillator can alternatively be used as a VCO. The frequency is controlled by varying either the supply voltage or the capacitive loading on each stage. Such VCOs generally have poorer effective Q than a well-designed LC oscillator, and so suffer more jitter and instability than other types. However, the ring oscillator approach offers the advantage of requiring no off-chip components or on-chip inductors. They may also have larger tuning ranges than other kinds.

The loop filter Key characteristics of a practical frequency synthesizer include: the time taken for the system to switch from channel to channel, time to lock when first switched on, and how much noise appears at the output. All of these are a function of the loop filter. This is a low-pass filter placed between the output of the frequency comparator and the input of the VCO. In the most basic systems, a simple RC network may be adequate. Typically the output from the frequency comparator is in the form of short error pulses, but the input of the VCO must be a smooth noise-free DC voltage. Any noise on this signal will cause unwanted frequency modulation of the VCO. Heavy filtering will make the VCO slow to respond to changes, causing drift and slow response time, but light filtering will produce noise and other problems with harmonics. Hence the design of the loop filter is critical to the performance of the system and its optimisation may consume a great deal of design time.



Design Choices In the pursuit of this project you will need to make a number of design choices at different stages. A detailed specification has been given for the performance of the ring oscillator design, and one of the themes of this project is the interplay between the details of layout and the performance that can be achieved. This will be investigated in Lab 7, and in the laboratory experiment organised to accompany this project.

However, we want to leave you with greater freedom of choice in the development of the digital part of the design. From the foregoing it is clear that there must be several viable approaches to the design of a programmable divider suitable for use in a synthesiser. Rather than specify these in minute detail, we will present an outline specification for the required operating frequency, and allow you to investigate the options and make the necessary design choices. You are of course welcome to discuss these options with a Demonstrator; you should be able to establish their feasibility at an early stage using functional simulation (Lab Guide 2), and it will be possible to adapt them (after discussion with a demonstrator). For example, you might conclude that a different Master Oscillator frequency will suit the needs of your project better than the one proposed. If your design might need additional inputs or outputs to/from the chip, you should also discuss this with a Demonstrator

You are expected to include in your First Interim Report as detailed a specification as possible of the target design your group has converged upon, and should include a block diagram clarifying those elements you will design, and those which will be provided externally.

Frequency Synthesiser Specification

Design Parameter Specification Number of discrete channel frequencies 60 minimum Nominal frequency of operation 3.5 – 3.8 MHz Channel frequency spacing 5 kHz Master Oscillator reference frequency 1 MHz Dual modulus counter (if required) ÷2, ÷3

Computer-based project in VLSI Design Lab Guide 1 - Falcon Framework

D M Holburn Apr 2007 EN2002.2 43 C6lab1.doc

Computer-Based Project on VLSI Design Co 3/6

Laboratory Guide 1 - a brief introduction to the Falcon Framework

This laboratory guide provides an introduction to the features of the Mentor Graphics Falcon Framework, Design Manager and the Adobe Acrobat-based On-Line Documentation Browser. 1. Login as instructed using the login assigned to you and your partner. Use the

information in the Getting Started pamphlet to start up Design Manager. You should see a Tools window and a Navigator window. Identify the framework icon in the Navigator window, and double-click with the left mouse button. Observe the readme file in the Navigator window.

2. Left-click on the readme file. It should appear selected (in reverse video). Now click on the selected readme file with the rightmost mouse button (Menu).

A menu appears. Move the cursor down the list until it is on Edit, then move it to the right onto the arrow symbol; a sub-menu will appear. Move the cursor so as to highlight the command: Copy, and right-click again.

A prompt bar appears in the lower left of the screen. Enter the name of the new file to be created, which will be a copy of readme, e.g. my_copy.

Now left-click the OK button on the prompt bar. The Navigator window will be updated to show a copy of the file with the name you gave it.

3. Start up the System Default Editor on this file, by doing the following: Select the copied file by left-clicking on it. Right-click the selected file and move the cursor down to the arrow on the right of

Open, and a sub-menu will appear listing all the Mentor tools that are capable of starting up with the selected design object.

Select Default Editor and left-click it. This starts up the Mentor Notepad editor. You will make use of this utility in later sessions to prepare scripts and other documents.

Observe that the Design Manager menu bar changes; the commands available are now those for the Notepad utility. Verify that you can edit the text that you now see; when ready, close the Notepad editor by double-clicking on the system icon in the upper left corner of the window. Save the changes if you wish.

Note the availability also of a Read Only Editor, provided for viewing files without changing them in any way.

4. Examine the references of a design object. Select cell_X. Display its external references (i.e. the other design files or

resources upon which it depends) by using the (menu bar) > Report > Show References pulldown menu item.

Examine the test window that appears. You should see that cell_X refers to a Process (denoted by MIETEC_CMOS24_IC_PROC), a set of Rules (denoted by MIETEC_CMOS24_IC_RUL), and a second cell, cell_Y.

When ready, close the References window by double-clicking on its system icon.



5. Copy design objects cell_X and cell_Y to another directory. Open a further Navigator window by clicking the Navigate icon in the palette;

switch this new Navigator window to the framework directory by double-clicking its icon. Identify the sub_dir directory icon, and enter the directory in a similar way.

Back in the original Navigator window, select the object cell_X by clicking on it. Then select the object cell_Y as well, by depressing the Ctrl key while clicking on it. Both cells should now be selected.

Copy these two cells to the directory sub_dir by holding down the Shift key and dragging the two icons into the new Navigator window.

Activate the new Navigator window by clicking in it. Then give the command: (menu bar) Report > Show References. Two reference windows should now appear.

The reference window for cell_X will show that the copied version references not the original cell_Y, but the new cell_Y in the directory sub_dir. The Mentor copy operation has actually changed the references; it is evidently a much more powerful operation than the Unix cp command.

Close both Reference windows. Close the sub_dir Navigator window.

6. Examine a design cell containing a faulty reference. In the original Navigator window, select the object bad_object, then give the

command: (menu bar) Edit > Check Refs. OK the prompt bar. You will see in a dialogue box that one reference is broken. Cancel the dialogue

box when ready.

7. Use Acrobat to read about broken references. Select the item: (menu bar) Help > Open Bookcase to start up Adobe Acrobat.

Note that the Acrobat utility is accessible by means of the (menu bar) Help menu from any of the Mentor applications. You may wish to drag the Acrobat window to a different fvwm virtual screen. The resultant window, should contain a menu of Mentor Bookcases (Manual Collections) from which you can select. If necessary, give the following command in the Acrobat window: (menu bar) MGC > View Installed Bookcases.

Click once on Falcon Framework. Note the comprehensive list of documents - this is but a small fraction of the

material that is available. Scroll down to find the Design Manager User's Manual and click it once.

The manual will open up, typically in a much larger window. Expand the Acrobat window to fill as much as possible of the screen by dragging out the lower right hand corner. You may need to move the window to a different virtual screen (grab the left or the right margin with the pointer) in order to access its menu bar. Once you have done this, you can use the Maximise button (double-click at rightmost end of title bar) to maximise the window’s size.

8. In the Design Manager User's Manual child window, give the command: (menu bar) > View > Single Page. Depending on the screen resolution available and your own preference, you may wish to view two pages side by side: if so, try the



command (menu bar) View > Continuous – Facing, and, if wished: (menu bar) > Window > Hide Bookmarks to suppress the bookmarks and dedicate the whole window to text. Note that icons are provided in the toolbar to help you make these adjustments more quickly. Experiment with them if you wish.

9. If the bookmarks were suppressed in (8) above, reinstate them temporarily. Click on the INDEX bookmark, visible in the left pane of the Acrobat display, headed:

Bookcase. Acrobat will now display the index section of the document.

Now find the entry for "References, fixing" (3-85), by turning the pages (click on the Page turn icons, and , in the toolbar, or use keyboard shortcuts Control+2 and Control+3 to move backwards and forwards through the index section.

Place the cursor on "3-85" and click. Read the section on fixing broken references, especially page 3-86 to 3-87.

Note: you can safely ignore references to V7.x data, which correspond to earlier versions of Mentor.

If time permits, explore the other bookcases and documents, by reverting to the small Acrobat bookcase window – click on the Bookcase in the bookmark panel.

10. Now, back in Design Manager, ensure the Navigator window is active, and re-select bad_object.

Give the command: (menu bar) Edit > Check Refs. With the help given by Bold Browser you should be able to fix the broken reference.

Hint: the reference should actually be to cell_X. Now re-check the references. A message: "No broken references were found"

should appear in the message area at the foot of the Design Manager window. This concludes our preliminary investigation of Design Manager. If you plan to continue with the next Lab Guide which explores Design Architect, leave Design Manager running. If you propose to log out, first close down the Acrobat browser and any other tools that remain open; finally; close Design Manager and log out.



Computer-based project in VLSI Design Hardware Description Language VHDL

D M Holburn Apr 2007 EN2002.2 47 C6vhdl.doc


Hardware Description Language VHDL

This pamphlet briefly introduces the hardware description language VHDL and its basic characteristics, and describes the emerging role of this technique in the specification and verification of digital circuit designs. The traditional approach to integrated circuit design involves the capture of a schematic - a collection of symbols and wires which expresses the structure of the design. While schematics are useful in allowing the designer to have access to a graphical picture of the design, a serious shortcoming of the approach is that it is difficult to embody the behaviour of the design in a schematic. Hence the verification of the correctness of a design by examining schematics is at best an indirect process. Hardware description languages (HDL) can replace circuit diagrams, flowcharts and other documents as the primary documentation medium for circuit structure and behaviour. They are especially well suited to the design verification process, because, with appropriate supporting software, an HDL description can be directly executed to simulate the circuit it describes. HDLs also provide a convenient way to describe the input/output data used by logic synthesis tools.

The value of a description language can also be illustrated in a different way: suppose you have designed a 12-hour digital clock and you now wish to redesign it as a military-style 24-hour clock. In the schematic form of digital systems implementation, you would need to redesign your clock schematic substantially, changing and re-specifying gates and rewiring the design. With a design described in a hardware description language, you could simply revise your specification, changing 12 to 24 in a number of places, verify the description on a computer to check it behaves as expected, and use the result as input to an automated semi-custom layout system similar to that available with the Mentor Graphics suite.

An attractive approach for specifying behavioural descriptions is through a hardware description language. These languages look much like conventional high-level computer programming languages and contain many of the constructs of languages like C or Pascal. However, conventional programming languages rather compel the user to think of executing a single statement of the program at a time. This is unsuitable for hardware, which is inherently parallel: all gates are constantly sampling their inputs and producing new outputs. The high degree of parallelism in most hardware is one of the things that makes hardware design and verification difficult.

VHDL (VHSIC Hardware Description Language) is a widely used language for hardware description, and is based on the programming language ADA. We do not attempt to present VHDL in anything like its complete form here, but the notes below may hint at the power of the technique.

A piece of digital hardware at any complexity level from an entire system to a primitive gate is called a design entity, and is specified by a composite VHDL statement of the form: entity Name is . . . end;



Figure 1 begins with an entity statement that identifies the hardware item of interest as mux, a user-specified name, and lists its primary input/output signals and their types. The input/output signal list is introduced by the keyword port (a term often used to refer to a group of associated input/output lines in a digital system). The signal direction in or out is indicated in the port statement, as well as the signal type (in this case bit, meaning that the named signals assume the binary values 0 and 1 only). Alternative signal types might include an unknown value X, or we might wish to treat the signals as integers, in which case the keyword bit would be replaced in the port statement by the keyword integer.

In Figure 1, both structural and behavioural descriptions of the design are included. The structure and behaviour of the target circuit are described within a compund VHDL statement of the form:

architecture Name is begin . . . end;

which in Figure 1 follows the entity statement. Note that timing information such as component delays and signal rise and fall times can also be included in an architecture specification.

A basic VHDL construct is a signal assignment such as:=

Z <= not A;

which states the the signal Z is assigned the current value of the expression on the right of the assignment. To specify a timing delay, the keyword after may be used, thus:

Z <= not A after 2ns;

The familiar if-then-else construction can be used to add further logical conditions to a signal assignment: for instance:

if M = '0' then Z <= not A after 2 ns; else Z <= A or (not B) after 2.8 ns; end if;

Here M serves as a control signal, its value 0 or 1 determining the logical operation used to calculate the value of the data signal Z. When a large number of control conditions exist, a sequence of if statements can be replaced by a more concise case statement:

case C is when C1 => Z <= f1(X); when C2 => Z <= f2(X); M when Cn => Z <= fn(X); end case;

Other standard language features include the use of pre-defined functions and the association of types like bit and integer with signals and other variables. The following section is a convenient summary of VHDL command syntax.



Gate-Level Representation of Two-input Multiplexer 0 -- Code of Structural Description for a Multiplexer 1 ENTITY mux IS -- entity declaration 2 PORT (dO, dl, sel: IN bit; q: OUT bit); --port clause 3 END mux; 4 5 -- architecture body 6 ARCHITECTURE struct OF mux IS 7 COMPONENT and2 -- architecture declaration 8 PORT(A, b: IN bit; C: OUT bit); 9 END COMPONENT; 10 COMPONENT or2 11 PORT(A, b: IN bit; c: OUT bit); 12 END COMPONENT; 13 COMPONENT inv 14 PORT (a: IN bit; c: OUT bit); 15 END COMPONENT; 16 17 SIGNAL aa, ab, nsel: bit; --signal declaration 18 19 FOR ul : inv USE ENTITY WORK.invrt(behav); config. 20 FOR u2, u3: and2 USE ENTITY WORK.and_gt(dflw); specif. 21 FOR u4 : or2 USE ENTITY WORK.or_gt(archl); 22 23 BEGIN 24 ul:inv PORT MAP(sel, nsel);--architecture statement part 25 u2:and2 PORT MAP(nsel,dl,ab); 26 u3:and2 PORT MAP(DO, sel,aa); 27 u4:or2 PORT MAP(aa, ab, q); 28 END struct; 0 -- Code of Behavioral Description for a Multiplexer 1 ENTITY mux IS -- entity declaration 2 PORT (dO, dl, sel: IN bit; q: OUT bit); --port clause 3 END mux; 4 -- architecture body 5 ARCHITECTURE behav OF mux IS 6 BEGIN 7 fl: -- process statement 8 PROCESS (dO, dl, sel) sensitivity list 9 BEGIN 10 IF sel = '0' THEN -- process statement part 11 q <= dl; 12 ELSE 13 q <= d0; 14 END IF; 15 END PROCESS fl; 16 END behav;

Figure 1



VHDL Command Summary

Concurrent Statements

block_statement label: block [(guard_expression)]

[generic] [ports] [declarations]

begin

concurrent_statements

end block [label]; component_instantiation_statement

label : name [ generic map (map) ] [ port map (signals) ]; concurrent_assertion_statement

assert condition

[ report string_expression ] [ severity NOTE | WARNING | ERROR | FAILURE ];

concurrent_procedure_call [ label : ] procedure_name [ (parameters) ];

concurrent_signal_assignment_statement [ label : ] [ conditional_assignment | assignment | selected_assignment ];

generate_statement label : [ for specification | if condition ] generate


end generate [label]; process_statement

[label : ] process [ (sensitivity_list) ]

[ variable_declaration ] [ type_declaration ] [subprogram_declaration ] [ declarations ]

begin

sequential_statements -- Cannot contain a wait statement if sensitivity_list is used

end process [ label ];



Sequential Statements assertion_statement

assert condition -- When condition is false [strng_expression] is printed

[ report string_expression ] [severity NOTE | WARNING | ERROR | FAILURE ];

case_statement case expression is -- Avoid the use of parenthesis, if possible when choices_1 => sequential_statements . . when choices_n => sequential_statements end case;

exit_statement exit [ label ] [ when condition ];

if_statement if condition then

sequential_statements elsif condition then sequential_statements [ else sequential_statements ]

end if; loop_statement

[ label : ] [ while condition | for loop_specification ] loop sequential_statements end loop [ label ] ;

next_statement next [ label ] [ when condition ];

null_statement null;

procedure_call_statement procedure_name [ (parameters) ] ;

return_statement return expression; --For use in a Function return; --For use in a Procedure

signal_assignment_statement target <= expression [ after time_expression ] . . , expression [ after time_expression ];

variable_assignment_statement target := expression ;



wait_statement wait --A Function may not contain a wait_statement

[ on signal_name , signal_name ] [ until conditional_expression ] [ for time_expression ] ;

Specifications attribute_specification

attribute attribute_name of entity_name is expression ;

configuration_specifications for component_name use [ generic_map_part ]

[port_map_part] ;

Library & Use Clause library_clause

LIBRARY names ; use_clause

USE selected_names ;

Declarations alias_declaration

alias name1 : type [ (indexes) ] is name2 [ (indexes) ] ; attribute_declaration

attribute name : type ; component_declaration

component identifier : [ generic (generic_list) ; ] [ port (port_list) ; ] end component ;

constant_declaration constant name : type := expression ; constant name : array_type [ (indexes) ] := expression ;

file_declaration file name : type is [ mode ] logical_name ;

signal_declaration signal names : type [ constraint ] [ := expression ] ;

port_declaration port ( names : direction type [ := expression ] [ ; more_signals ] );



subprogram_declaration procedure name [ (parameters) ] | function name [ (parameters) ] return type;

sub_program_body is

declarations

begin

sequential_declarations

end [name] ; subtype_declaration

subtype name is [ resolution_function] type [constraint] ; type_declaration

type name is definition; variable_declaration variable names : type [ constraint ] [ := expression ] ;

Library Units architecture_body

architecture name of entity_name is

[types] [constants] [signals] [subprograms] [other declarations]

begin


end [name]; configuration_declaration

configuration name of entity_name is

declarative_part block_configuration

end [name]; entity_declaration

entity name is

[generics] [ports] [declarations]



[begin statements] --typically, an entity does not have statements. If it does, the statements cannot operate on signals end name;

package_body package body name is

[subprogram] [type] [constant [signal] [declarations]

end [name]; package_declaration package name is

[subprogram] [type] [constant] [signal] [file] [alias] [USE clause] [declarations] end [name];

Computer-based project in VLSI Design Lab Guide 2 - Simulation with ModelSim

D M Holburn May 2007 EN2002.2 55 C6lab2.doc


Laboratory Guide 2 - Functional HDL Simulation with ModelSim

This laboratory guide provides an introduction to functional simulation using sets of abstract models – hardware descriptions – so as to allow a clear understanding of the target design before any commitment needs to be made to detailed design. The session will introducs the features of the VHDL hardware description language, as well as the use of Mentor Graphics ModelSim compiler and simulator for VHDL.

The uses of VHDL in digital systems design have been described in another pamphlet. In this session we shall begin by using VHDL to express the structure of the ring oscillator which forms the heart of this project, as well as a behavioural model for the two-input NOR gate used in its construction. You will see how a wide range of digital hardware can be modelled in terms of statements similar to those in computer programs, e.g. Pascal or C. These models will then be simulated using ModelSim. Once the operation of the ring oscillator has been explored we shall incorporate the additional features of the design, viz. the counter, comparator and associated logic required in a frequency synthesiser.

At this stage of the design process we may have made no decisions about the way in which the hardware will ultimately be implemented, but by use of models of this kind we can gain considerable insight into the way the design will work and explore a number of 'what if' scenarios – for example, the effect of different gate propagation delays for rising and falling edges. Later in the project, if time permits, we shall substitute into the VHDL model the parameters corresponding to the delays for the actual NOR2 gate which you yourself will design in week 3.

The way in which we shall be using ModelSim (with abstract models) will not involve direct transfer of modelling information between this package and others in the Mentor Graphics Falcon Framework - say, QuickSim II. This will not detract from the value of the technique, however, and it is worth mentioning that in other circumstances using VHDL for synthesis of designs is a perfectly viable approach. Also, the arrangements with ModelSim for printing out waveforms are slightly different from those used for other Mentor applications.

Before you start work with ModelSim, you will need to give thought to the form of the ring oscillator module. This may usefully be done off-line, away from the workstation. You should review the material in the introductory document Design of logic gates in CMOS, together with data in the Design Specification pamphlet, especially the specification for the ring oscillator itself. You may find it helpful to start with a schematic sketch of the ring oscillator. The number of gates required will be dictated by the delays and oscillation period specified in the Design Specification.

You should be logged in at a workstation as described in the Getting Started section, with Design Manager running. A number of VHDL source files for a 2-input NOR gate, counter, and other elements are provided in the directory $CBT_WD/vhdl. You will need to edit and adapt these to model your proposed design. Initially we shall examine a simple ring ring oscillator based on the 2-input NOR gate alone, then extend the design progressively to explore the additional features. We shall start by considering the 2-input NOR gate.



1. Change Mentor's working directory to $CBT_WD/vhdl. For the most part we shall generate schematics, cells, etc in the $CBT_WD

directory, which corresponds for each user to the cbt subdirectory of their Mentor workspace. For the case of VHDL, however, it is more appropriate to place the corresponding files in a directory of their own. To ensure that all files accessed and created in this phase are held in this directory is necessary to change Mentor's working directory.

Note: you must remember to restore Mentor's working directory to $CBT_WD when you complete this session on VHDL.

To change the directory, give the following Design Manager command: (Menu bar) > MGC > Location Map > Set Working Directory. Enter the path: $CBT_WD/vhdl into the prompt bar that appears, and OK it.

Navigate to the $CBT_WD/vhdl directory, and observe that a number of component containers exist. These do not have associated schematics, but instead contain VHDL textual representations.

2. Open Design Architect on the nor2_vhdl VHDL object. Select nor2_vhdl, and open Design Architect on this object. Note that when

Design Architect starts up, it displays a text window rather than a schematic. This Notepad window allows you to edit and save the text. It has a number of additional features which can be helpful in generating VHDL from scratch. Examine the VHDL model provided and compare with the pamphlet provided on VHDL. You may note similarities to Pascal, especially in the nor_inputs section. Note also the Entity declaration, the architecture entitled behav which encapsulates a model for the NOR gate, and the Library statement to invoke the mgc_portable library, which contains definitions of the signals and their data types (for example: 0, 1, X and Z), which are recognised by the ModelSim simulator which we shall use later.

Note: this model requires some updating to match specific characteristics of the Mietec NOR2 gate which we shall initially use. It also contains at least one basic error, which you will be able to correct with ease provided you have studied and understood the listing. The listing of the nor2_vhdl source is reproduced at the end of this section.

Study the model, and, referring to the printed information supplied for the Mietec NOR2 gate (pages 30-31), edit the VHDL so it most accurately reflects that gate. When you are content with the result, save it using the command: (Menu bar) > File > Save. If you wish to generate a printed copy of this or any other VHDL object, check with a demonstrator for details of how to proceed.

3. Compile the nor2_vhdl VHDL object. Before the VHDL object can be simulated, it must be compiled using the

ModelSim compiler. This can be carried out from within Design Architect. First give the command: (Palette) > Set Compiler Options. In the Set VHDL

Compilations Options dialogue box, the Work Library should be set to $CBT_WD/vhdl. Observe the other available options, but leave them unchanged. OK the dialogue box.

Now give the command (Palette) > Compile. You may see a message warning about a missing initialisation file QuickHDL.ini. You can safely ignore this.



A double-purpose Compilation Report window should then open in front of the Notepad window to record the compiler's progress. If not, use the command (Palette) > Select Window … and choose the Compilation Report. Resize the two windows so they can be viewed simultaneously.

If the compilation is successful you should see the message: HDL compilation completed successfully appear at the end of the Compilation Report. Otherwise, one or more warning/error messages may appear. Click any message to select it, then click on the Highlight button, and observe the Notepad window, where the offending line of code will be highlighted in yellow. Make any necessary corrections, save and recompile. Repeat for any remaining errors.

4. Edit and compile the ring_oscillator_vhdl and top_level_vhdl VHDL objects. When you are happy with nor2_vhdl, close the design window; the Compilation

Report window will also close.

Give the command: (Menu bar) > File > Open > VHDL. In the Open VHDL DB dialogue box, press the Yes button associated with Inside component, and use the Navigator to select the top_level_vhdl component. OK the Navigator box. Make sure the VHDL source name is set to top_level_vhdl, (not $CBT_WD/vhdl, which is the default), and OK the dialogue box. Alternatively, after choosing the Inside component option, you can use the Navigator to navigate right down into the top_level_vhdl component and choose the top_level_vhdl item within. This approach should ensure that the correct text appears in the VHDL source name field without requiring you to type it in.

As before, a Notepad window will open revealing the VHDL model. A typical source listing for top_level_vhdl is reproduced at the end of this section. The template provided represents the bare minimum required to represent the core of your design. You will adapt this in stages to represent progressively more and more of the target design. For reference, a printed listing at the end of this section shows one possible form that a basic top_level_vhdl might take, but do not simply key in the complete text at this stage, as errors will result.

Follow exactly the same procedure to inspect the ring_oscillator_vhdl component. As supplied, this represents a model for a very simple 5-element oscillator. This will not meet the requirements for this design as it stands, and you will need to adapt it as necessary.

Study the model and modify it so that it represents the ring oscillator module you designed as a schematic component. A certain amount of cut-and-paste editing may be required for this purpose. Consult a demonstrator if you are uncertain how to proceed. When the model is complete, save it and compile as for the nor2_vhdl object. Correct any errors if necessary. Note that if you attempt to compile ring_oscillator before nor2_vhdl has been successfully compiled you will encounter error messages.

Finally, close the design window and re-open it on top_level_vhdl, which will represent the topmost hierarchical level of your design. Consider whether any changes are needed, and save as necessary. Then compile as for the previous two models. Once you have achieved a clean compilation of the three VHDL objects you are ready to undertake simulation of the design.



5. Initiate a ModelSim session on the VHDL design. In ModelSim, it is possible to control operation either by entering text commands

in the ModelSim window, or by use of interactive menus. We shall make use of both approaches; for fuller details, use the Acrobat utility to explore the Help volume: ModelSim User’s Guide and Reference Manual, Section 5, ‘Using the Simulator’s Graphical Interface’.

With both files now successfully compiled into ModelSim objects, it is possible to begin the simulation. With the Compilation Report window active, give the command: (Menu Bar) > ModelSim > Simulate ... When the vsim Simulate dialogue box appears, check the Library Name field, and change it if necessary to $CBT_WD/vhdl. Click the ns button to select time units in nanoseconds. The Design Unit Type should be Configuration. Enter top_level_vhdl into the Entity/Configuration field. OK the dialogue box.

A new window should appear, entitled ModelSim EE/Plus 5.3a. This is the main control window (referred to as the ModelSim window). Move this window to a clear area. A number of Loading … messages should appear, showing that the three design entities nor2_vhdl, ring_oscillator_vhdl and top_level_vhdl entities were successfully loaded.

At this stage you should minimise any underlying windows to give a clear and uncluttered background.

With the ModelSim window active, use the View pull-down menu to open the following sub-windows: Structure, Source, Signals, and Wave. Giving the View > All command also produces the required windows, but may leave the screen congested. You should investigate the characteristics of the other windows once the significance of these initial four is clear. Rearrange the windows if necessary to obtain a clear view. Their positions are recorded in an initialisation file for use in later sessions.

The Source window displays the VHDL source corresponding to the entity selected (highlighted) in the Structure window, which shows a hierarchical picture of your design. Click the various elements in the Structure window to confirm this.

The Signals window lists the signals visible in the Structure entity currently selected, together with their current states. You can use this window to force specific values upon signals.

The Wave window displays graphical waveforms resulting from ModelSim simulation runs. The signals displayed here may be selected in the Signals window.

6. Use ModelSim to verify the performance of the ring oscillator. Before running a simulation it is necessary to set up the values of any external

signals. For the simulated ring oscillator to run, this requires that the signal enb be set to an appropriate value. Make sure top_level_vhdl in selected in the Structure window. Then, in the Signals window, select signal ring_osc_enb. Select the pull-down Edit > Force menu command, and in the resultant dialogue, set the signal to an appropriate value. Choose Freeze for the signal Kind, and click OK to accept the settings. If necessary, re-select ring_osc_enb in the Signals window to display its updated value.



Note that a force command relating to the enb signal has now appeared in the ModelSim window. This shows an alternative method of applying forces to signals. With the ModelSim window active, force commands (and others) may be entered directly as text strings. For example, the command:

force ring_osc_enb 1 0, 0 50, 1 100

will apply logic 1 to the signal at time 0; logic 0 at time 50 ns, and logic 1 at time 100 ns. You may need to use this technique to generate a more complex stimulus in a later section. For very involved sequences it is also possible to store sets of force commands in a do file, which can be executed on command using the pull-down menu command: File > Execute command file .... For further details, use the Help system to examine the ModelSim User’s Guide (see paragraph 5 above).

In the Signals window, select those signals you wish to monitor (hold down Shift while you click the second and subsequent signals). Use the View > Wave > Selected Signals pull-down menu command to send them to the Wave window.

To run the simulation, click the Run button in the ModelSim window, or type in the run command, followed by Enter. You can alter the length of time for which the simulation runs by editing the Default Run field in the Simulation Options dialogue, which may be called up by means of the Options > Simulation .. pull-down menu command. Note also the step command which allows you to run the simulation line by line through the VHDL sources.

You should now experiment with suitable force, run, and step commands to characterise the behaviour of the ring oscillator.

Caution: Do not be tempted to use the command run -all. Although this may seem like a convenient short-cut to produce many cycles of oscillation, it is not possible to interrupt such a run. Your working directory will fill up with unwanted wave data until your quota is exhausted. You then risk not being able to save files you may be editing, and you may lose data! Use (for example) run 10000 instead.

7. Generate printouts of ModelSim waveforms. If necessary, generate printouts of the waveforms for your records. Using appropriate ModelSim commands, generate the required waveforms in the

Wave window. Then, from the Wave window, issue the pull-down menu command: File > Print Postscript. In the resultant dialogue box select the File option and edit the File field as necessary to give a convenient file name, adding the file extension .ps. Do not change the directory in which the file is created. If necessary, select A4 paper size, and choose portrait or landscape orientation as preferred. OK the dialogue box.

ModelSim’s printing arrangements are slightly different from other members of the Mentor suite. A special script has been supplied to convert Postscript files (generated as described above) into a form suitable for printing.

To invoke this, activate the ModelSim window and give the command: exec vhdlplot, followed by Enter. Vhdlplot should list any Postscript wave files it has processed. To complete the printing process, use the following procedure (also used with other tools) to preview and print the results. This requires the use of a further special utility, mgcplot.

Open a new X terminal window, and when the Unix prompt appears, give the



command: mgcplot. The right mouse button, clicked with the cursor over the patterned wallpaper, offers a menu item which invokes mgcplot in a new X terminal window.

For the moment, press Enter when asked if you wish to process colour or A3 plots. Examine the list of output files you have so far generated, and select one by number. Mgcplot will now prompt you with a numbered list of output possibilities, including a Preview to Screen. You are recommended to use this to verify the results before committing them to paper. When you are ready, exit the ghostview Preview utility, and choose a printer if appropriate. One of the options allows you to save a copy of the Postscript output in your personal home directory – useful if you want to include the output in a report.

Note: Unless you hear to the contrary, only the A4/monochrome printing options are available, with local printers ljmr1 and ljmr2.

8. Investigate modified forms of the ring oscillator design. Investigate the effect on ring oscillator performance of using a NOR gate with

delay for rising edges three times that for falling edges.

One way of doing this would be to revert to Design Architect, modify the parameters Trise and/or Tfall in the VHDL source, recompile, and re-run the simulation. However, this would be fairly tedious.

A simpler and quicker method is by means of the Variables window. The Variables window displays the values of constants and other parameters defined in the VHDL source currently being simulated.

In order to make these visible, use the Step command in the ModelSim window to step the simulation through until the Source window shows the nor2_vhdl source. Then give the pull-down menu command: View > Variables ... The Variables window should appear, displaying the values of Trise and Tfall. Select these as required, and use the Edit > Change command to modify their values. Run the simulation as necessary and observe the effects.

Question How do these new results compare with your expectations? If necessary, discuss your findings with a demonstrator.

9. Using the techniques illustrated in paragraphs 6 and 8, investigate the expected behaviour of your own ring design (assuming the Mietec NOR2 gate is installed) when a pulse of the form shown below is applied. Note: consider carefully what form and duration of initialisation signal needs to be applied to ring_osc_enb prior to the double pulse. Also, bear in mind that this version of ModelSim accepts only integer values for time delays. You can circumvent this by restarting the simulator with time units set to picoseconds. Use the Design > Load New Design command in the ModelSim window to achieve this, and in the Load Design dialogue box, click the Simulator Resolution button to select a different time unit. You will need to repeat the Force setup in section 6.

10

enb 0 5 10 15 20 ns



Examine the resultant output waveforms, paying particular attention to the period and the relative amount amount of time spent by each output in the logic 0 and logic 1 states.

Question Under these conditions - that is, with a short double-pulse applied to the ring_osc_enb input - does the ring oscillator appear to oscillate at its calculated operating frequency? If not, why is this so, and what is now the measured operating frequency? Hint: consider what you would measure if you were able to connect the output to a digital frequency counter, which simply counts the number of transitions passing in unit time.

10. Use ModelSim to model a basic ÷16 counter driven by the ring oscillator Within the vhdl folder you will find simple models to represent counters and

other elements. We will use these now to model the behaviour of a slightly more elaborate design, comprising the ring oscillator already designed (used as clock source), plus a 4-bit counter. We will later progress from this to a more elaborate counter, with 6, 8 or more bits, and the comparator and other logic required to convert this into a programmable divider. This approach is to give you more familiarity with VHDL modelling, but it also mimics what we will later carry out using CMOS library cells.

You can see listings of the models provided at the end of this Lab Guide; for the most part they are indentical with the corresponding templates supplied in the vhdl folder. Note: the supplied models are simplified, and may or may not include delays. Not all will necessarily be required for the present work, and it will also be necessary to create one or two templates from scratch, using those provided for reference.

Using Design Architect to open up the corresponding component containers, study the structure of these using the Notepad editor (within Design Architect), or by using the printed listings appended to this sheet, and make any alterations you feel are necessary. You may need to edit these so they have the required characteristics – adapting the code supplied to give the correct initialisation and other characteristics – for example, a counter with preset to 1s or clear to 0s, as required. Use the procedure of section 3 to compile the new sources.

Adapt the top_level_vhdl source to reference the additional components. Establish port mappings so that one of the ring_oscillator outputs drives the clock input on the counter; allow for the counter to be reset at will, and make its outputs available as external signals.

Plan your code carefully and use a hierarchical approach – the specimen code at the end of this guide should help. You should expect to spend some time away from the workstation preparing your design and the VHDL code to model it.

Compile using the procedure of section 4, and invoke simulations using the approach of section 5.



Objectives Use these resources to investigate the following:

Operation of the basic 4-bit digital counter using a standard clock ♦ Demonstrate a full cycle of counting ♦ Show the operation of the manual Reset facility

Include the results of these investigations in your First Interim Report. 11. Developing the programmable divider system

In this section you should select from and adapt the available modules to develop the divider architecture proposed for the target frequency synthesiser design. This will require you to incorporate more than one counter component (to achieve the required precision); to incorporate a comparator that can detect the state of certain of the counter outputs so that the counter can be reset after a a pre-determined number of counts, in effect becoming a programmable counter. Finally, you should add the necessary control structures, inputs and outputs so this hypothetical model adequately emulates the target design.

You are recommended to proceed in stages, examining the behaviour of the new components separately before integrating them and closing the feedback loop, then finally adding the ring_oscillator module – see the test objectives below.

Study and adapt the appropriate VHDL sources and recompile if necessary

Objectives

Use the adapted models to investigate the behaviour of the counter in programmable form. A series of tests demonstrating different division rations is the objective.

(a) Incorporation of a comparator with the counter ♦ Use of the comparator to detect a pre-determined counter state ♦ Demonstrate detection of at least three different states by using different

combinations of force commands applied to the programming inputs

Now edit the top_level_vhdl source to extract a signal from the comparator that could be used to reset the counter to zero. Route this feedback signal to the counter Reset input. Recompile the top_level_vhdl source.

(b) Development of the complete programmable counter ♦ Demonstrate operation of the programmable counter counting modulo-N

for at least three different N. ♦ Show how to produce a divided output with 1:1 duty cycle.

Make appropriate modifications to your design as required so it works reproducibly and generates the required outputs.

Include the results of these investigations in your First Interim Report.



12. Use ModelSim to verify the performance of the complete design The final design will incorporate the ring oscillator already considered as clock

input to the counter. This will represent the voltage-controlled oscillator (VCO) used in the synthesiser.

Adapt the top_level_vhdl source to incorporate this feature and any others you consider important. You should plan your code carefully and use a hierarchical approach – the specimen code at the end of this guide should help. You should expect to spend some time away from the workstation preparing your design and the VHDL code required to model it. Incorporate additional models for combinational and sequential logic elements, as required. You can see listings of these at the end of this section.

Using Design Architect to open up the corresponding component containers, study the structure of these using the Notepad editor (within Design Architect), or by using the printed listings appended to this sheet, and make any alterations you feel are necessary. Note: the supplied models are simplified, and may or may not include delays. You will need to edit these so they have the required characteristics. Use the procedure of section 3 to compile the new sources.

Compile this using the procedure of section 4, and invoke a simulation using the approach of section 5.

Objectives

♦ Demonstrate that the ring oscillator is capable of driving the programmable counter.

♦ Show that the design counts correctly when provided with the ring oscillator input and appropriate programming inputs. Produce a timing diagram showing inputs and outputs to demonstrate correct operation for at least three different programmed inputs.

Hence develop a model for a complete representation of the system (whose schematic structure is shown in the opening handout).

Include the results of these investigations in your First Interim Report. You are recommended to keep a copy – you will need it for Lab Session 4.

13. Reinstate the Working Directory for your Mentor session Before proceeding with any other lab sessions, be sure to return to Design

Manager and restore your Mentor Working Directory to $CBT_WD. See the instructions in paragraph 1 for guidance.

Later in the project you will make further use of the VHDL model created in this session, in order to predict the performance of the ring oscillator module using the 2-input NOR gate of your own design.

♦♦♦




Appendinx – VHDL Source Listings

The following section contains VHDL source listings for reference. All models invoke the Mentor mgc_portable library which contains definitions of the signals that are accepted by the Modelsim simulator. For convenience, the signals have been chosen to be compatible with the QuickSim II simulator to be used in later sessions. A number of alternative libraries are available, including IEEE-endorsed ones and some contributed by device manufacturers.

The library package qsim_logic contains a basic 4-state data type called qsim_state: the four states are 0, 1, Z (for high impedance) and X (for unknown), as well as definitions of all relational operations based on these states. In addition, a 12-state data type qsim_12state is defined, along with supporting resolution, conversion, and operator functions.

More complete details of the mgc_portable library are available on the web at: http://www-g.eng.cam.ac.uk/mentor/pdf/mgc_portable.pdf



VHDL source listings for reference -- 2 INPUT NOR GATE LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY nor2_vhdl IS PORT(A, B : IN qsim_state; Y : OUT qsim_state); END nor2_vhdl; ARCHITECTURE behav OF nor2_vhdl IS CONSTANT Trise: time:= 10 ns; -- Typical delay, 0-1 transition CONSTANT Tfall: time:= 12 ns; -- Typical delay, 1-0 transition -- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project -- Their values must be changed to correspond to the Mietec design. -- All references to Trise/Tfall below must be carefully checked!! BEGIN nor_inputs : PROCESS (A,B) BEGIN IF (A OR B) = '1' THEN Y <= '0' AFTER Trise; ELSIF (A AND B) = '0' THEN Y <= '1' AFTER Trise; END IF; END PROCESS nor_inputs; END behav; -- TEMPLATE FOR SIMPLIFIED RING OSCILLATOR (5 STAGES) LIBRARY mgc_portable ; USE mgc_portable.qsim_logic.ALL ; ENTITY ring_oscillator_vhdl IS PORT ( ENB : IN qsim_state ; OUT1 : OUT qsim_state ; OUT2 : OUT qsim_state ); END ring_oscillator_vhdl ; ARCHITECTURE struct OF ring_oscillator_vhdl IS COMPONENT nor2v PORT (A, B : IN qsim_state; Y : OUT qsim_state); END COMPONENT; SIGNAL nor_out : qsim_state_vector(0 TO 4); FOR u1, u2, u3, u4, u5: nor2v USE ENTITY WORK.nor2_vhdl(behav); BEGIN u1:nor2v PORT MAP(ENB,nor_out(4),nor_out(0)); u2:nor2v PORT MAP(nor_out(0),nor_out(0),nor_out(1)); u3:nor2v PORT MAP(nor_out(1),nor_out(1),nor_out(2)); u4:nor2v PORT MAP(nor_out(2),nor_out(2),nor_out(3)); u5:nor2v PORT MAP(nor_out(3),nor_out(3),nor_out(4)); OUT1 <= nor_out(4); OUT2 <= nor_out(1); END struct;



-- INITIAL TOP-LEVEL DESIGN INCLUDING ONLY RING OSCILLATOR LIBRARY mgc_portable ; USE mgc_portable.qsim_logic.ALL ; ENTITY ring_vhdl IS PORT( ring_osc_enb : IN qsim_state;

OUT1, OUT2 : OUT qsim_state; ); END ring_vhdl; ARCHITECTURE struct OF ring_vhdl IS COMPONENT OSCILLATOR PORT (ENB: IN qsim_state; OUT1, OUT2 : OUT qsim_state); END COMPONENT; signal osc1, osc2 : qsim_state; FOR u1: OSCILLATOR USE ENTITY

WORK.ring_oscillator_vhdl(struct); BEGIN u1:OSCILLATOR PORT MAP(ring_osc_enb,osc1,osc2); OUT1 <= osc1; OUT2 <= osc2; END struct; -- 4 BIT SHIFT REGISTER WITH PRESET LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY shift_vhdl IS PORT( data_in, clock, preset : IN qsim_state; shift_out : OUT qsim_state_vector(0 TO 3)); END shift_vhdl; ARCHITECTURE behav OF shift_vhdl IS CONSTANT Tdelay : time := 10 ns; -- Typical delay BEGIN check_clock : PROCESS(clock, preset) VARIABLE internal_out : qsim_state_vector(0 TO 3); BEGIN IF (preset = '1') THEN internal_out := "1111"; ELSIF ( clock'last_value = '0' and clock = '1' ) THEN internal_out(3) := internal_out(2); internal_out(2) := internal_out(1); internal_out(1) := internal_out(0); internal_out(0) := data_in; END IF; shift_out <= internal_out AFTER Tdelay; END PROCESS check_clock; END behav;



-- 4 BIT COUNTER WITH RESET LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY count4_vhdl IS

PORT(clock, reset : IN qsim_state; data_out : OUT qsim_state_vector(0 TO 3));

END count4_vhdl; ARCHITECTURE behav OF count4_vhdl IS

CONSTANT Tdelay : time := 10 ns; -- Typical delay BEGIN check_clock : PROCESS(clock, reset) VARIABLE count : qsim_state_vector(0 TO 3) := "0000"; BEGIN IF ( reset = '0') THEN count := "0000"; ELSIF ( clock'last_value = '0' and clock = '1') THEN IF (count = "1111") THEN count := "0000"; ELSE count := count + "0001"; END IF; END IF; data_out <= count AFTER Tdelay; END PROCESS check_clock; END behav; -- 2 INPUT XOR COMPONENT LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY xor2_vhdl IS

PORT(A, B : IN qsim_state; Y : OUT qsim_state); END xor2_vhdl; ARCHITECTURE behav OF xor2_vhdl IS

CONSTANT Trise: time:= 20 ns; -- Typical delay, 0-1 transition CONSTANT Tfall: time:= 20 ns; -- Typical delay, 1-0 transition

-- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project BEGIN xor_inputs : PROCESS (A,B) BEGIN IF (A XOR B) = '0' THEN Y <= '0' AFTER Tfall; ELSIF (A XOR B) = '1' THEN Y <= '1' AFTER Trise; END IF; END PROCESS xor_inputs; END behav;



-- OTHER COMPONENTS -- 2 INPUT AND GATE LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY and2_vhdl IS PORT(A, B : IN qsim_state; Y : OUT qsim_state); END and2_vhdl; ARCHITECTURE behav OF and2_vhdl IS CONSTANT Trise: time:= 8 ns; -- Typical delay for 0-1 transition CONSTANT Tfall: time:= 6 ns; -- Typical delay for 1-0 transition -- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project -- Their values must be adjusted to correspond to the Mietec design. BEGIN PROCESS (A,B) BEGIN IF (A AND B) = '1' THEN Y <= '1' AFTER Trise; ELSIF (A AND B) = '0' THEN Y <= '0' AFTER Tfall; END IF; END PROCESS; END behav; -- 3 INPUT AND GATE LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY and3_vhdl IS PORT(A, B, C : IN qsim_state; Y : OUT qsim_state); END and3_vhdl; ARCHITECTURE behav OF and3_vhdl IS CONSTANT Trise: time:= 9 ns; -- Typical delay for 0-1 transition CONSTANT Tfall: time:= 9 ns; -- Typical delay for 1-0 transition -- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project -- Their values must be adjusted to correspond to the Mietec design. BEGIN PROCESS (A,B,C) BEGIN IF (A AND B AND C) = '1' THEN Y <= '1' AFTER Trise; ELSIF (A AND B AND C) = '0' THEN Y <= '0' AFTER Tfall; END IF; END PROCESS; END behav;



-- SIMPLE INVERTER LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY inverter_vhdl IS PORT(A : IN qsim_state; Y : OUT qsim_state); END inverter_vhdl; ARCHITECTURE behav OF inverter_vhdl IS CONSTANT Trise: time:= 5 ns; -- Typical delay for 0-1 transition CONSTANT Tfall: time:= 5 ns; -- Typical delay for 1-0 transition -- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project -- Their values must be adjusted to correspond to the Mietec design. BEGIN PROCESS (A) BEGIN IF (A) = '1' THEN Y <= '0' AFTER Tfall; ELSIF (A) = '0' THEN Y <= '1' AFTER Trise; END IF; END PROCESS; END behav; -- 2 INPUT INCLUSIVE OR GATE LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY or2_vhdl IS PORT(A, B : IN qsim_state; Y : OUT qsim_state); END or2_vhdl; ARCHITECTURE behav OF or2_vhdl IS CONSTANT Trise: time:= 6 ns; -- Typical delay for 0-1 transition CONSTANT Tfall: time:= 6 ns; -- Typical delay for 1-0 transition -- Trise and Tfall values are indicative and may not apply to the -- Mietec process used in this project BEGIN PROCESS (A,B) BEGIN IF (A OR B) = '0' THEN Y <= '0' AFTER Tfall; ELSIF (A OR B) = '1' THEN Y <= '1' AFTER Trise; END IF; END PROCESS; END behav;



-- D-TYPE BISTABLE (WITH RESET) LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY d_ff_rl_vhdl IS

PORT(clock, reset, data_in : IN qsim_state; data_out, data_out_bar : OUT qsim_state);

END d_ff_rl_vhdl; ARCHITECTURE behav OF d_ff_rl_vhdl IS CONSTANT Tdelay : time := 10 ns; -- Typical delay BEGIN

PROCESS(clock, reset)

BEGIN IF ( reset = '0') THEN data_out <= '0'; data_out_bar <= '1';

ELSIF ( clock'last_value = '0' and clock = '1') THEN data_out <= data_in AFTER Tdelay; data_out_bar <= NOT data_in AFTER Tdelay;

END IF; END PROCESS; END behav; -- COMPLETE COUNTER AND COMPARATOR DESIGNS ARE LEFT -- TO INDIVIDUAL DISCRETION. TEMPLATE DESIGNS MAY -- BE BASED ON THE METHODS OUTLINED ABOVE -- AND THE OUTLINE SPECIFICATION -- PROVIDED BELOW



-- BASIC VHDL TEMPLATEs FOR SIMPLE DIVIDER -- Note that behavioural and structural models are presented. -- BEHAVIOURAL MODEL -- For reference, one approach to implementing a Behavioural -- model for a divider is shown below LIBRARY mgc_portable; USE mgc_portable.qsim_logic.ALL; ENTITY ClockDivider IS generic(Modulus: in Positive range 2 to Integer'High);

PORT( ClkIn: in qsim_state; Reset: in qsim_state; ClkOut: out qsim_state); END ClockDivider; ARCHITECTURE behav OF ClockDivider IS begin process (ClkIn, Reset)

variable Count: Natural range 0 to Modulus-1; begin if Reset = '1' then

Count := 0; ClkOut <= '0';

elsif ClkIn = '1' and ClkIn'event then if Count = Modulus-1 then

Count := 0; else

Count := Count + 1; end if;

if Count >= Modulus/2 then

ClkOut <= '0'; else

ClkOut <= '1'; end if;

end if; end process; end behav;



-- STRUCTURAL MODEL -- STRUCTURAL TEMPLATE FOR TOP-LEVEL DESIGN -- NOTE: This template is indicative only and will -- need considerable adaptation for your purposes -- In particular, the size of state_vectors, counters & comparators -- will depend on the level of design chosen -- It will need further extension for a pulse-swallow design LIBRARY mgc_portable ; USE mgc_portable.qsim_logic.ALL ; ENTITY top_vhdl IS PORT( ring_osc_enb, reset : IN qsim_state;

OUT1, OUT2, DIV_out : OUT qsim_state; Compare_inputs : IN qsim_state_vector(0 TO ??) ); END top_vhdl; ARCHITECTURE struct OF top_vhdl IS COMPONENT OSCILLATOR PORT (ENB: IN qsim_state; OUT1, OUT2 : OUT qsim_state); END COMPONENT; COMPONENT COUNTER PORT (clock, reset: IN qsim_state;

data_out : OUT qsim_state_vector(0 TO ??)); END COMPONENT; COMPONENT COMPARATOR PORT (compare_A : IN qsim_state_vector(0 TO ??);

compare_B : IN qsim_state_vector(0 to ??); comp_out : OUT qsim_state);

END COMPONENT; COMPONENT CONTROL_LOGIC

PORT(comp_in, ext_reset : IN qsim_state; reset : OUT qsim_state);

END COMPONENT; signal osc1, osc2 : qsim_state; signal divider_out : qsim_state; FOR u1: OSCILLATOR USE ENTITY

WORK.ring_oscillator_vhdl(struct); FOR u2: COUNTER USE ENTITY

WORK.count??_vhdl(struct); FOR u3: COMPARATOR USE ENTITY

WORK.comparator_vhdl(struct); FOR u4: CONTROL_LOGIC USE ENTITY

WORK.control_logic_vhdl(struct); BEGIN u1:OSCILLATOR PORT MAP([to be completed] osc1, osc2); u2:COUNTER PORT MAP([to be completed]);

u3:COMPARATOR PORT MAP([to be completed]); u4:CONTROL_LOGIC([to be completed]); OUT1 <= osc1; OUT2 <= osc2; divider_outputs <= DIV_out; END struct;





Computer-based project in VLSI Design Lab Guide 3 - Transistor schematics

D M Holburn May 2007 EN2002 75 C6lab3.doc

Computer-Based Project in VLSI Design Co 3/6 Laboratory Guide 3 - Transistor schematics

This laboratory guide introduces the Mentor Graphics Design Architect application for the capture and manipulation of transistor level schematics. Lab session 4, which follows, will focus more directly on the use of Design Architect itself. Here we use the tool to investigate the transistor level schematic for the 2 input NOR gate, to be designed as a CMOS mask set, and explore some of the key constraints that govern the design procedure. The information gathered in this session forms an important part of the First Interim Report.

This lab session is divided into three sections.

Section I Familiarisation with Design Architect. Print out schematics. Section II Determination of correct design parameters for transistors in nor2t. Section III Adaptation of the nor2t schematic for use in later sessions.

Once you have investigated the transistor-level specification of the 2 input NOR gate and generated a printed copy of the schematic (Section I), a substantial part of the work covered in this guide can be completed off-line, away from the workstation. Only a brief session is required at the workstation in order to gather the necessary information.

You should be logged in at a workstation as described in the Getting Started chapter, with both Design Manager and Design Architect running, but with no schematic or symbol window open.

Section I - Familiarisation with Design Architect

1. Open the existing sheet nor2t. Click on the OPEN SHEET button in the palette window. The Open Sheet

dialogue box appears. Fill in the Component Name box with: $CBT_WD/nor2t. Leave the sheet name as sheet1 and OK the dialogue box. When the Edit window appears, study the resulting schematic. You should see

wires and ports similar to those used in the schematics of earlier sessions, but notice that the components used are those corresponding to standard p-type and n-type MOS transistors rather than logic gates.

You will find it useful to generate a printed copy of the schematic for later study. The following sections describe how to obtain printed schematics.

2. Set up Design Architect for printing

First review the material in the Getting Started document on Generating Hardcopy, which introduces some general concepts.

In order to set up Design Architect for printing, give the command: (menu bar) MGC > Setup > Printer. When the Setup Printer dialogue appears, enter the Printer name in the corresponding text box. Normally this will be mgcps_a4. Leave the number of copies set at 1 - the utility mgcplot will provide a means for printing a copy for each team member. Check that the Object Type is set to Design, and that Scale is set to Fill Page. Orientation should be set to Best Fit;



you may ignore the Panel Name box and the Priority and Notification settings. OK the dialogue.

3. Issue the Print Sheet command In order to print the sheet, give the command (menu bar) File > Print Sheet: When the Print Object prompt bar appears, verify that it contains the correct printer name, and correct if necessary. OK the prompt bar. A status message should confirm that operation has been successful.

4. Preview and print the resultant output As discussed in the introductory document, a special procedure is required to send the resultant postscript file to a suitable printing device. This is accomplished with a local utility, mgcplot. Open a new X terminal window, and when the Unix prompt appears, give the command: mgcplot. For the moment, press Enter when asked if you wish to process colour or A3 plots. Examine the list of output files you have so far generated, and select one by number. Mgcplot will now prompt you with a numbered list of output possibilities, including a Preview to Screen. You are recommended to use this to verify the results before committing them to paper. When you are ready, exit the ghostview Preview utility, and choose a printer if appropriate.

You can defer printing until a later session if you prefer. However, note that you must run mgcplot on the same server as that which was used to give the Print Sheet command in paragraph 4.

Note: Unless you hear to the contrary, only the A4/monochrome printing options are available.

The remainder of the work in this Lab Guide consists of design exercises and should be completed away from the workstation.



Section II - Determination of Design Parameters Exercises (to be completed away from the workstation)

The principles of the design of simple logic gates using MOS transistors have been covered briefly in the introductory lecture and in the pamphlet Logic gates in CMOS. You are now asked to explore how these principles apply to the detailed design of the two input NOR gate. The information gathered in the following sections will form an important contribution to the First Interim Report.

Use a printed copy of the nor2t schematic for the following exercises. Exercise 1

• Determine the function of the ports A, B and Y. • Identify the two different polarities of transistor, annotating your copy. • Identify also the electrodes G, D and S on each transistor and annotate your

schematic accordingly. • What is the significance of the fourth electrode shown on each transistor, and

why are they connected as shown?

Exercise 2

Construct a table indicating the state of conduction or non-conduction for each transistor with every possible combination of logic inputs, using the normal convention that logic 0 corresponds to 0 V, and logic 1 corresponds to 5 V.

Hence confirm the logical function of the gate.

What further information is required to determine the transfer function of the gate (i.e output voltage as a function of input voltage)? Exercise 3

Some simple rules of thumb were given in the introductory lecture concerning MOS transistor channel conductances. The dimensions of the two transistors connected to ground are shown (units are micrometres). Using the process information appended to this sheet, determine the approximate conductance of each of these devices when conductive. Exercise 4

Assume that the drain electrodes and associated interconnect linked to the output terminal of the nor2 gate can be represented by a capacitance of 0.1pF (we shall determine this value much more accurately in a later section). Hence, using the simple approximations given in the lecture, deduce the approximate delay before the output terminal falls to logic 0 when:

• one input is brought abruptly to logic 1 (does it matter which input? Explain, qualitatively);

• both inputs are brought abruptly and simultaneously to logic 1.



Exercise 5

Now consider the remaining two transistors, whose dimensions are not specified. These are to be chosen such that the output delay observed when both inputs are brought abruptly to logic 0 (i.e. for a rising output) matches the falling delay when a single input is brought to logic 1 - see Exercise 4.

Using the Mietec CMOS24 process information appended, which includes numerical values for the mobility µ for n and p-type devices, determine plausible values for the W dimension of these transistors, assuming that L is fixed at 3µm for all transistors. Where appropriate, refer also to the data supplied for the Mietec NOR2 gate.

Exercise 6

Discuss briefly what determines the magnitude of the current drawn from the power supply (represented by a voltage source 5V). How does this depend on:

• the precise voltage at the inputs? • the nature of the input waveform?

Using the concepts introduced in Logic gates in CMOS, estimate the worst-case current consumption for a single gate of this specification if it were to be used in your ringarray design. Assume for the moment that the gate output is a regular pulse train of period 50 ns (but note that your actual design may operate at a different frequency). You will have to make reasonable assumptions about other circuit parameters, which you should attempt to deduce from the information supplied. State any assumptions you make.

To what power dissipation does this correspond? What would be the current and power consumption of an integrated circuit consisting of 100,000 gates* of these characteristics, all operating under the same conditions? Comment! *Note that this corresponds to about 400,000 transistors, representing a comparatively simple circuit compared with, say, the Intel Pentium which now has upwards of 10 million transistors! However, in such a device as the Pentium, only a proportion of the devices would be configured as combinational gates.



Mietec CMOS24 process information The IC process CMOS24 employed in this project is supplied by Mietec-Alcatel. It defines a CMOS technology comprising p- and n- channel devices, which may be designed with channel length L of 3 µm minimum, and channel widths W also 3 µm minimum. These minimum dimensions represent a simple example of design rules, a collection of critical measurements and other constraints that must be satisfied by any IC layout if it is to be manufactured. The juxtaposition of layers required to form transistors will be described briefly in a lecture, and some details of the Mietec design rules will also be discussed.

The CMOS24 process offers two separate layers of metallisation (METAL1 and METAL2) to simplify layout of complex interconnections. In addition, the process provides for two separate layers of polysilicon (POLY1 and POLY2). POLY1 is used to fabricate the MOSFET gate electrodes, and it can also be used as interconnect for signals over short distances – say, 20 µm. Special structures known as vias (conceptually similar to plated-thru holes in PCBs) are used to make connections between layers. POLY2 is used primarily for implementing high value parallel-plate capacitors, and will not be mentioned further. The availability of two metal interconnect layers, plus polysilicon gives a topological freedom rather greater than that found with two layer printed circuit board technology. The Mietec process has design rules for metal and polysilicon interconnect layers, and for vias; these broadly specify layer widths and spacings which ensure that with expected processing tolerances, tracks are guaranteed to be conductive (no breaks) and adjacent tracks will not short-circuit.

The fundamental electrical characteristics of the process are given below. More complete details are available in the lab if needed. Supply rail voltage Vdd 5 volts

Mobility µp 0.023 m2V

–1s

–1

µn 0.061 m2V

–1s

–1 Gate capacitance per unit area Cox 8.2 × 10 –4 F m –2 = 0.82 fF/µm2

Gate oxide thickness tox 40 × 10 –9 m

Threshold voltage VTn +0.9 V

VTp –0.85 V

Interconnect capacitance per unit area metal 1 - substrate Cm1 0.02 fF/µm2 polysilicon-substrate Cp 0.045 fF/µm2

Interconnect sheet resistance metal 1 Rm1 25 × 10 –3 Ω/square polysilicon Rp 23 Ω/square



Section III - Adaptation of the nor2t schematic

This part of the laboratory guide returns to the use of the Mentor Graphics Design Architect application in the capture and modification of transistor level schematics for the 2-input NOR gate which will later be designed as a mask layout. Correct transistor-level schematics are required for two main reasons:

• For comparison against the layout to check its correctness (LVS) • To receive the back-annotation data obtained from the layout in the form of

parasitic capacitances, for the purposes of detailed simulation with AccuSim.

When you complete this short session, you will have successfully adapted the nor2t schematic supplied part-completed for use in later simulation phases. You can carry out this activity at any time, but be sure to read the notes below which inform you of important actions which must be carried out before you start.

Important Before you begin this section, you should be sure you understand the simple treatment of delays in CMOS logic gates and the simple techniques for obtaining equalised worst-case delays by attention to transistor channel dimensions (W/L) covered in the pamphlet Design of logic gates in CMOS. You should have studied the schematic and Mietec process information in Laboratory Guide 3, Section B – Determination of design parameters, and you should have carried out exercises 1-6 above.

Don’t begin this session until you have attended to these points.

To begin, you should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. The current Mentor Working Directory should be $CBT_WD. Design Architect should also be running, but with no schematic or symbol window open.

1. Open the existing sheet nor2t. Click on the OPEN SHEET button in the palette window. The Open Sheet

dialogue box appears. Fill in the Component Name box with: $CBT_WD/nor2t. Leave the sheet name as sheet1 and OK the dialogue box.

2. Edit the MODEL properties of the four MOS transistors. As supplied, the nor2t schematic contains insufficient information about the

electrical characteristics of the transistors for successful simulation of the device’s behaviour using AccuSim. Channel width and length dimensions are incomplete; moreover, there is no indication of the physical characteristics of the devices - for example, the channel mobility, specific capacitances, etc. This information is provided in a set of technology files, normally by the manufacturer, and it is necessary to identify in the schematic a model name by which the required parameters can be accessed.

In the Mietec process, n- and p-type transistors have model names: tr_n and tr_p.

Use the command: (Menu bar) > Edit > Edit commands > Properties > Change Text Values - or any equivalent technique - to change the model name for each transistor to the correct value.



3. Edit the INSTPAR property. AccuSim requires information from the schematic about the dimensions L and W

of each MOS transistor, which it obtains from the INSTPAR property. If this information is not given explicitly, the transistor channels are assumed by AccuSim to have dimensions 1m × 1m. The INSTPAR property is of the form:

L=xU W=yU

where x and y are suitable dimensions (basic units are metres) and the suffix U represents a multiplier of 10-6. Use an appropriate property editing command to change the value of these properties to the values you calculated in the Exercises of Lab Guide 2a.

4. Check the resulting schematic visually, and confirm that the connections, models and properties are correct. In later lab sessions you will rely on the correctness of this schematic and its properties in a procedure which verifies the characteristics of an IC mask layout, so it is vital that it contain no errors or omissions.

Use the appropriate Design Architect command to perform a syntax check on the sheet (but bear in mind that it will not warn you of incorrect model names or ridiculous dimensions). Save the modified nor2t schematic. Generate a hard copy using the procedure outlined earlier.

For the time being this completes the work required on the transistor-level specification of the 2-input NOR gate. We shall return to this when we consider how to design the physical layout of the 2-input NOR gate, for the purposes of comparison and simulation using ICtrace, ICextract and the AccuSim simulator. First interim report

The first interim report will comprise the formal specification for the ringarray ring oscillator integrated design. You should therefore be sure you have read and understood the foundation material in the introductory sheets, and that you are confident you know what the basic design criteria are. The report should also include: • the results of VHDL modelling (described in Lab Guide 2), • exercises in pamphlet: Design of logic gates in CMOS & Lab Guide 3 (above), • annotated printouts of the transistor-level schematics produced so far, printed

using the procedure introduced in this Guide. The information gathered while carrying out Lab sessions 1, 2 and 3 should be of considerable help in compiling your report.

Please note that full digital schematics (described in Lab Guide 4) and material on QuickSimII digital simulation (described in Lab Guide 5) should be kept for the Second Interim Report.

Please refer to the CamTools VLSI Web to access the latest information about recommendations for the first interim report.



Computer-based project in VLSI Design Lab Guide 4 – Digital Schematics

D M Holburn Apr 2007 EN2002 83 C6lab4.doc

Computer-Based Project on VLSI Design Co 3/6 Laboratory Guide 4 – Digital schematics with Design Architect

This laboratory guide provides further experience in the use of the Mentor Graphics Design Architect package, emphasising its value for digital schematic capture and symbol creation. In this session you will create a schematic specification and a symbol corresponding to the ring oscillator element, ring_oscillator. You will then be able to use a similar approach to develop the remaining parts of the design (relating to the programmable frequency synthesiser). Finally, you will create a component, named top_level, in which all the elements of the target design are embodied. When you complete the session, you should have a complete schematic representation for the programmable divider unit, which includes the ring oscillator design and all its supporting elements.

Before you commence work with Design Architect, it is necessary to give some thought at this point to the form of the schematic sheet for the ring_oscillator module. This may usefully be done off-line, away from the workstation. Review the results of Lab Session 2, and, if necessary, consult the Ring Oscillator Specification pamphlet, which describes the system requirements for the ring oscillator. Then draw a rough sketch of your proposed schematic. Although the appearance of the schematic has no bearing on the functionality of the entity it represents, a neat and regular diagram clearly contributes to the process of understanding its operation. Show your plan to a demonstrator before you enter it into Design Architect.

Once this paper design is complete, you should log in at a workstation and start up Design Manager, as described in the Getting Started pamphlet.

1. Start Design Architect. Select the design_arch icon in the Tools window, and either double click it, or give the command: (menu bar) Object > Open.

Iconise Design Manager. When the Design Architect window appears, drag and resize it to a convenient format. Note the availability of (menu bar) commands, soft keys (listed at the foot of the screen), and command palette (column at right).

2. Open the supplied sheet for the top_level design, by clicking on the OPEN SHEET button in the palette window. The Open Sheet dialogue box appears.

Fill in the Component Name box with: $CBT_WD/top_level. Leave the sheet name as sheet1 and OK the dialogue box. A new Edit window

appears, containing the sheet, which is an incomplete version of the target design. Spend a few moments examining the contents. You should see:

• Input pads (column at left hand side) • Output pads (column at right hand side) • Power and ground pads (top)

Input and output pads provide a means of making a physical connection (i.e. with wires or printed circuits) to the on-chip circuitry. Power and ground pads have pre-defined functions in terms of providing supply current, and certain input pads and output pads have already been assigned to functions; in each case, the yellow NET property indicates the name anticipated for the signal. Designers are at liberty to change these, by editing the corresponding property – see below – but this will need to be taken into account in later sections. A few pads have not



been allocated (their NET property name is still the default: Net); it will be up to each design group to determine a suitable allocation of those pads to the remaining input and output signals. Note: The physical sites of the pad cells have been pre-determined (through the Place property) – for example, L1 – to avoid problems at the layout stage. You should avoid editing the properties of these components indiscriminately. Ask a demonstrator if you cannot identify these items, or if you have a question.

3. Refer to the block diagram Figure 1 (page 29), which depicts the logic modules required by the design, and lists the signal inputs and outputs that are needed. You will see that certain key items are omitted from the schematic sheet for the top_level design, including the counter, the shift register, the ring oscillator module, and certain other gates. Nor is there any indication of how the modules are to be connected. These deficiencies will be remedied during the course of this session.

4. Find the Mietec library components. At this stage, the 2 input NOR gate to be used is a primitive component contained

in a large library of components supplied by Mietec Alcatel. Each item in the library has a characteristic graphic symbol, and an assortment of properties, which specify its various electrical and other characteristics. The library is held in a collection of design files and directories in a fixed place in the Mentor filespace, and is accessible to any designer for reading, but cannot be changed. Later in this project, we shall substitute in place of this library item a NOR gate of our own design and with properties which we shall determine through a detailed modelling procedure.

Give the command (menu bar) Libraries > Mietec Library. The palette should now show CMOS24, the product name given by Mietec to this library (which is built using CMOS technology with transistors of gate length 2.4 µm).

Click on: CMOS24 > Digital Cells > Core Cells > Simple Gates. If necessary, enable scroll bars on the resulting palette menu by using the menu

item Show Scroll Bars available on the right mouse button. Before proceeding, note that you can ascend through the sequence of library

menus by using the (pull down) Back menu item, accessed with the right mouse button (Menu). Using this facility, investigate the library menus and explore the variety of gates provided in the Mietec library. Ask a demonstrator for details of any gates whose purpose is not clear. When ready, return to Simple Gates.

5. Place a 2 input NOR gate. Click on NOR2. The ADD INstance prompt bar appears at the foot of the screen with the At

Location box highlighted in red. Move the cursor onto the sheet; a ghostly image of a NOR2 will follow the cursor. Click to drop the component in a suitable location, somewhere near the bottom of the sheet.

Note the Active Symbol window now shows a NOR2 symbol. To place a further NOR2 you can click in the Active Symbol window, then position the ghostly image as above. You can reposition the symbol once placed by clicking it to select it, then depressing the Alt key followed by the middle mouse button.

You will need to use these procedures again when creating the ring_oscillator schematic discussed later.



6. Wire up the NOR gate The inputs and outputs of the NOR gate are to be connected (via input or output

pads) direct to external pins. The input and output pads (library components) have already been placed on the sheet. Each is connected to a pin element described as a portin or a portout, as appropriate, signifying an external connection to the system. Each has a property NET, which needs to be assigned an unambiguous symbolic name for the benefit of downstream simulation tools. Examine the schematic and determine convenient pins for the NOR gate.

Unselect all by pressing function key F2. Give the command: (menu bar) Libraries > Display Schematic Palette. With

the ADD/ROUTE palette displayed, click the Add Wire icon. If you prefer, you can instead use (Pulldown) ADD > Wire, or press function key F3 to begin wiring. The ADD WIre prompt bar and a wiring cursor (cross) will appear. To connect two points, click on the first point, click on any intermediate points, and double click on the last point to finish the wire.

The ADD WIre prompt bar remains until cancelled; the next wire can then be placed immediately without the need to issue the Add Wire command again.

If you are not satisfied with the appearance of you hand-drawn wires, you can delete them and try again. Alternatively, with the wires selected (left click), you can use the ROUte SELected command in the ADD/ROUTE palette to snap them to the internal grid.

7. Change the NET property You must now change the NET property for the newly wired pins, as described,

to represent appropriate external names. The suggested names are A, B and NOR. You can if you wish use names of your own choosing, but if you do so you must be prepared to substitute the appropriate names in all later parts of the session. To do this, first unselect all. Give the command:

(Menu bar) Edit > Edit Commands > Properties > Change Text Values. A Change Text Values dialogue box appears, showing a single text box. Enter

A in this box, and a further box will appear. Use the mouse to get to it and enter B. Enter NOR in a similar way. OK the dialogue box.

A sequence of messages (in the message area) and prompt bars will then appear asking you to position the items of text. Click on the appropriate instance of NET to change the property. Repeat this for the two remaining pins.

You can use the same procedure if you wish to change the NET properties assigned to any of the other pins.

8. Save the work done so far It is wise before proceeding to save the work done so far. Design Architect

encourages the designer to perform a number of elementary checks on the schematic before it is saved. Although at this stage the design, being incomplete, will generate a number of warning messages, we shall execute the check nonetheless. Give the command: (Menu bar) Check > Sheet > With Defaults.

A window will appear, reporting the results. There should be no errors. You can safely ignore the warning about unconnected pins, as these will be resolved later. Ask a demonstrator if you encounter errors or unexpected warnings.

Close the report window. Give the command: (Menu bar) File > Save Sheet > Default Registration to save the part-completed sheet. Repeat this procedure at any time to save your work.

9. Place a counter component on the sheet.



The counter is provided in your design directory under the name 4bit_counter. This is not itself a library component, but is a hierarchical element, itself consisting of a set of primitive library parts. In contrast with the NOR2 part, it can be explored and edited in just the same way as the top_level schematic you are currently editing. You will later have an opportunity to make a minor modification to the 4bit_counter schematic using Design Architect.

Since the counter is not actually a part of the Mietec library, a different procedure has to be adopted to incorporate it.

Give the command: (menu bar) Libraries > Display Schematic Palette. Click the Choose Symbol icon in the palette. Note: depending on the size of the

Design Architect window, you may need to enable scroll bars to see this icon. A Navigator dialogue box opens. Select the 4bit_counter component, and OK

the dialogue box. Position the ghostly image that appears in an appropriate site and drop it by

clicking. OK the ADD INstance prompt bar.

10. Wire up the counter Use the wiring technique described above to link all four outputs of the counter

and its RB input to suitable pins. Edit the NET property of each associated pin to an appropriate name (see the block diagram in figure 1).

Check the sheet and save.

11. Try to add the ring_oscillator block. At this stage it is necessary to add the ring_oscillator block, representing the

ring oscillator module. Note that ring_oscillator is not in the Mietec library, nor is it provided in your working directory. Verify this by using the Add instance procedure just described, and cancel the dialogue box when ready.

You will therefore have to create a symbol by which to represent the ring oscillator, and define its content in terms of library elements (2 input NOR gates NOR2). Both these operations can be accomplished using Design Architect.

As stated before, we shall later substitute a 2 input NOR gate of our own design.

12. Compose the ring_oscillator schematic For convenience, we shall first create the ring_oscillator schematic, to define its

content in terms of logic gates. We shall then create a symbol, also named ring_oscillator, to represent the ring_oscillator entity within the top-level schematic top_level.

Mentor keeps these separate but related design entities in a container (actually a sub-directory) so that they may be accessed conveniently.

Give the command: (Menu bar) Libraries > Display Schematic Palette. Click the Session icon in the palette; the title bar of the top_level daughter window will grey as that window is temporarily de-activated.

Click on Open Sheet in the palette. When the dialogue box appears, fill in the name ring_oscillator, leave the sheet name as sheet1, and OK the dialogue. A new sheet appears (overlaying the inactive top_level sheet).

13. Enter the ring_oscillator schematic You should by now have given consideration to the form of the schematic for the

ring_oscillator module. If not, review the material at the start of this sheet, and carry out this part of the design, away from the workstation.

14. Place and wire the necessary primitive gates



You will need to place a number of primitive gates from the Mietec library and wire these together. The detailed instructions for doing this will not be repeated here. Carry out these operations using the placing and wiring techniques practised earlier.

Be sure to check and save your work from time to time.

15. Place portin and portout elements On this occasion, you will also need to place portin and portout elements which

allow the input and output signals from the module to be made available in the ring schematic sheet. These are provided in the CMOS24 library, under: CMOS24 > Digital Cells > Schematic.

Note that input and output pads are not required in this part of the design, since these are provided in the higher-level schematic sheet top_level. This is an important consequence of the hierarchical approach we have chosen for the design process.

Place and wire the portin and portout elements just as you did the NOR2 cell, and edit the NET property on each to an appropriate name (see Figure 1).

Check the sheet. Once it is complete, there should be no errors and no warnings. When you are satisfied, save the ring_oscillator sheet, but do not close the schematic window just yet.

16. Generate a symbol for ring_oscillator In order to represent ring_oscillator within the top_level schematic, we require a

suitable symbol. In the hierarchical design process, the symbol serves to conceal the complexity of the underlying logic and provides a clean and well-understood interface to other symbols. We shall use Design Architect's inbuilt facility for generating a symbol from an existing schematic.

Give the command: (menu bar) Miscellaneous > Generate Symbol. Observe the Generate Symbol dialogue box which appears, but do not change

anything. OK the dialogue box. A new symbol editing window should appear showing an automatically generated symbol for the ring_oscillator component, with pins matching the input and output ports on the schematic sheet.

Give the command: (menu bar) Check > With Defaults. There should be no errors, but you may observe some benign warnings appertaining to the symbol's interface. Close the results window, and save the symbol using the command: (menu bar) File > Save Symbol > Default Registration. This operation also registers the interface exposed by the symbol so it can be reconciled with any schematic in which it appears. Note that if you now repeat the check operation carried out prior to saving, it generates no warnings, indicating that the saved copy is correctly prepared. Close the symbol editing window, and resume editing the top_level schematic.

17. Place and wire an instance of ring_oscillator Now that a symbol and schematic have been prepared for ring_oscillator, it is

possible to wire up that component. Using the procedure you adopted for the 4bit_counter component, place an instance of the ring_oscillator component in a convenient position. Wire up its pins appropriately, and edit any NET properties that remain to be changed. Check and save the schematic.



18. Simulate the basic design using QuickSimII At this point we recommend you switch to Lab Guide 5, and familiarise yourself

with the general techniques needed for simulating the target design using the cmos24 digital cell library. This resembles the approach used in Lab 2, in which a basic design comprising the ring oscillator and a 4-bit counter was modelled in order to gain familiarity with the ModelSim VHDL environment.

It may be convenient to make use of time outside the scheduled sessions to plan the more elaborate programmable counter design, which will comprise more than one counter element, a comparator, and control logic. You will need to make a number of design choices and research the availability of suitable cmos24 library cells, details of which can be seen via the CamTools VLSI web board.

Once you have successfully accomplished this, you should return to Design Architect to complete entry of the schematic form of the synthesiser design. Several more components are required in order to complete the design as specified, representing the programmable counter stages, comparator and control logic. However, you are recommended to retain the basic experimental design just used for QuickSimII modelling. Use the Save Sheet As… command to save it under a different name – for example top_level_4bit – and resume your development using the top_level schematic cell.

19. Place and wire other instances as needed Several more components are required in order to complete the design as

specified. Although there are many possible ways of completing the design, we strongly encourage you to use a hierarchical approach, creating schematics and symbols as you proceed, and use a consistent naming structure. We recommend you use the following names, or derivatives of them: divider and comparator, and control, although it is perfectly possible to change these. The notes below and in subsequent Lab Guides assume that a naming structure of this form has been used. If you wish to use different names, you must be prepared to substitute in place of those given the names you have actually used in your design.

For the programmable divider, counters of 6 to 10 bits will be required. This is not supplied in a ready-to-use form, and you will need to find a way to implement it. One approach might be to use 4bit_counter as a model, and craft a schematic to provide n-bit counters, as selected for the target design. Another, possibly quicker, though less elegant approach, will be to craft larger counters using instances of the 4bit_counter cell, which is freely available in your cbt directory. A comparator element is also required. This would commonly be implemented using exclusive-OR or exclusive-NOR gates. Gates exor and exnor are the corresponding Mietec digital library cells. Certain other combinational and sequential gates may also be required to fulfil the final specification. Consult the CamTools VLSI web board for a summary of the library contents.

Using the procedure described in paragraphs 12 - 16, place the necessary instances, save the various schematic sub-cells, create symbols, and load any necessary instances into top_level. Wire up the pins of the new instances, and edit any NET properties that remain to be changed. Check and save the schematic.



20. Gather material for the Second Interim Report. Your report should include schematic diagrams and other design information, as

well as answers to exercises contained in the Lab Sheets and elsewhere. You should also list the primitive cells used by your design, and indicate the function of each. To assure yourself of this information, you may need to open the 4bit_counter and other schematics in Design Architect to get a view of the primitive cells each one contains. If you do this, be sure not to make any inadvertent changes to the schematic - i.e. do not save it at this stage. You can alternatively use Design Manager to list the cells by selecting either component and giving the command: (menu bar) Report > Hierarchy.

You may wish to generate printouts of the schematics and symbols created so far for inclusion in your Second Interim Report. The procedure is described below.

21. Predict the expected performance of the design Study the block diagram and specification of the top_level design (Figure 1).

Consider the specifications and schematics for the main modules of the design, viz. divider, comparator and control. Referring as necessary to the results of your VHDL simulations in Lab 2, sketch the waveforms you expect to see at each of the outputs of the design. Include these results in your Second Interim Report, but keep a copy. You will find this information useful in later phases of the design to compare against the results of numerical modelling, and hence for verifying correct operation of your design.

Printing out schematics or symbols

First review the material in the Getting Started document on Generating Hardcopy, which introduces some general concepts.

In order to set up Design Architect for printing, give the command: (menu bar) MGC > Setup > Printer. When the Setup Printer dialogue appears, enter the Printer name in the corresponding text box. Normally this will be mgcps_a4. Leave the number of copies set at 1 - the utility mgcplot will provide a means for printing a copy for each team member. Check that the Object Type is set to Design, and that Scale is set to Fill Page. Orientation should be set to Best Fit; you may ignore the Panel Name box and the Priority and Notification settings. OK the dialogue.

In order to print the sheet, give the command (menu bar) File > Print Sheet: (or Print Symbol:, as appropriate). When the Print Object prompt bar appears, verify that it contains the correct printer name, and correct if necessary. OK the prompt bar. A status message should confirm that operation has been successful.

The final stage of printing requires the use of mgcplot. Open a new X terminal window, and when the Unix prompt appears, give the command: mgcplot. For the moment, press Enter when asked if you wish to process colour or A3 plots. Examine the list of output files you have so far generated, and select one by number. Mgcplot will now prompt you with a numbered list of output possibilities, including a Preview to Screen. You are recommended to use this to verify the results before committing them to paper. When you are ready, exit the ghostview Preview utility, and choose a printer if appropriate.

If you wish to include output in your interim or final report, consider the option: Save a copy in your home directory, which will place a copy of the Postscript file in your



(personal) workspace. Note that it may be desirable for each team member to do this. Further processing of the Postscript files can be carried out with a range of Unix or Windows-based utlities, but this is beyond the scope of the lab guide!

Note: Unless you hear to the contrary, only the A4/monochrome printing options are available.

Computer-based project in VLSI Design Lab Guide 5 - QuickSim II



Laboratory Guide 5 - Digital Simulation with QuickSimII

This laboratory guide provides an introduction to the features of the Mentor Graphics QuickSimII digital simulator, and its uses in modelling digital systems and verifying their behaviour. When you complete this laboratory session, you should have confirmed the correctness of operation of your design – and made some perhaps unexpected discoveries about the characteristics of certain of the parts used.

You should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. Your ring oscillator schematic design (covered in Lab session 3) should be complete, checked and saved. If you have Design Architect running you should close it down for the time being.

QuickSimII cannot directly process the schematic files that comprise your ring oscillator design. Like many of the Mentor Graphics downstream tools, it requires a Design Viewpoint to be generated. A design viewpoint acts as a set of rules to enable a tool to interpret schematics correctly. It also acts as a container object in which information relating to the simulation can be held. A design viewpoint, together with a component (i.e. a set of schematic designs) is formally termed an Electronic Design.

The standard tool for creating design viewpoints is DVE. Certain simulators, including QuicksimII, are capable of creating their own viewpoints without the assistance of DVE. However, the viewpoints created in this way do not contain the links to the Mietec libraries that are required in order that proper simulation models are available. In other words, although it is possible to start up QuickSimII on a component based on Mietec parts without first running DVE, no simulation can be carried out under these circumstances.

1. Start QuickSim II on the top_level component. Select the top_level icon in the Navigator window, and use the (Navigator) >

Open > QuickSim II command to start up Quicksim II. Iconise Design Manager - it will be needed again. When the simulator window appears, resize it to a convenient format. Note, as with Design Architect, the availability of (menu bar) commands, soft keys (listed at the foot of the screen), and a palette of commands (column on right). A window entitled Info Messages should appear. Examine the messages it contains, which list references that could not be resolved owing to the absence in the viewpoint of any linkage to the Mietec libraries. This is the outcome typically expected when the default design viewpoint constructed by QuickSimII is found to be unusable with our design.

2. Cancel this unsuccessful QuickSimII run using the system icon or system menu. When a dialogue box appears asking if you wish to exit QuickSim either After Saving or Without Saving, click on the Exit without Saving button.

3. Restore the Design Manager window, or if you do not have an instance of Design Manager, start one now. Make sure that you have a Navigator window open on the $CBT_WD directory, and select the top_level.



4. Start up DVE to create a design viewpoint on top_level With the top_level selected in the Navigator window, use the command

(Navigator Window) > Open > DVE. When DVE starts up, resize its window to a convenient format, and examine the Design Configuration window that appears. This window lists any rules that have been set up for tools to use when interpreting the schematic. It contains four distinguishable fields, each corresponding to a different class of rule under the control of a design viewpoint; but note that all of the fields are empty. DVE has opened for you an empty design viewpoint named default; once prepared for use by means of the procedure below, it will be saved within the top_level.

5. Prepare a design viewpoint for top_level based on the Mietec library. Note that there exists a set of options within the (Menu Bar) > Setup pulldown

menu for setting up viewpoints. Although no harm will come if you select one of these options, you should not save the resulting design viewpoint. These options generate viewpoints based on the generic libraries supplied by Mentor Graphics which are not suited to our purpose. A further (Menu Bar) option has been provided specifically for this requirement. It consists of programmed statements (Userware) written by Mietec Alcatel for distribution to users of their device libraries. This userware is loaded automatically by DVE at startup, and results in the (Menu Bar) > Mietec pulldown menu.

Give the command: (Menu Bar) > Mietec Setup (Quick) Sim, Fault, Path and Grade. This operation generates a viewpoint for QuickSimII using Mietec components. Examine the several new rules that appear in the Configuration window.

6. Close the design viewpoint and save it. Click on the CLOSE VPT palette menu icon. A dialogue box will appear asking

if you wish to save changes to the viewpoint; click on Yes. Shut down DVE by using the system menu or by double clicking the system icon at top left of its window. The Design Manager session you used earlier should reappear.

7. Restart QuickSim II on top_level and its new viewpoint. If necessary, in Design Manager's Navigator window, re-select the top_level

component. Then start QuickSimII on that object by using the Open command as before. On this occasion, QuickSimII detects the pre-existing design viewpoint and does not attempt to create one automatically. Note that the Info Messages window does not appear, and the message: Design loaded successfully may be briefly visible in the message area. At this stage we shall confine ourselves to the ring oscillator part of the design; later you will have opportunities to simulate the design in its entirety, including the sequence generator and the Manchester encode/decoder.

8. Open a schematic window to view the design. Display the schematic view window for the top-level component in the design

(top_level) by giving the command: (Menu Bar) > File > Open Sheet; alternatively, use the OPEN SHEET palette menu icon. This schematic window provides a restricted set of Design Architect functions.



9. View the ring_oscillator component on the sheet. Select the ring_oscillator component in the Schematic window by clicking on it.

Use the (Session Window) > Open > Down menu item. A schematic view of ring_oscillator will be opened. When you are satisfied that it corresponds to your earlier work, minimise the ring_oscillator window to an icon to allow unrestricted view of the top-level component ring.

10. Trace some of the input signals to the top_level design. In the schematic view of top_level, use the left mouse button to drag a box

around (and hence select) the pins bearing the input signals to the NOR gate (at the left hand edge of the sheet). Give the (Menu Bar) > Add > Traces command. The Add Traces dialogue box should appear; if necessary, choose Selected Signals, and OK the box. Observe that a Trace window is displayed with the signals A and B (as yet inactive) contained in it.

11. Add the output signals to the Trace window. In the schematic view of top_level, drag a box around the pin bearing the single

NOR gate's output signal (at the right extremity of the schematic), and click on the TRACE button in the palette menu. This will add the new signal NOR to the Trace window. Note that no waveforms are yet visible, because the simulation has not yet begun. With all three pins selected, click on the LIST palette menu button to create a text window listing these signals. Note the highlighting of the selected signals in each window in which they appear.

12. Apply appropriate stimuli to the design. Create a clock to be attached to the input signal A on the single 2-input NOR

gate. Type the following with the mouse pointer positioned anywhere in the QuickSimII window, followed by Return.

set clock period 100

Set the first value of the clock (which is to be 0 at time 0). Type the following with the mouse pointer anywhere in the QuickSim II window, then Return:

force /A 0 0 -repeat

Now set the second value of the clock (which will be 1 at time 50 ns) by typing the following with the mouse pointer in the QuickSimII window, then Return:

force /A 1 50 -repeat

The -repeat argument calls for these values to be repeated at the same relative times, at intervals defined by the clock period. Now set up a periodic signal to be applied to input B. The combination of signals should exercise the NOR gate through all four possible input states so as to generate a truth table. Determine suitable values and timings for B, and enter them using the procedure just given, being sure to position the mouse pointer in the QuickSimII window before beginning to type.

Now set up the default simulation run time, by giving the following command: (Menu Bar) > Setup > Kernel > Run Parameters. In the resulting dialogue, set Run Time to 10000, and ensure that the Remove Default Run Value box is unchecked. OK the box. Finally give the command:

run 1000

and observe the Trace and List windows. Study the resulting traces carefully.



Question Are the observed traces fully consistent with your expectations for the NOR gate? Note your observations for inclusion in the next interim report.

In the schematic window, select the yellow net linking the NOR gate to the output circuitry and pin. Click the TRACE button. Note that the new trace will not bear the name NOR, but will be identified by a numeric code. If necessary, re-run the simulation, and compare the new trace with that from the NOR pin.

Question Can you account for any differences you observe? Discuss your findings with a demonstrator, and consider the implications this may have for your later observations of signals from the ring oscillator and four bit counter.

12. If required, generate a hard copy printout at this stage. Set up the printer using (Menu bar) > MGC > Setup > Printer ... as before; select the window containing the trace you wish to output, and give the command (Menu bar) > File > Print > Active Window ... When the Print Traces dialogue appears, confirm that the Print/Plot option is selected, and OK the dialogue. Use the mgcplot procedure to preview and print the result. Consult a demonstrator if you encounter difficulties with this procedure.

13. Investigate the behaviour of the ring oscillator and counter. The same procedures can now be extended to other parts of the design. Initially

we shall verify correct operation of the counter, since its outputs are required to drive the encoder and decoder. First determine which additional inputs and outputs are to be observed, select them and add them to your trace window, using the procedure described in paragraph 11. To generate appropriate stimuli, a similar approach to the method of paragraph 12 is required; in this case, force statements are required for the ENB_RING_OSC and RESET_COUNTER signals. You may be able to anticipate the specification required for these stimuli; if not, a little trial and error should quickly result in full operation. Run the simulation and examine the display carefully.

Question Determine the timing parameters T, t1 and t2. The intended values for these parameters were set out in the Ring Oscillator Specification

Do these match your expectations? Almost certainly not!

If any serious functional errors are apparent - e.g. no oscillations available under any circumstances, you may have made an error in one of the schematics. If this is the case, discuss the situation with a demonstrator. You will need to remedy any problems and rebuild the design viewpoint before you proceed. If (as expected) the only problems appear to be timing idiosyncrasies (e.g. unexpected oscillation frequency), you should proceed with the steps below.

14. Investigate QuickSimII's alternative timing modes. QuickSimII offers a number of different timing modes. When you enter via

Design Manager's Navigator window, a default Unit delay timing mode is entered in which all gates are assumed to have a delay of 0.1 ns. All technology files providing timing models for individual gates are ignored. All delays arising from parasitic capacitance are ignored. This mode has the advantage of minimum computing penalty and is therefore very fast even for very large



designs. It is well suited to the verification of truth tables and correctness of logic functions; however, the timing figures produced by it are quite arbitrary and give us no useful information about the likely speed of operation of our ring oscillator. We need to switch to a different timing mode.

Give the following command: (Menu Bar) > Setup > Kernel > Analysis. When the Setup Analysis dialogue box appears, click the Delay button. To see further details, click the Visible button. Discuss with a demonstrator if you wish. When ready, OK the dialogue box.

For later simulations of more elaborate designs (comprising counters, comparators, etc), you should be sure to use the Delay model, otherwise you may see unexpected results. Each time you enter QuickSimII to get detailed timing information, you will need to select the accurate timing model.

15. Re-run the ring oscillator/counter simulation run. You may wish to clear away previous traces and reset the simulator time back.

To do this, give the command: (Menu Bar) > Run > Reset. When the dialogue box appears, use the mouse to check only the state item, and uncheck the Save results item if necessary. OK the dialogue box.

Now re-run the simulation using either the run command, as before, or click the RUN icon in the palette. Study the resulting waveform, and determine the timing parameters for the ring oscillator.

Question Are the observed traces now fully consistent with your expectations for the NOR gate? Note your further observations for inclusion in the interim report.

If you find discrepancies between the observed timing of the ring outputs and your design specification, you may wish to study the timing information QuickSimII uses for each of the gates in ring_oscillator. To do this, select any gate that is of interest and give the command: (menu bar) Report > Timing… . When the Report Timing Info dialogue box appears, check the following buttons: Selected Objects, Kernel, and Source, then click OK. QuickSimII will display a report window from which you should be able to identify other factors that affect the timing. Note: this information is available only in the Delay timing mode. Discuss your findings with a demonstrator if necessary.

16. Detailed properties of the 4-bit counter Study also the outputs from the counter. Verify the relationship between its outputs and that of the ring oscillator. Verify that the counter reset function performs as expected.

Question Do you have any observations on the specifics of the counter's function? Discuss your findings with a demonstrator.

Generate printed copies of the traces for inclusion in your Second Interim Report using the procedure described above.

At this point you should return to Lab Guide 4 to continue development of the programmable divider specified for use in a frequency synthesiser. When the new design is complete, create a viewpoint for it according to paragraph 4, and resume verification by following the guidelines in paragraph 17 and following.



17. Investigate the operation of the programmable divider Devise simulation experiments to demonstrate fully the correct operation of:

(i) the ring oscillator enable function; (ii) the counter’s correct operation when programmed to execute a full-

scale count without reset; (iii) operation of the comparator for a range of different comparison values; (iv) correct resetting of the counter so it behaves as a pogrammable divider; (v) satisfactory output signal to feed to the (external) phase detector.

You will need to plan these experiments with some care, and it will be necessary to determine what combinations of signals need to be applied to system inputs (by means of force commands), and which outputs should be monitored. Above all, it is critical to consider what measures need to be taken to provide suitable initialisation (reset) signals for the sequential logic elements – counter, shift register, decoder, and so on. These are an essential prerequisite in simulation as in real life – without them your design will start in an ‘unknown’ initial state. In simulation many of the outputs will be seen to remain at logic ‘X’. In a real implementation there would be risk of the system entering an unused state and possibly locking up.

You should include a description of your planned procedures in your Second Interim Report and explain how the procedures used will verify correct operation. Generate printed copies of the traces, as necessary, for inclusion in your Second Interim Report. Note any special features of the traces and check carefully they meet the requirements of the design.

18. Correct any functional errors in your design If at this stage any problems were apparent with the functionality of your design, you should correct them now using Design Architect to edit the appropriate schematic sheet. Use the techniques developed in Lab Session 2 for this purpose.

Computer-based project in VLSI Design IC Layout & Symbolic Representation

D M Holburn May 2007 ICFlow 2003 97 C6iclay.doc


IC Layout and Symbolic Representation

This pamphlet introduces the topic of IC layout in integrated circuit design and discusses the role of Design Rules and design rule checking (DRC) in the design process. It briefly describes the key features of Mentor Graphics' ICstation IC Design package which we shall use in this project to investigate the mask-level design of a CMOS 2-input NOR gate.

You may find it useful to refer to the pamphlet on Design of Logic Gates in CMOS which discusses some of the underlying theory.

Integrated Circuit Design Styles

The most detailed level of design specification for integrated circuits involves the specification of the materials from which they are manufactured, plus the fabrication procedures (typically oxidation, implantation, deposition and lithography). These are under the control of the IC Process Engineers.

At the other extreme, at the highest level of abstraction (sometimes called front-end design), the designer specifies system blocks, often in schematic form or using a VHDL-like language, and may have no knowledge of the underlying process.

Between the two extremes lie various strata of activities, some of which we have already investigated, including IC layout, layout verification and mask preparation, and simulation.

Full Custom Design

IC layout (or full-custom design) involves the specification of the lithographic masks used in the fabrication process to define the shapes and sizes of the conductors and semiconductors within the circuit. It is a style of design in which small details can have a dramatic effect on overall circuit performance, but which can also be the means of developing a compact and cost-effective layout.

Within the continuum of design activities over the IC industry as a whole, the proportion of layout designers (for digital designers at least) is actually quite small. This is largely because of the popularity of the semi-custom approach in which a library of standard cells is provided to fulfil the standard digital functions, combinational and sequential. This approach is also percolating through to linear/analogue system design.



ICstation

ICstation is a collection of tools (including ICgraph, ICplan and ICblocks) for use in physical layout of ICs. During physical layout, you build the mask data for the IC. You can handcraft each polygon forming the definition of the masks (sometimes known more or less affectionately as ‘polygon-pushing’) in a full-custom approach, or you can use automated layout using standard cells and blocks of cells to assist you (semi-custom). Polygon layout generally gives you the most compact designs; a standard cell layout is generally faster to design, but is not as efficient in its usage of silicon. We shall investigate both approaches in this project.

In polygon layout, the designer makes use of a dedicated CAD editor package to draw and manipulate mask shapes. A typical CMOS process may require the definition of up to 12 different masks, all of which must be mutually compatible. The layout package must therefore display these simultaneously and clearly, and allow the designer to recognise and correct any adverse interactions. Mask shapes are displayed using a standard set of colour codes for clarity and consistency - for example the following colours are commonly used:

• Blue Aluminium interconnect • Red Polysilicon (interconnect & transistor gates) • Green Active region (n-type, for n-channel transistors) • Green within Yellow Active region (p-type, for p-channel transistors)

The editor provides a great many commands to add shapes and manipulate them in various ways. The majority of these involve selecting objects to be manipulated, which then become highlighted. A command is then invoked, and its action controlled by dialogues, prompts or signals from the mouse or keyboard.

ICstation's layout editor ICgraph has many features in common with Design Architect, and many of the short-cut keyboard commands work in a similar way. However, whereas in Design Architect we manipulate symbols or pre-designed schematics, in ICgraph the basic design objects are simply graphical shapes. Note that ICgraph fully supports the concepts of hierarchy, in which a design may be specified at a high level in terms of subordinate modules or cells, which may in their turn be hierarchically specified.

Laboratory session 6 will include a number of exercises to help familiarise you with the practice of creating and modifying a mask layout using ICstation's polygon editor.

Semi-custom design

Semi-custom design centres on the concept of a library of standard cells which are made available to a designer. In the simplest situations, a design will consist solely of a set of elements chosen from the library, organised where appropriate into blocks of circuitry. The only layout-related activities that are then required involve positioning of the cells or blocks in specific sites within the physical design (Placement), and the wiring together of these elements using interconnect in accordance with a schematic or other design (Routing).

ICstation provides a subset of commands for use in Placement and Routing. These may be carried out manually, or automatically. Manual placement and routing are generally tedious and time-consuming activities, but this approach may be essential for analogue or very high frequency designs where layout may have subtle but important effects on performance. Automated layout may lead to a sub-optimal



design (i.e. one in which space or the length of interconnections are not minimised), but the saving in time may be very significant. These commands actually summon up separate Mentor applications (ICplan and ICblocks respectively), but this is effectively transparent to the user. With ICstation you can mix design methods within a cell, and change methods at any time.

Laboratory session 8 will introduce the use of the higher-level tools for semi-custom design, and will culminate in the development of a layout ready for submission to a fabrication foundry.

Design Rules

The IC designer usually wishes to make his designs as small as possible. Small transistors generally switch faster, consume less current, and - of course - occupy less space. As device sizes reduce, the implication is that a given system will fit onto a smaller and cheaper silicon chip, and will operate faster and with lower power consumption. All of these are admirable marketing attributes.

However, like any manufacturing process, IC fabrication is affected by tolerances. With a given set of manufacturing steps it is simply not possible to make satisfactory devices smaller than a certain size. As this critical dimension is passed, reliability falls sharply and the proportion of working devices at the end of the fabrication process also falls. The physical mechanisms for this are varied, but include vibration, thermal expansion, difficulty of maintaining precise conditions for chemical processing, optical diffraction in the photolithographic stages .. and several others. The process engineer will therefore wish to keep device dimensions sufficiently large that reliability and yield do not suffer.

Clearly a compromise is necessary between these conflicting demands. The result is a set of dimensional tolerances (or Design Rules) which the designer must observe in order that the design can be manufactured using a specific manufacturer's fabrication process. These can sometimes be be simply expressed - for example, in the Mietec process, the minimum dimension of polysilicon structures is stated as 3 µm. The minimum spacing between polysilicon structures is also 3µm.

The interpretation is simple: attempt to make polysilicon structures smaller than 3µm, and you risk that they will exhibit breaks on fabrication; specify the minimum spacing less than 3µm and you risk them shorting together. Other rules are specified in a more complex form, and vary with the context. There are about 100 rules applying to the Mietec process in use for this project. An example - the set of rules for just one of its key layers, the polysilicon layer - is attached as an appendix to this document.

The variety of design rules in a typical process is such that the average human is quite unable to avoid inadvertently infringing them, especially when a primary objective in full-custom layout is to make designs as compact as possible. However, the workstation environment lends itself well to automating the procedure of detecting design rule violations. These can be highlighted on the screen with warning messages to assist the designer in correcting them.

It is normally required that all designs pass through design rule checking without violation before they can be fabricated.



Stick diagrams

One of the difficulties of full-custom layout is that the set of mask layers is, superficially at least, quite different in appearance from the original schematic. At the layout level, the boundaries between one device and the next may blur. Extra structures are often provided to satisfy process requirements, and the layout may be folded, redimensioned and warped in innumerable ways relative to the appearance of the schematic to achieve compactness, adjust parasitics, and generally to achieve the electrical performance sought.

For these reasons, a hybrid form of symbolic layout style is often used to represent cells. Like mask layout, this is often heavily colour-coded for visibility, but in the interests of simplicity omits selected layers (for example, semiconductor wells), and uses stylised structures for vias and contacts which ignore design rules.

Semiconductor devices are shown at unit dimensions (whereas in layout, correct dimensions would be arrived at by detailed design). Wires and transistors are arranged on a convenient grid. The resulting stick design is a valuable intermediate representation between schematic and layout, and allows the complexity of the physical structure to be concealed while assisting the layout designer to achieve a topologically correct result. We shall consider some simple schematics and the corresponding stick diagrams and IC layouts.

The inverter

By examining the schematic for the inverter, we can effect a physical layout by substituting layout symbols for the schematic symbols. In a schematic, lines drawn between device terminals represent connections. Connections between separate devices are dealt with simply by crossing lines - for example, the connection between the drain of the n-channel transistor and the drain of the p-channel transistor - see Figure 1(a) opposite. In a physical layout, however, we have to concern ourselves with the interaction of physically different interconnection layers.

We know that the source and drain of an n-channel transistor are fabricated from n-type material, while the p-channel device uses p-type semiconductor for these elements.

In CMOS technology, it is generally not possible to make a direct electrical connection from n-type material to p-type material (why not?). Thus we have to make the simple drain-to-drain connection in the physical domain with at least one conductive wire, in metal, and two contacts. Substituting layout symbols, the partial inverter in Figure 1 (b) results.

By similar reasoning, the simple connections to power, Vdd, and ground, Vss, are made using metal interconnect and contacts (c). The common gate connection may be a simple polysilicon strip or 'wire'. The resultant symbolic schematic is shown in Figure 1(d).

We continue the progressive conversion to a symbolic layout by representing the transistor devices as the superposition of polysilicon upon p-type or n-type active material. The schematic transistor symbols thus become unit rectangles of semiconductor material, yielding the symbolic layout or stick diagram shown in Figure 2(a), overleaf (to be completed). Note that there is potential to vary the layout to suit particular requirements. In Figure 2(b), the transistors are aligned horizontally instead of vertically. Other



arrangements are possible if, for example, an inverter of minimum height but non-critical width were required to fit an existing design.

Similar reasoning can be applied to the 2-input NAND and NOR schematics. Figure 3 shows possible symbolic representations of these gates.

(a) (b) (c) (d)

Figure 1 - From schematic to layout



Contact (black)

P-active (orange)

Polysilicon (red)

N-active (green)

Metal (blue)



NAND2 NOR2









Active, transistor channel

Polysilicon



Computer-based project in VLSI Design Lab Guide 6 - IC layout with ICgraph

D M Holburn May 2007 ICFlow 2003 109 C6lab6.doc

Computer-Based Project in VLSI Design Co 3/6 Laboratory Guide 6 - IC layout with ICgraph

This laboratory guide provides an introduction to full-custom IC layout using Mentor Graphics' ICgraph tool, which forms a part of the ICstation package. The exercises in this session will lead to the creation of a layout for the 2-input NOR gate nor2 which we shall substitute in place of the Mietec library version of that gate. The ultimate objective will be to obtain a neat, compact layout, free from design rule violations, with the fastest possible rise and fall times at the output terminal.

The starting point is a part-complete version of the required nor2 layout. This is provided in your ~/cbt directory, and a plot is attached as an appendix to this guide. The layout supplied determines certain key aspects of the design - for example, the pitch between the metal interconnect lines corresponding to the supply rails, and the positions of the two inputs and the output - to ensure compatibility with other gates and cells used in the design. However, as provided, the nor2 layout has no polysilicon transistor gate electrodes and some interconnect is omitted. In the later sections, you will remedy these omissions, adapt and enhance the design, and check that the resultant layout does not violate the applicable design rules. Before you begin, however, you should carry out the following preparatory exercises. You should include the resulting material in your final report.

The following activities do not require the use of the workstation. You need to complete these before you commence work on IC layout.

Consider the nor2t transistor level schematic studied in Lab Session 2. Use it to construct a simple stick diagram for the nor2 gate, in the manner shown in the lecture. Compare your diagram with the given nor2 layout, and determine the information listed below.

• Identify the positions of the various input and output ports on the layout.

• Determine the position of the supply rails, and use the ruler to measure their width and separation. What governs the width of the metal traces used for power supplies?

• The supplied nor2 layout does not indicate the position of the gate, source and drain electrodes for the various transistors. Study the nor2t schematic and the nor2 layout, and, taking into account the required transistor dimensions, attempt to determine the most suitable positions for these electrodes. You may find it helpful to refer to the notes on IC Layout and Symbolic Representation. Note also that there is no unique answer to this question, as a number of different possible layout styles are likely to be suitable.

• Annotate the nor2 layout provided with the intended source and drain positions, and the sites where the polysilicon gate electrodes are required.

• Consider how to modify the layout to implement an electrical connection between the drain electrodes you have proposed, and the output port Y of the gate.

Discuss your conclusions briefly with a demonstrator.



In the following activity, you will modify the part-completed nor2 layout to make it suitable for incorporation into your ring design.

You should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. The current Mentor working directory should be $CBT_WD (which is the soft prefix for your $HOME/cbt directory), and you should select that same directory with the Navigator. An incomplete layout for the nor2 cell is provided in that directory.

1. Open ICgraph on the cell nor2. The characteristic IC cell icon for the design nor2 should be visible in the

Navigator window. Select this icon, and use the Data-Centred mode of invocation to start up ICgraph: press the right (Menu) mouse button with the cursor over the Navigator window, and select the Open option in the menu that results; note that ic (for ICgraph) and iclink are the only tools eligible to be used with this type of object. Choose ic, and when the ICgraph design window appears, drag and adjust it as necessary to fill the screen. Examine the ICgraph session window.

2. Add two rulers to the layout to assist in sizing and placing objects. The partial cell design as supplied has a coordinate origin at the lower left corner:

note the cross symbol which signifies this. Give the command: (Menu bar) > Objects > Add > Ruler. When the prompt bar appears, leave the settings at their defaults. Observing the

cursor coordinates provided on the status bar, place the cursor at a horizontal coordinate of 0, and a vertical coordinate of around -5. At these coordinates, press and hold down the Select mouse button, and drag the resultant line horizontally to the right until it reaches a horizontal coordinate of 60 or so. Repeat this operation, but this time create a ruler starting at (-5,0) and extending vertically for the height of the design.

If you make a mistake creating a ruler, use the command: (Menu bar) > Edit > Delete > Ruler. This will pop-up a prompt box that will allow you to click in the offending ruler

and remove it.

3. Reserve the cell for Edit operations. Experimentally give the command: (Menu bar) > Edit in order to see the Edit

menu. Note that at this stage virtually all the commands are greyed and unavailable. In fact, all commands for editing or changing the cell are disabled until an operation known as reserving the cell for edits is carried out. Since Mentor Graphics is a multi-user system, the possibility of two designers simultaneously attempting to edit a design must be avoided. Once a cell has been reserved by one designer, it cannot be reserved by any other user (or even the same designer in a separate ic session) until the original edit reservation is cancelled. In effect, cells are 'read-only' unless reserved for edit; then they become 'read-write'.

In this project, each mentorx user has a private copy of the original nor2 cell.

To reserve your private copy for edits, give the following command: (Menu bar) > File > Cell > Reserve > Current context.



4. Change the Visible Layers seen on the screen. Examining the nor2 layout shows that it consists of a number of colour coded

superimposed shapes or layers. As explained, the masks used in the various stages of the fabrication procedure are each represented by a colour-coded set of shapes. For the purposes of carrying out the design, it is vital to be able to visualise the complete mask set, to ensure that each mask is consistent with the remainder. However, this can lead to a rather complex cluttered appearance. Moreover, there are a number of layers which have significance to other parts of the design process but do not represent masks. Sometimes it is helpful to suppress display of certain kinds of shapes.

For example, the entire nor2 cell appears to be covered with hatched blue shapes which may impede visualisation of the design. These shapes are actually formed of two design layers: firstly, the mask for the METAL1 aluminium interconnect used to interconnect devices; secondly, a layer which signifies to the automatic routing tool (to be explored later) regions in which METAL1 may not be routed - referred to as METAL1 blockage. This second layer is not a mask layer, and it may enhance visibility of the design to suppress displaying the corresponding shapes.

To experiment with this capability of ICgraph, give the following command: (Menu bar) > View > Visible Layers. This should result in the Set Visible Layers dialogue box being displayed. Using the scroll bars, scroll up and down the list, to get an impression of the kinds of layers available in this design, and how they look.

Set the Action switch in the dialogue box to Remove, and select the METAL1.BLKG layer. OK the dialogue box,and study the resulting layout. Note that this has not changed the design in any way; it has simply made parts of it invisible.

Using the same dialogue box, set the Action switch to Replace, and select the three layers: METAL1, CONTACT, and POLY1. You will need to hold down the Ctrl key while selecting the second and third layer. OK the dialogue box, and note that the resultant display is considerably simpler: only conducting (as opposed to semi-conducting) layers are now visible.

Restore display of all layers by setting the Action switch of the Set Visible Layers dialogue box to Replace, and entering All in the And/Or type in layers text box, and finally OK the dialogue box.

You may find it convenient to restrict visibility of the layers in the way just explored while carrying out the modifications described below.

5. Investigate the basic commands for placing shapes. Experiment with the keystroke commands +, - (on the Numeric Keypad) and

Shift+F8, which control the display zoom factor. Zoom the display so that there is a substantial clear region to left and right of the nor2 structure.

Give the command: (Menu Bar) > Objects > Add > Shape. This allows you to add a rectangle or polygonal shape to the layout. When the prompt bar appears, click the Options button, and select POLY1 in the scrolling list of layer names that appears. Check the Keep Option Settings button, and OK the Options dialogue box. Now, with the cursor over a clear area of the design window, and with the Select mouse button depressed, drag out a rectangle. Observe that the size of the rectangle is read out in the status bar. Release the button when the



rectangle is about 40 µm square, and observe that it is displayed selected, in bold, dashed red. Observe also the bold white I at one corner of the shape. This is the basepoint. When you Copy or Move selected objects, they are placed so that when you identify the destination point with the mouse, the basepoint is placed here, and all other elements of the selection are placed relative to it.

Experiment with (Menu bar) > Edit > Move and (Menu bar) > Edit > Copy, (Menu bar) > Edit > Flip and (Menu bar) > Edit > Rotate, using them to move

your shape to a different position, manipulate it, and create a duplicate. When you finish with these commands, press F2 to de-select all objects.

Repeat the (Menu Bar) > Objects > Add > Shape command, leaving the options at their defaults. However, on this occasion, instead of dragging out a rectangle, define a closed polygon in the shape of a T - in a clear area of the design, by clicking the Select button at its vertices and double-clicking at the end point (which should coincide with the start point). The shape outlined should be displayed, selected, as polysilicon.

6. Investigate the Notch and Stretch commands for editing shapes. First investigate the Notch command. De-select all shapes by pressing F2. Select

just one of your shapes by clicking it. Give the (Menu bar) > Edit > Notch command. When the prompt bar appears, place the cursor within your shape, and using the Select button, drag out a rectangular region which extends outside the shape. Release the Select button. Observe the results.

Repeat the command, but on this occasion begin dragging outside your shape and allow the rectangle being dragged out to enter the shape. Experiment further with this command if you wish.

Now investigate the Stretch command. Ensure just one of your shapes is selected, and give the command: (Menu bar) > Edit > Stretch. Drag out a rectangle (using the Select button) which fully encloses one edge of the selected shape. The white rectangle should persist; now drag out a line starting at a point within the white rectangle, and roughly perpendicular to the chosen edge, and finishing outside the box. Release the Select button, and observe the results. Experiment further with Stretch if you wish.

Now delete the two experimental shapes you have created by selecting them (only), and using the (IC Window) > Edit > Delete command.

In order to ensure you start with a clean copy of nor2, close the cell now by double clicking the system button at the top left of the design window. When the dialog box: Save changes to nor2 ? appears, click the Discard button and OK the box. Re-open the nor2 cell by giving the command:

(Menu bar) > Open > Cell, and navigate to the nor2 design if necessary. Reserve the cell for edits.

7. Run ICrules to check for any existing design rule violations The importance of ensuring that any mask layout comply with the manufacturer's

design rules has been mentioned. When a layout is being edited manually, it is necessary periodically to run a check that none of the shapes laid down violates the set of rules. This is done by means of ICrules, an interactive tool controlled from within ICgraph, which detects and highlights any rule violations. ICrules is a complex application in its own right, with a large number of options and facilities. However, our use of it will be comparatively straightforward.



As provided, the nor2 cell has some design rule violations which you are asked to identify and correct. To run the design rule check (DRC), click the ICrules entry in the IC palette, which switches to display a different palette, that for ICrules itself. The nor2 design is automatically set up to use the correct rule set (Mietec CMOS24).

To begin the check, click the Check palette menu item, and note that a prompt bar appears. You can investigate the options by clicking the appropriate button, but leave them at their defaults. You can further optionally specify a rectangular area (using the mouse select button to drag out an area) in which the check is to be confined. In this case we shall leave the area unspecified, causing ICrules to check the entire design. OK the prompt bar and observe the status line.

You may observe some warning messages flash past. When the check is complete, any warnings or errors are gathered into a database. Access the first by clicking the First item in the palette. You should observe a portion of the design flash three times, then remain illuminated. This identifies the site of the error. The description is presented in the status line. Study the layout and the error description carefully, and try to identify the correction(s) required. Consult a demonstrator if you are unsure. When you have made the necessary change, you can move to the next violation by clicking the Next item. When you have corrected all problems in this way, re-check the design once again. You need to aim for a clean DRC, in which the report: Total results: 0 will be seen at the foot of the screen.

When you achieve this, save the cell by giving the command: (Menu bar) > File > Cell > Save Cell. Note that the act of saving the cell also removes the edit reservation. In order to

continue editing the cell after each Save, you will need to reserve it for editing once again.

8. Lay out the gate electrode for input A. Referring to your stick diagram and annotated layout, decide where to place the

polysilicon gates to form the n- and p-type transistors required in the nor2 design to connect to input A (at the base of the design). Broadly speaking, you need to create a set of vertical strips - though not necessarily of uniform width or in straight lines - connected to the corresponding input port and crossing two active regions. Be careful that the layout you choose will not impede you in designing a similar structure for input B.

Use the (Menu bar) > Objects > Add > Shape command investigated above to generate the gate connected to input port A. You may have to do this in a number of stages, using abutted or overlapped rectangles of different sizes. Use ICrules at frequent intervals to verify that the structures you design are free from violations. Although this may seem irksome, it is probably more efficient in the long run than laying down an entire complex structure and having to wade through a plethora of violation messages at the end. The demonstrators will help you interpret any less obvious warning/error messages.



9. Lay out the gate electrode for input B. Referring to your stick diagram and annotated layout, decide now where to place

the polysilicon gates corresponding to input B (at the base of the design). Again, a vertically oriented strip of polysilicon is likely to be required. On this occasion, instead of laying out a set of abutting shapes, we shall use ICgraph's facility for laying out path structures. With this command, you determine the position of the centre line of a rectangular shape, which may have jogs and changes of direction if required; software then 'fleshes out' the centre line to the required width. Path structures can as a result be recognised by the existence of a prominent centre line.

Determine a suitable width for the path, noting that this will be constant over the whole of its length. Give the command: (Menu bar) > Objects > Add > Path. When the prompt bar appears, click the Options button and examine the dialogue box that results. Select POLY1 as the layer name for the path, and enter the value you have chosen for its width (in µm). OK the dialogue box. Using the Select button, mark the position of the start point and, in order, any other vertices required, double clicking at the end point. The path will then be displayed, filled out to the prescribed width, and selected.

If you are unhappy with the course of the path, perhaps because it violates a design rule, or for any other reason, you may delete it like any other shape. Alternatively, you can use Stretch to extend a segment. Note that you can also select a segment of the path itself, by giving the command:

(Menu bar) > Select > Select > Edge:, then clicking the Select button with the cursor over the centre of the segment in question.

The (Menu bar) > Edit > Move command may then be used to reposition the path as required. Alternatively, with the whole of the path selected, you can use (Menu bar) > Edit > Edit Ctrline to continue the path. When you are satisfied, check that ICrules runs clean, save the design and reserve it for further edits.

Take great care that your polysilicon gate electrodes have the correct dimensions so they correctly define the length of the conductive channel. They must of course satisfy the design rule requirements, but you will only achieve the anticipated electrical performance if the transistor dimensions are chosen correctly and laid out in accordance with your earlier calculations. Edit if necessary.

10. Insert interconnect to link the output port The output port Y (at the base of the cell) marked on the layout nor2 is not

physically connected to any of the semiconductor devices of the NOR gate. As shown in the earlier exercise, additional interconnect is required to achieve this. Study the layout and schematic carefully, and check the viability of your proposed scheme for linking the points in question. You may need to investigate carefully what layers already exist at and around the two points, changing the Visible Layers setting in order to confirm matters where there is any uncertainty. Note that any additional structures you create must not stray outside the white rectangular floorplan boundary (layer fp1). If you are in doubt about the options available, consult a demonstrator.

Use either the .. Add > Shape or the .. Add > Path command to add appropriate shapes or paths to achieve the required linkage. As always, use ICrules to check for design rule violations, and when you are content with the result, save the cell.



11. You will probably wish to generate a checkplot of your completed nor2 layout. At this stage a monochrome laser printout should serve your needs, but you may wish to annotate or colour code the result for inclusion in your report in the interests of clarity. The procedure for generating hardcopy of layout files resembles that for schematics and waveforms, but with a few important differences. Follow the procedure set out below.

Give the command: (Menu bar) > MGC > Setup > Printer... When the Setup Printer - General dialogue box appears, enter mgcps_a4 in the Printer Name field. Check that the Object type is set to design (correct if necessary). Leave the remaining fields in their default states, and OK the dialogue box.

In order to print the cell, you must have it visible on the screen, and the design window must be active.

Give the command: (Menu bar) > File > Print > Print Cell ... When the Print Cell dialogue box appears, first click the Setup Print... button. A further, Setup Print dialogue box appears. In this box set the Paper Width to 7 inches and the Paper Length to 10 inches. Leave the other settings at their default values and OK the dialogue box.

When the Print Cell dialogue is revealed again, you must enter again the parameters for the paper to be used. Enter 7 in the Wid field, and 10 in the Len field. Units are inches in both cases. Now click the Set button just below the Len entry field. Click in sequence the Set buttons to the right of the Pages and the Scale fields.

Finally, click the Set Layers button. You are strongly advised to suppress printing of the Metal1.blkg and Metal2.blkg layers, since these occupy much of the layout and are shown as a strongly hatched design on the plot, obscuring much of the detail below. To achieve this, you must select the list of layers you do wish to see, and ensure that this does not include the unwanted blockages. Starting at the top of the list in the scrolling box, click the layers down to number 13, pressing the Shift key while you click, so as to obtain an additive selection. Select also any other layers you particularly wish to include. When you have finished selecting layers, OK the dialogue, and note that the Layers item is now set to Other in the Print Cell dialogue box. OK the Print Cell dialogue.

The plot will then be prepared and placed in a temporary directory. To send it to the laser printer, run the utility mgcplot from an xterm shell or similar. The name of the cell you plotted should then be listed. Follow the screen prompts to preview the plot (using ghostview) before committing it to paper. When you are happy with the result, exit from ghostview and follow the prompts to direct the output to the laser printer.

A similar procedure will be required in the final lab session, in which you will plot the layout corresponding to the entire design, including input/output pads and all other essential elements. At that stage it is anticipated that colour printing facilities should be available, but note that a slightly different procedure is required to obtain colour prints.



Layout of nor2 cell before modification

Dimensions of the rectangular bounding box are 106 µm × 57 µm

Computer-based project in VLSI Design Analogue Simulation & AccuSim

D M Holburn May 2007 ICFlow2003.3 117 C6accu.doc


Analogue Simulation & Accusim

This pamphlet briefly describes the role of analogue simulation in integrated circuit design and introduces the Mentor Graphics AccuSim simulator, which is based on the industry-standard SPICE simulation package developed at Berkeley University.

Accusim is an analogue circuit simulator that allows you to verify the functionality of analogue electronic designs produced with Design Architect. AccuSim offers:

• interactive control of the simulation which includes the facility to let you apply signals, list them, run the simulation with chosen constraints, and create charts of results

• the ability to save setup conditions, stimuli, results and particular states of the simulation so they can be restored at any future time

• incremental design capabilities that let you update property values during the simulation, allowing you to use heuristic or 'what if' methods for improving the design you create

• compatibility at the interface level with Mentor full-custom and verification tools allowing layout parasitics to be incorporated in the simulation

• a substantial library of standard component models (AccuParts) which are pre-characterised and identified by industry-standard part names. For example, if your design calls for a 741 op-amp, you can specify that the AccuParts model for this device be used in your simulation

• compatibility with the industry-standard SPICE analogue simulator from which AccuSim was developed.

AccuSim's great strength is that it performs a full numerical analysis of the voltages and currents appearing at every node of the circuit being simulated. AccuSim is capable of DC analyses, DC sweeps (allowing transfer functions to be determined), AC analyses (including frequency response and noise analysis), transient response, and a number of others. For logic gate simulation, transient responses and DC analyses and sweeps tend to be of greates use. Stimuli can be expressed as DC voltages or currents, sinusoids, exponentials, pulses or piece-wise linear waveforms. The numerical models used are highly elaborate - for example, in the case of MOS transistors is may be necessary to specify 40 or more parameters per device.

For example, the kind of models used to describe the MOSFETs fabricated according to the Mietec CMOS24 process are shown below: .model tr_n NMOS (LEVEL=3 VTO=0.86 KP=5.171e-05 GAMMA=0.26 PHI=0.62 + PB=0.65 CGBO=5.57e-10 RSH=33.42 CJ=6.9e-05 MJ=0.5 CJSW=3.43e-10 MJSW=0.27 + JS=0.001 TOX=4.029e-08 NSUB=1.39e+15 NFS=1.35e+11 XJ=3e-07 LD=2.2e-07 + UO=611.37 UCRIT=10000 VMAX=158000 DELTA=0.85 THETA=0.05 ETA=0.07 KAPPA=1.4) .model tr_p PMOS (LEVEL=3 VTO=-0.85 KP=1.914e-05 GAMMA=0.69 PHI=0.67 + PB=0.76 CGBO=5.57e-10 RSH=35.01 CJ=0.00031 MJ=0.5 CJSW=3.67e-10 MJSW=0.38 + JS=0.001 TOX=4.246e-08 NSUB=9.1e+15 NFS=3.92e+11 XJ=5e-07 LD=3.5e-07 + UO=233.84 UCRIT=10000 VMAX=225670 DELTA=0.96 THETA=0.12 ETA=0.06 KAPPA=9.23)



This information includes the following key parameters:

• Device threshold voltage (VTO) • Gate oxide thickness (TOX) • Specific device capacitances (C...) • Doping parameters (NFS, NSUB) • Mobility (U0, UCRIT)

and several others.

In addition to the MOSFET modelling information, AccuSim needs to know for each MOSFET the identity of the nets in the schematic to which it is connected, as well as the dimensions L and W of its channel, in order to evaluate the device voltages and currents. This information is extracted from the connectivity of the schematic, and by examining the INSTPAR property set up for each device in Design Architect.

Finally, for realistic transient responses, AccuSim needs to know the nature and magnitude of the parasitic capacitances (and sometimes the resistances) of the various interconnections. This information depends on the exact details of the layout, and is therefore not available directly from the schematic. In fact, it is obtained by an indirect process known as Back Annotation. In back annotation, parasitic elements in the layout are evaluated by an extraction program (ICextract) which takes into account the physical characteristics of the material involved (polysilicon, metal, etc) as well as the dimensions of the corresponding mask shape. The capacitance (and, where appropriate, the resistance) values are then inserted back into the corresponding schematic, appearing as annotations on the schematic display.

Mentor Graphics furnishes a utility DVE (Design Viewpoint Editor) to handle the issue of back annotation. With DVE a designer may associate a number of different sets of extracted parameters - possibly corresponding to a number of different layouts under evaluation - with a named schematic, and may connect and disconnect these at will.

A typical complete Accusim input file is shown opposite, corresponding to an inverter, with comments. Note that this input data is not normally seen by the designer. Each basic element (primitive) is identified by a characteristic initial - for example, voltage sources by V, capacitors by C, MOSFETs by M, followed by a distinguishing identifier. This is then followed by a set of identifying numbers (node numbers) which indicate the way the standard terminals of the element are connected to other elements. The allocation of node mumbers is fairly arbitrary, and bears no relation to any identifiers generated in Design Architect. For this reason there is a translation table which identifies the correspondences between Mentor entities and the Accusim node list. A series of directives beginning with a 'dot' specify the kind of analysis to be undertaken - for example, DC sweep, transient response, etc.

Note that information about the connections between the devices and about L and W comes from the schematic, and not from the layout. This may seem strange, since it is the layout that actually expresses the connectivity and device dimensions of the manufactured device, by defining the shapes and sizes of the corresponding mask shapes. This is a deliberate policy; the approach used by Mentor of back-annotating layout and parasitic information onto a schematic allows for the possibility of implementing the same schematic circuit in a number of different ways (for example, different layout styles, libraries or even different processes).



ACCUSIM INPUT FILE (INVERTER) Title... SPICE netlist .options tnom=27 .temp=27 * * Set up voltage sources for Vdd and A (DC supply and a pulse) vdz2 501 0 DC 5 vdz1 503 0 PULSE 0 5 5e-09 5e-09 5e-09 1e-07 2e-07 * * List nodal capacitances cnn1 501 0 3.8499e-14 cnn3 503 0 3.48362e-14 cnn4 502 0 7.78117e-12 cnn5 504 0 3.4324e-14 * * List MOSFET connections and models * D G S B terminals miz2 501 503 502 501 m2 l=3e-06 w=3.6e-05 miz1 502 503 0 0 m3 l=3e-06 w=7e-06 * * List MOSFET model information .model m2 PMOS (LEVEL=3 VTO=-0.85 KP=1.914e-05 GAMMA=0.69 PHI=0.67 + PB=0.76 CGBO=5.57e-10 RSH=35.01 CJ=0.00031 MJ=0.5 CJSW=3.67e-10 MJSW=0.38 + JS=0.001 TOX=4.246e-08 NSUB=9.1e+15 NFS=3.92e+11 XJ=5e-07 LD=3.5e-07 + UO=233.84 UCRIT=10000 VMAX=225670 DELTA=0.96 THETA=0.12 ETA=0.06 KAPPA=9.23) .model m3 NMOS (LEVEL=3 VTO=0.86 KP=5.171e-05 GAMMA=0.26 PHI=0.62 + PB=0.65 CGBO=5.57e-10 RSH=33.42 CJ=6.9e-05 MJ=0.5 CJSW=3.43e-10 MJSW=0.27 + JS=0.001 TOX=4.029e-08 NSUB=1.39e+15 NFS=1.35e+11 XJ=3e-07 LD=2.2e-07 + UO=611.37 UCRIT=10000 VMAX=158000 DELTA=0.85 THETA=0.05 ETA=0.07 KAPPA=1.4) * * Define swept input source and transient analysis times .dc vdz1 0 5 0.1 .tran 1e-09 2e-07 0 * * begining of translation table for device INSTANCE names * netlist_name original_name * * miz1 /I$1 * miz2 /I$2 * cnn1 /N$208_cap_net * cnn2 /N$6_cap_net * cnn3 /A_cap_net * cnn4 /Y_cap_net * vdz0 d$0 * vdz1 d$1 * vdz2 d$2 * end of translation table for device INSTANCE names * * begining of translation table for device MODEL names * netlist_name original_name * * m2 tr_p * m3 tr_n * end of translation table for device MODEL names * * begining of translation table for NODE names * netlist_name original_name * * 0 //ground * 501 /N$208 * 502 /Y * 503 /A * end of translation table for NODE names .end

A typical Accusim input file (slightly edited for clarity)



The implications of this approach are quite profound, however. How can we be certain that the layout we have designed, possibly quite independently of the schematic, actually matches the schematic in every applicable way? This is clearly something that must be checked as part of the verification process. One can visualise the chaos that would surely ensue if a design were fabricated on the basis of a schematic which simulated perfectly (using QuickSimII or Accusim), but whose layout had a couple of missing interconnections or shorts that went undetected by eye.

Clearly, the correspondence between layout and schematic must be verified. In the Mentor Graphics package this is achieved by a procedure known as LVS (Layout Versus Schematic), in which the interconnection information and transistor details are taken from the layout and compared, feature by feature, with the corresponding elements in the schematic, and every discrepancy recorded.

The approach described is capable of taking into account as much information as can be obtained about parasitic elements inherent in the layout, and can lead to results of considerable accuracy. However, this accuracy is only achieved at a comparatively high cost in terms of computing overhead. It is generally reckoned that the computing time rises approximately as the square or cube of the number of devices present in the simulation. Hence, it is not normally possible to consider simulating with AccuSim circuits consisting of more than a few dozen transistors. This means that most designs of any size must be broken down into manageable elements each of which can be modelled in isolation using AccuSim. The detailed functional and timing results from AccuSim can then be embedded in a higher level model (e.g. a VHDL model) which can be invoked in a high level simulation tool such as QuickSimII, which is better suited to the needs of verifying entire designs.

This approach is well suited to the semi-custom style of design, in which a library of pre-characterised cells is made available to designers. The cells themselves are created (typically involving use of IC layout tools) and modelled by the library developer using simulators like AccuSim and by direct measurements on fabricated designs. The resulting QuickSimII or other models are then supplied to the semi-custom designer, who may for most circumstances use these rather than carrying out detailed AccuSim simulation runs. In certain cases, the designer will wish to use a combination of pre-characterised standard cells, plus custom cells designed for a specific purpose and modelled using AccuSim. We shall use this approach during the course of this project.

Like QuickSimII, AccuSim operates interactively. A graphical presentation package SimView provides the control interface to the AccuSim simulation itself, and serves to display the results. For ease of interpretation, AccuSim provides means for viewing the original schematic on which the simulation is being carried out, allowing cross-probing, an operation in which the designer selects nodes and nets in the original schematic in order to reference these in AccuSim commands.

AccuSim cannot operate directly on component schematics. It requires a design viewpoint to be created to provide it with the correct set of rules for interpretation of the schematic. In this project, the viewpoint needs to express the appropriate Mietec conventions for design interpretation. Although Design Architect and even AccuSim itself have the ability to create default design viewpoints, these do not contain the necessary references to the Mietec models we require. The creation of design viewpoints for Accusim, ICgraph and QuickSimII must therefore be done using Mentor Graphics DVE utility, using its (Menu bar) > Mietec > ... commands.

Computer-based project in VLSI Design Lab Guide 7 - Verification & Simulation


Computer-Based Project in VLSI Design Co 3/6 Laboratory Guide 7 - Verification and Simulation

This laboratory guide provides an introduction to some important techniques for analogue simulation of IC layouts using Mentor Graphics' AccuSim tool, which forms a part of the Analog Station package. For more details about AccuSim, refer to the pamphlet: Analogue Simulation & Accusim.

The exercises in this session will give us detailed information about how the 2-input NOR gate nor2 (designed earlier in this project using ICgraph) will operate when incorporated into the ringarray design. We shall first verify that the circuit behaves functionally as a NOR gate, with consistent input and output logic levels. Secondly, we shall use AccuSim to determine (as accurately as possible) the rise and fall times of the gate, determined by transistor characteristics and parasitic capacitances. Our aim is to achieve fast but equalised rise and fall times at the output terminal of the gate, and we should be prepared for the possibility that modifications to the layout may be necessary to achieve this.

To put this session into perspective, let us first summarise the progress made thus far in the project. We have:

• developed the concept of the ring oscillator (RO) • confirmed using Modelsim that the RO concept is valid • explored using Modelsim the effect of varying NOR gate delays • built a symbol and schematic for the RO based on the Mietec library NOR2 gate • predicted the timing characteristics of the RO based on the Mietec NOR2 gate • verified the behaviour of the RO based on the Mietec NOR2 using QuickSimII • examined the transistor level schematic for a simple 2-input NOR gate • designed mask layouts for a 2-input NOR gate nor2 • corrected any design rule violations in the nor2 layout

Note that although our own nor2 layout may be free of design rule violations, this does not in any way imply that it actually represents a 2-input NOR gate! It is necessary to verify that no errors have occurred in translating from the transistor schematic representation (perhaps via a stick diagram) to the layout. When we are satisfied of this, we need to confirm that the electrical performance is as required -- that is, that the particular combination of devices and interconnections actually functions as a NOR gate, and has the desired transfer and timing characteristics. Once these requirements are satisfied, the nor2 design may be incorporated in a library for use in the Ring Oscillator design or in other layouts where the NOR function is required.

Thus the key stages in the verification process are as follows: • verify the correspondence between the nor2 layout and the nor2t schematic • determine the parasitic elements present in the nor2 layout • back-annotate the parasitics to the corresponding nets of the nor2t schematic • simulate the result using AccuSim • account for parasitics arising when the nor2 gate is connected to other elements



Schedule

The remainder of this guide is divided into four key sections:

Section I Layout-Versus-Schematic (LVS) using ICtrace Section II Manual estimation of parasitic capacitances Section III Extraction of parasitic capacitances using ICextract Section IV Simulation of the back-annotated nor2t schematic using AccuSim

Note: section II contains an exercise to be carried out in advance of the lab session. You may wish to schedule your work to give yourself an interval away from the workstation for that purpose.

Section I Layout-versus-Schematic (LVS) using ICtrace

You should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. The current Mentor working directory should be $CBT_WD (which is the soft prefix for your $HOME/cbt directory), and you should select that same directory with the Navigator.

1. Remove the +5V voltage source from the nor2t schematic. Prior to beginning the Accusim modelling work, a small change is required to the

nor2t transistor-level schematic. This involves removing the +5V voltage source inserted originally. This will allow for the possibility of changing the supply voltage during the simulation. First open up Design Architect on the nor2t schematic. The nor2t component icon should be visible in the Navigator window. Select this icon, and use the Data-Centred mode of invocation to start up Design Architect: press the right (Menu) mouse button with the cursor over the Navigator window, and select the Open option in the resulting menu; choose design_arch.

When the Design Architect window opens up with the schematic sheet displayed, select the +5V source, and use the following command to delete it:

(Menu bar) > Edit > Edit Commands > Delete In a similar way, delete also the immediately connected nets, but take care not to

disrupt those nets interconnecting the MOSFET source and substrate electrodes, and do not delete the earth symbol.

Give the command: (Menu bar) > Check > Sheet > With Defaults and verify that there are no errors. Then save the design and leave Design Architect.

2. Open DVE and create a Design Viewpoint on the schematic nor2t for AccuSim. With Design Manager restored, start up the DVE application. In the Tools

window, double click on the DVE item. When the DVE design window appears, examine the session window, noting particularly the Mietec item in the menu bar. This contains entries that summon up utilities to create design viewpoints in the appropriate form for QuickSimII, AccuSim, and ICgraph.

Give the command (Menu bar) File > Open > Design Viewpoint. When the Open Design Viewpoint dialogue appears, use the Navigator to select the component nor2t, and change the Viewpoint Name to accusim_vpt1. OK the dialogue box.

Now give the command: (Menu bar) > Mietec > Setup AccuSim. Be sure to allow the Setup userware to run to its completion. Wait before

proceeding until you see the message:

Mietec setup for AccuSim/Analog Interface is done and cmos24 modelfile is connected

appear in the status line at the foot of the screen. This may take 10-15 seconds.



3. Create a Design Viewpoint for AccuSim (continued) DVE will construct the required viewpoint. Note the list of Primitive elements, particularly MN and MP, recognised by AccuSim as representing MOSFETs. Note also the appearance of a back-annotation object (a repository for extra information about the design). We shall later manipulate these back-annotation objects to provide AccuSim with new information about circuit parasitics.

4. Close the design viewpoint. The design viewpoint just created will later be operated on by the verification tools ICtrace and ICverify. In order to avoid problems with file locking, we must now close the design viewpoint (which has already been saved by the Mietec > Setup AccuSim operation carried out in paragraph 2). Give the command: (Menu bar) > File > Close Design Viewpoint. Do not use a Save command explicitly - experience suggests this may cause corruption of the viewpoint. Do not exit from DVE; it will be required later.

5. Open ICstation on the nor2 layout and prepare for mask-level LVS. We shall compare the nor2 layout we created in ICstation against the nor2t

schematic. Restore the Design Manager window, and select the icon corresponding to the nor2 IC cell. Open ICstation on this object. Maximise the ICstation window, and minimise the Design Manager window. In the Session Palette, click the ICtrace(M) item. The ICtrace(M) palette appears.

First we open a Rules file (to allow ICtrace to determine the kinds of interconnection allowed in this process). Click the Load Rules item in the ICtrace(M) palette. Check that the Rules File field contains the entry:

$MIETEC_CMOS24_IC_RUL, signifying the Mietec CMOS24 Design Rules. If not, type in this item taking care to avoid errors. OK the dialogue box.

Now set up for the LVS procedure. Click the LVS item in the ICtrace(M) palette. When the LVS (Mask) dialogue box appears, enter in the Source Name field the path to the design viewpoint accusim_vpt1 you created in DVE (it should lie within the nor2t component). Use the Navigator if necessary.

Leave the other fields unchanged for the moment. Click the Setup LVS button. When the Setup LVS dialogue box appears, review

the five Property fields, and edit if necessary so they contain the following:

Type properties: phy_comp element comp Pin name properties: phy-pin Power names: VDD Ground names: VSS Component Subtype: COMP_SUBTYPE

Check the Ignore Ports box. Click the No button for Recognise gates (since we wish to match schematic against layout transistor by transistor). OK the dialog box.

For the moment ignore the Setup Trace Props.. button, and OK the LVS (Mask) dialogue box. The LVS should run. Click the palette item Report, and select LVS from the sub-menu. A report window should open, and should confirm the success of the LVS comparison. If not, speak to a demonstrator. You should be able to print out the result (several pages), using the procedure used earlier for setting up the printer. Consult a demonstrator for details.



6. Investigate the cross-probing feature Assuming the LVS ran clean, investigate the probe-from-schematic feature which

becomes available on successful completion of LVS. Close the report window, if open. With the layout window active, click the Logic item in the ICtrace(M) palette menu, and choose Open. When the dialogue box appears, enter the path to the Accusim viewpoint you created, and OK the box. A design window should open, showing the nor2t transistor level schematic. You may need to re-arrange windows on the screen in order to see both layout and schematic simultaneously.

Now use the mouse to select nets or transistor instances in the schematic window, and note that the corresponding elements in the layout become highlighted.

7. Identify a minor discrepancy between layout and schematic Remembering that ICtrace is ignoring ports when performing its comparison,

study the correspondence between schematic/layout entities and try to identify a further subtle (but benign) discrepancy between layout and schematic.

Use: (Palette menu) > Unshow > All to remove the highlighting. You can leave the schematic window open while you continue.

8. Verify that LVS is capable of detecting a layout error You should confirm that ICtrace is actually capable of detecting a discrepancy

between the layout and the schematic (implying a layout error). Close the report window, and make a minor circuit change to the nor2 layout. For example, temporarily removing the contact cut at the centre of the pair of n-channel transistors is an easy way of changing the connectivity. There is no need to save the changed design, since LVS is carried out on the layout as displayed. Repeat the LVS procedure outlined above, and study the report. Use the cross-probing feature to attempt to identify the errors diagnosed by ICtrace.

Restore the connectivity to the original situation. For example, if you chose to remove a contact cut as described above, replace it now, and re-run the LVS. Confirm that it now runs without error. If time permits, make a small layout amendment that does not imply a change in connectivity -- for example, re-route a piece of interconnect. Verify that this has no effect on the outcome.

9. Investigate ICtrace's ability to detect incorrect device properties. When we ran LVS the first time, we ignored the Setup Trace Props.. feature.

This is provided to let ICtrace detect discrepancies between device properties specified in the schematic and those implied in the layout. The most useful application of this feature in digital IC design is to check that the transistors have been laid out with correct W & L values.

With the layout design window active, return to LVS by clicking the LVS item on the ICtrace palette menu. There should be no need to enter the Setup LVS dialogue (unless you exited from ICstation between sections) since the settings persist. Click the Setup Trace Props.. button. The resultant dialogue box exceeds the size of the screen, and you may need to use the mouse or Page Up and Page Down keys in order to navigate around it. Each entry in the table corresponds to a parameter which ICtrace can estimate and compare with any corresponding specification (in the instpar property) provided in the schematic.

Note particularly the mn and mp entries which correspond to n-channel and p-channel MOSFETs respectively. ICtrace recognises MOS transistors by detecting the superimposed mask layers, which are quite characteristic, and it can easily determine the length and width of the transistor channels.



Enable tracing of L and W for n- and p-type transistors, by clicking the four Yes buttons for the corresponding items. Note that you can specify a tolerance (%), within which no warning will be issued. Ignore the remaining device types, which do not appear in our design. OK the dialogue box, and OK the parent dialogue in order to run the LVS.

If you were careful in your schematic and layout design, your LVS should still run without problem. However, if there are discrepancies between the L and W parameters specified in the nor2t schematic and those determined in the nor2 layout, ICtrace will warn you of these. If so, you will need to correct one or possibly both designs, using the appropriate editor.

If necessary, do this before continuing to the next stage. Be sure your design runs with no design rule violations and with no LVS errors before you proceed to the next stage.

The following section should be carried out away from the workstation. You need a printed copy of your completed nor2 cell layout in order to proceed.



Section II - Analysis of parasitic capacitances

Appreciation of the parasitic capacitances associated with a design is vital. Delay will be introduced by any capacitive element that has to be charged and discharged while the gate is operating. This applies to many, though not all, of the capacitive elements found in your design.

Later we shall use the tools within Mentor to analyse these capacitances with considerable accuracy. However, this process cannot be completely automated. When considering a design it is very easy to overlook important contributions to capacitance and thus obtain an over-optimistic impression of performance. It is clearly important for a designer to have an appreciation of which contributions to capacitance have the most serious effect on performance, so that they can be minimised. The purpose of this section is to identify the most important contributions that need to be taken into account. Some are inherent in the layout for the nor2 cell (already carried out), while others will arise from interconnect used to link the cells. This interconnect has not yet been laid out, so its effects can only be estimated.

The following activity is to be carried out away from the workstation before proceeding with the automated extraction exercise. You will need a printed copy of your completed nor2 cell layout in order to proceed. If necessary, use the procedure in Lab Guide 6 to produce one, or refer to the copy included as an Appendix to that Lab Guide. It may be useful when estimating dimensions to note that the size of the entire nor2 layout cell as supplied is 106 µm tall by 57 µm wide. You may wish to include one or more rulers in the checkplot to help estimate dimensions. Note also the availability of the ICgraph command: (Menu bar) Report > Selected, which reports (among other things) the area in µm2 of any layer currently selected.

Parasitic capacitances arising from interconnect

Three main forms of interconnect are used in digital IC layout. These are: polysilicon, metal1 and metal2. All are separated from the substrate by means of dielectric layers of SiO2, polyimide or other material, and thus exhibit a defined capacitance to the substrate. The thickness of the dielectric is different in each of these cases, however, with the result that different materials have rather different specific capacitances (per unit area). Clearly there must also be inter-layer capacitances - for example, wherever polysilicon is overlaid by metal1 - but we shall ignore these effects for this project.

Figure 1 below illustrates some of the capacitance contributions within a typical nor2 gate due to interconnect.

Figure 1: Some capacitances due to interconnect



Other contributions to parasitic capacitance

In addition to the parasitic capacitances arising from interconnect, there are contributions due to the semiconductor devices themselves. These can be identified:

• at each gate (where a MOS capacitor is formed with plates comprising the gate electrode and the channel; the dielectric is the thin gate oxide);

• at each drain and source, owing to the reverse-biased p-n junction formed between the source or drain and the substrate in which it lies.

These capacitances are closely controlled by the detailed dimensions of the devices, as well as by the characteristics of the materials used. We shall not evaluate the semiconductor capacitances here, as the models employed are quite complex. They will be determined later by AccuSim, using extracted dimensions, and we shall consider the importance of these contributions at a later stage.

You can read about the evaluation of parasitic capacitance in CMOS gates in: Analysis and Design of Digital Integrated Circuits 2nd Edition, by Hodges & Jackson. See p 75.

Analysis of parasitic capacitances due to interconnect

The next two sections will provide important data for inclusion in your Final Report.

The table below contains figures provided by Mietec Alcatel. They comprise typical specific capacitance values for three main forms of interconnect. In order to apply these values, you must estimate the area corresponding to to each element of interconnect. It is apparent that several shapes corresponding to different materials may be electrically connected. Strictly speaking, we should also evaluate the electrical resistance of each element of interconnect and consider the entire structure as a set of interconnected R-C ladders. To simplify matters we shall asssume that we can neglect the electrical resistance of the interconnect, and that capacitive contributions may be combined as parallel capacitances.

• Study the nor2 layout and schematic. Using data from the table, estimate the capacitance (to within about 10%) between each interconnect mask shape and substrate, using reasonably accurate scale measurements of area. Annotate your layout diagram accordingly. NB 1fF = 10-15 F.

• Use the table templates in the Appendix to this Lab guide to present your data.

• Comment on the relative merits of the three forms of interconnect from the point of view of designing compact, high speed circuits.

Mietec CMOS24 Technology - Interconnect specific capacitances

Material Polysilicon Metal1 Metal2 Units

Specific capacitance to substrate

4.03 × 10-2 2.3 × 10-2 1.73 × 10-2 fF µm-2 [1fF = 10-15 F]



Estimating delay in interconnected gates

In real logic circuits consiating of many gates, estimates of delays must take into account not only this delays due the the capacitances (and other parasitic elements) within any gate, but must also consider effects caused by any other logic gates connected to it, and by the interconnect used to do this. Clearly, there are many different gate types, and myriad ways of interconnecting gates, so the problem can easily become complex. However, a number of useful simplifications can be made.

When estimating the delay introduced by a logic gate in a circuit consisting of several gates, it is convenient to suppose that all the elemental capacitances (due to wiring, other gate inputs, etc) to which the output terminal is linked can be combined as a single ‘lumped’ capacitor. The time taken to charge/discharge this capacitance can then be determined by considering the conductances in the pull-up and pull-down chains.

Using this approach facilitates a straightforward approach to analysis of timing delay which is nonetheless realistic and gives sensible results.

We shall now assume that the output of your nor2 gate is to be connected using metal1 interconnect to the two inputs of a succeeding identical nor2 gate (as in the ring oscillator). Both gates operate electrically as inverters - see Figure 2 opposite.

• Draw (by hand) a schematic representation (based on Figure 1 and Figure 2) of the situation that exists when two (or more gates) are connected in cascade. It should help you identify those capacitances that contribute to delay.

Note: It is very easy to overlook capacitive contributions and get an impossibly optimistic but meaningless estimate for the delay. Equally, it is important to be aware of those capacitances that are connected to static nodes (where the potential does not change). These do not affect delay, and including them would also give a false impression. You must take care to avoid falling into either of these traps!

• Making reasonable assumptions about the siting of the two abutted nor2 cells, estimate the area of metal1, assumed to be of width 4 µm, required to make these connections, and hence estimate its capacitance to substrate. Yo can deduce the form and size of the nor2 cell elements from the plot shown as an Appendix to Lab Guide 6 (IC layout with ICgraph). Then, being careful that you have considered all contributions, estimate the total capacitance due to interconnect being driven by the first gate. Use the table templates given in the Appendix to help gather and present the data. Record the total capacitance, and annotate your schematic for later reference.

Delays in more complex logic systems

We are now in a position to account for the capacitive effects within individual logic gates themselves, and those arising from interconnect used to link gate inputs and outputs. • Consider carefully which of the various capacitative elements will contribute

directly to the delays observed in the case of a multi-stage design such as the ring oscillator. Study the transistor level schematics of Figure 1 and elsewhere, and the nor2 layout annotated with parasitics.



Use the table templates supplied in the Appendix to this Lab Guide to assemble and present these elements. Accordingly, update your schematic representing the cascaded gates of Figure 2. Annotate it to show all relevant contributions towards parasitic capacitance that affect delay. Some of these have been specifically mentioned above, while others have not, and you should think carefully about which contributions are likely to be of greatest significance in determining the speed of the gate. The table of specific capacitances (in Section II of this Guide, above) should be of help in deciding relative values.

YA

B

A B Y

YA

B

A B Y

Figure 2: Estimation of additional interconnect capacitance

The following section needs to be undertaken at the workstation.



III Extraction of parasitic capacitances using ICextract 10. Extract interconnect parasitic capacitance values using ICextract(M). Before a proper simulation can be carried out it is necessary to determine the

magnitudes of any parasitic components (for example, resistances or capacitances) inherent in the layout of the IC. ICextract provides facilities for extracting resistance and capacitance values in various forms, including lumped or distributed capacitances between pairs of layers as well as from each layer to substrate (ground). However, in this project we shall confine ourselves to determining only the lumped capacitances between interconnect and substrate (since these are a primary determinant of rise and fall time).

ICextract has two modes of operation: Mask level (M) and Direct (D). The former descends to the foot of any hierarchy and prepares a 'flattened' list of extracted parasitics for back-annotation to a transistor-level schematic. Direct-mode extraction inspects only interconnect at the highest hierarchical level and does not explore any sub-cells. For this work we shall use Mask Level extraction.

Important note: If you commence this section at the beginning of a session, you must first carry out an LVS using the procedure described in paragraph 4 above.

With ICgraph's Design window active, revert to the IC Palettes menu, if necessary by clicking the Back option in the ICtrace(M) palette. Click on the ICextract(M) item. The ICextract(M) palette appears.

If necessary, load the Mietec process and design rules by clicking on the Load Rules item in the palette. Enter: $MIETEC_CMOS24_IC_RUL in the text box.

If you have a schematic window open on the logic, close it temporarily by giving the command (Palette Menu) > Logic > Close.

Click the Lumped item in the palette. When the Extract Mask Lumped Parameters Dialogue box appears, click the Yes button for Specify Schematic Source, and the Yes button for BackAnnotate. The dialogue box will enlarge at each click, disclosing additional options.

Set the BA Name field to flat_ba, and choose eddm for Source type. In the Source Name field, enter the path to the AccuSim viewpoint. No Navigator is available for this item, so you will need to key it in explicitly, for example $CBT_WD/nor2t/accusim_vpt1.

Change the entry in the Lumped Capacitance – Name field so that it reads cap_net (instead of icap_net). Ensure that the Lumped Resistance and Coupling Capacitance options (at the foot of the dialogue) are both set to No, but leave all other items as they are. OK the dialogue box. Extraction should proceed.

To view the results, give the command (Palette Menu) > Logic > Open. The Logic Name should already be set to the appropriate viewpoint, but if not, enter or navigate to this. OK the dialogue box, and watch for the schematic window to appear. It should appear annotated in red with capacitance values (picofarads) at all key nodes. Enlarge the window, and study the values.

• Are the capacitances similar to the values you estimated by hand? Comment. • Record the capacitances observed at the three main ports A, B and Y. • Note also the capacitance values given for the Vdd and Vss nets. How do you

expect these to affect the operation of your design?



11. Verify that ICextract responds to changes in layout. Refer to the section: Analysis of parasitic capacitances due to interconnect

(above), which considers the capacitance due to interconnect used to connect the output of the gate under consideration to other gate inputs.

Using ICstation's layout commands, temporarily add to your layout a strip of interconnect. Imagine that you plan to connect the output port Y to the input ports A and B of a fictitious gate, placed adjacent to the first, and lay out the additional interconnect accordingly. (Only a reasonable approximation of the geometry is required). Do not save the modified layout. Re-run the ICextract utility, and observe and record the modified capacitance values.

Exit from ICstation. When prompted to save changes to the cell, be sure to choose the Discard option, so that the temporary interconnect is not saved.

12. Use DVE to connect back-annotated parasitics to the Accusim viewpoint. You should still have a DVE session running from a previous phase. Restore its

window on the screen. Open the AccuSim viewpoint you created in paragraph 2. If you have no DVE session, use Design Manager to open a DVE session on the AccuSim design viewpoint created in paragraph 2.

Study the Design Viewpoint window. In addition to the reference to a back-annotation object: accusim_modfile.ba, you should see listed an object entitled: flat_ba. This is the back-annotation derived from the ICextract session you performed. If you do not see this reference, speak to a demonstrator.

Close the design viewpoint using the command (Menu bar) > File > Close Design Viewpoint.

Important. You may encounter difficulties in AccuSim if you leave the design viewpoint open in DVE. However, you should leave your DVE session running in spare window, or minimised; you may need it later.

When your design runs cleanly through LVS and you have satisfactorily extracted parasitic capacitance information and back-annotated this to the design viewpoint, you are ready to carry out a simulation with AccuSim.

13. Use Design Manager to check your viewpoint is ready for simulation You should carry out the following check using Design Manager to confirm that

all has gone well with your creation of the accusim_vpt1 viewpoint.

In Design Manager, navigate to the new viewpoint (within the nor2t component). Select it, and using the Popup menu available from the right mouse button, give the command: (Popup) > Explore > References. In the resulting screen you should see a reference to: MIETEC_CMOS24_ACCUSIM_MODFILE (the upper case characters are significant).

NB: on closing this window you will have to start a new Navigator using: (Menu Bar) > Windows, or using the menu palette.)

If you can see the reference described, you should be safe to proceed to Accusim in paragraph 14. If not, please mention this to a demonstrator before you continue.



IV Simulation of the schematic design using AccuSim

In this section you will run the AccuSim simulator to determine the electrical behaviour of your nor2 design when driven with typical signals. The results you obtain will give you a good indication of the efficiency of your design, and should show evenly matched rise and fall times of a few nanoseconds, dependent upon the details of your layout.

Running AccuSim consists broadly of two distinguishable operations:

• preparing power supplies, signals and other stimuli • running the simulation and inspecting the results.

Before you proceed with the AccuSim section, you should have completed all previous sections in this guide, and you should have a Design Manager session and (preferably) a DVE session running. 14. Open AccuSim on the back-annotated viewpoint. Restore your Design Manager session to the screen. In the Navigator window,

open up the nor2t object to expose the various design objects, including the AccuSim viewpoint you created and back-annotated. Select this by clicking it, and use the method of data-centred invocation to start up AccuSim on this object.

Note: You must start up AccuSim on the specific design viewpoint object. In particular, do not attempt to start AccuSim on the nor2t component, in the hope that it will somehow identify the correct design viewpoint! If you do, AccuSim will generate a default viewpoint with no embedded Mietec device models, and you will be unable to run the simulation.

Watch the screen as AccuSim starts up. Apart from the palette window, you should see two sub-windows appear; one containing the schematic corresponding to the viewpoint being modelled; the other displays simulator status messages. The schematic window should display the red back-annotations generated in ICstation. If not, or if any other unexpected messages appear, speak to a demonstrator.

15. Set up AccuSim to perform a DC Sweep analysis on the nor2 gate We shall determine the transfer function of the gate by holding input A fixed (at 0

volts), while varying input B over the range 0 - 5 volts. Before the simulation can begin, we must first set up some voltage and signal sources (referred to in AccuSim as forces). In most cases this can be achieved by selecting nets in the schematic, but some typing will also be required.

First we set up the power supply. In the schematic window, select the net to be connected to the positive VDD supply by clicking on it. Make sure the DC Mode palette menu is selected, and click on (Palette Menu) > ADD FORCE. When the dialogue box appears, note the Signal identifier or net ID - it may be required later. Set the Type to DC and the Magnitude to 5. OK the dialogue box.

Now we set up a static voltage of zero at each of the inputs A and B. We shall later specify that B will be varied in order to determine a transfer characteristic. Select one of these two nets in the schematic by clicking on it. Click on the (Palette Menu) > ADD FORCE item. The corresponding name should appear in the Signal field of the dialogue box; if it does not, type it in. Enter 0 for in the



Magnitude field, and type the name of the second net to be set in the field labelled: Other signals of the same DC force – e.g. /A. OK the dialogue box.

Review the forces that have so far been applied by giving the command: (Menu bar) > Report > Forces on Schematic. An Info Messages window pops

up. Check the specification of each of the forces. Note that each force has a characteristic Forced Net identifier: note the IDs for the three forces.

16. Run the simulation to determine the transfer characteristic of the nor2 gate. Now set up the simulation run. Click the SETUP ANALYSIS item in the palette

menu. In the resulting dialogue box, select DC Sweep, and enter the force ID you noted in paragraph 15 for signal B. In the From, To and Increment Value fields enter 0, 5, and 0.1 respectively. OK the dialogue box.

Finally, determine which waveforms to keep for observation. In a large design it would be necessary to be selective, but in this case no serious penalty results from keeping them all. With the schematic window active, select inputs A, B, and output Y. Click the ADD KEEPS item in the palette menu. In the Add Keeps dialogue, click Selected and check the keep ALL schematic signals box. OK the dialogue. Give the command:

(Menu bar) > Report > Keeps to verify the information that is to be kept.

To run the simulation, click the RUN item in the palette menu. If all is well, the simulation should run within a second or two, and the Results palette menu should appear.

If a problem has arisen with the creation of the viewpoint, you may be greeted with messages like "Can't find models for TR_N and TR_P". If you encounter this problem, please discuss it with a demonstrator before trying to continue.

To chart the results, with the schematic window active, select input B and output Y; then click the CHART item in the palette menu. You should see graphs including one of output voltage against input voltage. Note the availability of screen cursors (key F5) to help with quantitative measurement. It is also possible to print the active graph using the command: (Menu bar) > File > Print > Active window, using a procedure similar to that described in Lab Guide 5 for QuickSim II. Please ask if you need further details for setting up printing.

• From the graphs, determine the maximum linear amplification of the gate with respect to input B, i.e. ( ∂ ∂V VY B/ ).

• At what input voltage level is maximum linear gain achieved? • Consider the accuracy of the measured linear gain value. How might you set

up the simulation conditions (paragraph 16) in a slightly different way in order to enhance the accuracy obtained?

• Determine the input switching level (at which VY = VB). • Now determine the transfer function, gain and switching level relative to

input A. • Estimate the noise margins (E1 course notes or see Weste & Eshraghian). • How might you use AccuSim to determine the transfer function with both

inputs being swept simultaneously (rather than just A)?



From the foregoing, you should be in a position to decide whether or not the circuit has suitable functional characteristics for use as a NOR gate. However, this analysis has given no information about the dynamic performance of the gate (i.e. its speed). The following paragraphs detail how to carry out a transient response analysis of the nor2 design.

17. Set up a Pulse stimulus for use in transient analysis In order to predict the rise and fall time of the nor2 gate, and hence the delay

imposed by it on digital signals, we must carry out a transient analysis. In AccuSim a transient response is constructed by evaluating nodal voltages and currents at intervals determined by a time-step until a specified stop-time is reached. It is necessary also to specify at least one input signal as a time-varying function. AccuSim offers several possibilities for this, including sinusoids, pulses, exponentials, or piece-wise linear waveforms. In digital circuit modelling, the most useful of these is the pulse waveform. To specify a pulse, several parameters are required. These are illustrated by the waveform in Figure 3 below.

It is important to establish realistic values for the Rise and Fall times; however, for the time being, the suggested settings of 1ns will be satisfactory.

Figure 3: Force Pulse Signal Parts

To set up the analysis, click the SETUP ANALYSIS item in the DC Mode

palette menu. When the Setup Analysis dialogue appears, click Transient. Note that it is possible here to adjust the Stop Time and the Time Step; however, these need not be changed for the moment. OK the dialogue box.

For the time being we shall keep the signal connected to input A fixed at 0 volts, and apply a pulse waveform to input B. Give the command: (Menu bar) > Report > Forces, and verify that the signals applied at VDD and A are still correct. Correct these if necessary. With input B selected in the schematic window, click the ADD FORCE item in the palette menu. When the dialogue box appears, select the Pulse option, and fill out the dialogue box to generate a waveform to exercise the gate and cycle the output Y through each possible transition. Be sure to set the Initial Value and Pulsed Value to appropriate magnitudes, and be aware that the units of time are seconds unless qualified by the prefix n, etc. When all values are appropriately set, OK the dialogue box.



18. Carry out a transient analysis on the nor2 gate. Use the RUN item in the palette menu to initiate the simulation.

Note: If you should observe the error message: "Internal timestep too small", you may need to adjust either the rise/fall times of your pulse waveform, or certain other AccuSim tolerance parameters. Please speak to a demonstrator.

To view the results, select in the schematic window the inputs and outputs required, then click the CHART item in the palette menu. You may wish to use cursors to help determine accurate rise/fall/delay times, or to generate a print-out. When recording your results you must state the capacitance being driven, as without this information your results are meaningless.

• Determine the output rise/fall time (10% to 90%) under these conditions. • Determine the delay between input stimulus and output response, by

measuring the delay that elapses between the input signal passing through VDD/2 and the output signal passing through the same level.

• Determine a suitable PULSE force to apply to input A so that the combination of signals applied to A and B exercises the nor2 design through all possible input and output states. Compare the rise/fall delay times for every possible input combination.

• If time permits, investigate the effect of varying the rise time/fall time of the applied pulse waveform(s).

• Use the table templates in the Appendix to help with presentation of the data.

19. Determine the effect of external parasitic elements. In an earlier section you evaluated ‘by hand’ the capacitance associated with the

metal interconnect required to connect the output of the nor2 cell to the inputs of an adjacent nor2 stage (as in the ring oscillator), and thus determined the total capacitive load driven by the original gate. However, the transient response you just determined was for the nor2 cell totally isolated from any other circuits. Under these conditions, which are not truly realistic, AccuSim cannot be expected to give accurate values for the expected ring oscillator frequency.

One way to circumvent this would be to edit the nor2 layout temporarily, adding metal and other shapes typical of the kind of interconnect we might reasonably expect. ICextract could then be used to regenerate more accurate back-annotations. If you wish to try this approach you may; however, we shall explore here a more convenient technique which will achieve the same objectives.

We shall instead edit the back-annotation information supplied to the design viewpoint, and re-run the transient response determination, in a form of heuristic 'what if' experiment.

With the schematic window active, select the output net Y. Give the command: (Menu bar) > Edit > Property > Change... The Change Properties dialogue should appear, listing the single property of that net which can be changed: cap_net, the capacitance property that was established by ICextract when it earlier applied the back-annotation data. This represents only the internal capacitance, due to interconnect inside nor2. Select this property, and OK the dialogue box. A new, Change Property dialogue should appear. Edit the Value field so it contains a new capacitance value corresponding to the sum of the old value plus the external contribution, determined in paragraph 8. Record this value, and OK the dialogue box. You should see the red annotation in the



schematic update in consequence of the change you just applied. Give the command: (Menu bar) > Report > Design Changes, and confirm that the new listed back-annotations are consistent with your expectations.

Re-run the simulation, chart the transient response, and determine the new timing characteristics of the gate. Be sure to specify the capacitance being driven when you record your data. As before, if you should observe the error message: "Internal timestep too small", you may need to adjust either the rise/fall times of your pulse waveform, or certain other AccuSim tolerance parameters. Please speak to a demonstrator.

20. Investigate the effect of varying supply voltage VDD. The effect of the supply voltage VDD in determining the conductance of the

transistor channel was discussed in an introductory sheet, and you may by now have had the opportunity to investigate the measured performance of a real ring oscillator at various different supply voltages. We shall use AccuSim to try and model the performance of our ring oscillator design at a reduced supply voltage of 3 V, and hence predict the dependence of oscillation frequency on VDD. In order to investigate this using AccuSim, it is necessary to modify the specification for the voltage source set up in paragraph 15, as well as the amplitude of the pulse stimulus set up subsequently for the transient analysis.

On the schematic, select the appropriate net corresponding to the VDD supply rail, and use the (Palette Menu) > ADD FORCE item to modify the supply voltage VDD to 3 V. If necessary, change the magnitude of the signal applied to input A so it lies within the range 0-3 V. Finally, select net B, and use the FORCE item in the palette menu to change the amplitude of the pulse signal applied to 3 V. Use the (Menu Bar) > Report > Forces command to confirm these modifications have been correctly carried out. Carry out a transient analysis as in paragraph 18, and compare the results obtained. Compare these also with the results obtained from direct measurement on the experimental ring oscillator.

21. Investigate the effect of varying W/L. The effect of aspect ratio (W/L) on worst-case gate delays has already been

described. Careful choice of W/L is required to ensure that the delays corresponding to rising and falling signals are matched. You should by now have discovered how effective this matching process has been in your own case! In any event, we shall now briefly investigate the effect of modifying the W/L ratio for the p-channel transistors. As already discussed in paragraph 19, this could clearly be achieved by modifying the original design (the schematic in this case, rather than the layout); however, it is more convenient to carry out this experiment directly in AccuSim. This can easily be achieved, because the information is actually transmitted to AccuSim by means of the instpar property.

With the schematic window active, select one of the p-channel transistors. Give the command: (Menu bar) > Edit > Property > Change. When the dialogue box appears, select the instpar property for editing. Change L and/or W in such a way as to alter the aspect ratio by a factor 2-3. Repeat this procedure for the second p-channel transistor. Re-run the simulation and determine, and record, the new rise and fall times. If time permits, collect sufficient results to allow you to plot a graph showing the variation of delay time with W/L.



Note: during the procedures described in paragraphs 18 onward, you may encounter one of the limitations of AccuSim. When simulating circuits such as this with fast, but varying transient responses, AccuSim is occasionally unable to achieve numeric convergence at points in the simulation corresponding to rapid changes at the input(s). You may find it necessary to alter the rise and/or fall times of the input pulse waveform or AccuSim’s tolerance parameters in order to obtain useful results.

22. Investigate other important sources of parasitic capacitance

Carry out this section if time permits. Otherwise proceed to paragraph 23.

So far we have looked in some considerable detail at the parasitic capacitances arising within the nor2 gate from metal and polysilicon interconnect. You can see for yourself the values of capacitance used by examining the output file generated by AccuSim. To do this, give the command: (menu bar) Report > View Outfile, In the resultant listing, study the section following the line beginning: .OPTIONS

You should be able to reconcile most of the source, gate and drain connections to the MOSFETs (M) with the port names A, B, and Y; comparison with the schematic in the ICGraph window should allow you to recognise all the interconnect capacitances (C) identified by ICExtract and back-annotated to the schematic. Refer to the supporting pamphlet: Analogue Simulation & Accusim for a simple explanation of the format used. Consult a demonstrator if you still have difficulty interpreting this listing.

However, there is a vital source of capacitance that has so far been completely overlooked; the capacitance due to the source and drain regions of each of the MOS transistors. For a more complete discussion of the origin of these capacitances, see for example: Analysis and Design of Digital Integrated Circuits, by Hodges & Jackson, p 75. Manufacturer’s process data invariably includes coefficients that relate the capacitance to the area and perimeter of the source and drain – in the AccuSim models in use here these are the parameters CJ and CJSW. You should be able to identify these parameters in the early part of the output file generated by AccuSim. AccuSim is in fact perfectly capable of evaluating these contributions to parasitic capacitance; however, their effect can only be quantified if the area and perimeter of each source and drain (in contact with the substrate) is known. In the present case this information is not available from ICExtract, however, and can only be provided via the instpar property.

Use the layout plot for the nor2 cell to estimate the area (AS and AD) and perimeter (PS and PD) of each source and drain of the four transistors. Record and tabulate your results (use the templates given in the Appendix). Update the schematic to change the instpar parameter correspondingly. You can do this in a temporary way, by following the procedure of paragraph 21, or, more permanently, by updating the original schematic in Design Architect. A typical modified instpar might appear as below:

W=20U L=3U AS=400P PS=60U AD=400P PD=60U

Note the use of the suffix: P to signify a factor of 10-12 (Pico).

• With the instpar parameters updated, re-run the transient response and determine the new (and much more realistic) delay for rising and falling edges. What is now the capacitance being driven? How do these figures compare with the delays measured in sections 18 and 19?



23. Collect and present the results from this session. Gather the accumulated simulation results together and present them in an appropriate form using tables or graphs – a number of suggested templates are given in the Appendix. You should include as many as possible of the following conditions:

• DC Sweep Analyis, providing data about the gate’s transfer function • transient response with internal circuit parasitics (paragraph 18) • transient response with internal/external parasitics (paragraph 19) • transient response incorporating other effects (paragraphs 20 - 22)

Be sure to state very clearly the conditions applying to the simulations. For example, in transient responses, the results are meaningless if the aggregate driven capacitance is not quoted. It is very easy to ignore capacitive effects and get an impossibly optimistic figure for the delay. You must take care to avoid falling into this trap.

Include also in your tabulated results any relevant results obtained from measurement on the experimental ring oscillator.

24. Use results from AccuSim to model the behaviour of your design with VHDL Select those simulation results you consider to be the most realistic and characteristic for your NOR2 when used in the ring oscillator design (explaining why). Then use the procedure of Laboratory Guide 2 (Functional simulation with Modelsim) to model the overall system behaviour of your ring oscillator design based on the predicted timing characteristics of your nor2 cell. Hence determine the key timing parameters of the proposed ring oscillator module designed in this way.

Conclusion

The last few paragraphs should have given you some insight into the issues that most directly affect the behaviour of fast CMOS logic gates. We shall leave the verification process at this point, but should perhaps observe that there is considerably more that could be done.

• Although we have made reasonable estimates of interconnect capacitances, the real ringarray has not yet been laid out, so we do not know what parasitic capacitances might arise owing to the interconnect used to link outputs to inputs, etc. A slightly different kind of extraction can elicit this data once the layout has been performed.

• AccuSim is not suitable for modelling the entire design, so at this stage, having assured ourselves of the satisfactory performance of our nor2 cell, we might develop a QuickSimII timing model for it and use that simulator for the remaining work.

The remainder of the project is concerned with the use of semi-custom tools associated with ICstation, to prepare for the entire top_level design a set of masks ready for despatch to the fabrication facility.



Laboratory Guide 7 – Appendix I

The following suggested table templates may be of help in the presentation of material in the sections of the Final Report relating to this Lab Guide. Please adapt the formats to meet your own specific requirements.

Interconnect capacitances

Index Interconnect type Description Area / µm2 Capacitance / fF

1 2 3

…. A similar table may be used to present calculated or extracted capacitance values. Capacitances associated with ports

This table may help with assessment of the parasitic capacitance being driven by each gate output owing to coupled interconnect and input ports.

Port Identifier Area references Capacitances / fF Total Capacitance / fF

A similar table may be used to present calculated or extracted capacitance values. Areas and perimeters of transistors

Source Drain Gate Transistor ref. Area (µm2) Perim (µm) Area (µm2) Perim (µm) Area (µm2) Perim (µm)

Rise, Fall and Delay times for transient inputs

O/P Rise/ Fall

Original setup External

capacitances included

Reduced supply voltage

Doubled W/L ratio for p Other conditions Input

conditions Rise/fall

ns Delay

ns Rise/fall

nsl Delay

ns Rise/fall

ns Delay

ns Rise/fall

ns Delay

ns Rise/fall

ns Delay

ns A falls B falls Both fall

Rise

….. Similar tables may be used in other parts of the report, e.g. in Lab 8 to present area & number of vias for various procedures applied to flattened or hierarchical layouts.



Computer-based project in VLSI Design Lab Guide 8 - Semi-Custom Design

D M Holburn May 2007 ICFlow2003.3 141 C6lab8.doc


Laboratory Guide 8 - Semi-Custom Design

This laboratory guide provides an introduction to the techniques of Semi-Custom Design of IC layouts using Mentor Graphics' ICgraph tool, together with the subsidiary tools: ICplan, ICblocks, and ICcompact. All work is done within the ICstation environment. In this form of semi-custom design, we begin with the schematic design for top_level, and lay out complete circuits in silicon using automated place-and-route procedures. The circuits we create will comprise sets of standard cells, each of which corresponds to a symbol in the schematic. One of these standard cells will be the nor2 layout cell created and verified in lab sessions 3, 6 and 7.

The result is a layout consisting of cells in neat rows with routing in between, providing power distribution and interconnecting signals as required. The entire design is placed within a power frame and equipped with pad drivers and bond pads at the periphery.

Although this design will not be sent for fabrication, it would be perfectly possible to do so. Instead, we shall satisfy ourselves with printing out a checkplot of the entire chip layout. It is expected that colour printer output will be available as well as monochrome laser printer output.

Orientation The laboratory guide is divided into three main sections.

In the first section (I), you will make preparations for carrying out the design, by building a library of layout cells and generating a design viewpoint for ICgraph.

In the second (II), you will construct a cell (named top_level_flat) in which the constituent core gates are loaded in flattened form, i.e. they are placed and routed so that the electrical connections are connect, but in an arbitrary configuration, i.e. they are not grouped to correspond with the original schematic. You will then have an opportunity to experiment with via reduction and compaction. The second section also gives details of how to go about generating a colour hardcopy of the completed design.

All groups should complete Sections I and II and should attempt Section III.

In the third section (II), you will generate a hierarchical layout (top_level_hier) with the primitive gates grouped into functional blocks.

Editor modes There are three important modes in which ICgraph can be operated when being used for editing layouts.

When designing the nor2 cell, ICgraph was used in a mode known as Geometry Editing (GE). In GE mode, there are no direct restrictions on the kind of edits that can be carried out. We shall meet two new modes in this session.

Semi-custom design requires that ICgraph be run in a special mode, known as Correct by Construction (CBC). In CBC mode, the nature of the editing operations that can be carried out is significantly reduced so that layout changes carried out by hand do not cause connectivity violations (for example, the inadvertent deletion of a track or path). Naturally, layout changes must not violate design rules either.

ICgraph has an intermediate mode of operation known as Connectivity Editing (CE). In CE mode, no restrictions are placed on edits, but warnings are issued if an operation results in a change of connectivity.



In the version of Mentor (ICFlow 2003.3) being used for this project it is possible to remain in the CBC mode for the whole of this session. This ensures that no violations of design rules should occur, and that the layouts produced correspond exactly to the schematics from which they are derived.

Circuit blocks and interconnect All the essential elements of the proposed design are held in a top-level cell. Here these elements comprise circuit blocks and interconnect.

The circuit blocks are collections of cells which may have a direct correspondence with the separate components comprising the schematic design, e.g. 4bit_counter, comparator. However, such a correspondence is not always necessary. Often cells may be assembled in groups together more by virtue of their physical shape and size, or their nature (analogue, digital, memory etc) rather than their status within the schematic. The cells being referred to include I/O pads and drivers (ic, oi2), which are conventionally positioned around the periphery of the cell. Since I/O pads are physically large, their number may determine the physical size of the cell far more directly than the core cells.

The interconnect comprises metal1 and metal2 wires which carry signals between the blocks, and between their constituent cells, as well as power supplies. Power supplies may be required to carry significant current, and are typically laid out as broad, gridded strips of metal1 or metal2, usually as the first stage of the automated routing process. The I/O pad drivers typically consume a large proportion of the total chip power requirement, and are therefore sited on or near a power frame constructed of broad metal interconnect, which distributes necessary power supplies to them. Power is brought onto the circuit by means of dedicated pads (in this case iovdd and iovss), which are joined directly to the power frame.

Cell library We shall use the nor2 cell studied, laid out and verified earlier in this project, to form the heart of the ring_oscillator module. As a result of the detailed modelling work carried out in the last lab session, this cell is by now well characterised and suited to this requirement. Other cells used in this design will be taken from the set provided by Mietec,

In order to achieve this this, we shall build a cell library ringlib (which will be specific to this project), and place in it details of all the cells required in the final layout. The nor2 cell used will be the layout carried out in Lab Guide 6, while the remaining cells (digital gates and I/O pads) will be drawn from the database of cells supplied by Mietec. Creation of the library is carried out using commands available in ICgraph.

Note that no cell data as such is actually placed in the library; the library consists of a list of references (directory paths) to the required set of cells, most of which are held in a centralised database.



Section I – Creation of design viewpoint and library

In this section, you will make preparations for carrying out the design, by building a library of layout cells and generating a design viewpoint for ICgraph.

You should be logged in at a workstation as described in the Getting Started pamphlet, with Design Manager running. The current Mentor working directory should be $CBT_WD (which is the soft prefix for your $HOME/cbt directory), and you should select that same directory with the Navigator.

1. Determine the list of cells required. Before it is possible to build a chip layout, we need to assemble the complete set of

cells required into a single library. You will probably have determined the names of the full set of schematic cells embodied in the top_level design before now, but if necessary, carry out the following instructions in order to build the list of cells.

Within Design Manager, select the top_level component icon in the Navigator window. Open the Component Hierarchy window by giving the command: (Menu bar) > Report > Open Hierarchy Window. You should recognise the various major schematic cells on which you have worked: ring_oscillator, comparator, etc. Left click each in turn; using the right mouse button, give the command: (Popup Menu) > Show Levels. You should then be able to determine the lower-level schematic cells. Most are marked with a diamond: ♦, signifying they are schematic cells.

Compile a list, preferably in alphabetical order, of the different low-level schematic cells in the design, including the I/O pad cells. Note that certain of the I/O pad cells are held as schematic, non-primitive cells, while others are primitive. Each cell name should appear just once on your list. Ensure also that your list contains both the power pads iovdd and iovss – these are essential. Do not descend beyond the level of the library cells – if you see names like nand2_analog appear, use (Popup Menu) > Hide/Show Hierarchy to retreat upwards. The number of distinct names will clearly depend on how widely you have drawn from the Mietec library in developing your design.

If you wish, you can generate a printed version of the full-length report. To do this, right-click in the Component Hierarchy window and select the command (popup) > Report. A HW Report text window should appear. Give the Design Manager command: (Menu) > File > Print > Print Document to generate a Postscript file for printing. If required, specify the printer as mgcps_a4.

Use mgcplot to preview and print the resultant document file.

2. Create a design viewpoint upon top_level for ICgraph. In order to carry out the semi-custom layout, ICgraph needs a viewpoint to be

constructed upon the top-level schematic in the design. This requires DVE.

With the Design Manager Navigator window active and open on the $CBT_WD directory, select the top_level component. Using the method of data-centred invocation, start up DVE upon that object. When DVE displays its menu, give the command: (Menu bar) > Mietec > Setup ICgraph. Observe the message "Mietec setup for ICgraph is done" in the message area.

We now save the newly constructed viewpoint with a distinctive name. Give the command: (Menu bar) > File > Save Design Viewpoint > Save As...

In the New Name field, enter the name: icgraph_vpt1, and OK the dialogue box. The message area should show that the viewpoint was saved successfully. You can now close the DVE application and revert to Design Manager.



3. Construct the cell library using ICstation and generate a printed listing. Start up ICstation. Do this by double-clicking its icon in Design Manager's Tools

window, in order to avoid opening any specific cell.

We shall create a library named ringlib, and add to it the cells required for this design. Give the command: (Menu bar) > File > Library > Create. When the dialogue box appears, use the Navigator to ensure the current directory is $CBT_WD, then enter the name ringlib into the Library field. OK the dialogue.

Now we add cells to the ringlib library. The operation of adding cells must be done in two stages; first, the single nor2 cell from the $CBT_WD directory; and second, the remaining digital cells from the Mietec library.

Give the command: (Menu Bar) > File > Library > Add To .. When the Add to Library dialogue appears, click the Browse.. button and select the nor2 layout cell in your own $CBT_WD working directory. OK the navigator box.

The Add To.. procedure only allows us to add one cell at a time, whereas we wish to incorporate several further cells from the Mietec cell library into our own ringlib library. Give the command: (Menu bar) > File > Library > Edit.. and enter $CBT_WD/ringlib, or use the Navigator to select it. Click on the Browse button below the Cell List window. You should see the Select cells from directory dialogue box, showing the cells available in the $CBT_WD directory. Click in the Look in: field, and enter directly: $MIETEC_LIB in place of the existing text, followed by Enter. Now navigate to: $MIETEC_LIB/layout/cmos24/cells, by clicking the appropriate entries in the list. Select the remaining cells required from the list that appears in the scrolling box. Do not select nor2 here – your own version of this cell has already been inserted into the library. You can select additional cells without de-selecting the first by holding down the Control key before clicking on them. When you have selected the required cells, OK the dialogue box. The path names for the complete set of chosen Mietec cells should now appear, selected, in the listbox of the Edit Library dialogue. Make sure the Append and Save Library buttons are checked, then OK the dialogue.

Give the command: (menu bar) Report > Library.., enter ringlib as the Library name and choose Window for the report target. Review the list of cells now contained in the library, and check there are no omissions. Remedy if necessary by using the Edit.. procedure just described. You will first need to use the (Menu bar) > File > Library > Reserve.. command in order to reserve the ringlib library for edits.

For your report you will require a printed list of the library cells used.

To obtain this, switch temporarily to Design Manager. With ringlib selected in the Navigator window, click on (palette window) > HIERARCHY.

When the Open Hierarchy dialog appears, make sure that $CBT_WD/ringlib is selected, and OK the dialog. An IC Hierarchy window will appear. Right-click in this, and choose the command: (popup) > Setup > Display. In the resultant dialog, select Show Full Path and OK the dialog. The cells used in your library should be listed, complete with their paths. Verify that these are complete and appear to be correct before proceeding.

To generate a printable report, right-click in the IC Hierarchy window and select the command (popup) > Report. A HW Report text window should appear. You can now use the Design Manager command: (Menu) > File > Print > Print Document to generate a Postscript file for printing. If required, specify the printer as mgcps_a4.

Use mgcplot to preview and print the resultant document file.



Section II Creating a flattened layout

In this section you will create a flattened layout for the ring design. All designers should complete this section. If time permits, continue with section II, which indicates how to build a hierarchical layout.

4. Create an empty cell to hold the complete layout. The top-level cell is the repository for circuit blocks (including I/O pads) and

interconnect. At this stage, we know very little about the organisation of its contents, but we must provide certain basic information about it for use by the automated tools. To create the cell, click the Create button in the Session palette menu. The Create Cell dialogue box appears. This is one of Mentor’s more complex dialogues – take care to enter the data correctly.

First set up the following conditions by entering data or clicking the corresponding buttons, as appropriate: if you prefer, use the Navigator to select the name for the Attach Lib entry:

Cell name top_level_flat Attach Library $CBT_WD/ringlib Process $MIETEC_CMOS24_IC_PROC Rules File Leave blank

Site types Leave blank Angle mode 45 Cell type Block

Connectivity With Connectivity

The dialogue box should now expand to show a further area headed EDDM Schematic Viewpoint, and will offer other options. Enter as follows:

Eddm schematic viewpoint $CBT_WD/top_level/icgraph_vpt1

or use the Navigator to select the viewpoint file. Click on the Logic Loading Options button: a further dialogue box should open. Check that Viewpoint Directory is set to $CBT_WD; select the following option:

Logic Loading Flat

Don’t change any other entries. OK the dialogue.

Finally, OK the Create Cell dialogue box and observe the message area for possible diagnostic messages. If any errors are reported, consult a demonstrator. You may be invited to view a file named logic_load, which you should find in $CBT_WD. If you examine this file you will note warning references to dangling nets. These are in fact benign - they refer to the bond pads, to which external wired connections will be made when the circuit is connected up. ICgraph is simply warning you that at this point they are unconnected.

If all is well, a cell window should now open, but will appear blank as it contains no cells or interconnect at this stage.

Note: if you should subsequently decide to abandon this cell and start over, you should do the following:

• Close the design window by double-clicking its system icon, or otherwise. • Answer: Discard when prompted to save the cell. • Give the command: (Menu bar) > File > Unload Cells. • Return to the start of paragraph 4.



5. Set up the rules to allow the cell to be built in CBC editing mode. In order to build the design in CBC (Correct-by-Construction) mode, a set of Rules has to be specified for the process. Give the command: (Menu bar) > File > Load Rules... Enter the response: $MIETEC_CMOS24_IC_RUL. Verify that the cell mode is correct: the status line at the top of the design window should show CBC after the cell’s name. You are now ready to create a Floorplan for the design.

6. Create a floorplan for the design. We now enter the ICplan module in order to create a floorplan for the design. The floorplan is simply a set of rectangular shapes identifying suitable sites to place the cells. The size and format of the shapes is determined automatically by the floorplanning utility by considering the number and size of the cells and pads that must be placed; however, no allocation of cells to sites is done yet.

Click the Place & Route item in the Session palette. The Place and Route palette should appear. Click on Autofloorplan. On this occasion, do not change any of the options; simply OK the dialogue box.

After a few moments, you should see a completion message generated by ICplan.

Press Shift+F8 to ensure you are viewing the entire design. You should see a ring of I/O pad cells surrounding rectangular areas delineated in green; these represent rows on which the necessary core layout cells will be aligned. Their area has been calculated by ICplan to be sufficient for the cells required by the design.

7. Place the standard cells in the design. The remaining standard cells from the ringlib library must now be placed before

routing can take place. In the Place & Route palette, click the StdCel item. The Autoplace Standard Cells prompt bar should appear, and offers an Options button. Click this to call up the Standard Cell Placer Options dialogue box. No changes should be required to the entries in this dialogue; however, you should confirm that the following settings are in force, and select them if necessary.

Under the item Placement Method, check the box for the option: Initial+improve. For Wire Bias select Balanced. OK the dialogue box, and the prompt bar.

After a short period of processing, you should see the design screen update to show all the cells in automatically chosen sites. Zoom in and try to identify the key modules of the design (ringarray, nor2, comparator etc, and their derivatives). Depending on the details of your own cells, you will almost certainly find that there is no clear distinction between them. This is typical of a flattened layout.

8. Automatically route the layout. It remains to insert the power frame, power rails, and wire all the core cells together

and to the I/O pads. This is accomplished with ICblocks, as follows.

Under the Autoroute heading in the Place & Route palette, click on All. A prompt bar should appear at the foot of the screen. For the moment do not change any of the options, but click OK. In approximately 30 seconds (dependent upon system loading) the circuit should be fully routed.

• Inspect the layout, and try to make an assessment of the efficiency of the placement and routing. Are the blocks regularly placed and the connections between them short and direct?

• Consider the set of nor2 cells which – in the schematic – are regularly interconnected to form the ring oscillator array. Has the regular schematic given



rise to a regular layout? Is there any evidence of apparently unnecessary loops of interconnect?

• Make a note of the design’s total X and Y dimensions. Use the command: (Menu bar) > Report > Active > Context and determine the dimensions fom the

Extent paremeters. You may wish first to use (Menu bar) > Report > Setup Reports to direct your reports to a scrolling window rather than a popup box for ease of reading.

• Note also the number of via objects and nets generated by this operation.

• If you were unfortunate, ICblocks may have been unable to complete the routing. You may see a few yellow overflows, signifying connections that could not be made automatically. If you see these, the demonstrators may be able to advise on possible remedies. For the circuit to work, these problems need to be resolved, but this may be time consuming! We shall leave this problem for now, but return to it in Part III where we develop a fully hierarchical layout.

At this stage, it is wise to save the cell, using the command: (Menu bar) > File > Cell > Save Cell. Be sure to reserve it for edits before continuing.

9. Attempt to reduce the number of vias. The initial attempt at automatic placement and routing may need optimisation. For

example, the router may have used more vias than actually necessary in planning the crossovers (i.e. structures to allow wires to cross over other wires of the same material -- see the example in the diagram below).

Metal 1

Metal 2

BeforeVia Minimisation

Metal 1

After Via Minimisation

Metal 2

Metal 1

Metal 1

To minimise the vias, first make sure nothing is selected (press F2).

Now click on the MinVia item in the Place & Route palette, under the heading P & R Edit. A prompt bar will appear. You must now identify the sequence of routing levels at which minimisation will be attempted, and the maximum length of interconnect that will be searched. In this dialogue, levels 1 and 2 correspond to the layers Metal1 and Metal2 respectively.

Enter 1 in the From Route Level field, and 2 in the To Route Level field.

Enter 500 in the Maximum Length field, and OK the dialogue box.

When the minimisation is complete, execute the command: (Menu bar) > Report > Active > Context. Note the new number of vias.

Repeat the via minimisation operation, this time with From Route Level set to 2, and To Route Level set to 1.

Again determine the reduction in the via count achieved. 10. Compact the design. The initial layout is unlikely to be the most compact that can be achieved. ICplan is

fairly conservative about the size of the floorplan it constructs, to minimise the risk that routing cannot be achieved. The operation of via minimisation is likely further to



reduce the actual area required by the design. Compaction seeks to condense the design down to the minimum possible size, without modifying cells or connectivity, but purely by moving interconnect and eliminating unused space.

Often the principal determinant of the cell size is the number of I/O pads and drivers required. In these circumstances, little compaction may be achieved.

Compaction must be carried out independently in two perpendicular directions. This requires that the command be given twice, rather like for via minimisation.

Click the Compct item in the Place & Route palette (under the P & R Edit heading). A prompt bar should appear. In the two scrolling list boxes within it, select Down for the Direction, and Centre for the Reference. OK the prompt bar. Compaction should begin.

When it completes, use the command: (Menu bar) > Report > Active > Context to determine the new dimensions, and compare them with the original values.

Repeat the Compct operation, this time setting the Direction parameter to Right. Note the improvement in compactness. Note also that the improvement achieved is dependent on the number of pads required, (which determines the perimeter of the chip) as well as the space occupied by the core elements.

12. Generate a checkplot of the design (monochrome) You will probably wish to generate a checkplot of the output. For black and white

output proceed in the usual way:

Give the command: (Menu bar) > MGC > Setup > Printer... When the Setup Printer - General dialogue box appears, enter in the Printer Name field:

mgcps_a4 for black-and-white output (standard laser printer)

Check that the Object type is set to design (correct if necessary). Leave the remaining fields in their default states, and OK the dialogue box.

In order to print the cell, you must have it visible on the screen, and the design window must be active.

Give the command: (Menu bar) > File > Print > Print Cell ... When the Print Cell dialogue box appears, first click the Setup Print... button.

A further, Setup Print dialogue box appears. In this box, set the Paper Width to 7 inches and the Paper Length to 10 inches. Leave the other settings at their default values and OK the dialogue box.

When the Print Cell dialogue is revealed again, you must re-enter the parameters for the paper to be used. Enter 7 in the Wid field, and 10 in the Len field. Units are inches in both cases. Now click the Set button just below the Len entry field. Click in sequence the Set buttons to the right of the Pages and the Scale fields.

Finally, click the Set Layers button. You are recommended to suppress printing of the Metal1.blkg and Metal2.blkg layers, since these occupy much of the layout and appear as a strongly hatched design on the plot, obscuring much of the detail below. To achieve this, you must select the list of layers you do wish to see, and ensure that this excludes the unwanted blockages. Starting at the top of the list in the scrolling box, use the cursor down key to navigate down to layer number 13, pressing the Shift key as you do so, in order to obtain an additive selection. Select also any other layers you particularly wish to include.

When you have finished selecting layers, OK the dialogue, and note that the Layers item is now set to Other in the Print Cell dialogue box. OK the Print Cell dialogue.



The plot will then be prepared and placed in a temporary directory. You should then use mgcplot to preview the plot and direct it to the laser printer

12 (Continued) Generate a colour checkplot of the design It should be possible to direct one copy of your final plot (per designer) to a colour printer. Please do not exceed this number. To generate a plot, follow the instructions below, which are different from the foregoing, and rather long.

First check with a demonstrator that this service is currently available (it is provided via the computer operators who require prior warning of the need for colour output).

• With the design you wish open in ICgraph and on the screen, with its window activated, give the command: File > Print > HotPlot.

• The HotPlot dialogue should appear. Under Plot Handling select Use Formatter.

• Click the Set Formatter Options button, and in the Formatter Only Options dialogue, use the Browser button by the top text box to find and select the Plotcap file, called Plotcap, which is to be found in your cbt directory. OK the dialogue box.

• Click the Select Printer button, and select the only available printer "Postscript" that appears in the Select Hotplot Printer dialogue. OK the dialogue box.

• Click the Browse button next to the Setup File text box, and use the Select Hotplot Setup File browser to locate and select the file setup.p which is also to be found in your cbt directory. OK the dialogue box.

• Click the Select Layers button, and in the Print Layers dialogue, with the shift key pressed, select the layers 1 to 17, from n-well down to n-window. OK the dialogue box.

• Click the Maximize button, followed by the Compute Plot Size button, then the Scale by Width/Length button.

• Click the Set Plot Attributes button and in the Hotplot Plot Attributes dialogue that appears, check that Send Plot to Printer is checked. OK the Hotplot Plot Attributes dialogue, and OK the Hotplot dialogue. Phew! Your plot should be sent to the Colour Laserjet, cljmr1, in the Operators' area.

You may need to experiment with the scaling and rotation parameters to get the best fit of your design to the printed sheet.

Note: you can uncheck Send Plot to Printer to have HotPlot create a Postscript file in your cbt directory; typically it will be called topaxxxx, if your design is called top_level_flat or top_level_hier, where xxxx is a numeric string; you can preview this using gv topaxxxx from a shell window. This exercise is strongly recommended - zooming in to study key elements (for example, in the ring oscillator, or in an input or output pad driver) is far more practicable on a screen-based image, and will throw much light on the structure.

When you are happy with the result, exit from ghostview and repeat the operation if necessary with Send Plot to Printer checked. In due course the output will be made available by the computer operators.



Section III Creating a hierarchical layout

In this section we shall create a hierarchical layout (top_level_hier) for the top_level design.

This requires us to interact with the list of schematic cells used in the design and partition them into groups. This is done by means of a hierarchy window.

We shall construct the layout in the form of a number of distinct blocks. The blocks that apply to your design will depend on how the design is most naturally partitioned; if you have adapted the design, you may need to consider a different partitioning from that desicribed below. For instance, one likely arrangement could comprise:

• the frequency synthesiser divider (fs_divider); • the digital comparators in the programmable divider (fs_comparator); • the control logic and output stage delivering a 1:1 signal (fs_control) • the set of identical NOR gates making up the ring oscillator (ring_oscillator); • a small block containing one remaining logic gate (ring_glue).

Note that the blocks named are layout blocks, which do not necessarily have to coincide with the schematic blocks defined in Lab 4, though if they do correspond this may make visualisation of the layout stage more straightforward. If you use a different partitioning arrangement, or if you change the names, you will need to substitute the chosen ones in the sections that follow. We strongly recommend you give this some thought before making a start and compile your own design procedure based on the notes below.

We shall lay out the floorplans for each of these blocks interactively rather than automatically as in section II. The key stages are as follows:

• Create an empty cell to hold the hierarchical layout • Use the hierarchy window to expose the hierarchical structure of the design • Identify cells to go in the fs_divider block; place, route and save fs_divider • Identify cells to go in the fs_comparator block; place, route and save • Identify cells to go in the fs_control block; place, route and save • Identify cells to go in the ring_oscillator block; place, route and save • Assign remaining cell to the ring_glue block; place, route and save • Place all the new blocks in the top_level_hier cell • Add ports and route interconnect to complete top_level_hier

Along the way you may possibly meet minor problems relating to placement of cells and routing. It should become apparent that there are quite serious limits to the capabilities of even the best automated layout tools.

The remaining sections of this guide are quite long, though the activity itself should not take more than an hour – provided no errors are made! Once cell creation is under way it is quite difficult to break off the work and resume in a later session, so allow yourself an hour or more to carry out this activity, with allowance for a restart. Also, if an error is made during cell creation, it is often difficult to re-enter the procedure. If you do go wrong you are strongly recommended to restart with a new empty cell. In these circumstances:

Follow the instructions at the end of paragraph 13

Please consult a demonstrator if in any doubt.



13. Create an empty cell to hold the hierarchical layout. As in section II, we must provide certain basic information about the content of the

top-level cell for use by the automated tools. To create the cell, click the Create button in the Session palette menu to call up the Create Cell dialogue box. If you have just completed creating the top_level_flat design, several of the settings remain the same as in section II - the changes are italicised for emphasis.

Cell name top_level_hier Attach Library $CBT_WD/ringlib Process $MIETEC_CMOS24_IC_PROC Rules file leave blank Site Types leave blank Angle Mode 45 Cell type Block Connectivity? With connectivity

As you select the With connectivity option, the dialogue will extend and present additional options. Enter the following:

Eddm Schematic Viewpoint $CBT_WD/top_level/icgraph_vpt1

Click on the Logic Loading Options button: a further dialogue box should open. Check that Viewpoint Directory is set to $CBT_WD; select the following option:

Logic Loading Full Hierarchy

OK the Logic Loading Options dialogue. OK the Create Cell dialogue box and observe the message area for possible diagnostic messages. If any errors are reported, consult a demonstrator. As with top_level_flat, you may be invited to view the file named logic_load, which you should find in $CBT_WD.

A cell window should open, as before, but will appear blank as it contains no cells or interconnect at this stage.

Note: as before, if you should subsequently decide to abandon the cell and start over, you should do the following:

• Close the design window by double-clicking its system icon, or otherwise. • Answer: Discard when prompted to save the cell. • Give the command: (Menu bar) > File > Unload Cells. • Return to the start of paragraph 13, and use a new name – e.g.,

top_level_hier2. 14. Load the Rules required to allow the cell to be built in CBC editing mode.

At a later stage in the procedure we shall need to switch between CE mode and CBC mode, and back again. For convenience, we shall load the Rules file here. Give the command: (Menu bar) > File > Load Rules... If necessary, enter the response: $MIETEC_CMOS24_IC_RUL.

You are now ready to open the hierarchy window.



15. Open the hierarchy window The hierarchy window is a text window which lists all the cells and blocks of cells

involved in a design, in a form which emphasises the hierarchical relationships between them. The instance name corresponding to each cell and its component name are shown in the window. A cell can be selected in the hierarchy window, and the same cell will be selected in the design window. Each cell has a code letter describing its status, as follows:

• E signifies an external cell (I/O pad driver) • S signifies a standard layout cell • B indicates a block, itself composed of cells or blocks. • No letter signifies that the cell has been placed on the layout.

The code letter is removed when the cell is placed on the layout, but restored if the cell is removed from the layout by means of the Unplace command. The hierarchy window is controlled by commands in the Floorplan palette.

Click on the Floorplan item in the Session palette. The Floorplan palette should be displayed. Click on the OpnWin item, under the heading Hier. When the window opens, you will need to resize it so that both it and the design window are visible. Rearrange the windows so that the hierarchy window is narrow and positioned at the left, while the cell window is to the right and occupies the remaining space. You should see in the hierarchy window references to the top-level cells involved in the top_level design; these should include ring_oscillator, divider, comparator etc.

Note: had you elected for flattened logic loading in paragraph 13 rather than the hierarchical mode, these references would not have been present; the complete set of their schematic sub-cells would have been listed instead.

You should also see one instance of nor2 - the single test gate in the top_level design.

The paragraphs that follow are somewhat lengthy and at first reading they may seem rather complex. However, their objective is simply to create laid-out versions of the main blocks of logic – fs_divider, fs_comparator, fs_control, ring_oscillator and ring_glue, each comprising standard cells and interconnect. Thus, paragraphs 16 to 20 represent the creation of fs_divider; paragraphs 21 to 25 are effectively a repeat of the same procedure to create fs_comparator. Paragraphs 26 to 30 are concerned with creation of fs_control, and paragraphs 31 to 34 are concerned with the ring_oscillator block. Paragraphs 35 to 38 deal with the remaining logic, ring_glue. Finally, paragraphs 39 and after put the finishing touches to the design. Since later sections effectively repeat procedures already carried out in paragraphs 16 – 20, some are presented in a more concise form. You will need to adapt these procedures if you have planned a different partitioning or if you have used different names.

Most of the required commands are conveniently available in the Floorplan, Plan & Place, Hierarchy and Place & Route palettes, and these will be used wherever possible. Others, particularly less-common commands in the ICplan module, must be invoked by use of (Menu Bar) commands.

You are now ready to generate a cell block (fs_divider) representing the divider component, for later placement

in top_level_hier.



16. Flatten the divider cell. In the hierarchy window, click on the divider cell to select it. Click on the Flatten

item in the Hierarchy palette (under the Floorplanning heading). A prompt bar should appear. In the bar, use the scrolling list boxes to choose the following options:

Place place Copy norouting

OK the prompt bar. Observe in the hierarchy window that the divider schematic has been flattened into its constituent sub-cells, coded S. If your divider design contains any sub-blocks – for example, schematic counter elements – these will be coded B. Any such blocks must also be flattened, using a similar approach. If the design contains only simple gates (S codes) this will not be necessary

Click on the B-coded block or blocks in the hierarchy window to select them. Click on the Flatten item in the Hierarchy palette. Set the prompt bar options as before, and OK the prompt bar. The block/s should now have been flattened into their constituent cells, all coded S. Repeat until all blocks are decomposed.

17. Combine the standard cells into a new block. We shall now gather together all the cells from the flattened divider and assemble

them into a new block. Prior to doing this it is necessary to detach the current library. With the design window active, give the command: (Menu bar) > File > Library > Detach.

Now, in the hierarchy window, select all cells bearing the code letter S. When you have done this, check in the status bar that the correct number cells have been selected (Sel: item).

Click on the Partition item in the Hierarchy palette (under the Floorplanning heading). In the resulting dialogue, enter fs_divider in the New Cell name field. Select the Preserve Placement setting. OK the dialogue.

Observe the resulting changes in the hierarchy window, and in particular, the presence of a new part, fs_divider.

18. Lay out a floorplan shape for the cell fs_divider. We shall interactively lay out a floorplan shape for the new block.

Make sure fs_divider is selected in the hierarchy window - click it if necessary. Then activate the design window and give the command: (Menu Bar) > Packages > ICplan > Add FP shape. In the prompt bar that results, use the Tab key to outline the Shape Extent item (or click with the mouse). Now, in the design window, with the Select button depressed, drag out a rectangular shape. Note that a small percentage figure is shown by the cursor; continue dragging until this reaches at least 250%. This figure indicates the relative size of the floorplan compared with the net area (excluding interconnect) of the cells it must accommodate. The greater the figure, the smaller the risk that auto-routing will fail.

Now we must extract the cells selected in the hierarchy window (now represented by the name ring_count) into the newly created floorplan shape. To do this, give the command: (Menu Bar) > Packages > ICPlan > Link Shape. The shape should acquire the name fs_divider.

19. Change the editing context to fs_divider and set up the cell. We must now complete the creation of the fs_divider cell and save it so it can later be

placed in the top-level top_level_hier cell.



Change the editing context to fs_divider by giving the following commands: (Menu bar) > Context > Hierarchy > Peek, and OK the resulting prompt bar. The fs_divider cell should appear shaded.

Now give the command: (Menu bar) > Context > Hierarchy > Set context. Click within the fs_divider floorplan shape. Observe in the title bar of the design

window that the context has now changed from top_level_hier to fs_divider, and that the floorplan shape is now outlined in green.

Re-attach the library with the following command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib

cell library. OK the dialogue box.

Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. In the Floorplan palette, click on:

• Autofp and OK the dialogue box; • Back, followed by Place & Route (to select the Place & Route palette); • StdCel (under Auto Place), and OK the prompt bar.

At this stage press Shift+F8 if necessary to view the entire layout. The cells have been placed, but interconnections still need to be routed. You should see networks of yellow overflow links, representing the set of interconnections still to be resolved. Continue with the following commands, from the Floorplan palette:

• Ports (under Autoplace), and OK the dialogue box; • All (under Autoroute), and OK the prompt bar.

• Use Shift+F8 to view the entire cell layout

Note that ports are virtually invisible when placed at this stage, but they can be seen as small rectangles within the green border around the floor plan shape.

You should now observe a placed and routed block. In most cases ICblocks can automatically generate all the required interconnections using metal1 and/or metal2, but if the structures are complex there is a risk this operation may fail, and you will continue to see yellow overflows. Consult a demonstrator if this is the case.

Save the cell at this point: (Menu bar) File > Cell > Save Cell.

20. Change editing context temporarily back to top_level_hier. Give the two following menu commands: (Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar.

Make sure the cell fs_divider is selected in the hierarchy window, then activate the design window is before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_count part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to generate a cell block (fs_comparator), representing the comparator used in the pogrammable divider

component, for later placement in top_level_hier.



21. Flatten the comparator cell. In the hierarchy window, click on the comparator cell to select it. Click on the

Flatten item in the Hierarchy palette (under the Floorplanning heading). In the prompt bar, choose the following options:


OK the prompt bar. Observe in the hierarchy window that the shift register has been flattened into constituent sub-cells, coded S. If any new blocks (B codes) result, see the notes in paragraph 16 to flatten these.

22. Combine the standard cells into a new block. We shall now gather together the standard cells from the flattened comparator

schematics and assemble them into a new block fs_comparator.

In the hierarchy window, select the cells now bearing the code letter S. When you have done this, check in the status bar and by comparison with your written list that all required cells have been selected.

Re-activate the design window, and detach the current library by giving the command: (Menu bar) > File > Library > Detach. Re-activate the hierarchy window and click on Partition in the Hierarchy palette; in the resulting prompt bar, enter fs_comparator in the New Cell Name field. Select the Preserve placement setting and OK the prompt bar. Observe the appearance of a new part, fs_comparator.

23. Lay out a floorplan shape for the cell fs_comparator. We shall interactively lay out a floorplan shape for the new block.

Make sure fs_comparator is selected in the hierarchy window. Then activate the design window and and give the command: (Menu Bar) > Packages > ICplan > Add FP shape. In the prompt bar, use the Tab key to outline the Shape Extent item. In the design window, with the Select button depressed, drag out a rectangular shape until its size reaches at least 250%. Give the command: (Menu Bar) > Packages > ICPlan > Link Shape. This extracts the cells selected in the hierarchy window into the newly created floorplan shape; the shape will acquire the name fs_comparator.

24. Change the editing context to fs_comparator and set up the cell. Change the editing context to fs_comparator by giving the following commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. The fs_comparator cell should appear shaded.

Now give the command: (Menu bar) > Context > Hierarchy > Set context. Click within the fs_comparator floorplan shape. Note that in the title bar of the

design window the context has now changed from top_level_hier to fs_comparator, and that the floorplan shape is now outlined in green.

Re-attach the library with the following command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib

cell library. OK the dialogue box.

With the Floorplan palette selected, click on Autofp and study the dialogue which appears. OK the dialogue box.

ICblocks should now create a compact, triple or possibly quadruple row of cell sites. Consult a demonstrator if this is not the case.

Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. In the Floorplan palette, click on:



• P & R (to select the Place & Route palette); • StdCel (under Auto Place), and OK the prompt bar. • Ports (under Autoplace), and OK the dialogue box; • All (under Auto Route), and OK the prompt bar.


You should now observe a placed and routed block with all overflows resolved. Study it carefully and try to trace the key signal flows. Save the cell at this point:

(Menu bar) File > Cell > Save Cell.

25. Change editing context temporarily back to top_level_hier. Give the two following menu commands: (Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar.

Make sure the cell fs_comparator is selected (in the hierarchy window) and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the fs_comparator part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to generate a cell block (fs_control) representing the control logic component for later placement in top_level_hier.

26. Flatten the fs_control schematic. Return to the hierarchy window, and select the control schematic object. Note that

this is labelled B (implying that it is an unplaced block cell). We shall now create a floorplan shape for the control schematic, so generating a fs_control layout cell.

Click on the Flatten item in the Hierarchy palette (under the Floorplanning heading). In the prompt bar, choose the following options:


OK the prompt bar. Observe in the hierarchy window that the control circuitry has been flattened into its constituent sub-cells, all coded S. Once again, if any new sub-blocks (coded B) are revealed by this procedure, they should be dealt with as in paragraph 16.

27. Combine the standard cells into a new block and generate a floorplan shape. We shall now gather together all the standard cells from the flattened control logic

schematic and assemble them into a new block fs_control.

In the hierarchy window, select the sub-cells corresponding to the control logic.

Check in the status bar, by comparison with your written list, that all the required cells have been selected and there are no surplus cells.

Re-activate the design window and its associated Floorplan palette. Detach the current library by giving the command: (Menu bar) > File > Library > Detach. Re-activate the hierarchy window and click on Partition; in the resulting prompt bar, enter fs_control in the New Cell Name field. Select the Preserve placement setting, and OK the prompt bar. Observe the appearance of a new part, fs_control.



Make sure fs_control is selected in the hierarchy window. With the design window activated give the command: (Menu Bar) > Packages > ICplan > Add FP shape. In the prompt bar, use the Tab key to outline the Shape Extent item. As before, use the mouse to drag out a rectangular shape until the percentage readout is at least 250%. Give the command: (Menu Bar) > Packages > ICPlan > Link Shape. The shape will acquire the name fs_control. Peek into the fs_control cell, set the editing context and re-attach the library by giving the following three commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the prompt bar; (Menu bar) > Context > Hierarchy > Set Context, and click within the new shape.

(Menu bar) > File > Library > Attach... , and select the ringlib cell library. OK the dialogue box.

28. Place and route the fs_control cell. Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. With the

design window activated, switch to the Place & Route palette.

In the Place & Route palette, click on the following:

• Autofp and OK the dialogue box; • StdCel (under Auto Place) and OK the dialogue box; • Ports (under Auto Place) and OK the dialogue box; • All (under Auto Route), OK the prompt bar and wait.


Save the completed fs_control cell, using (Menu bar) > File > Cell > Save Cell. Restore the context to top_level_hier, and unpeek, by giving the commands:

(Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar; (Menu bar) > Context > Hierarchy > Unpeek.

Unplace the fs_control cell by ensuring it is selected, then giving the command: (Menu bar) > Objects > Unplace. Press F2 to unselect all objects.

You are now ready to generate a layout cell representing the array of ring oscillator NOR2 gates (ring_array), for later placement in

top_level_hier.

The procedure here is a little more involved because we shall aim to incorporate in this cell only those NOR2 gates used in the ring

oscillator in this cell.



29. Flatten the ring_oscillator schematic. Return to the hierarchy window, and select the ring_oscillator schematic object.

Note that this is labelled B (implying that it is an unplaced block cell). We shall now create a floorplan shape for the ring_oscillator schematic, so generating a ring_array layout cell.

Click on the Flatten item in the Hierarchy palette (under the Floorplanning heading). In the prompt bar, choose the following options:


OK the prompt bar. Observe in the hierarchy window that the ring oscillator has been flattened into its constituent nor2 sub-cells, all coded S.

30. Combine the standard cells into a new block and generate a floorplan shape. We shall now gather together all the standard cells from the flattened ring oscillator

schematic and assemble them into a new block ring_array.

In the hierarchy window, select all the nor2 cells from the ring oscillator.

Remember that your design contains at least one further nor2 gate, provided as a simple test structure at the top level. We shall place this in a different cell (ring_glue), not ring_array.

Since the ring devices are in a sub-cell, and the test device is not, you can easily distinguish them. The ring gates will have instance identifiers of the form: I$XXX/I$YYY, while the test gate will have a simpler identifier of the form: I$ZZZ.

Use this information to help select the ring oscillator gates only. When you have done this, check in the status bar, by comparison with your written list, that all the required cells have been selected and there are no surplus cells. The number of selected cells and the number you designed in your ring_oscillator schematic must match.

Re-activate the design window and its associated Floorplan palette. Detach the current library by giving the command: (Menu bar) > File > Library > Detach. Re-activate the hierarchy window and click on Partition; in the resulting prompt bar, enter ring_array in the New Cell Name field. Select the Preserve placement setting, and OK the prompt bar. Observe the appearance of a new part, ring_array.

Make sure ring_array is selected in the hierarchy window. With the design window activated give the command: (Menu Bar) > Packages > ICplan > Add FP shape. In the prompt bar, use the Tab key to outline the Shape Extent item. As before, use the mouse to drag out a rectangular shape until the percentage readout is at least 250%. Give the command: (Menu Bar) > Packages > ICPlan > Link Shape. The shape will acquire the name ring_array. Peek into the ring_array cell, set the editing context and re-attach the library by giving the following three commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the prompt bar; (Menu bar) > Context > Hierarchy > Set Context, and click within the new shape.

(Menu bar) > File > Library > Attach... , and select the ringlib cell library. OK the dialogue box.



31. Place and route the ring_array cell. Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. With the

design window activated, switch to the Place & Route palette.




Save the completed ring_array cell, using (Menu bar) > File > Cell > Save Cell. Restore the context to ring_hier, and unpeek, by giving the commands:

(Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar; (Menu bar) > Context > Hierarchy > Unpeek.

Unplace the ring_array cell by ensuring it is selected, then giving the command: (Menu bar) > Objects > Unplace. Press F2 to unselect all objects.

You are now ready to generate the final cell block (ring_glue), for later placement in ring_hier.

32. Combine the last remaining standard cell/s in the ring_glue block.

In the hierarchy window, select the last remaining cell bearing the code letter S. This should be nor2 only – if you see others you may have overlooked cells earlier!

No flatten operation is required in this instance. With the design window active, detach the library with the command: (Menu bar) > File > Library > Detach. Click on the Partition item in the Floorplan palette (under the Hierarchy heading). In the resulting prompt bar, enter ring_glue in the New Cell Name field. Select the Preserve placement setting and OK the prompt bar. Observe the appearance of a new part, ring_glue.

33. Lay out a floorplan shape for the cell ring_glue. We shall interactively lay out a floorplan shape for the new block.

Make sure ring_glue is selected in the hierarchy window. Then activate the design window and give the command: (Menu Bar) > Packages > ICplan > Add FP shape. In the prompt bar, use the Tab key to outline the Shape Extent item. In the design window, with the Select button depressed, drag out a rectangular shape until its size reaches at least 250%. Give the command: (Menu Bar) > Packages > ICPlan > Link Shape. This extracts the cells selected in the hierarchy window into the newly created floorplan shape; the shape will acquire the name ring_glue.

34. Change the editing context to ring_glue and set up the cell. Change the editing context to ring_glue by giving the following commands:

(Menu bar) > Context > Hierarchy > Peek , and OK the resulting prompt bar. (Menu bar) > Context > Hierarchy > Set context. Click the ring_glue floorplan. (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box.



Now use Autofloorplan, Autoplace, & Autoroute to complete the cell. With the design window activated, switch to the Place & Route palette.




Save the cell at this point: (Menu bar) File > Cell > Save Cell.

35. Change editing context back to top_level_hier. Give the two following menu commands: (Menu bar) > Context > Hierarchy > Set Context Up, and OK the prompt bar.

Make sure the cell ring_glue is selected and the design window is activated before giving the command:

(Menu bar) > Context > Hierarchy > Unpeek. Unplace the ring_glue part by giving the command: (Menu bar) > Objects > Unplace. Now press function key F2 to de-select all objects.

You are now ready to lay out the top level cell top_level_hier.



36. Place the three cell blocks in top_level_hier, and try to add the I/O ports. In the Place & Route palette, click the Blocks item. The Autoplace Blocks dialogue

box should appear. No changes should be required to the entries in this dialogue; OK the dialogue box. The various blocks already prepared: fs_divider, fs_comparator, fs_control, ring_array and ring_glue should appear in the design window. You may need to enter Shift+F8 in order to see these.

Give the command: (Menu bar) > File > Library > Attach... , and use the Navigator to select the ringlib cell library. OK the dialogue box.

Attempt to add the I/O pads. Select all the remaining items (marked E) in the Hierarchy Window. Then, with the design window active, click on the Ports item (under the heading Autoplace) in the Place & Route palette. Choose Selected for the Place item, and OK the dialogue box. Enter Shift+F8 to see the newly placed ports, which should include the I/O circuits and pads.

If you are fortunate, the port placement will proceed without problem. If so, move on to paragraph 37. However, because of the new constraints on the shape of the core logic blocks brought about by our use of a hierarchical structure, it is quite possible that the port placement will fail. One or two pads may be left unplaced - see the Hierarchy Window for pad cells with a remaining E code, signifying unplaced. If more than two I/O pads are unplaced, consult a demonstrator!

To circumvent this difficulty, should it arise, study the floorplan. You should be able to see that by stretching the green floorplan shapes at the edges of the layout it will be possible to make space for the remaining ports. Select each of the shapes in turn, and use the (Menu bar) > Edit > Stretch command to stretch the shape upwards, downwards, left or right, as appropriate, to make it large enough to accommodate further I/O pads.

Then, with the design window active, re-attempt port placement. Select the few remaining unplaced pad items in the Hierarchy Window, and click the Ports item. Ensure that the Place field is still set to Selected. All ports should now be placed.

37. Automatically route the layout. Finally, autoroute the entire layout. Under the Autoroute heading in the Place &

Route palette, click on All. A prompt bar should appear at the foot of the screen. For the moment do not change any of the options, but click OK. In approximately 30 seconds (dependent upon system loading) the circuit should be fully routed.

Inspect the layout, using the peek facility if needed, and again make an assessment of the efficiency of the placement and routing, in comparison with the flattened version. Make a note of its total X and Y dimensions. This information is available in the output generated by the following command:

(Menu bar) > Report > Active > Context.

At this stage it is wise to save the cell, using the command: (Menu bar) > File > Cell > Save Cell. Be sure to reserve it for edits before continuing.

38. Check for remaining overflows and attempt to route them manually It is possible that ICblocks will have been unable to complete the routing for every net in this final operation, and yellow overflows may be visible. If the number of overflows is small, it may be worth routing these individually. Select one of the overflows by left-clicking it. In the Place & Route Palette, choose the Ovrflw option under the Autoroute heading; when the prompt bar appears, choose Probe Extent



and use the mouse to sketch out a generous box surrounding of the overflow. OK the prompt. If this procedure is effective, try it on any remaining overflows. Otherwise, ask a demonstrator for advice.

39. Carry out via minimisation and compaction. Via minimisation and compaction can now be carried out as described in paragraphs 9

and 10 earlier. If you attempt these, monitor the reduction in the number of vias and the design dimensions as you pass through the various phases.

Note that compaction applied to top_level_hier is unlikely to produce such a dramatic improvement as was observed with top_level_flat. In order to achieve significant compaction with the hierarchical layout, it is necessary to apply the process to each of the logic blocks viz. fs_divider, fs_comparator, fs_control, ring_array and ring_glue, before beginning routing of ring_hier. If you wish to attempt this additional refinement, consult a demonstrator.

40. Generate a checkplot of the design. You will probably wish to generate a checkplot of the output. It should be possible to

direct one copy of this (per designer) to a colour printer. Please do not exceed this number, as the operators may suppress excessive colour prints.

To generate a colour (or black-and-white) plot, follow the instructions in paragaph 12.

Computer-based project in VLSI Design Performance of CMOS Ring Oscillator

D M Holburn May 2007 (iv) 163 C6e25.doc

Computer-Based Project on VLSI Design Co 3/6 Electrical Characterisation of CMOS Ring Oscillator

This pamphlet describes a laboratory activity based on an integrated circuit originally designed and tested as a student project. Its purpose is the measurement of the switching speed of some CMOS logic gates on a 2 µm n-well technology silicon integrated circuit. The MOSFETs employed have threshold voltages of ±1 volt approximately. You will have an opportunity to investigate the behaviour of these circuits as a function of supply voltage and in a range of configurations, and compare with simulated results.

1. Test chip layout

As you can see from the optical micrograph in Figure 1 and the corresponding diagram in Figure 2(a), the upper and lower ring oscillators contain 113 and 115 gates of the same type, respectively. The input and output pads to the circuits are as shown in Table 1; the inputs have multiple functions as noted below. INPUT and OUTPUT numbers are those numbers assigned on the test board with the jumper wires, and the pin numbers are the pin assignments on the chip. A circuit schematic of the test unit is shown in Figure 3.

Figure 1 Photomicrograph of part of ring oscillator IC

The power supply Vdd and ground Vss are supplied on the 2nd and 1st levels of metal on lines x=18 and x=21, pins 32 and 12 respectively.

The 6 logic gates in the area between the oscillators (grid reference x=85, y=53 and x=28-55, y=53) are similar to the elements in the ring.

There is an edge triggered divide-by-two circuit at (x=10, y=65) in Fig.2.



Input Description Grid Ref

INPUT 3 (pin 3) Controls element 1 of ring-113 Controls element 1 of ring-115 Controls one input to the single device

(x=100, y= 66) (x=108, y=400) (x= 85, y= 53)

INPUT 4 (pin 4) Controls three elements of ring-113 (x= 40, y= 66) (x=108, y= 66) (x=108, y= 97)

INPUT 2 (pin 39) Controls element 115 of ring-115 Controls one input to the single device

(x=115, y= 40) (x= 85, y= 53)

OUTPUT 5 (pin 5) From the single device (x= 85, y= 53)

OUTPUT 6 (pin 6) From the ring-113, after an extra buffer element

(x= 30, y= 91)

OUTPUT 7 (pin 7) From the ring-113, after an extra buffer element

(x= 30, y= 65)

OUTPUT 8 (pin 8) From the divide-by-two circuit which has output 9 as its input

(x= 10, y= 65)

OUTPUT 9 (pin 9) From the fifth logic gate in the line (no buffer element)

(x= 26, y= 53)

OUTPUT 10 (pin 10) From the ring-115 after element 16 after an extra buffer element

(x= 30, y= 40)

Table 1 Input and output pins

Figure 2 Ring Oscillator Circuit Schematic



2. Experimental Procedure: Testing the single device.

Important: Be sure to use Box A for sections 2-8.

Before measuring the ring oscillator we shall first test the single gate (x=85, y=53) on which both rings are based. Ensure that the measurement box in Fig. 3 contains a chip with design 21.

To change chips, move the lever over to release the pins, lift out the chip (without touching the pins - this could damage the circuit by electrostatic discharge). Push the pins into the pad of protective black conductive foam for storage, mount chip with dots aligned, and pull the lever to clamp the pins.

The supply voltage can be set to any value in the range 0.2 – 9 V approximately using the control knob at lower right on the test box. The meters provided allow accurate measurement of supply voltage and current. Note from Fig. 3 that current consumption is sensed by measuring the voltage drop across a 1Ω resistor – the meter must be set to measure voltage and the result converted mentally to a current. Setting the meter to a current range will give incorrect results.

• Please record the serial number of your chips: (e.g. 21-10) .

• Ensure that the positive power supply is connected to pin 32 on the chip and the ground is connected to pin 12. Set the power supply VDD to 3V.

• Set INPUT 3 (pin 3) HIGH.

The input and output pads are inverting; i.e. the three-way switch in the left position (labelled HI) to one of the chip inputs gives a LOW input at the internal circuit. Note: the switches are not debounced and can introduce multiple pulses into the ring.

• Set INPUT 4 (pin 4) LOW • Feed a square wave to INPUT 2 (pin 39) (switch set to the right - BNC input), amplitude

about 3V, frequency about 1MHz • Sketch what you observe when OUTPUT 5 and INPUT 2 (pin 39) are displayed together

on a dual trace oscilloscope. • Write down the logic function performed by the single gate. • Use the oscilloscope to estimate the gate delay. What factors limit the accuracy you can

expect to achieve?

3. Testing ring-115.

Ring oscillators ring-113 and ring-115 are made up of 2-input gates identical to that examined in section 2; ring-115 has two inputs which can be used to control the oscillation. First examine the behaviour of the ring when free-running with VDD at 3V.

• Set INPUT 2 (pin 39) to HI to allow the ring to free-run. Trigger the oscilloscope with OUTPUT 10 and observe the waveform.

Caution: The ring may go into a high order resonance owing to switch contact bounce. If so, first set INPUT 3 to LO to stop the ring and then set it to HI again. You may need to repeat this procedure more than once. Alternatively, with the switches set as required, reduce the supply voltage to zero and bring it up gradually to the desired value. This normally achieves a smooth start to the oscillations. You are strongly recommended to monitor all output waveforms using the oscilloscope, to guard against inadvertently selecting a harmonic mode.

Now investigate how the oscillation can be gated on and off by means of a pulse train.

• With the square wave connected to INPUT 2 (pin 39), adjust the input frequency at INPUT 2 (pin 39) to about 100kHz with a duty cycle of 50%.

• With the switch at INPUT 2 (pin 39) set to INPUT, observe OUTPUT 10 and INPUT 2 (pin 39) on the oscilloscope, using the input as a trigger. Sketch the waveforms.

Show how to use this approach to determine the ring frequency as a multiple of the pulse frequency, and record the ring frequency obtained in this way.



Figure 3 Test box circuit schematic



4. Determining the gate delay by measurements on ring-115 and ring-113. With the setup of section 3, carry out the following experiments:-

• Make a rough measurement of the period of the high-frequency oscillations from the oscilloscope.

• Using the most suitable method to determine the natural ring oscillator frequency (counter-timer or oscilloscope), find the gate delay per stage in the ring with VDD set to 3V, making sure that you are not in error by a factor of 2!

• Now using ring-113, investigate a further way to estimate the gate delay. Display

OUTPUTS 7 and 6 on the dual trace oscilloscope, set ring-113 oscillating and divide the observed delay by the number of intervening gates.

• Find the number of gates by counting the gates in Figure 2, bearing in mind that the buffer gates on each output are external to the ring.

• Does OUTPUT 7 come before OUTPUT 6, or vice versa? Compare and contrast the methods explored in sections 2 - 4 for obtaining the gate delay. 5. Measure the effect of varying the power supply voltage.

The switching characteristics are expected to depend on the supply voltage VDD. In this section you will make a detailed investigation of the nature of the variation over a wide range of voltages.

• First determine the minimum power supply voltage required to establish full-amplitude oscillations by setting the switches so that only one ring free-runs, the other ring being off. Determine also the lowest frequency at which oscillations can be detected. Is this consistent with what you know of the characteristics of the transistors?

• Measure the frequency of the free-running ring using the frequency counter as the power supply voltage is varied. Plot the result and note the rate of change in frequency with power supply voltage VDD at 3 V.

• Interpret your plot of frequency vs. ring voltage. Is it an accurate straight line? Suggest reasons for any deviations.

6. Performance comparison with different transistors in the ring

As explained, test chip designs 28 and 21 have similar transistors in the elements of the ring oscillators except that the p-channel transistors in design 28 are three times wider than those in design 21. This affects both the on-state channel conductance and the capacitive load presented to the previous stage of the ring.

To change chips, move the lever over to release the pins, lift out the chip (without touching the pins as this could damage the circuit by electrostatic discharge). Push the pins into the pad of protective black conductive foam for storage, mount the new chip with the dots aligned, and pull the lever to clamp the pins.

What is the percentage difference in performance between the designs at supply voltage VDD = 3 V and VDD = 5 V? Explain on the basis of the transistor dimensions why you would expect a difference, and estimate the magnitude of the expected change. Make reasonable assumptions (with explanations) about parameters not explicitly stated.



7. Simulation of the device performance.

The output of an AccuSim simulation of a portion of the ring oscillator is given in Figure 4, which also contains a sketch of how the five gates are interconnected in the simulation.

The voltage waveform V(A) consisting of a linear ramp up from 0 to 5 V, a flat region and a linear ramp back down to zero, is supplied to the input to gate A. The outputs of gates B, C, D and E are determined using AccuSim. Note that the simulation provided corresponds to chip design 28 rather than the design just measured, and assumed VDD = 5 V. Test chip designs 28 and 21 have similar transistors in the elements of the ring oscillators except that the p-channel transistor in design 28 is three times wider than that in design 21. This affects both the on-state channel conductance and the capacitive load presented to the previous stage of the ring.

Highlight in a bright colour the waveforms C and E on the diagram. Explain how waveforms B-E arise, and why the shape of waveforms C and E are similar to each other. Why are they different in detail from waveform A?

Using the curves in Figure 4, estimate the delay in the ring oscillator and compare it with your experimental measurement for 5V power supply voltage.

It may also be helpful to know that the AccuSim run carried out takes into account the MOSFET channel resistances and all parasitic capacitances to substrate, but does not model other resistances in the circuit, such as the 2 µm wide polysilicon lines interconnecting the devices. 8. Stroboscopic pulse generator

This experiment requires a little extra determination, but carefully carried out, gives deep insight into the subtleties of the performance of the circuit, and of the accuracy of the simulation results that guided its design. Small changes in supply voltage can have a dramatic effect on your observations, owing to the strong dependence of gate delay on VDD. Also, chip designs 21 and 28 have slightly different characteristics and it may sometimes be easier to observe the effects on chip design 28.

In the schematic of Figure 4, the sense gate F with inputs from E and B gives a high output only when both inputs are low. This function is also realised on the chip by the gates at (x=40, y=53) and at (x =55, y=53). The result appears at OUTPUT 9 (pin 9). There is also an edge-triggered divide-by-2 circuit on the chip at (x=15, y=60). Its input is internally connected to OUTPUT 9 and can be monitored at OUTPUT 8 (pin 8).

Given that the sense gates on the chip each span 5 elements of the rings (note that in Figure 4 only 3 are spanned),

• Describe the circumstances in which the output from the sense gate will be in the logic HIGH state during normal operation of the ring.

• What output do you expect from OUTPUT 9 of chip design 28 in Figure 2 when:-

a) ring-113 and ring-115 are running freely with the same VDD – consider what their relative frequencies are expected to be;

b) when INPUT 4 is LOW (i.e. HIGH after inversion at the input pad), and ring-115 alone is running?

• Verify your predictions by experiment. Change to chip design 28 only if necessary. • First, observe OUTPUTS 10 and 9 on the oscilloscope with both rings free-running. To

achieve this, switches at INPUTS 2-4 must be set to HI. Use a low supply voltage of approximately 0.6 - 0.7 V, and guard against either ring entering a harmonic mode. Once you have observed the sense waveform, consider applying it to the oscilloscope’s External Trigger input so you can monitor both ring outputs in the vicinity of the sense signal.



• Confirm that the circuit performs the expected function over a small range of supply voltages and increase/decrease the power supply voltage until it just no longer works. Record your observations.

• Next, observe OUTPUTS 10 and 9 on the oscilloscope with a fairly low power supply voltage, and ring-115 only in operation. To achieve this requires the switches at INPUTS 4, 3 and 2 (pin 39), set LO, HI and HI respectively. Investigate the divide-by-2 output, at OUTPUT 8 (pin 8), and show that it works as expected over a range of supply voltages, and record the range. Outside this range the rise/fall of the input edge may be too slow or too fast to clock the divide-by-2 stage.

• If the range of operating voltages for the divide-by-two and the strobe pulse generator overlap, you should be able to set the switch at INPUT 4 HI again, and observe the strobe pulses divided by two, at a suitably chosen VDD. However, it is possible you will come to the conclusion that the operable ranges do not coincide. Full operation is only possible on a few sample chips where fabrication tolerances dictate. This idiosyncratic behaviour can not be directly predicted by the simulation tools with the models available.

Figure 4 Simulation at VDD=5V of a portion of ring 28



9. Ring oscillators with realistic loads on the devices in the ring (Optional)

The second measurement box provided (Box B) has been developed for the purpose of investigating the behaviour of ring oscillators operating under more realistic and variable loading conditions. It relies on a CMOS device specifically designed and fabricated for the purpose.

Note: the process dimensions used are not the same as those for chips 21 & 28.

The measurement box has additional switches to select one of a number of ring oscillators, and a precision potentiometer for adjusting the supply voltage. In other respects it resembles the unit used to test chips 21 & 28.

The device contains 8 ring oscillators, four implemented with NAND gates and four with Inverter/NOR gates. In contrast to the first ring oscillator chip you measured, the load at the output of each gate in the ring is varied in this experiment. A total load of 2 (as with NAND 2), for example, means that each ring gate drives the next ring gate input plus a similar, dummy input. A load of 3 indicates that the extra dummy input imposes twice the load presented by a standard ring input, and so on.

Table 1 shows the number of elements in each ring. Layout considerations mean this varies across the set of oscillators. The information is needed to calculate gate delay from measured frequencies. To economise on the number of input and output pins to the chip, a multiplexed control system is used to determine which ring is active. Use the switch settings given in Table 1 to select the chosen ring type.

Choose a fixed supply voltage (such as 5 V) and measure the oscillation frequencies of the rings. Plot the delay associated with each logic gate as a function of the load the gate has to drive as you measure it, and interpret the results. What are the implications for design of complex logic circuits (as opposed to simple oscillators)?

Measure the performance of Inverter 1 as a function of supply voltage, comparing your data with those obtained in Section 5.

Gate type and Load

No in ring

Switch settings (Chip pin numbers in brackets)

Output on Box

1 2 3 4 5 6 (26) (27) (24) (25) (22) (23)

Inverter 1 181 HI LO LO HI HI HI Output 1 (pin 37)

Inverter 2 81 LO HI HI LO LO LO Output 1 (pin 37)

Inverter 3 81 HI LO HI LO HI HI Output 2 (pin 36)

Inverter 4 79 LO HI LO HI LO LO Output 2 (pin 36)

NAND 1 135 HI LO HI HI LO HI Output 3 (pin 39)

NAND 2 65 LO HI LO LO HI LO Output 3 (pin 39)

NAND 3 65 HI LO HI HI HI LO Output 4 (pin 38)

NAND 4 65 LO HI LO LO LO HI Output 4 (pin 38)

Table 1: Switch assignments and pin allocation

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