Part A Final Part A Final presentation presentation Dynamic System Dynamic System on Programmable on Programmable Chip Chip

Part A Final Part A Final presentation presentation Dynamic System Dynamic System on Programmable on Programmable Chip Chip

By: Nir Shahar and Amir KleinhendlerSupervisor: Ina Rivkin

Spring/Winter 2006

Global Project goalsGlobal Project goalsGlobal Project goalsGlobal Project goals• Designing A New Experiment for Designing A New Experiment for

undergraduate students at the High undergraduate students at the High Speed Digital Systems Laboratory Speed Digital Systems Laboratory Based on a Dynamic System (using Based on a Dynamic System (using SOPC platform). SOPC platform).

• Dynamic Peripheral Designing and Dynamic Peripheral Designing and Implementation.Implementation.

• Designing A New Experiment for Designing A New Experiment for undergraduate students at the High undergraduate students at the High Speed Digital Systems Laboratory Speed Digital Systems Laboratory Based on a Dynamic System (using Based on a Dynamic System (using SOPC platform). SOPC platform).

• Dynamic Peripheral Designing and Dynamic Peripheral Designing and Implementation.Implementation.

• Dynamic Peripheral Designing and Dynamic Peripheral Designing and Implementation.Implementation.

• Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral.• Learning The FPGA Methodology.Learning The FPGA Methodology.

– FPGA Logical Structure. FPGA Logical Structure. – XUP Board, Virtex II pro , PPC. XUP Board, Virtex II pro , PPC. – FPGA Design Flow. FPGA Design Flow. – FPGA Design Tools ( EDK , ISE , Chip-Scope).FPGA Design Tools ( EDK , ISE , Chip-Scope).– Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral.

• Learning VHDL Design Methodology.Learning VHDL Design Methodology. – VHDL for Synthesis. VHDL for Synthesis. – MODEL-SIM for Simulation. MODEL-SIM for Simulation. – HDL Design Tool.HDL Design Tool.

• Dynamic Peripheral Designing and Dynamic Peripheral Designing and Implementation.Implementation.

• Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral.• Learning The FPGA Methodology.Learning The FPGA Methodology.

– FPGA Logical Structure. FPGA Logical Structure. – XUP Board, Virtex II pro , PPC. XUP Board, Virtex II pro , PPC. – FPGA Design Flow. FPGA Design Flow. – FPGA Design Tools ( EDK , ISE , Chip-Scope).FPGA Design Tools ( EDK , ISE , Chip-Scope).– Implementing a Simple Dynamic Peripheral.Implementing a Simple Dynamic Peripheral.

• Learning VHDL Design Methodology.Learning VHDL Design Methodology. – VHDL for Synthesis. VHDL for Synthesis. – MODEL-SIM for Simulation. MODEL-SIM for Simulation. – HDL Design Tool.HDL Design Tool.

PART A Goals PART A Goals PART A Goals PART A Goals

PPC 2PPC 1

PERIPHERY 3

BRIDGE

OPB

PLB

PERIPHERY 4 PERIPHERY 5 PERIPHERY 6

PERIPHERY 1 PERIPHERY 2

PERIPHERY 5A

PPC 2PPC 1

PERIPHERY 3

BRIDGE

OPB

PLB

PERIPHERY 4 PERIPHERY 5 PERIPHERY 6

PERIPHERY 1 PERIPHERY 2

PERIPHERY 5A

The Dynamic System ConceptThe Dynamic System ConceptThe Dynamic System ConceptThe Dynamic System Concept

When we simulate a problem we can dynamically remove or replace a peripheral in-order to fix the simulated problem.

Option 1Option 2Option 3

Status UpdateStatus UpdateStatus UpdateStatus Update• We have crossed the final step for the We have crossed the final step for the

project’s first part. project’s first part.

• We Have implemented a dynamic We Have implemented a dynamic periphery. periphery.

• The knowledge we have acquired will be The knowledge we have acquired will be used for the second part of our project. used for the second part of our project.

• The periphery we have implemented The periphery we have implemented here will demonstrate several problems here will demonstrate several problems students will encounter during the students will encounter during the experiment. experiment.

• We have crossed the final step for the We have crossed the final step for the project’s first part. project’s first part.

• We Have implemented a dynamic We Have implemented a dynamic periphery. periphery.

• The knowledge we have acquired will be The knowledge we have acquired will be used for the second part of our project. used for the second part of our project.

• The periphery we have implemented The periphery we have implemented here will demonstrate several problems here will demonstrate several problems students will encounter during the students will encounter during the experiment. experiment.

System Creation Flow 3 bit FASystem Creation Flow 3 bit FASystem Creation Flow 3 bit FASystem Creation Flow 3 bit FA• We planned the block diagram of the complete We planned the block diagram of the complete

system. system. • We implemented the VHDL code. We implemented the VHDL code. • Ran Model Sim simulations for the design (for logic Ran Model Sim simulations for the design (for logic

validation). validation). • We created a new user periphery with the new logic We created a new user periphery with the new logic

block (in EDK and ISE). block (in EDK and ISE). • Wrote the C code for the periphery usage.Wrote the C code for the periphery usage.• We inserted a ChipScope probe into the design (this We inserted a ChipScope probe into the design (this

part was the most problematic part of the project). part was the most problematic part of the project). • We validated the functionality of the dynamic FA of We validated the functionality of the dynamic FA of

the FPGA with the ChipScope.the FPGA with the ChipScope.

• We planned the block diagram of the complete We planned the block diagram of the complete system. system.

• We implemented the VHDL code. We implemented the VHDL code. • Ran Model Sim simulations for the design (for logic Ran Model Sim simulations for the design (for logic

validation). validation). • We created a new user periphery with the new logic We created a new user periphery with the new logic

block (in EDK and ISE). block (in EDK and ISE). • Wrote the C code for the periphery usage.Wrote the C code for the periphery usage.• We inserted a ChipScope probe into the design (this We inserted a ChipScope probe into the design (this

part was the most problematic part of the project). part was the most problematic part of the project). • We validated the functionality of the dynamic FA of We validated the functionality of the dynamic FA of

the FPGA with the ChipScope.the FPGA with the ChipScope.

FA LOGIC CHANGE

REVERSED FF

GOOD_FA

Carry problem

MU

X

Bus à select

Bus

à

in_1

, in_

2,P

ush_

But

ton_

1,P

ush_

But

ton_

2,re

st

Clk

Clk

Clk

Bus à Result

Clk

Periphery Top OverviewPeriphery Top Overview The block diagram of the complete system. The block diagram of the complete system.

Periphery Top OverviewPeriphery Top Overview The block diagram of the complete system. The block diagram of the complete system.

We implemented the VHDL code. We implemented the VHDL code. We implemented the VHDL code. We implemented the VHDL code.

Created a new user periphery with Created a new user periphery with the new logic block (in EDK and ISE).the new logic block (in EDK and ISE).

Created a new user periphery with Created a new user periphery with the new logic block (in EDK and ISE).the new logic block (in EDK and ISE).

• In this stage we use several VHDL files In this stage we use several VHDL files to implement a design. In the Xilinx to implement a design. In the Xilinx environment implementing user logic environment implementing user logic with several HDL files was challenging. with several HDL files was challenging.

• We’ve done it by using the PAO file and We’ve done it by using the PAO file and importing libs. importing libs.

• In this stage we use several VHDL files In this stage we use several VHDL files to implement a design. In the Xilinx to implement a design. In the Xilinx environment implementing user logic environment implementing user logic with several HDL files was challenging. with several HDL files was challenging.

• We’ve done it by using the PAO file and We’ve done it by using the PAO file and importing libs. importing libs.

C code for the periphery usage.C code for the periphery usage.C code for the periphery usage.C code for the periphery usage.

• We wrote the C code using the Xilinx special commands. We wrote the C code using the Xilinx special commands.

For example: For example:

• XGpio_InitializeXGpio_Initialize((&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID)); ; // // set the GpioDipSwitch valueset the GpioDipSwitch value

• XGpio_SetDataDirectionXGpio_SetDataDirection((&GpioDipSwitch, 1, 0x1&GpioDipSwitch, 1, 0x1));;// // set the GpioDipSwitch as an inputset the GpioDipSwitch as an input

• FA_mWriteSlaveReg0FA_mWriteSlaveReg0((XPAR_FA_0_BASEADDR, TempXPAR_FA_0_BASEADDR, Temp)); ; //writing data to the unit//writing data to the unit

• Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unit//reading data from the unit

• XGpio_DiscreteWriteXGpio_DiscreteWrite((&GpioOutput, 1, dip_stat&GpioOutput, 1, dip_stat)); ; //writing to the leds//writing to the leds

• We wrote the C code using the Xilinx special commands. We wrote the C code using the Xilinx special commands.

For example: For example:

• XGpio_InitializeXGpio_Initialize((&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID&GpioDipSwitch,XPAR_DIPSWS_4BIT_DEVICE_ID)); ; // // set the GpioDipSwitch valueset the GpioDipSwitch value

• XGpio_SetDataDirectionXGpio_SetDataDirection((&GpioDipSwitch, 1, 0x1&GpioDipSwitch, 1, 0x1));;// // set the GpioDipSwitch as an inputset the GpioDipSwitch as an input

• FA_mWriteSlaveReg0FA_mWriteSlaveReg0((XPAR_FA_0_BASEADDR, TempXPAR_FA_0_BASEADDR, Temp)); ; //writing data to the unit//writing data to the unit

• Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); Fa_stat=FA_mReadSlaveReg0(XPAR_FA_0_BASEADDR); //reading data from the unit//reading data from the unit

• XGpio_DiscreteWriteXGpio_DiscreteWrite((&GpioOutput, 1, dip_stat&GpioOutput, 1, dip_stat)); ; //writing to the leds//writing to the leds

Inserted a ChipScope probe Inserted a ChipScope probe into the design .into the design .

Inserted a ChipScope probe Inserted a ChipScope probe into the design .into the design .

Problems : •RTL optimization problem.

When we synthesized our design with EDK, the ISE tool automatically ran its optimizations , and “optimized away” some of our signals , for efficiency.

This phenomena was very problematic on our behalf because we wanted students to be able to see all the design signals .

•Signals naming problem.

After the synthesis stage, some of our original signals received different names , as a part of the synthesis process. It was very difficult to distinguish which were the relevant signals.

Problems : •RTL optimization problem.

When we synthesized our design with EDK, the ISE tool automatically ran its optimizations , and “optimized away” some of our signals , for efficiency.

This phenomena was very problematic on our behalf because we wanted students to be able to see all the design signals .

•Signals naming problem.

After the synthesis stage, some of our original signals received different names , as a part of the synthesis process. It was very difficult to distinguish which were the relevant signals.

Inserted a ChipScope probe into the designInserted a ChipScope probe into the designInserted a ChipScope probe into the designInserted a ChipScope probe into the design

• Signals naming problem. ( example ) • Signals naming problem. ( example )

Solution for the post synthesis Solution for the post synthesis naming/optimizing problem naming/optimizing problem

Solution for the post synthesis Solution for the post synthesis naming/optimizing problem naming/optimizing problem

• There were several stages for the solution : There were several stages for the solution : – First we synthesized our periphery in an independent way First we synthesized our periphery in an independent way

using ISE. using ISE. – We learned which libraries are needed in order for us to be We learned which libraries are needed in order for us to be

able to “dive into” modules in our design. able to “dive into” modules in our design. – We found a method of synthesis which preserves the signal We found a method of synthesis which preserves the signal

names. names. – We then transferred this knowledge to the EDK environment We then transferred this knowledge to the EDK environment

, and found a method of synthesizing our design with , and found a method of synthesizing our design with command line instructions for the ISE. command line instructions for the ISE.

– Finally the synthesized peripheries kept their original Finally the synthesized peripheries kept their original names and we are now able to monitor all signals of our names and we are now able to monitor all signals of our design. design.

– The signals were also not optimized away The signals were also not optimized away

• There were several stages for the solution : There were several stages for the solution : – First we synthesized our periphery in an independent way First we synthesized our periphery in an independent way

using ISE. using ISE. – We learned which libraries are needed in order for us to be We learned which libraries are needed in order for us to be

able to “dive into” modules in our design. able to “dive into” modules in our design. – We found a method of synthesis which preserves the signal We found a method of synthesis which preserves the signal

names. names. – We then transferred this knowledge to the EDK environment We then transferred this knowledge to the EDK environment

, and found a method of synthesizing our design with , and found a method of synthesizing our design with command line instructions for the ISE. command line instructions for the ISE.

– Finally the synthesized peripheries kept their original Finally the synthesized peripheries kept their original names and we are now able to monitor all signals of our names and we are now able to monitor all signals of our design. design.

– The signals were also not optimized away The signals were also not optimized away

Dynamic validation using the chip scope Dynamic validation using the chip scope Dynamic validation using the chip scope Dynamic validation using the chip scope

• We picked a collection of signals which are crucial We picked a collection of signals which are crucial for the observations the students are to make at the for the observations the students are to make at the experiment. experiment.

• We picked a collection of signals which are crucial We picked a collection of signals which are crucial for the observations the students are to make at the for the observations the students are to make at the experiment. experiment.

• Designing The New Dynamic System Designing The New Dynamic System Experiment.Experiment.

• Building The Experiment Files ( EDK ).Building The Experiment Files ( EDK ).• Simulating The Complete Experiment.Simulating The Complete Experiment.• Building an Experiment Folio.Building an Experiment Folio.

– Pre-experiment learning kit ( includes Pre-experiment learning kit ( includes preparation questions ). preparation questions ).

– Preparing an experiment booklet. Preparing an experiment booklet.

– Preparing a station startup script.Preparing a station startup script.

• Designing The New Dynamic System Designing The New Dynamic System Experiment.Experiment.

• Building The Experiment Files ( EDK ).Building The Experiment Files ( EDK ).• Simulating The Complete Experiment.Simulating The Complete Experiment.• Building an Experiment Folio.Building an Experiment Folio.

– Pre-experiment learning kit ( includes Pre-experiment learning kit ( includes preparation questions ). preparation questions ).

– Preparing an experiment booklet. Preparing an experiment booklet.

– Preparing a station startup script.Preparing a station startup script.

PART B: Goals PART B: Goals PART B: Goals PART B: Goals

• Our plan for the second part of the Our plan for the second part of the project is to implement several different project is to implement several different peripheries like the one we peripheries like the one we implemented here . Each periphery will implemented here . Each periphery will have several different problems.have several different problems.

• The students will have to detect the The students will have to detect the problems with the chip scope and fix problems with the chip scope and fix them by selecting a different them by selecting a different configuration for the periphery. configuration for the periphery.

• Our plan for the second part of the Our plan for the second part of the project is to implement several different project is to implement several different peripheries like the one we peripheries like the one we implemented here . Each periphery will implemented here . Each periphery will have several different problems.have several different problems.

• The students will have to detect the The students will have to detect the problems with the chip scope and fix problems with the chip scope and fix them by selecting a different them by selecting a different configuration for the periphery. configuration for the periphery.

PART B: The ExperimentPART B: The ExperimentPART B: The ExperimentPART B: The Experiment

Several Ideas for PeripheriesSeveral Ideas for PeripheriesSeveral Ideas for PeripheriesSeveral Ideas for Peripheries

• A Led lighting design. A Led lighting design. • Full adder.Full adder.• 4 bit counter. 4 bit counter. • Stop light designStop light design• Etc…(more are optional)Etc…(more are optional)

• In each periphery we will plant several In each periphery we will plant several hardware and software problems. Which will hardware and software problems. Which will be implemented similar to the way we have be implemented similar to the way we have implemented them with our FA. implemented them with our FA.

• A Led lighting design. A Led lighting design. • Full adder.Full adder.• 4 bit counter. 4 bit counter. • Stop light designStop light design• Etc…(more are optional)Etc…(more are optional)

• In each periphery we will plant several In each periphery we will plant several hardware and software problems. Which will hardware and software problems. Which will be implemented similar to the way we have be implemented similar to the way we have implemented them with our FA. implemented them with our FA.

QUESTIONSQUESTIONSQUESTIONSQUESTIONS

GOOD VERSIONGOOD VERSIONGOOD VERSIONGOOD VERSION

Q

QSET

CLR

D

Q

QSET

CLR

D

BUS_CLK

MU

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MU

X

IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

SU

LT

[0]

RE

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[1]

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[2]

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[3]

Q

QSET

CLR

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CLR

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BUS_CLK

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X

IN1

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PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

SU

LT

[0]

RE

SU

LT

[1]

RE

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LT

[2]

RE

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[3]

BACKBACK

LOGIC CHANGELOGIC CHANGELOGIC CHANGELOGIC CHANGE

Q

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PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

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[0]

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[1]

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[2]

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[3]

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IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

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LT

[0]

RE

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[1]

RE

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[2]

RE

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[3]

BACKBACK

CARRY PROBLEMCARRY PROBLEMCARRY PROBLEMCARRY PROBLEM

Q

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CLR

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Q

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BUS_CLK

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MU

X

IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

SU

LT

[0]

RE

SU

LT

[1]

RE

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LT

[2]

RE

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LT

[3]

Q

QSET

CLR

D

Q

QSET

CLR

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BUS_CLK

MU

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X

IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

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LT

[0]

RE

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[1]

RE

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[2]

RE

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[3]

BACKBACK

3 BIT ADDER3 BIT ADDER3 BIT ADDER3 BIT ADDER

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]BACKBACK

LOGIC PROBLEMLOGIC PROBLEMLOGIC PROBLEMLOGIC PROBLEM

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]BACKBACK

REVESED FF PROBLEMREVESED FF PROBLEMREVESED FF PROBLEMREVESED FF PROBLEM

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]BACKBACK

FULL ADDER GOODFULL ADDER GOODFULL ADDER GOODFULL ADDER GOODAB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

AB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

BACKBACK

FULL ADDER CARRYFULL ADDER CARRYFULL ADDER CARRYFULL ADDER CARRYAB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

AB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

BACKBACK

REVERSED FFREVERSED FFREVERSED FFREVERSED FFAB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

AB

CINS

S = A xor B xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

BACKBACK

FA LOGIC PROBLEMFA LOGIC PROBLEMFA LOGIC PROBLEMFA LOGIC PROBLEMAB

CINS

S = (A and B) xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

AB

CINS

S = (A and B) xor CinCout = ( Cin and (A xor B) ) or ( A and B )

Cout

AB

CIN

BACKBACK

REVERSED FF PROBLEMREVERSED FF PROBLEMREVERSED FF PROBLEMREVERSED FF PROBLEM

Q

QSET

CLR

D

Q

QSET

CLR

D

BUS_CLK

MU

X

MU

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IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

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LT

[0]

RE

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[1]

RE

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[2]

RE

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[3]

Q

QSET

CLR

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QSET

CLR

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BUS_CLK

MU

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MU

X

IN1

IN2

PUSH_BUTTON_1

PUSH_BUTTON_2

0:2 0:2

3 BIT FULL ADDERA B

CIN

RE

SU

LT

[0]

RE

SU

LT

[1]

RE

SU

LT

[2]

RE

SU

LT

[3]

BACKBACK

CARRY PROBLEMCARRY PROBLEMCARRY PROBLEMCARRY PROBLEM

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]

Cin

ADDER

ADDER

ADDER

A[0]

A[1]

A[2]

B[0]

B[1]

B[2]

CIN

Co

ut

S[0]

S[1]

S[2]

Co

ut

S[3]

Cin

BACKBACK