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IEEE Real-Time Systems Symposium

Conference Program

Slim Ben-AmorCristian MaximYasmina Abdeddaim Walid TalaboulmaChristine Anocq

OrganizersGeneral Chair:Frank Mueller, North Carolina State University, USA

Ex-Officio (TC Chair):James Anderson, University of North Carolina at Chapel Hill, USA

Program Chair:Isabelle Puaut, University of Rennes/IRISA, France

Local Arrangements Chair:Liliana Cucu-Grosjean, Inria, Paris

Finance Chair:Karl-Erik Arzen, Lund University, Sweden

Track Chairs:Cyber-Physical Systems Track: Rodolfo Pellizzoni, University of Waterloo, CanadaHW-SW integration and system level design Track: Petru Eles, Linköping University, SwedenInternet of Things Track: Tarek F. Abdelzaher, University of Illinois at Urbana Champaign, USA

Publicity Co-chairs:Björn Brandenburg, Max Planck Institute, GermanyNan Guan, Hong Kong Polytechnic University, Hong KongCong Liu, University of Texas at Dallas, USA

Workshops Chair:Song Han, University of Connecticut, USA

Industrial Liaison Co-chairs:Jan Mathieu (Europe/Africa)Shinpei Kato (Asia/Pacific)Bjorn A. Andersson (Americas)

Chair of RTSS@work:Damir Isovic, Mälardalen University, Sweden

Brief Presentations Chair:Luca Santinelli, Onera, Toulouse, France

Artifact Evaluation:Stanley Bak, Air Force Research Lab, USA

Publications Chair:Sibin Mohan, University of Illinois at Urbana-Champaign, USA

Web Chair:Harini Ramaprasad, University of North Carolina at Charlotte, USA

Local organizing team:Liliana Cucu-GrosjeanChantal GirodonXiaoting LiAdriana GogonelRob Davis

Useful informations

Workshops venue

The workshops venue, the ECE school, is located at 10 rue Michel Sextius, 75015 Paris. ECE can be reached by Metro line 6, station Bir Hakeim or RER C, station Champ de Mars- tour Eiffel. The simplest way to reach ECE from CNA is to take the metro M9 from Saint Augustin to Trocadero (6 stops, direction Pont de Sevres) and from metro station Trocadero take M6 to Bir-Hakeim (M6, 2 stops, direction Nation).

Lunch

The lunch for the workshop attendees will be served within the ECE school.

Transportation inside Paris

The Parisian subway and bus network is very reliable and it is operated by RATP. The same tickets work on subway, bus, tramway RER (train network inside of Paris). Tickets cost 1,90€ if bought at the station and 2€ if bought on the bus, and you can use it even for trips including transfers. A 10 tickets pack costs 14,90 €. If you stay for the week you may consider buying a 3-days package costs 26.65€ or a 5-days package (38.35€) and is valid on the Paris network.

Useful smartphone applications

Vianavigo, Citymapper, RATP (for the Parisien public transportation network). Google maps works very well in France. Uber is also well developed in Paris.

December, 5th (Tuesday)

CERTS 2nd Workshop on Security and Dependability of Critical Embedded Real-Time Systems (ECE building – SC 315 )Chairs: Marisol García Valls and Sibin Mohan

08:30 Registration Opens09:00-9:15 Introduction and Welcome Remarks09:15-10:30 Keynote Talk: Matthias Schunter, Intel Labs 10:30 - 11:00 Coffee break

11:00-12:30 Session 1

Facing the Safety-Security Gap in RTES: the Challenge of Timeliness > Marcus Völp, David Kozhaya and Paulo Esteves-Verissimo

IDHCC: A Security-Enhanced ID Hopping CAN Controller Design to Guarantee Real-Time > Wufei Wu, Roy Kurachi, Gang Zeng, Yutaka Matsubara, Hiraoki Takada and Renfa Li

A Byzantine Fault-Tolerant Key-Value Store for Safety-Critical Distributed Real-Time Systems Validation and Performance Analysis of Cyber-Physical Systems in UPPAAL > Maite Appel, Arpan Gurjati and Björn B. Brandenburg 12:30- 14:00 Lunch (cafeteria) 14:00 -15:00 Session 2

Lower-Bounding the MTTF for Systems with (m,k) Constraints and IID Iteration Failure Probabilities > Arpan Gurjati, Mitra Nasri and Björn B. Brandenburg

SeedStrainer : An Approach to Improve the Hit Ratio of Malicious Candidate URLs > Yasuyuki Tanaka and Atsuhiro Goto

15:00-15:15 Discussion on the future of security in real-time systems. 15:15-15:30 Closing Remarks. 15:30 - 16:00 Coffee break 17:00-17:45 RTSS@work Presentation session (cafeteria)17:45-20:00 Diversity cocktail and Posters from RTSS@work (cafeteria)

December, 5th (Tuesday)

CRTS 10th International Workshop on Compositional Theory and Technology for Real-Time Embedded Systems (ECE building – SC 324 )Chairs: Laurent George and Jin Hyun Kim

08:30 Registration Opens09:15-10:30 Keynote Talk: Probabilities - a key solution for tomorrow real-time compositional frameworks Liliana Cucu-Grosjean at Inria Paris 10:30 - 11:00 Coffee break 11:00-12:30 Session 1

Invited Paper: Kim G Larsen, Aalborg University

Short Paper: Continuous Time Markov Chain Modeling for Probabilistic Schedulability Analysis: Jasdeep Singh, Guillaume Infantes, Luca Santinelli, David Doose and Julien Brunel

Invited Paper: Giuseppe Lipari, University of Lille 12:30- 14:00 Lunch (cafeteria) 14:00-15:30 Session 2

Workflow Composition and Analysis for Industry 4.0 Warehouse Automation > Ajay Kattepur

HVMD_CC : Heterogeneous Value with Multiple Deadlines and Communication Contention > Mayo Nakagawa, Takuya Azumi, Yuto Kitagawa and Nobuhiko Nishio

Beyond the Accuracy-Complexity Tradeoffs of Compositional Analyses using Network Calculus for Complex Networks > Ahlem Mifdaoui and Thierry Leydier 15:30-16:00 Coffee break 16:00 - 17:00 Session 3

Assessing the Flexibility of Real-Time Systems > Alain Girault, Rafik Henia, Christophe Prevot, Sophie Quinton and Laurent Rioux

A Mixed NoC/AFDX Architecture: Problems and Challenges > Laure Abdallah, Jérôme Ermont, Jean-Luc Scharbarg and Christian Fraboul

Dynamic Arbitration of Memory Requests with TDM-like Guarantees > Farouk Hebbache, Mathieu Jan, Florian Brandner and Laurent Pautet 17:00-17:45 RTSS@work Presentation session (cafeteria)17:45-20:00 Diversity cocktail and Posters from RTSS@work (cafeteria)

December, 5th (Tuesday)

TuToR 2nd Tutorial on Tools for Real-Time Systems(ECE building – EM 325)Chairs: Enrico Bini, Martina Maggio and Sophie Quinton

08:30 Registration Opens 9:00-09:45 pyCPA: a Python implementation of Compositional Performance Analysis > Rolf Ernst, Johannes Schlatow and Leonie Ahrendts 09:45-10:30 SCHED_DEADLINE: a real-time CPU scheduler for Linux > Luca Abeni and Juri Lelli

10:30-11:00 Coffee break 11:00-12:30 pyCPA and SCHED_DEADLINE Hands-on session 1 (rooms EM 325 & SC 322 ) 12:3-14:00 Lunch (cafeteria) 14:00-14:45 Validation and Performance Analysis of Cyber-Physical Systems in UPPAAL > Kim G. Larsen 14:45-15:30 CapeCode: an IoT modeling environment based on Ptolemy II > Edward A. Lee and Christopher Brooks 15:30-16:00 Coffee break 16:00-17:30 UPPAAL and CapeCode Hands-on session 2 (rooms EM 325 & SC 322 )

17:00-17:45 RTSS@work presentation session (cafeteria)17:45-20:00 Diversity cocktail and Posters from RTSS@work (cafeteria)

December, 5th (Tuesday)

WMC 5th International Workshop on Mixed Criticality Systems (ECE building – SC 316)Chairs: Arvind Easwaran and Kunal Agrawal

08:30 Registration Opens

09:15-10:30 Session 1

Challenges in Applying Mixed-Criticality Systems to Aircraft Engine Control Systems > Iain Bate (University of York, UK) and Stephen Law (Rolls-Royce Control Systems, UK 10:30-11:00 Coffee break 11:00-12:30 Session 2 Porting a Safety-Critical Industrial Application on a Mixed-Criticality Enabled Real-Time Operating System > Antonio Paolillo, Paul Rodriguez, Vladimir Svoboda, Olivier Desenfans, Joel Goossens, Ben Rodriguez, Sylvain Girbal, Madeleine Faugère and Philippe Bonnot

Selective Real-Time Data Emission in Mobile Intelligent Transport Systems > Laurent George, Damien Masson and Vincent Nelis

Probabilistic Analysis of Low-Criticality Execution > Martin Küttler, Michael Roitzsch, Claude-Joachim Hamann and Marcus Völp 12:30-14:00 Lunch (cafeteria) 14:00-15:30 Session 3

Defining and Delivering Resilience in Mixed-Criticality Systems > Alan Burns (University of York, UK)

Mixed Criticality Systems - A History of Misconceptions? > Borislav Nikolic (TU Braunschweig, Germany) 15:30-16:00 Coffee break 16:00-17:00 Session 4

Revisiting the Computational Complexity of Mixed-Critical Scheduling > Rany Kahil, Peter Poplavko, Dario Socci and Saddek Bensalem

Response Time Analysis for Mixed Criticality Systems with Arbitrary Deadlines > Alan Burns and Robert Davis 17:00-17:45 RTSS@work presentation session (cafeteria)17:45-20:00 Diversity cocktail and Posters from RTSS@work (cafeteria)

December, 5th (Tuesday)

RTSS@Work (ECE building – cafeteria)Chair: Damir Isovic

17:00-17:45 Presentation session 5 minutes each

An ECU-Close Design/Verification Tool for Automotive Systems > Wonseok Lee, Kyoung-Soo We, Seunggon Kim, Sangyoun Paik, Johnathon Soulis and Chang-Gun Lee

Demonstrating Model- and Component-based Development of Vehicular Real- time Systems > Alessio Bucaioni, Saad Mubeen, Mikael Sjödin, John Lundbäck, Mattias Gålnander and Kurt-Lennart Lundbäck

Modeling and Timing Analysis of Ethernet-AVB in Rubus-ICE > Mohammad Ashjaei, Saad Mubeen, John Lundbäck, Mattias Gålnander, Kurt- Lennart Lundbäck and Thomas Nolte

pWCET estimator for real-time systems > Adriana Gogonel, Cristian Maxim and Liliana Cucu-Grosjean

MC-SDN: Supporting Real-Time Mixed Criticality Scheduling in Software Defined Networks > Kilho Lee and Insik Shin

Heterogeneous Hybrid Networks Reliability Simulation > Pablo Gutiérrez Peón, Francisco Pozo and Guillermo Rodriguez-Navas

Rising abstraction level in Hardware Dependent Software Development with Leon2ViP > Antonio Da Silva, Pablo Parra, Sebastián Sánchez and Oscar Rodríguez Polo 17:45-20:00 Diversity cocktail and Posters RTSS@work

Accomodation & venue

Conference venue

The conference venue, the Cercle National des Armées (CNA), is located at 8 place Saint Augustin, 75008 Paris. Lunch is served in the same CNA building on the 2nd floor. The conference will take place on the second floor too, on 6th and 8th of December. On 7th of December the presentations sessions will be on the 1st floor in the CNA building.

CNA can be reached by Metro line 9 to station St-Augustin or by Metro 3, 12, 13, 14, RER E to station Gare Saint- Lazare. (map below)

Wifi connection

Cercle National des ARmées is sharing its network with RTSS participants. You may need your mail adress to login.

Speakers

Today, real-time behavior of programs is a property that emerges from implementations rather than a property that is specified in models. Control over timing behavior of software is difficult to achieve, and timing behavior is neither predictable nor repeatable.

I will argue that this problem can be solved by making a commitment to deterministic models that embrace temporal properties as an integral part of the modeling paradigm.

I will show moreover that deterministic timing is practical today without sacrificing performance for many useful workload models. Specifically, I will describe a class of computer architectures called Abstract PRET Machines (APMs) that deliver deterministic timing with no loss of performance for a family of real-time problems consisting of sporadic event streams with hard deadlines.

Keynote speechUnderstanding Time, from Physics to Informatics and Music

Gérard Berry, ProfessorCollege de France

Award speechA Personal View of Real-Time ComputingEdward A. LeeRobert S. Pepper Distinguished ProfessorUniversity of California at Berkeley

Time is one of the greatest mysteries. Physics is able to measure time with an incredible precision, without being able to understand its real nature. On the opposite, our intuitive view of time is very flaky, as exemplified by the way we talk about it: I waited long minutes, time passes fast, etc. In classical software, time is merely absent from programming concerns, being only viewed as a quantity to optimize for efficiency. In hardware circuits, time used to be associated with regular clocks, which made it easy to understand and deal with.

These happy times are over: circuit clocks vary continuously to save energy, and machine instruction timing has become largely unpredictable due to caching, pipelining, speculation, etc. But more and more applications require a much better understanding of temporal issues: real-time programs found in many embedded applications of course, but also time-aware data bases, continuous / discrete simulation of physical phenomena, worldwide clock synchronization, real-time computer music, etc.

The talk will address time in Informatics by stressing and exemplifying several points concerning the specification, implementation, and verification of time-aware applications.

First, synchronous languages such as Esterel, Lustre, Signal, and their followers have shown that we should not restrict time to milliseconds, but instead deal equally with logical clocks generated by the repetition of any arbitrary event using a synchronous model of concurrency. We will explain why the SCADE 6 synchronous language and system of Esterel Technologies has become a standard for high-security temporal applications.

Second, temporal logics and hybrid systems make it possible to perform analysis and proofs of complex temporal applications impossible to analyze by hand; we will illustrate this with the UPPAAL verification system. Third, we shall see that modelers such as Simulink and Modelica exhibit incorrect behaviors when mixing continuous and discrete time; this problem has been elegantly solved in the new Zelus language.

Finally, we will discuss time in music, which is by no way simple. For instance, a score is written with a straight logical time for notes, while interpretation expressivity requires constantly varying the tempo and articulation in physical time. Using as examples the Antescofo score follower and musical synchronous language and the Omax/Improtex co-improviser, we discuss fascinating questions and solutions related with relating logical and physical time during musical performance.

December, 6th (Wednesday morning)

RTSS Conference (CNA building 1st floor)

7 :45 Registration Opens

8:15-8:30 Welcome - Frank Mueller (North Carolina State University) and Isabelle Puaut (Université de Rennes 1/IRISA) 8:30-9:00 Award Speech, Session Chair: Frank Mueller A Personal View of Real-Time Computing > Edward A. Lee, University of California at Berkeley 9:00-10:00 Scheduling and analysis, Session Chair: Joël Goossens

An Exact and Sustainable Analysis of Non-Preemptive Scheduling > Mitra Nasri and Bjorn Brandenburg

Sustainability in Mixed-Criticality Scheduling > Zhishan Guo, Sai Sruti, Bryan Ward and Sanjoy Baruah 10:00-10:30 Coffee break 10:30-12:30 Resource management and simulation, Session Chair: Jian-Jia Chen

Regular Composite Resource Partition in Open Systems > Wei-Ju Chen, Pei-Chi Huang, Quan Leng, Al Mok and Song Han

Network Scheduling for Secure Cyber-Physical Systems > Vuk Lesi, Ilija Jovanov and Miroslav Pajic

Temporal Capabilities: Access Control for Time > Phani Kishore Gadepalli, Lucas Baier, Robert Gifford, Michael Kelly and Gabriel Parmer

Functionally and Temporally Correct Simulation of Cyber-Systems for Automotive Systems > Kyoung-Soo We, Seunggon Kim, Wonseok Lee and Chang-Gun Lee 12:30-14:00 Lunch (cafeteria)

December, 6th (Wednesday afternoon)

RTSS Conference (CNA building 1st floor)

14:00-15:30 Scheduling of parallel tasks, Session Chair: Cong Liu

Semi-Federated Scheduling of Parallel Real-Time Tasks on Multiprocessors > Xu Jiang, Nan Guan, Xiang Long and Wang Yi

Real-Time Scheduling and Analysis of OpenMP Task Systems with Tied Tasks > Jinghao Sun, Nan Guan, Yang Wang, Qingqiang He and Wang Yi

GPU Scheduling on the NVIDIA TX2: Hidden Details Revealed > Tanya Amert, Nathan Otterness, Ming Yang, Jim Anderson and F.Donelson Smith 15:30-16:00 Coffee break 16:00-17:30 Outstanding papers, Session Chair: Enrico Bini

The Virtual Deadline based Optimization Algorithm for Priority Assignment in Fixed-Priority Scheduling > Yecheng Zhao and Haibo Zeng

Analysis Techniques for Supporting Hard Real-Time Sporadic Gang Task Systems > Zheng Dong and Cong Liu

Fixed-Priority Schedulability of Sporadic Tasks on Uniprocessors is NP-hard > Pontus Ekberg and Wang Yi 17:30-18:30 Brief presentations*: Session Chair: Luca Santinelli 19:00-23:00 Posters and welcome reception – French wine and cheese tasting. 4 Place Jussieu, Paris, Batiment Esclangon. Métro station Jussieu (line 7)

Useful information

The Brief Presentation Posters and the welcome reception proposing French wine and cheese tasting

It takes place at another location: Batiment Esclangon on the Jussieu campus. The exact address is 4 Place Jussieu, Paris. To get from CNA to Jussieu Campus there are two options:

Walk on the Haussman Boulevard for 13 minutes up to the metro station Chaussée d’Antin La Fayette on metro line 7 and take the metro from there to Jussieu (M7, 8 stops, direction Villejuif Louis Aragon or Mairie d’Ivry).

Take metro M9 from Saint Augustin to Chaussée d’Antin La Fayette (2 stops, direction Mairie de Montreuil) and from metro station Chaussée d’Antin La Fayette take M7 to Jussieu (M7, 8 stops, direction Villejuif Louis Aragon or Mairie d’Ivry).

*Brief presentations

Work-in-Progress

Maximizing Model Accuracy in Real-time and Iterative Machine Learning> Rui Han, Fan Zhang, Lydia Y. Chen and Jianfeng Zhan

Isochronous Execution Models for Mixed-Criticality Systems on Parallel Processors> Bader Alahmad and Sathish Gopalakrishnan

An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling> Enrico Mezzetti, Jaume Abella, Carles Hernandez and Francisco Cazorla

Design-Space Exploration of Multi-core Processors for Safety-Critical Real-Time Systems> Dolly Sapra and Sebastian Altmeyer

TTI: A Timing ISA Supporting Logical Execution Time Model in Safety-critical Systems> Bo Wan, Xi Li, Haizhao Luo, Chao Wang, Xianglan Chen and Xuehai Zhou

Networked Control of Autonomous Underwater Vehicles with Acoustic and Radio Frequency Hybrid Communication> Mehrullah Soomro, saeed Nourizadeh Azar, Ozgur Gurbuz and Ahmet Onat

RT-CASEs: Real-Time Containers for large-scale mixed-criticality systems> Marcello Cinque and Gianmaria De Tommasi

Adaptive scheduling with approximate computing for audio graphs> Pierre Donat-Bouillud and Christoph Kirsch

A Flexible Router Architecture for 3D NoCs> Mostafa Abdelrehim, Mostafa Khamis and Ahmed Shalaby

Best-case response time analysis for Ethernet AVB> Hector Joao Rivera Verduzco, Pieter J.L. Cuijpers and Jingyue Cao

Dealing with Aperiodic Tasks on Quasi-Partition Scheduling> Flávia Nascimento, George Lima and Ernesto Massa

Cache-Aware Partitioned EDF Scheduling for Multi-Core Real-Time Systems> Zhishan Guo, Ying Zhang and Zhenkai Zhang

Toward a Coq-certified Tool for the Schedulability Analysis of Tasks with Offsets> Xiaojie Guo, Sophie Quinton, Pascal Fradet and Jean-François Monin

*Brief presentations

Journal papers never presented in conferences

Hard Real-Time Guarantees in Feedback-based Resource Reservations> Alessandro Vittorio Papadopoulos, Martina Maggio, Alberto Leva and Enrico Bini

The Quadratic Utilization Upper Bound for Arbitrary Deadline Real-Time Tasks> Enrico Bini

Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation>Jaume Abella, Maria Padilla, Joan Del Castillo and Francisco Cazorla

Provably Good Task Assignment for Two-type Heterogeneous Multiprocessors using Cutting Planes> Bjorn Andersson and Gurulingesh Raravi

Symbolic WCET Computation> Clément Ballabriga, Julien Forget and Giuseppe Lipari

Schedulability Analysis of Ethernet Audio Video Bridging Networks with Scheduled Traffic Support> Mohammad Ashjaei, Gaetano Patti, Moris Behnam, Lucia Lo Bello and Thomas Nolte

An Efficient Schedulability Analysis for Optimizing Systems with Adaptive Mixed-Criticality Scheduling> Yecheng Zhao and Haibo Zeng

Dynamic Active Log Pool for Improving Worst-case Performance of Memory Cards> Ilhoon Shin

On the Compatibility of Exact Schedulability Tests for Global Fixed Priority Pre-emptive Scheduling with Audsley’s Optimal Priority Assignment Algorithm> Robert Davis, Marko Bertogna and Vincenzo Bonifaci

December, 7th (Thursday)

RTSS conference (CNA building ground floor) 9:00-10:00 Keynote speech, Session Chair: Isabelle Puaut Understanding Time, from Physics to Informatics and Music > Gérard Berry, Collège de France 10:00-10:30 Coffee break 10:30-12:30 Networks, Session Chair: Miroslav Pajic

Awakening Power of Physical Layer: High Precision Time Synchronization for Industrial Ethernet > Kun Qian, Tong Zhang and Fengyuan Ren

Aerial Video Stream over Multi-hop using Adaptive TDMA Slots > Luis Ramos Pinto, Luís Almeida and Anthony Rowe

Offset Assignment to Signals for Improving Frame Packing in CAN-FD > Prachi Joshi, S.S. Ravi, Soheil Samii, Unmesh D. Bordoloi, Sandeep Shukla and Haibo Zeng

Synthesis of Queue and Priority Assignment for Asynchronous Traffic Shaping in Switched Ethernet > Johannes Specht and Soheil Samii 12:30-14:00 Lunch (1st floor) 14:00-15:30 Industrial panel, Session Chair: Sophie Quinton 15:30-16:00 Coffee break 16:00-18:00 Hardware-aware scheduling and WCET estimation, Session Chair: Francisco Cazorla Integrated Analysis of Cache Related Preemption Delays and Cache Persistence Reload Overheads > Syed Aftab Rashid, Geoffrey Nelissen, Sebastian Altmeyer, Robert Davis and Eduardo Tovar

Schedulability Analysis of Non-preemptive Real-time Scheduling for Multicore Processors with Shared Caches > Jun Xiao, Sebastian Altmeyer and Andy Pimentel

Memory Bank Partitioning for Fixed-Priority Tasks in a Multi-Core System > Sheng-Wei Cheng, Jian-Jia Chen, Jan Reineke and Tei-Wei Kuo

On Using GEV or Gumbel Models when Applying EVT for Probabilistic WCET Estimation > Karila Palma Silva, Luís Fernando Arcaro and Rômulo Silva de Oliveira 18:00-19:00 TC meeting All welcome. Vote for the location of RTSS’19 20:00 Banquet, at the Le train Bleu, Place Louis-Armand, 75012 Paris. Close to station Gare de Lyon (line RER A, line 1, 14)

Banquet

The banquet will be hosted at the “Le Train Bleu” on December 6th. The restaurant’s address is Place Louis Armand 75012 Paris, which is close to Gare De Lyon. There is a direct subway line, M14 between the CNA (St Lazare) and the restaurant.

December, 8th (Friday)

RTSS Conference (CNA building 1st floor)

End-to-End Network Delay Guarantees for Real-Time Systems using SDN > Rakesh Kumar, Monowar Hasan, Smruti Padhy, Konstantin Evchenko, Lavanya Piramanayagam, Sibin Mohan and Rakesh Bobba

Event-Driven Bandwidth Allocation with Formal Guarantees for Camera Networks > Gautham Nayak Seetanadi, Javier Cámara, Luís Almeida, Karl-Erik Arzen and Martina Maggio

Revisiting GPC and AND Connector in Real-Time Calculus > Yue Tang, Nan Guan, Weichen Liu, Linh Thi Xuan Phan and Wang Yi 10:00-10:30 Coffee break 10:30-12:30 Internet of things, Session Chair: Robert Kaiser

RT-IFTTT: Real-Time IoT Framework with Trigger Condition-aware Flexible Polling Intervals > Seonyeong Heo, Seungbin Song, Jong Kim and Hanjun Kim

Jitter-compensated VHT and its application to WSN clock synchronization > Federico Terraneo, Fabiano Riccardi and Alberto Leva

REC: Predictable Charging Scheduling for Electric Taxi Fleets > Zheng Dong, Cong Liu, Yanhua Li, Jie Bao, Yu Gu and Tian He

Model Predictive Real-Time Monitoring of Linear Systems > Xin Chen and Sriram Sankaranarayanan 12:30-14:00 Lunch (1st floor) 14:00-16:00 Multiprocessor scheduling, Session Chair: Rob Davis

Global EDF scheduling of multiple independent synchronous dataflow graphs > Abhishek Singh and Sanjoy Baruah

On the Soft Real-Time Optimality of Global EDF on Uniform Multiprocessors > Kecheng Yang and Jim Anderson

Beyond Implicit-Deadline Optimality: A Multiprocessor Scheduling Framework for Constrained-Deadline Tasks > Hyeongboo Baek, Hoon Sung Chwa and Jinkyu Lee

An O(log log m)-competitive Algorithm for Online Machine Minimization > Sungjin Im, Benjamin Moseley, Kirk Pruhs and Clifford Stein

16:00-16:15 Best presentation award and closing remarks

8:30-10:00 Networks and distributed systems, Session Chair: Christian Fraboul

Notes