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Dr. Martin März © Fraunhofer IISB
1
ECPE Workshop „Future Trends for Power Semiconductors“ ETH Zürich, 27.1.2012
Fraunhofer Institute for Integrated Systems and Device Technology (FhG-IISB)
Schottkystrasse 10 ● 91058 Erlangen / Germany ● Tel. +49 9131/761-310
www.iisb.fraunhofer.de
Dr. Martin März
Parasitics in Power Electronics Avoid them or Turn Enemies into Friends
Dr. Martin März © Fraunhofer IISB
2
Are Modern Power Semiconductors too Fast?
„Help, the new power semiconductors
are uncontrollable ...“
„... the passive components can not
keep pace with this development ...“
„... the expense for EMC measures will over-compensate
other earnings in system performance ...“
„... why switching so fast?“
Snapped up Statements
„…. we had to extra slow-down our
latest power semiconductors ...“
Dr. Martin März © Fraunhofer IISB
3
Ultra-fast Switching with Modern Power Semiconductors
Rg
Cgs
Cgd Rd
Cds
chip
G
S
D
Unipolar Devices
allow switches without a forward threshold voltage
also with wide band-gap (WBG) materials like SiC
or GaN;
feature an inner control mechanism that can be
considered as infinite fast for nearly any power
electronics application;
show dynamic properties that are basically defined
by the parasitic elements on chip and package level.
MOSFET, JFET, Schottky-Diode (SBD) etc. are device concepts
basically without any relevant restriction in dynamic performance.
Dr. Martin März © Fraunhofer IISB
4
Ultra-fast Switching with Modern Power Semiconductors
0 10 20 30 40 50
Power Density P [W/cm3]
Eff
icie
ncy
140
120
100
80
60
40
20
0
99
98
95
90
Po
wer
Qu
ali
ty F
ac
tor
QP
1
P
P
Q
Q
Efficiency
Power Quality Factor
lossP
PQ out
P
Performance Factor1)
P PQP QFOM
1) FOM: Figure-of-Merit
Power Density
P
3cm
W
Vol
Pout500
3000
1000
FOMQP in
3cm
W
Power Density vs. Efficiency
Dr. Martin März © Fraunhofer IISB
5
Ultra-fast Switching with Modern Power Semiconductors
Controllability1)
Parasitics2)
EMI
What´s most important?
1) of the active devices
2) on device and system level
Dr. Martin März © Fraunhofer IISB
6
Ultra-fast Switching with Modern Power Semiconductors
t1
Vgs
Id
t t3 t4 t7 t8
Vds
Id
dt
dVds
t5 t6 t10
0 100 200 300
Drain-Source Voltage Vds [V]
10.000
1.000
100
10 Fe
ed
ba
ck
Ca
pa
cit
an
ce C
gd [p
F]
D-MOSFET
SJ-MOSFET
)(
)(
dsgd
gds
VC
I
dt
tdV
Rg
Cgd
G
S
D
Ig
Vgs,th
t3
Controllability is lost if
Cgd becomes too small
but also if t5 - t1 >> t3´- t3 1)
1) because pulse timing becomes no longer manageable in real applications using simple gate resistors for dV/dt control.
Controllability Controlling the dV/dt
Dr. Martin März © Fraunhofer IISB
7
Ultra-fast Switching with Modern Power Semiconductors
Id Ig
VLS LS
Vq,G Vgs
dt
tdI
dt
tdILIRVV
gdSgGGqgs
)()(,
RG
RG
load
Id
load
current
driver
current
= 3 Volt @ LS = 1 nH und dI/dt = 3 A/nsec
Controllability dI/dt Limitations
Even very small source inductance values
severly limit the switching speed!
Dr. Martin März © Fraunhofer IISB
8
Ultra-fast Switching with Modern Power Semiconductors
drain
... without leaving beaten tracks, it becomes a losing battle against parasitics
Typ. Package Inductances
Module TO-247 TO-220
Ld [nH] 20...40** 4..7 (<1)* 3..5 (<1)*
Lg [nH] 12...14 7...12
Ls [nH] 9...16 6...12
* via tab ** total inductance (Ld+Ls)
source
Rg
Cgs
Cgd Rd
Cds
chip
Lg
Ld
Ls
package
gate
Rs
Dr. Martin März © Fraunhofer IISB
9
Limitations of Hard switching
Example
V0
LS
I0
V
t
V (t)
dt
dILV S
V0
With the switching time tsw and the relative over-voltage
it follows from eq. (1):
0
1V
Vk
(1)
SW
S
tk
L
I
VZ
10
0
SW
St
ILVk 0
01 or
Commutation Cell Impedance
A
V10
nsec10%10
nH10
1
SW
S
tk
L
„If the commutation cell impedance drops in the range of a few Ohms or below, it becomes
more and more impracticable to realize the low loop inductance necessary for very fast switching.“
!
Dr. Martin März © Fraunhofer IISB
10
Limitations of Hard switching
1300
300
0
0
A
V
I
VZ
LS
The realization of a 10 nsec switching
time would require a total loop
inductance (Ls) of 1 nH or below,
…. which is obviously impracticable!
SWS tkZL 1
Example: 300 A DC/DC Converter
V0
I0
Multiphase concepts are a powerful approach to
overcome the problems of a to low commutation
cell impedance,
… but are not deployable in all applications.
Commutation Cell Impedance
! V0
I0
10 x I0
n = 10
1030
300
0
0
A
V
I
VZ
Dr. Martin März © Fraunhofer IISB
11
Limitations of Hard switching
Example
Coss,e of a 190m/600V CoolMOS: 80 pF
To keep the intrinsic dynamic losses below a certain
percentage k2 of the processed power 2), i.e.
the following impedance constraint must be fulfilled:
sw,
2
0
0
fC
k
I
VZ
eoss
00
2sw
2
0,22
1I
VkfVC eoss
A
V625
MHz1pF80
%5
sw,
2
fC
k
eoss
!
Dynamic Node Impedance
V0
I0
Even with dynamically ideal1) power semiconductors
intrinsic losses occur under hard switching conditions:
1) unipolar behaviour in the 1. and 3. quadrant
2) Coss,e: (energy) effective output capacitance; here: total capacitance loading the node (consider factor 2 in a half-bridge topology)
3) k2 must be less than a few percent therefore to get an acceptable part-load efficiency
osseffon EfIRP sw
2
intv,
Ieff
Note: The intrinsic dynamic losses are present also under no-load conditions3).
Dr. Martin März © Fraunhofer IISB
12
Limitations of Hard switching
Impedance Constraints in Hard Switched Topologies
sw,
2
fC
kZ
eoss Z
tk
L
SW
S 1
1 10 100 1000
Impedance [V/A]
fsw fsw
Multi-Phase
Topologies
Multi-Level
Topologies
The window of best performance becomes smaller with increasing frequency
eoss
onopt
Cf
RZ
,sw
The alternative:
Soft or Resonant Switching
Dr. Martin März © Fraunhofer IISB
13
Limitations of Hard switching
Active Chip Area A [mm2]
Po
wer
Lo
ss
es
[W
] Total Losses
ossoneff
A
oss
A
oneff
ERfI
ERfIP
sw
)()(
swminv,
2
2
)(
)(
sw
opt A
oss
A
oneff
E
R
f
IA
Intrinsic Losses in Hard Switched Topologies
sw
)(2)(
totalv, )( fAEIA
RAP A
osseff
A
on
Circuit FOM of power
semiconductor
technology1)
static
dynamic
1) as a Figure-of-Merit (FOM) this term characterizes a technology not only a certain device!
Dr. Martin März © Fraunhofer IISB
14
Limitations of Hard switching
Active Chip Area A [mm2]
Po
wer
Lo
ss
es
[W
] Total Losses
static
dynamic
22
swmaxminv,
f
fVIP eff
Intrinsic Losses in Hard Switched Topologies
22
,
)(
,
)(
2
1
fCRCR eosson
A
eoss
A
on
Using
2
max,2
1VCE eossoss
the loss minimum can be written as
and the output cut-off frequency
minv,P
*
22
swmax
21
f
f
resulting in an upper efficiency limit of approximately:
1) f22* considers total node capacitance
Dr. Martin März © Fraunhofer IISB
15
Limitations of Hard switching
Intrinsic Losses in Hard Switched Topologies
Example
Output cut-off frequency of CoolMOS™ C3 technology:
GHz0,45,0pF802
1
2
1
150,,
22
Coneoss RC
f
With no additional capacitive loading of the dynamic node,
the upper efficiency limit is:
MHz1@
kHz100@
kHz10@
%7,98
%6,99
%9,992
11
sw
sw
sw
22
sw
in
minv,
max
f
f
f
f
f
P
P
22
max0
in
effeff IVIVP
with
V0
I0
ideal diode
Ieff
1) values taken from a SPP20N60C3
Even in an ideal circuit environment it is not possible to
exceed this efficiency under hard switching conditions!
Dr. Martin März © Fraunhofer IISB
16
Limitations of Hard switching
0 10 20 30 40 50 60
Output Power [kW] E
ffic
ien
cy
[%
]
100
99
98
97
96
95
94
93
Output power: 100 kW (max.)
Switching frequency: 17,5 kHz
Efficiency: 99% (max.)
Topology: Multiphase Buck/Boost
Power density: ca. 10 kW/Liter
Boost mode: 240 V 380 V
Comparison of DC/DC converter solutions using different PS1) technologies
Bipolar / Bipolar Si-IGBT / Si-Diode (600 V)
1) Power Semiconductor
Dr. Martin März © Fraunhofer IISB
17
Limitations of Hard switching
0 40 80 120 160 200
100
95
90
85
Output Current ILV [A]
Buck mode: VHV = 450 V, VLV = 300 V
w/o phase removal
with phase removal
Bipolar / Unipolar Si-IGBT / SiC-Diode (600 V)
Output power: 100 kW (max.)
Switching frequency: 100 kHz
Efficiency: 97,5% (max.)
Topology: Multiphase Buck/Boost
Power density: 25 kW/Liter
Comparison of DC/DC converter solutions using different PS1) technologies
Eff
icie
ncy
[%
]
number of active phases
1 3 6 12
1) Power Semiconductor
Dr. Martin März © Fraunhofer IISB
18
Limitations of Hard switching
Eff
icie
ncy
[%]
100
99
98
97
96
95 0 20 40 60 80 100 120
Output Power [kW]
Buck/Boost Mode
VLV = 333 V
VHV = 400 V
VHV = 450 V
VLV
VHV
A project in cooperation of and
Comparison of DC/DC converter solutions using different PS1) technologies
Unipolar / Unipolar Si-MOSFET / SiC-Diode
U
I
unipolar
unipolar
Output power: 120 kW (max.)
Switching frequency: 200 kHz
Efficiency: 98,75% (max.)
Topology: Multiphase Buck/Boost
Power density: 40 kW/Liter
1) Power Semiconductor
Dr. Martin März © Fraunhofer IISB
19
Limitations of Hard switching
500
400
300
200
100
0
Time base [20 ns/div]
500
400
300
200
100
0
Volt
Turn on
Turn off
VHS
Time base [1 µs/div]
50
40
30
20
10
0
Cu
rre
nt
I L [A
]
500
400
300
200
100
0
Vo
lta
ge
VH
S [V
]
Switching frequency: 200 kHz
IL
dVHS/dt ca. 17 V/ns
dID /dt ca. 3 A/ns
dVHS/dt ca. 20 V/ns
overvoltage ≤ 45V (@35A)
Even in the 100 kW power range the current and voltage
transients are controllable with a well-designed set-up.
Note the low turn-off overvoltage and oszillations.
Mode: Buck
Unipolar / Unipolar Si-MOSFET / SiC-Diode
Comparison of DC/DC converter solutions
Dr. Martin März © Fraunhofer IISB
20
Limitations of Hard switching
500
3000
FOMQP
0 10 20 30 40 50
140
120
100
80
60
40
20
0
1000
99
98
95
90
unipolar/unipolar
200 kHz
bipolar/unipolar
100 kHz
100 kW DC/DC converters in comparison bipolar/bipolar
17,5 kHz
3cm
Win
1) FOM: Figure-of-Merit
Better Performance by Faster Switching
Eff
icie
ncy
Power Quality Factor
lossP
PQ out
P
Performance Factor1)
P PQP QFOM
Power Density
P
3cm
W
Vol
Pout
Power Density P [W/cm3]
Po
wer
Qu
ali
ty F
ac
tor
QP
Dr. Martin März © Fraunhofer IISB
21
Ultra-fast Switching with Modern Power Semiconductors
RF-like Device and System Designs are Mandatory
Key success factors are
minimization of parasitics
capacitors with exceptional high current rating
effective cooling of active and passive devices
high robustness (thermo/mechanical)
Dr. Martin März © Fraunhofer IISB
22
Ultra-fast Switching with Modern Power Semiconductors
EMI Encapsulation
DC/DC converters
relatively easy to perform
effective filters, shields and damping
materials available
DC DC
1) like inverters for drives, PV, welding, induction heating, lamp ballast, etc.
DC AC
DC/AC inverters1)
more critical due to accessible AC node
filters at the AC terminal – if necessary –
can become quite expensive
Dr. Martin März © Fraunhofer IISB
23
Ultra-fast Switching with Modern Power Semiconductors
Resonant and Soft Switching
IL
VDS
Ichannel Icap
VDS
IL
switching losses
Id
Hard Switching Zero Voltage Switching Basic Cell
ZVS ideally fits to the intrinsic properties of unipolar
power semiconductors
Especially interesting if frequency can be chosen so
high that resonant elements can be realized by circuit
parasitics (turn enemies into friends)
Allows switching frequencies up to deep in the mega-
hertz range when using a pure unipolare PS1) design
switching losses
1) Power Semiconductor
VDS
Icap
Dr. Martin März © Fraunhofer IISB
24
Ultra-fast Switching with Modern Power Semiconductors
The ZVS basic cell structure is
no carte blanche for offering
ultra-fast power semiconductors
in unsuitable packages!
Take Care of Parasitic Resonances
Chip
Package
Circuit
Cdgs
1) Cdgs: Feedback stray capacitance of circuit layout
Lσ
Cext
Basic ZVS cell = ?
Unwanted oscillations are preprogrammed
Dr. Martin März © Fraunhofer IISB
25
Are Modern Power Semiconductors too Fast?
Conclusion
Power Semiconductors can never be too fast !
but their controllability must be preserved and optimized by the manufacturers,
they must be provided in appropriate packages, and
must be operated in suitable circuit topologies and system environments.
Unipolar devices then allow to enter new regions in the trade-off
between efficiency and power density.
Modern unipolar WBG1) devices allow the extension of the performance level
reached in the application fields of 600V Si devices towards much higher voltages.
1) Wide band gap
Dr. Martin März © Fraunhofer IISB
26
Ultra-fast Switching with Modern Power Semiconductors
1 000 000
100 000
10 000
1 000
100
10
1
0,01 0,1 1 10 100 1000 Frequency [MHz]
Po
wer
[W
]
Inductive
Heating hardening, welding,
cooking
Microwave oven
Power Supplies
DC/DC Converters
Power Semiconductors
Dielectric
Heating
Plasma Generation lasers, plasma treatment ...
Ele
ctr
on
Vacu
um
Tu
bes
Drives
Fields of Application
Dr. Martin März © Fraunhofer IISB
27
ECPE Workshop „Future Trends for Power Semiconductors“ ETH Zürich, 27.1.2012
Your best resource for all aspects of power electronics
Fraunhofer-IISB
Thank You for Your attention!