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PARALLEL-SEARCH TRIE-BASED SCHEME FOR FAST IP LOOKUP
Author: Roberto Rojas-Cessa, Lakshmi Ramesh, Ziqian Dong, Lin Cai Nirwan Ansari
Publisher: IEEE GLOBECOM 2007
Speaker: Han-Jhen Guo
Date: 2008.09.02
OUTLINE
Parallel-Search Trie-Based Scheme Introduction Target levels Data structure
Implement Search Procedure
Outline Architecture and memory access Longest prefix selection
Complexity and Performance Conclusions
PARALLEL-SEARCH TRIE-BASED SCHEME- INTRODUCTION (1/2)
forwarding table binary trie
PARALLEL-SEARCH TRIE-BASED SCHEME- INTRODUCTION (2/2)
expanded forwarding table
extended-prefix tree
PARALLEL-SEARCH TRIE-BASED SCHEME- TARGET LEVELS (1/2)
select the target levels IPv4 BGP Reports
Prefix Length Distributions
BGP data obtained from AS65000; Report last updated at Tue Sep 2 00:10:57 2008 (UTC+1000).
a large number of the prefixes are found between levels 16 and 24
PARALLEL-SEARCH TRIE-BASED SCHEME- TARGET LEVELS (2/2)
4 target levels(root level = 0) bit vectors (global)
level 8 and 16 segments (partial)
level 24 and 32
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (1/7)
nexthop information (15-bit) one for each target level
scheme I: feasible amount of memoryfeasible amount of memory associate every bit within a segment with a next-hop
information without considering whether the prefix exists
scheme II: reduced memoryreduced memory store the next-hop information for the positions
where prefix exists require one extra memory-access time if the longest
prefix match is found on level 24 or 32
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (2/7)
example of level-8 and nexthop information
0 1 01 0 1 0 0...prefixVal80 1 32 4 5 254 255...
- A -A - C - -...
0 1 32 4 5 254 255...tableNext8(scheme I)
A A *C * * ...
1 2 43 5 6 ...tableNext8(scheme II)
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (3/7)
level-8 prefixVal (prefixVal8)
bitmap for prefix node (at level 8) tableNext (tableNext8)
nexthop information for prefix node (at level 8)
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (4/7)
example of level-16
0 1 0 0 1...prefixVal160 1 2 30 31...
0 0 0 0 1...
32 33 34 62 63...
0 0 1 0 0
216-1...
...
...
0 1 1 0 1...childVal24 0 1 0 1 1... 0 1 0 0 0...
0 0 0 1 0...childVal32 0 0 1 0 0... 0 0 0 0 0...
0offsetVal16 2 232
...
...
0
0
3
451
156
...
...
offsetVal24
offsetVal32
bit chunk 0 bit chunk 1 bit chunk 2047...
(16-bit)
(32-bit)
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (5/7)
level-16 prefixVal (prefixVal16) childVal (childVal24, childVal32)
indicates whether there is one or more prefixes of length between (17 and 24, 25 and 32) that share each 16-bit combination indexed by prefixVal16
offsetVal (offsetVal16, offsetVal24, offsetVal32) the total number of ones accumulated from all
previous chunks tableNext (tableNext16)
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (6/7)
example of level-24, level-32
0 1 0 0 1...prefixVal240 1 2 254 255...
0 0 0 0 1... 0 0 1 0 0
...
...
0offsetPort24 1 45
...
...
chunk 0 chunk 1 chunk r...
0 1 0 0 0...portInterval24 0 0 0 0 1... 0 0 1 0 0......
0 1 2 254 255... 0 1 2 254 255...
(24-bit, 32-bit)
(256-bit, 216-bit)
PARALLEL-SEARCH TRIE-BASED SCHEME- DATA STRUCTURE (7/7)
level-24 and 32 prefixVal (prefixVal24, prefixVal32) portInterval (portInterval24, portInterval32)
indicates the existence of the next hop information that is duplicated to reduce the number of port number memory
offsetPort (offsetPort24, offsetPort32) indicates the number of prefixes that has next hop
information in the previous segments of level (24, 32) tableNext (tableNext24, tableNext32)
can use scheme II for economical
IMPLEMENT
Separate blocks of memory for independent access
lv. 8bit vector
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
x31 … x24 x23 … x16 x15 … x8 x7 … x0IP Address
SEARCH PROCEDURE (1/7)- OUTLINE
proposed trie-based IP lookup algorithm① at the first memory access, searches for a
match in level 8 and 16② in the second memory access, verifies possible
matches at levels 24 and 32, and retrieves all possible next hops, one per level If using reduced memory, the third time memory
access is necessary for retrieves the nexthop information at levels 24 and 32.
③ if matches are achieved at different levels, the match belonging to the longest prefix is selected
SEARCH PROCEDURE (2/7)- ARCHITECTURE AND MEMORY ACCESS (1/5)
1st memory access
lv. 8bit vector
x31 … x24 x23 … x16 x15 … x8 x7 … x0
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
IP Address
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
bit# bit#
SEARCH PROCEDURE (3/7)- ARCHITECTURE AND MEMORY ACCESS (2/5)
after 1st memory access
lv. 8bit vector
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
chunk#
x31 … x24 x23 … x16 x15 … x8 x7 … x0IP Address
SEARCH PROCEDURE (4/7)- ARCHITECTURE AND MEMORY ACCESS (3/5)
2nd memory access
lv. 8bit vector
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
x31 … x24 x23 … x16 x15 … x8 x7 … x0IP Address
SEARCH PROCEDURE (5/7)- ARCHITECTURE AND MEMORY ACCESS (4/5)
after 2nd memory access
lv. 8bit vector
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
x31 … x24 x23 … x16 x15 … x8 x7 … x0IP Address
SEARCH PROCEDURE (6/7)- ARCHITECTURE AND MEMORY ACCESS (5/5)
3rd memory access (only for reduced memory)
lv. 8bit vector
lv. 16bit vector
lv. 24bit segment
lv. 32bit segment
tableNext8(scheme I)
tableNext16(scheme II)
tableNext24 tableNext32
selection
x31 … x24 x23 … x16 x15 … x8 x7 … x0IP Address
SEARCH PROCEDURE (7/7)- LONGEST PREfiX SELECTION
Possibilities of matching prefixVal bit at different levels
priority: low ←→ high
COMPLEXITY AND PERFORMANCE (1/2)
Complexity
Operation Memory Access Times
get matchings at level 8 1
get matchings at level 16, 24 and 32
2
using the memory reduction scheme for the next-hop information
(maybe) 3
COMPLEXITY AND PERFORMANCE (2/2)
Performance routing table AS65000 (August 1, 2007)
number of entries: 82835 average prefix length: 22 number of segments for level 24: 6305 number of segments for level 32: 82
actual memory requirement reduced memory scheme: 1.6 MB feasible amount of memory scheme: 10 MB
CONCLUSIONS
Schemes Advantage Disadvantage
Ternary Content Addressable Memories(TCAMs)
resolve the IP lookup in 11 memory-accesstime
a) high power consumption
b) large complexity
Trie with Random Access Memory (RAM)
require 33 or more memory-access times for IP lookup
proposed trie-based IP lookup algorithm
a)a) 22 memory access times with a feasible amount of memory
b)b) 33 memory access times with reduced memory