PAPER SOLUTION

SESSIONAL 1

Microprocessor & Microcontroller

2017-18 -

Department of Electronics & Telecommunication Engineering

ST. VINCENT PALLOTTI COLLEGE OF ENGINEERING & TECHNOLOGY

Q.1 (a) Draw and explain BIU & EU of 8086 microprocessor.

Ans:

The internal architecture of Intel 8086 is divided into two units, viz.,

Bus Interface Unit (BIU) and Execution Unit (EU).

Bus Interfacing Unit (BIU)-

It provides the interface of 8086 to external memory and I/O devices.

It operates with respect to bus cycles (machine cycles). This means it performs various machine cycles such as memory read, I/O read etc. to transfer data with memory and I/O devices.

BIU performs the following functions-

It generates the 20 bit physical address for memory access.

It fetches instruction from memory.

It transfers data to and from the memory and I/O.

It supports pipelining using the 6 byte instruction queue.

The main components of the BIU are as follows:

Segment registers-

CS register: CS holds the base address for the Code Segment. All programs are stored in the Code Segment.

CS is multiplied by 10H to give the 20 bit physical address of the Code Segment. E.g. If CS = 4321H then CS x

10H = 43210H→ Starting address of Code Segment.

DS register: DS holds the base address for the Data Segment. It is multiplied by 10H to give the 20 bit

physical address of the Data Segment. E.g. If DS = 4321H then DS x 10H = 43210H→ Starting address of Data

Segment.

SS register: SS holds the base address for the Stack Segment. It is multiplied by 10H to give the 20 bit physical

address of the Stack Segment. E.g. If SS = 4321H then SS x 10H = 43210H→ Starting address of Stack

Segment.

ES register: ES holds the base address for the Extra Segment. It is multiplied by 10H to give the 20 bit physical

address of the Extra Segment. E.g. If ES = 4321H then ES x 10H = 43210H→ Starting address of Code

Segment.

Instruction Pointer (IP)-

It is a 16 bit register. It holds offset of the next instructions in the Code Segment.

Address of the next instruction is calculated as CS x 10H + IP.

IP is incremented after every instruction byte is fetched.

IP gets a new value whenever a branch occurs.

Address Generation Circuit-

The BIU has a Physical Address Generation Circuit. It generates the 20 bit physical address using Segment and Offset

addresses using the formula: Physical Address = Segment Address x 10H + Offset Address

6 Byte Pre-fetch Queue-

It is a 6 byte first in first out (FIFO) RAM used to implement pipelining. Fetching the next instruction while

executing the current instruction is called pipelining.

BIU fetches the next six instruction bytes from the Code Segment and stores it into the queue.

Execution Unit (EU) removes instructions from the queue and executes them. The queue is refilled when at

least two bytes are empty as 8086 has a 16 bit data bus. Pipelining increases the efficiency of the

microprocessor.

Pipelining fails when a branch occurs as the pre-fetched instructions are no longer useful.

Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue.

Now, the next six bytes from the new location (branch address) are fetched and stored in the queue and pipelining continues.

Execution Unit (EU)-

It fetches instructions from the Queue in BIU, decodes and executes them.

It performs arithmetic, logic and internal data transfer operations within the microprocessor.

It sends request signals to the BIU to access the external module.

It operates with respect to T-stats (clock cycles) and does not depend upon which machine cycle is being performed by the BIU.

The main components of the EU are as follows:

General purpose registers- 8086 microprocessor has four 16 bit general purpose registers AX, BX, CX and DX.

These are available to the programmer for storing values during programs. Each of these can be divided into

two 8 bit registers such as AH, Al; BH, BL; etc. Beside their general use , these registers also have some

specific functions.

AX register (16 bits): It holds operands and results during multiplication and division operations. All I/O data

transfers using IN and OUT instructions use A register (AL/AH or AX). It functions as accumulator during

string operations.

BX register (16 bits): It holds the memory address (offset address) in indirect addressing modes.

CX register (16 bits): It holds count for instructions like loop, rotate, shift and string operations.

DX register (16 bits): It is used with AX to hold 32 bit values during multiplication and division. It is used to hold the address of the I/O port in indirect I/O addressing mode.

Special purpose registers-

Stack Pointer (SP 16 bits): It holds offset address of the top of the Stack. Stack is a set of memory locations

operating in LIFO manner. Stack is present in the memory in Stack Segment. It is used during instructions like

PUSH, POP, CALL, RET etc.

Base Pointer (BP 16 bits): BP can hold offset address of any location in the stack segment. It is used to access

random locations of the stack.

Source Index (SI 16 bits): It is normally used to hold the offset address for Data Segment but can also be used

for other segments using Segment Overriding. It holds offset address of source data in Data Segment during

string operations.

Destination Index (DI 16 bits): It is normally used to hold the offset address for Extra Segment but can also be

used for other segments using Segment Overriding. It holds offset address of destination in Ex tra Segment

during string operations.

ALU (Arithmetic Logic Unit) - It has a 16 bit ALU. It performs 8 and 16 bit arithmetic and logic operations.

Operand register-

It is a 16 bit register used by the control register to hold the operands temporarily. It is not available to the

programmer.

Instruction Register and Instruction Decoder-

The EU fetches an opcode from the queue into the instruction register. The instruction decoder decodes it and sends the information to the control circuit for execution.

Flag register (16 bits)-

It has 9 flags.

These flags are of two types: 6 Status flags namely carry flag, parity flag, auxiliary carry flag, zero flag, sign flag and 3 Control flags namely trap flag, interrupt flag and direction flag.

Status flags are affected by the ALU after every arithmetic or logic operation. They give the status of the current

result.

The Control flags are used to control certain operations. They are changed by the programmer.

Q.1 (b) Explain the function of pins of 8086 in maximum mode.

Ans:

S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state.

S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge 0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt 1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory 1 1 1 Passive State

These are used by the 8288 bus controller to generate all memory and I/O operation access control signals. Any

change by S2, S1, S0 during T4 is used to indicate the beginning of a bus cycle. These status lines are encoded as shown in table below.

QS0, QS1 (O): Queue – Status

Queue Status is valid during the clock cycle after which the queue operation is performed. QS0, QS1 provide status

to allow external tracking of the internal 8086 instruction queue. The condition of queue status is shown in table 4.

Queue status allows external devices like In-circuit Emulators or special instruction set extension co-processors to

track the CPU instruction execution. Since instructions are executed from the 8086 internal queue, the queue status

is presented each CPU clock cycle and is not related to the bus cycle activity. This mechanism allows (1) A processor to

detect execution of a ESCAPE instruction which directs the co- processor to perform a specific task and (2) An in-circuit Emulator to trap execution of a specific memory location.

QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

LOCK (O)

It indicates to another system bus master, not to gain control of the system bus while LOCK is active Low. The LOCK

signal is activated by the "LOCK" prefix instruction and remains active until the completion of the instruction. This

signal is active Low and floats to tri-state OFF during 'hold acknowledge'. Example:

LOCK XCHG reg., Memory ; Register is any register and memory GT0

; is the address of the semaphore.

RQ/GT0 and RQ/GT1 (I/O): Request/Grant

These pins are used by other processors in a multi -processor organization. Local bus masters of other processors force

the processor to release the local bus at the end of the processors current bus cycle. Each pin is bi -directional and has an internal pull up resistors. Hence they may be left un-connected.

Q.2 (a) Explain different addressing modes of 8086 with examples.

The different ways in which a source operand is denoted in an instruction is known as addressing modes. There are 8 different addressing modes in 8086 programming −

Immediate addressing mode

The addressing mode in which the data operand is a part of the instruction itself is known as immediate addressing

mode.

Example

MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH

Register addressing mode

It means that the register is the source of an operand for an instruction.

Example

MOV CX, AX ; copies the contents of the 16-bit AX register into

; the 16-bit CX register),

ADD BX, AX

Direct addressing mode

The addressing mode in which the effective address of the memory location is written directly i n the instruction.

Example

MOV AX, [1592H], MOV AL, [0300H]

Register indirect addressing mode

This addressing mode allows data to be addressed at any memory location through an offset address held in any of

the following registers: BP, BX, DI & SI.

Example

MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents

; 4895H are moved to AX

ADD CX, [BX]

Based addressing mode

In this addressing mode, the offset address of the operand is given by the sum of contents of the BX/BP registers and

8-bit/16-bit displacement.

Example

MOV DX, [BX+04], ADD CL, [BX+08]

Indexed addressing mode

In this addressing mode, the operands offset address is found by adding the contents of SI or DI register and 8-

bit/16-bit displacements.

Example

MOV BX, [SI+16], ADD AL, [DI+16]

Based-index addressing mode

In this addressing mode, the offset address of the operand is computed by summing the base register to the

contents of an Index register.

Example

ADD CX, [AX+SI], MOV AX, [AX+DI]

Based indexed with displacement mode

In this addressing mode, the operands offset is computed by adding the base register contents. An Index registers

contents and 8 or 16-bit displacement.

Example

MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]

Q.2 (b) Draw and explain clock generator 8284.

Note: Pin diagram and functions are not required for this answer this is put only for your reference.

Pin Functions:

The 8284A is an 18-pin integrated circuit designed specifically for use with the 8086/8088 microprocessors as shown

in fig1. The following is a list of each pin and its function.

(Note ‘*’ symbol is for bar/NOT)

AEN1* and AEN2*:

The address enable pins are provided to qualify the ready signals. RDY1 and RDY2, respectively. Which are used to

cause wait states, along with the RDY1 and RDY2 inputs. Wait states are generated by the READY pin of the

8086/8088 microprocessor. This is controlled by these two inputs.

RDY1 and RDY2:

The bus ready inputs are provided in conjunction with the AEN1* and AEN2* pins to cause wait states in an

8086/8088 microprocessor based system.

ASYNC*:

The ready synchronization selection input selects either one or two stages of synchronization for the RDY1 and RDY2

inputs.

READY:

Ready is an output pin that connects to the 8086/8088 microprocessor READY input. This signal is synchronized with

the RDY1 and RDY2 inputs.

X1 and X2:

The Crystal Oscillator pins connect to an external crystal used as the timing source for the clock generator and all its

functions.

F/C*:

The Frequency/Crystal select input results the clocking source for the 8284A. If this pin is held high, an extern al clock

is provided to the EFI input pin, and if it is held low, the internal crystal oscillator provides the timing signal.

EFI:

The External Frequency input is used when the F/C is pulled high. EFI supplies the timing whenever the F/C* pin is

high.

CLK:

The clock output pin provides CLK input signal to the 8086/8088 microprocessors and other components in the

system. The CLK pin has an output signal that is one-third of the crystal or EFI input frequency and has a 33 percent

duty cycle, which is required by the 8086/8088 microprocessors.

PCLK:

The Peripheral Clock signal is one-sixth the crystal or EFI input frequency and has a 50 percent duty cycle. The PCLK

output provides a clock signal to the peripheral equipment in the system.

OSC:

The Oscillator output is a TTL level signal that is at the same frequency as the crystal or EFI input. (The OSC output

provides and EFI input to other 8284A clock generators in some multiple processor systems).

RES*:

The reset input is an active-low input to the 8284A. The RES* pin is often connected an RC network that provides

power-on resetting.

RESET:

The Reset output is connected to the 8086/8088 microprocessors RESET input pin.

CSYNC:

The clock synchronization pin is used whenever the EFI input provides synchronization in systems with multiple

processors. When the internal crystal oscillator is used, this pin must be grounded.

GND:

The ground pin is connects to ground.

Vcc:

This power supply pin connects to + 5.0V with a tolerance of ± 10 percent.

The 8284A clock generator has three main functions:

(1) Clock generator, (2) RESET logic, and (3) READY synchronization.

Clock Generator

The 8284A can derive its basic operating frequency from one of two sources: (1) an external frequency source

connected to the EF I pin, and (2) a quartz crystal connected to X1 and X2. The control input F/C is used to select one

of these sources. The crystal frequency should be selected at three times the required CPU clock. The 8284A generates

three clock signals: OSC, CLK and PCLK. The OSC has the same frequency as the crystal (or the external frequency) and

can be used to test the clock generator or as and external frequency 32 Clock Generator 8284A input to other 8284A

chips. The CLK is 1/3 the frequency of the crystal (or the external frequency) with a 33% duty cycle designed to drive

the 8086 processor directly. The PCLK is a peripheral clock signal whose output frequency is 1/2 that of the CLK with

50% duty cycle.

RESET Logic

The 8284A generates an active HIGH signal (RESET) which is used to reset the 8086 microprocessor. This signal must

be held high for at least 50μs in order to guarantee a correct reset of the microprocessor. This requirement can be

achieved using a simple RC circuit as will be explained later in this experiment.

READY Synchronization

The READY signal is used by slow devices (memory or I/O peripherals) to request the processor to extend the bus cycle

to allow these device to finish reading/writing from/to the bus. The 8284A generates a READY signal that is

synchronized with the CPU clock.

Q.3 (a) Draw and explain the interrupt structure of 8086 microprocessor.

In general there are two types of Interrupts:

Internal (or) Software Interrupts

These are triggered by a software instruction and operate similarly to a jump or branch instruction.

External (or) Hardware Interrupts

These are caused by an external hardware module.

SOFTWARE INTERRUPTS–

INT nn is invoked software (sequence of code)

Examples:

DOS INT 21H, BIOS INT 10H.

INT 00 (divide error)

INT 01 (single step)

INT 03 (breakpoint)

INT 04 (signed number overflow)

HARDWARE INTERRUPTS

Hardware interrupts are generated by hardware devices when something unusual happens; this could be a key -press or a mouse move or any other action.

Maskable Interrupts:

The processor can inhibit certain types of interrupts by use of a special interrupt mask bit. This mask bit is part of the

flags/condition code register, or a special interrupt register. In the 8086 microprocessor if this bit is clear, and an

interrupt request occurs on the Interrupt Request input, it is ignored.

Non-Maskable Interrupts:

There are some interrupts which cannot be masked out or ignored by the processor. These are associated with

highpriority tasks which cannot be ignored (like memory parity or bus faults). In general, most processors support the

Non-Maskable Interrupt (NMI). This interrupt has absolute priority, and when it occurs, the processor will finish the

current memory cycle, then branch to a special routine written to handle the interrupt re quest.

Interrupt Vector Table

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the starting addresses of Interrupt

Service Procedures(ISP).Since 4-bytes are required for storing starting addresses of ISPs, the table can hold 256 Interrupt procedures.

The starting address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore the table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the vector & CS is put in high vector.

Example:

If you attempt to divide an operand by zero, the 8086 will automatically interrupt the currently executing program. At

the end of each instruction cycle, the 8086 checks to see if any interrupts have been requested. If an interrupt has been requested, the 8086 responds to the interrupt by stepping through the following series of major actions:

It decrements the stack pointer by 2 and pushes the flag register on the stack.

It disables the 8086 INTR interrupt input by clearing the interrupt flag in the flag register.

It resets the trap flag in the flag register.

It decrements the stack pointer by 2 and pushes the current code segment register contents on the stack.

It decrements the stack pointer again by 2 and pushes the current instruction pointer contents on the stack.

Divide-By-Zero Interrupt-Type 0:

The 8086 will automatically do a type 0 interrupt if the result of a DIV operation or an IDIV operation is too large to fit

in the destination register. For a type 0 interrupt, the 8086 pushes the flag register on the stack, resets IF and TF and

pushes the return addresses on the stack.

Single Step Interrupt-Type 1:

The use of single step execution feature is found in some of the monitor & debugger programs. When we tell a system

to single step, it will execute one instruction and stop. We can then examine the contents of registers and memory locations.

In other words, when in single step mode a system will stop after it executes each instruction and wait for further

direction from user. The 8086 trap flag and type 1 interrupt response make it quite easy to implement a single step

feature direction.

Non-maskable Interrupt-Type 2:

The 8086 will automatically do a type 2 interrupt response when it receives a low to high transition on its NMI pin.

When it does a type 2 interrupt, the 8086 will push the flags on the stack, reset TF and IF, and push the CS value and

the IP value for the next instruction on the stack. It will then get the CS value for the start of the type 2 interrupt service

procedure from address 0000AH and the IP value for the start of the procedure from address 00008H.

Breakpoint Interrupt-Type 3:

The type 3 interrupt is produced by execution of the INT3 instruction. The main use of the type 3 interrupt is to

implement a breakpoint function in a system. Whenever we insert a breakpoint, the system executes the instructions up to the breakpoint and then goes to the breakpoint procedure.

Overflow Interrupt-Type4:

The 8086 overflow flag will be set if the signed result of an arithmetic operation on two signed numbers is too large to be represented in the destination register or memory location.

Example: If we add the 8 bit signed number 01101100 and the 8 bit signed number 010111101, the result will be

10111101. This would be the correct result if we were adding unsigned binary numbers, but it is not the correct signed result.

Software Interrupts-Type O through 255:

The 8086 INT instruction can be used to trigger the 8086 to do any one of the 256 possible interrupt types. The desired interrupt type is specified as part of the instruction.

The instruction INT32, for example will cause the 8086 to do a type 32 interrupt response. The 8086 will push the flag

register on the stack, reset TF and IF, and push the CS and IP values of the next instruction on the stack.

INTR Interrupts-Types 0 through 255:

The 8086 INTR input allows some external signal to interrupt execution of a program. Unlike the NMI input, however,

INTR can be masked so that it cannot cause an interrupt. If the interrupt flag is cleared, then the INTR input is disabled. IF can be cleared at any time with CLEAR instruction.

Q.3 (b) Write a program to count number of 1’s in a given 16 bit data stored in memory location 21000 H and

store the result in extra segment with 5000:2000H.

DS:SI = 2000:1000, ES:DI = 5000:2000

Label Mnemonics Comments

MOV AX,2000H Move immediately 16-bit data 2000H into AX register MOV DS,AX Copy 16-bit data from AX register to DS and initialize data segment

MOV SI,1000H Move immediately 16-bit data 1000H into SI and initialize source index.

MOV CL,0FH Move immediately 8-bit data 0FH into register CL to count number of 1’s in 16-bit number.

MOV DH,00H Move immediately 8-bit data 00H into DH to store the count of 1’s

MOV AX,[SI] Load AX with 16-bit data from memory with address given by DS:SI L2: ROR AX,01H Rotate the data right by 1-bit with carry, stored inside AX

JNC L1 Jump if carry is not set (CY=0) to L1 and if CY=1 go to next instruction. INC DH Increment the value inside register DH by 1

L1: DEC CL Decrement the value inside register CL by 1 JNZ L2 Check Zero Flag if ZF=0 jump and go back to L2 if ZF=1 come out of the loop

MOV AX,5000H Move immediately 16-bit data 5000H into AX register

MOV ES,AX Copy 16-bit data from AX register to ES and initialize extra segment to store result.

MOV DI,2000H Move immediately 16-bit data 2000H into DI and initialize destination index. MOV ES:[DI],DH Store the result i.e. count of number 1’s into destination address given by ES:DI

HLT

Q.4 (a) Draw and explain the control word register format of PPI 8255.

Ans:

There are two basic operational modes of 8255:

1. Bit set/reset mode (BSR mode).

2. Input/Output mode (I/O mode).

The two modes are selected on the basis of the value present at the D7 bit of the control word register. When D7 = 1,

8255 operates in I/O mode, and when D7 = 0, it operates in the BSR mode.

The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C (PC0 - PC7) can be set/reset by suitably

loading the control word register. BSR mode and I/O mode are independent and selection of BSR mode does not affect the operation of other ports in I/O mode.

8255 BSR mode

D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.

Bits D3, D2 and D1 are used to select the pin of Port C.

Bit D0 is used to set/reset the selected pin of Port C.

Selection of port C pin is determined as follows:

Input/Output mode

This mode is selected when D7 bit of the Control Word Register is 1. There are three I /O modes:

Mode 0 - Simple I/O

Mode 1 - Strobed I/O

Mode 2 - Strobed Bi-directional I/O

I/O Control Word Format

D0, D1, D3, D4 are assigned for port C lower, port B, port C upper and port A respectively. When these bits are

1, the corresponding port acts as an input port. For e.g., if D0 = D4 = 1, then lower port C and port A act as

input ports. If these bits are 0, then the corresponding port acts as an output port. For e.g., if D1 = D3 = 0, then

port B and upper port C act as output ports.

D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0, mode 0 is selected and when D2 = 1, mode 1 is selected.

D5 & D6 are used for mode selection of Group A (port A and upper port C). The selection is done as follows:

Mode 0 - simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking signals. Port A, port B provide

simple I/O operation. The two halves of port C can be either used together as an additional 8-bit port, or they can be

used as individual 4-bit ports. Since the two halves of port C are independent, they may be used such that one -half is

initialized as an input port while the other half is initialized as an output port.

Mode 1 - Strobed Input/output mode

When we wish to use port A or port B for handshake (strobed) input or output operation, we initialise that port in

mode 1 (port A and port B can be initilalised to operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in mode 1. Some of the pins of port C function as handshake lines.

For port B in this mode irrespective of whether is acting as an input port or output port), PC0, PC1 and PC2 pins function

as handshake lines.

If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as handshake signals. Pins PC6 and PC7 are available for use as input/output lines.

Mode 2 - Strobed Bidirectional Input/Output mode

Only port A can be initialized in this mode. Port A can be used for bidirectional handshake data transfer. This means

that data can be input or output on the same eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for

port A. The remaining pins of port C (PC0 - PC2) can be used as input/output lines if group B is initialized in mode 0 or

as handshaking for port B if group B is initialized in mode 1. In this mode, the 8255 may be used to extend the system

bus to a slave microprocessor or to transfer data bytes to and from a floppy disk controller. Acknowledgement and

handshaking signals are provided to maintain proper data flow and synchronisation between the data transmitter and

receiver.

Q.4 (b) Interface 32Kb RAM memory with 8086 microprocessor.

a) Addressing decoding table

Hex Addr

Binary Address

32kb A 19

A 18

A 17

A 16

A 15

A 14

A 13

A 12

A 11

A 10

A 9

A 8

A 7

A 6

A 5

A 4

A 3

A 2

A 1

A 0

00000H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 07FFFH 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

b) Addressing decoding circuit

c) Interfacing diagram

Q.5 (a) Draw and explain the programmable interval timer/counter 8254 with different operating modes.

Ans: Operation modes:

Mode 0 : Interrupt on Terminal Count

Mode 1 : Hardware Retriggerable One-Shot

Mode 2 : Rate Generator

Mode 3 : Square Wave Mode

Mode 4 : Software Triggered Strobe

Mode 5 : Hardware Triggered Strobe

Use to generate CS Use to connect 16kb memory

Mode 0 (000): Interrupt on terminal count

Mode 0 is used for the generation of accurate time delay under software control. In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counti ng rate is equal to the input clock frequency.

The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT is

programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high unt il the counter is

reloaded or the Control Word is written. The counter wraps around to 0xFFFF internally and continues counting, but

the OUT pin never changes again. The Gate signal should remain active high for normal counting. If Gate goes low,

counting is suspended, and resumes when it goes high again.

The first byte of the new count when loaded in the count register, stops the previous count.

Mode 1 (001): programmable one shot

In this mode 8253/8054 can be used as a Monostable multivibrator. GATE input is used as trigger input.

OUT will be initially high. OUT will go low on the Clock pulse following a trigger to begin the one -shot pulse, and will

remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse afte r the next

trigger.

After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and

setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.

The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one -shot pulse can be

repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count i s written to

the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.

Mode 2 (X10): rate generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.

Like other modes, the counting process will start the next clock cycle after COUNT is sent. OUT will then remain high

until the counter reaches 1, and will go low for one clock pulse. The following cycle, the count is reloaded, OUT goes high again, and the whole process repeats itself.

The time between the high pulses depends on the preset count in the counter's register, and i s calculated using the following formula:

Mode 3 (X11): Square wave generator

This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will

then generate a low pulse for 1 clock cycle (a strobe) – after that the output will become high again.

GATE low suspends the count, which resumes when GATE goes high again.

Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE input.

After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the

GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE.

Q.5 (b) Interface 8255 with 8086 to work as a IO port. Initialize port A as O/P port, port B as I/P port and port C

as O/P port. Port A address should be 0740H. Write a program to sense switch position SW0-SW7

connected at port B. The sense pattern is to be displayed on port A, to which 8 LED’s are connected.

Thus 82H is the control word for the requirements in the problem. The port address can be done as given below.

The 8255 is to be interfaced with lower order data bus, i.e. D0-D7

The A0 and A1 pins of 8255 are connected to A01 and A02 pins of microprocessor respectively.

The A00 pin of the microprocessor is used for selecting lower byte of data bus.

Hence any change in the status of A00 does not affect the port to be selected.

Let us use absolute decoding scheme that uses all the 16 address lines for deriving the device address pulse.

Out of A0-A15 lines, two address lines A02 and A01 are directly required by 8255 for three port and CWR address

decoding.

Hence only A3 to A15 are used for decoding address.

Q.6 (a) Explain the block diagram of 8251 USART and explain each section in brief.

Data Bus buffer

Read/Write Control Logic

Modem Control

Transmitter

Receiver

1. Data Bus Buffer

D0-D7: 8-bit data bus used to read or write status, command word or data from or to the 8251A

2. Read/Write Control logic I

It includes a control logic, six input signals & three buffer registers: Data register, control register & status register.

Control logic: Interfaces the chip with MPU, determines the functions of the chip accordi ng to the control word in the control register & monitors the data flow.

3. Input signal

a) CS – Chip Select: When signal goes low, the 8251A is selected by the MPU for communication.

b) C/D – Control/Data: When signal is high, the control or status register is addressed; when it is low, data buffer is addressed. (Control register & status register are differentiated by WR and RD signals)

c) WR: When signal is low, the MPU either writes in the control register or sends output to the data buffer.

d) RD: When signal goes low, the MPU either reads a status from the status register or accepts data from data buffer.

e) RESET: A high on this signal reset 8252A & forces it into the idle mode.

f) CLK: Clock input, usually connected to the system clock for communication with the microprocessor.

4. Control Register

a) 16-bit register for a control word consist of two independent bytes namely mode word & command word.

b) Mode word: Specifies the general characteristics of operation such as baud, parity, number of bits etc.

c) Command word: Enables the data transmission and reception.

d) Register can be accessed as an output port when the Control/Data pin is high.

Status register

a) Checks the ready status of the peripheral.

b) Status word in the status register provides the information concerning regi ster status and transmission errors.

Data register Used as an input and output port when the C/D is low

CS C/D WR R Operation

0

0

0

0

1

0

0

1

1

×

1

0

0

1

×

0

1

1

0

×

MPU reads data from data buffer

MPU writes data from data buffer

MPU writes a word to control register

MPU reads a word from status register

Chip is not selected for any operation

3. Modem Control

DSR - Data Set Ready: Checks if the Data Set is ready when communicating with a modem.

DTR - Data Terminal Ready: Indicates that the device is ready to accept data when the 8251 is communicating with a modem.

CTS - Clear to Send: If it’s low, the 8251A is enabled to transmit the serial data provided the enable bit in the

command byte is set to ‘1’.

RTS - Request to Send Data: Low signal indicates the modem that the receiver is ready to receive a data byte from the modem.

4. Transmitter section

Accepts parallel data from MPU & converts them into serial data.

Has two registers:

Buffer register: To hold eight bits

Output register: To convert eight bits into a stream of serial bits.

The MPU writes a byte in the buffer register.

Whenever the output register is empty; the contents of buffer register are transferred to output register.

Transmitter section consists of three output & one input signals

TxD - Transmitted Data Output: Output signal to transmit the data to peripherals

TxC - Transmitter Clock Input: Input signal, controls the rate of transmission.

TxRDY - Transmitter Ready: Output signal, indicates the buffer register is empty and the USART is ready to accept the next data byte.

TxE - Transmitter Empty: Output signal to indicate the output register is empty and the USART is ready to accept the

next data byte.

5. Receiver Section

Accepts serial data on the RxD pin and converts them to parallel data.

Has two registers:

Receiver input register

Buffer register

When RxD goes low, the control logic assumes it is a start bit, waits for half bit time, and samples the line again. If the

line is still low, the input register accepts the following data, and loads it into buffer register at the rate determined by the receiver clock.

RxRDY - Receiver Ready Output: Output signal, goes high when the USART has a character in the buffer register & is ready to transfer it to the MPU.

RxD - Receive Data Input : Bits are received serially on this line & converted into a parallel byte in the receiver input

register.

RxC - Receiver Clock Input : Clock signal that controls the rate at which bits are received by the USART.

Q.6 (b) Explain the ICW's and OCW's of 8259. Also explain initialization process of 8259.

The command words of 8259A are classified in two groups

1. Initialization command words (ICW) and

2. Operation command words (OCW).

• Initialization Command Words (ICW): Before it starts functioning, the 8259A must be initialized by writing two to four command words into the respective command word registers. These are called as initialized command words.

If A0 = 0 and D4 = 1, the control word is recognized as ICW1. It contains the control bits for edge/level triggered

mode, single/cascade mode, call address interval and whether ICW4 is required or not.

• If A0=1, the control word is recognized as ICW2. The ICW2 stores details regarding interrupt vector addresses.

The initialisation sequence of 8259A is described in form of a flow chart in fig 3 below.

• The bit functions of the ICW1 and ICW2 are as shown in fig below.

Instruction Command Words ICW1 and ICW2

• T7 – T3 are A3 – A0 of interrupt address

• A10 – A9, A8 – Selected according to interrupt request level.

They are not the address l ines of Microprocessor

• A0 =1 selects ICW2

ICW4: The use of this command word depends on the IC4bit of ICW1. If IC4=1, IC4 is used, otherwise it is neglected.

The bit functions of ICW4 are described as follow:

• SFNM: If BUF = 1, the buffered mode is selected. In the buffered mode, SP/EN acts as enable output and the master/slave is

determined using the M/S bit of ICW

• M/S: If M/S = 1, 8259A is a master. If M/S =0, 8259A is slave. If BUF = 0, M/S is to be neglected.

• AEOI: If AEOI = 1, the automatic end of interrupt mode is selected.

Operation Command Words: Once 8259A is initialized using the previously discussed command words for initialisation, it is

ready for its normal function, i.e. for accepting the interrupts but 8259A has its own way of handling the received interrupts

called as modes of operation. These modes of operations can be selected by programming, i.e. writing three internal registers

called as operation command words.

In the three operation command words OCW1, OCW2 and OCW3 every bit corresponds to some operational feature of the mode

selected, except for a few bits those are either 1 or 0. The three operation command words are shown in fig with the bit selection

details.

• OCW1 is used to mask the masked and if it is 0 the request is enabled. In OCW2 the three bits, R, SL and EOI control the end of

interrupt, the rotate mode and their combinations as shown in fig below.

• The three bits L2, L1 and L0 in OCW2 determine the interrupt level to be selected for operation, if SL bit is active i.e. 1.