Paper Report

Presenter: Jyun-Yan Li

Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors

Antonis Paschalis Department of Informatics & Telecommunications University of Athens, GreeceDimitris Gizopoulos Department of Informatics University of Piraeus, GreeceProceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04)

Citing count: 12

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Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms.

In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components.

Abstract

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After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test.

Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.

Abstract (cont.)

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On-line test divides into concurrent and non-concurrent Concurrent utilizes hardware redundancy techniques

。Large increase silicon area

Non-concurrent is useful for periodic testing

Usually use hardware-based self-test (HBST) for on-line periodic testing Decrease performance, hardware overhead and increase power

consumption for embedded processor

Using software-based self-test (SBST) Generates high fault coverage test program

。Small memory footprint, small execution time and low power consumption

What is the Problem

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Related workSBST

functional structural

randomized[5-7]

Regular deterministic

TPG[9-10]

Test the critical components, like arithmetic & logic, register files

Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded ProcessorsThis

paper:

Targeting processor

components[8-10]

MIPS Plasma[13]

3 stage pipeline with forwarding RISC processor

high abstraction level as Instruction Set Architecture

targeting processorComponents as RTL descriptions

High fault coverage, but large number of instruction

Divide and conquer

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Test program execution time < a quantum time cycle If > quantum time, context switch overheads

Without unresolved data hazards Reduce pipeline stall cycles

Temporal locality for loop, spatial locality for sequentially executed instruction Reduce memory stall cycles

Small data structured in arrays Reduce memory stall cycles

On-line periodic test program characteristics

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Information extraction Identify the component’s inputs and outputs

。Multiplexers Near input and out Identify instruction that carry out specific operation Identify appropriate instruction(s) to control them

SBST MethodologyInformation Extraction

Component Classification & Test Priority(visible, partially, hidden)

Self-Test Routine Development(selection among 3 TPG strategies)

Phase A

Phase B

Phase C

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Visible components (VC) Data VC (D-VC)

。ALU, shifter, register file, data field of pipeline register Address VC (A-VC)

。Instruction fetch unit, memory address register Mixed (address-data) VC (M-VC)

。PC-relative addressing

Partially visible components (PVC) Generate control signal as Processor Control Unit

。implemented as FSM

Hidden components (HC) Increase performance

。Forwarding unit, hazard detection unit

Component classification

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Test priority

Data visible components (D-VC)

Partially visible components (PVC)

Address visible components (A-VC)

Mixed visible components (M-VC)

Test priority

Input: (1) immediate (2) register

(3) data memory

Output: (1) register file (2) data memory (3) data register

Affect the operation of visible components

A lot of memory reference & cache miss overhead

A lot of memory reference & cache miss overhead

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Combinational D-VC, Low gate-level 2 ways:

Immediate addressing In the memory and loop-based routine fetch

Deterministic ATPG based TPG strategy

Under test instruction

Store final result to memory

Immediate addressing Loop-based

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Combinational D-VC, low gate-level Loop-based software LFSR self-test routine

Psedorandom based TPG strategy

Implement software LFSR

Under test instruction

Store final result to memory

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Combinational or sequential D-VC, High-level 2 ways:

Immediate addressing In the memory and loop-based routine fetch

Regular deterministic based TPG strategy

Under testinstruction

Store final result to memory

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Deterministic ATPG based

(immediate)

Deterministic ATPG based (loop)

Psedorandom based

Regular deterministi

c based

application

CombinationalD-VC

Combinational

D-VC with irregular structure

Combinational or

SequentialD-VC

strategy Low gate-level Low gate-level High level

Execution time Small Large Large(*)

Miss rate High I$ Low I$High D$ Low I$ Low I$

feature Number of test patterns is small

acceptable fault

coverage

High fault coverage

Comparing 3 strategy

(*): no describing in the paper

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32 bits, 3 stage pipeline with forwarding MIPS processor 26080 gates by 0.35um Cache miss rate = 5%, miss penalty = 20 clock cycle quantum time cycle = 11000

Experimental result

80 for testing memory controller7 for unloaded to data memory

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3 SBST strategy for on-line periodic testing Deterministic ATPG based Psedorandom based Regular deterministic based

To improve reliability of embedded system My comment

Aim processor component。The programmer have to know the most critical

component How to compact test responses

Conclusion