PAGE 08: CLOCK DISTRIBUTION 1 OF 2 PAGE 15: POWERING · 2012. 11. 6. · PAGE 12: GBE PHY 1/15 LAST_MODIFIED=Tue Apr 26 17:33:29 2011 Project file:glib.cpm PCB by: PV DATE:

PAGE 15: POWERING

PAGE 05: FMC#1PAGE 06: FMC#2PAGE 07: CONFIGURATION

PAGE 02: SRAMSPAGE 03: FPGA PART1PAGE 04: FPGA PART2

PAGE 08: CLOCK DISTRIBUTION 1 OF 2PAGE 09: CLOCK DISTRIBUTION 2 OF 2PAGE 10: FPGA TRANSCEIVERSPAGE 11: BOARD MANAGEMENT

PAGE 13: FPGA DECOUPLING CAPACITORSPAGE 14: MLVDS FOR MTCA.4 + LEVEL TRANSLATORS

PAGE 12: GBE PHY

1/15LAST_MODIFIED=Tue Apr 26 17:33:29 2011

Project file:glib.cpm

PCB by: PV DATE: <DATE>

1/15

SYSTEM: <SYSTEM>

Design by: P.VICHOUDIS

MODULE:glib

EDA-02180-V2-0 PROJECT:GLIB

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1

1211 GENEVA 23SWITZERLAND

Project:Sheet:

Module:European Organizationfor Nuclear Research

4

EN/ICE

--------+-----+-----+-----+-----+-----+-----+----+

FLASH RD| 0 | 1 | 0 | X | 0 | X | 1 |C9-C8 FLASH WR| 0 | 0 | 1 | X | 0 | X | 1 |

--------+-----+-----+-----+-----+-----+-----+----+ACT\SIG: FCS_B FWE_B FOE_B CE1_B CE2 WE_B OE_B

--------+-----+-----+-----+-----+-----+-----+----+

CAPACITORS

CAPACITORS

3. FPGA IO -> CE1_B

1. FCS_B -> CE2

SRAM2 WR| 1 | X | 1 | 0 | 1 | 0 | X |

C4-C3

DECOUPLING

M5-M4

D8-D7D5-D4

M8-M7

N4-N3

SRAMS

N9-N8

PLACEMENT:

D8-D7

C9-C8

DECOUPLING

C4-C3

M8-M7

N4-N3

M5-M4

PLACEMENT:

WHEN THE PLATFORM FLASH IS USEDTHE CE2 GOES LOW, DISABLING THE SRAM2

N9-N8

D5-D4

4. OE_B -> NOT CE2

2. FWE_B -> WE_B

SRAM2 RD| 1 | X | 1 | 0 | 1 | 1 | 0 |

2/15LAST_MODIFIED=Fri May 06 09:48:51 2011



2/15

SYSTEM: <SYSTEM>


MODULE:glib


R27R108

TP10

C194

C195

C196

C199

C200C202

C201

C198

C197

C203

C204

C207

C208C210

C209

C206

C205

R24R23

41

2

IC17H11

B7

R5P7P5

R7

B8

A1P11

B1

P1

R1

N1

C1

C11

N11

M2M1L2L1K2K1J2J1

G2G1F2F1E2E1D2D1

G11G10F11F10E11E10D11D10

M11M10L11L10K11K10J11J10

B6A7

A6B3A3

B4A4A5B5

A8R11R10R9R8R4R3R2

P10P9P8P4P3P2

B10B9B2

A10A9A2P6R6

IC5

H11

B7

R5P7P5

R7

B8

A1P11

B1

P1

R1

N1

C1

C11

N11

M2M1L2L1K2K1J2J1

G2G1F2F1E2E1D2D1

G11G10F11F10E11E10D11D10

M11M10L11L10K11K10J11J10

B6A7

A6B3A3

B4A4A5B5

A8R11R10R9R8R4R3R2

P10P9P8P4P3P2

B10B9B2

A10A9A2P6R6

IC6

SRAM2_A21

SRAM2_CE1_L

SRAM2_MODE

SRAM2_A11

0R00R0SRAM1_MODE

SRAM1_OE_L

SRAM1_A7

VSS=GND;VDD=P2V5;VDDQ=P2V5

SRAM1_A14

SRAM1_TDISRAM1_TDOSRAM1_TMSSRAM1_TCK

VSS=GND;VDD=P2V5;VDDQ=P2V5

10V

VCC=P2V5

74AHC1G00DBV

SRAM1_DQB6

220NF

SRAM1_CE1_L SRAM1_DQD6SRAM1_DQD5

SRAM1_DQD7

SRAM1_A23SRAM1_A24

SRAM1_A13SRAM1_A12SRAM1_A11

SRAM1_A9


SRAM1_A0

SRAM1_DQD3

SRAM1_DQPASRAM1_DQA0SRAM1_DQA1SRAM1_DQA2

SRAM1_DQA4SRAM1_DQA3

SRAM1_DQA5SRAM1_DQA6SRAM1_DQA7

SRAM1_DQB1SRAM1_DQB0SRAM1_DQPB

SRAM1_DQB2SRAM1_DQB3SRAM1_DQB4SRAM1_DQB5

SRAM1_DQB7SRAM1_DQPCSRAM1_DQC0SRAM1_DQC1SRAM1_DQC2SRAM1_DQC3SRAM1_DQC4SRAM1_DQC5

SRAM1_DQC7SRAM1_DQC6

SRAM1_DQPD

SRAM1_A5SRAM1_A6

SRAM1_A8

SRAM1_A10

SRAM1_A22

SRAM1_A4

SRAM1_A15SRAM1_A16SRAM1_A17SRAM1_A18SRAM1_A19SRAM1_A20SRAM1_ADV_LD_LSRAM1_CLK

SRAM1_WE_LSRAM1_CEN_L

SRAM1_A21

SRAM1_DQD2

SRAM1_DQD0SRAM1_DQD1

SRAM1_DQD4

FPBGA

CY7C1470V25-200BZXC

200MHZ

220NF

10V220NF

10V220NF

10V220NF

220NF10V

220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V220NF

10V

3333

200MHZ

SRAM2_CE2

SRAM2_A10SRAM2_A9SRAM2_A8SRAM2_A7

SRAM2_A23

SRAM2_TDOSRAM2_TDI

SRAM2_TMSSRAM2_TCK

FPBGA

CY7C1470V25-200BZXC

SRAM2_DQB6


SRAM2_DQD7

SRAM2_A24

SRAM2_A13SRAM2_A12


SRAM2_A0

SRAM2_DQD3

SRAM2_DQPASRAM2_DQA0SRAM2_DQA1SRAM2_DQA2


SRAM2_DQA5SRAM2_DQA6SRAM2_DQA7

SRAM2_DQB1SRAM2_DQB0SRAM2_DQPB

SRAM2_DQB2SRAM2_DQB3SRAM2_DQB4SRAM2_DQB5

SRAM2_DQB7SRAM2_DQPCSRAM2_DQC0SRAM2_DQC1SRAM2_DQC2SRAM2_DQC3SRAM2_DQC4SRAM2_DQC5


SRAM2_DQPD

SRAM2_A5SRAM2_A6

SRAM2_A22

SRAM2_A4

SRAM2_A14SRAM2_A15SRAM2_A16SRAM2_A17SRAM2_A18SRAM2_A19SRAM2_A20SRAM2_ADV_LD_LSRAM2_CLK

SRAM2_WE_LSRAM2_CEN_L

SRAM2_DQD2


SRAM2_DQD4

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

DQB<6>

MODEZZ

CE1*

CE3*

BWA*

CE2

BWD*

OE*

BWB*BWC*

DQD<6>DQD<5>

DQD<7>

NC/576MNC/1G

A<13>A<12>A<11>

A<9>

TDOTDI

TCKTMS

A<1>A<2>A<3>

A<0>

DQD<3>

DQPADQA<0>DQA<1>DQA<2>

DQA<4>DQA<3>

DQA<5>DQA<6>DQA<7>

DQB<1>DQB<0>

DQPB

DQB<2>DQB<3>DQB<4>DQB<5>

DQB<7>DQPC

DQC<0>DQC<1>DQC<2>DQC<3>DQC<4>DQC<5>

DQC<7>DQC<6>

DQPD

A<5>A<6>A<7>A<8>

A<10>

NC/288M

A<4>

A<14>A<15>A<16>A<17>A<18>A<19>A<20>ADV/LDCLK

WE*CEN*

NC/144M

DQD<2>

DQD<0>DQD<1>

DQD<4>

GND

GND

P2V5

GND GND

P2V5

GND GND

P2V5

P2V5

P2V5

GND

GND

GND

GND

DQB<6>

MODEZZ

CE1*

CE3*

BWA*

CE2

BWD*

OE*

BWB*BWC*

DQD<6>DQD<5>

DQD<7>

NC/576MNC/1G

A<13>A<12>A<11>

A<9>

TDOTDI

TCKTMS

A<1>A<2>A<3>

A<0>

DQD<3>

DQPADQA<0>DQA<1>DQA<2>

DQA<4>DQA<3>

DQA<5>DQA<6>DQA<7>

DQB<1>DQB<0>

DQPB

DQB<2>DQB<3>DQB<4>DQB<5>

DQB<7>DQPC

DQC<0>DQC<1>DQC<2>DQC<3>DQC<4>DQC<5>

DQC<7>DQC<6>

DQPD

A<5>A<6>A<7>A<8>

A<10>

NC/288M

A<4>

A<14>A<15>A<16>A<17>A<18>A<19>A<20>ADV/LDCLK

WE*CEN*

NC/144M

DQD<2>

DQD<0>DQD<1>

DQD<4>

see UG370 p34

33R CLOSE TO IC

SWAP AA34,AA33 BY PAIR ONLYEXCEPT AA34,AA33,AD30,AC30,AE33

FPGA PART1

BANK 22: UNCONDITIONAL SWAP

SWAP BY PAIRDIFF.IMPEDANCE 100R

O.D.R.DIV.

BANK 12:



SWAP _CC PAIRS ONLY BETWEEN THEMNO SWAP V32, V33

SWAP BY PAIR

BANK 15:

SWAP BY PAIRDIFF.IMPEDANCE 100R

DIFF.IMPEDANCE 100RSWAP BY PAIR

AS LONG AS ALL INDIVIDUAL RESTRICTIONS ARE RESPECTED

BANK 14:

BANK 16:

DIFF.IMPEDANCE 100R

BANK 0: NO SWAP

SWAP _CC PAIRS ONLY BETWEEN THEM

SWAP BETWEEN BANKS 13,14,15,16,22,23,25,26,32,33,35 IS ALLOWED 3/15LAST_MODIFIED=Fri May 06 09:48:51 2011



3/15

SYSTEM: <SYSTEM>


MODULE:glib


R100

C112C134

C116

L10

L9

R119

R178

R180

R179

R99

R177

R176

R26R25

R71

R64

R57

R50

R98R92

R70

R63

R60

R53

R94

R101R56

R49

R74

R67

R175R174R93

AN27

AP20

K26

N28

AM27

AP21

K27

N29

AH25

AF19

D34

N32

AJ25

AE19

C34

P32

L28

AN28

AM20

K28

M28

AM28

AL20

J29

L33

AL28

AC20

C33

M32

AK28

AD20

B34

N27

AN29

AN19

G31

P27

AP29

AN20

H30

AL29

AK22

A33

P31

AK29

AJ22

B33

P30

M26

AP30

AP19

F30

M27

AP31

AN18

G30

K32

AG25

AG22

E32

K31

AG26

AH22

E33

AN30

AM18

J26

N25

AM30

AL18

J27

M25

AP25

AP22

J31

P29

AP24

AN23

J32

R29

AK23

AG20

L25

N34

AL24

AG21

L26

P34

AN25

AM22

G32

M30

AN24

AN22

H32

N30

K34

AM25

AK21

K33

L34

AL25

AJ21

J34

R26

AP27

AM23

D31

T26

AP26

AL23

D32

AJ24

AC19

H34

R31

AK24

AD19

H33

R32

R28

AL26

AM21

J30

R27

AM26

AL21

K29

AK26

AJ20

E34

P25

AJ26

AH20

F34

P26

AH23

AF20

F31

L29

AH24

AF21

E31

L30

AK27

AK19

F33

N33

AJ27

AL19

G33

M33

AH27

AE21

C32

M31

AH28

AD21

B32

L31

IC2

V18

U17

U18

V17

Y8

N8

AF8

AC8

AD8

AE8

G8

L8

V8W8

U8

V30

AD30

AG27W30

AC30

AG28

U31

AE34

AN33U30

AF34

AN34

U28

AA28

AH29V29

AA29

AH30

U33

AA25

AL34U32

Y26

AK34

U26

AE31

AF28U27

AD31

AF29

T33

AC33

AJ34T34

AB33

AH34

T30

AB30

AE28T31

AB31

AE29

R33

AD34

AH33R34

AC34

AH32

T28

AA30

AE27T29

AA31

AD27

W27

AB25

AL30W26

AC25

AM31

W25

AG31

AP32V25

AF31

AP33

Y28

AA26

AN32Y27

AB26

AM32

W31

AG33

AM33W32

AG32

AL33

W29

AB27

AL31Y29

AC27

AK31

Y33

AD32

AK33Y34

AE32

AK32

Y32

AB28

AJ29Y31

AC28

AJ30

V32

AB32

AJ31V33

AC32

AJ32

V28

AD29

AF26V27

AC29

AE26

V34

AE33

AF30W34

AF33

AG30

U25

AA34

AD25T25

AA33

AD26

P8

M8

W18W17

AA8

R8

H8

F8

K8

T17T18

IC2

BLM15HD601SN1

1.0UF

BLM15HD601SN1 FPGA_M0MONVCC

0R0

FPGA_TMSFPGA_TCKFPGA_TDO

SFP2_TXFAULTSFP3_MOD_ABSSFP2_RXLOS

V6_CPLD_4V6_CPLD_5

FPGA_TDI

10NF

MONGND

10NF

FPGA_DXPFPGA_DXN

VN

VP

FPGA_CCLK33

0603

4.7K

FPGA_INIT_B FMC1_HB20_P

V6_TO_TRANSLATOR_11V6_TO_TRANSLATOR_8

FMC1_HB20_N

TRANSLATOR_TO_V6_4V6_TO_TRANSLATOR_10V6_TO_TRANSLATOR_4


V6_TO_TRANSLATOR_13


TRANSLATOR_TO_V6_5V6_TO_TRANSLATOR_15V6_TO_TRANSLATOR_12TRANSLATOR_TO_V6_7TRANSLATOR_TO_V6_6V6_TO_TRANSLATOR_14

FPGA_RESET_BPOWER_ON_RESET_B

TRANSLATOR_TO_V6_2V6_TO_TRANSLATOR_3V6_TO_TRANSLATOR_0TRANSLATOR_TO_V6_0

TRANSLATOR_TO_V6_3V6_TO_TRANSLATOR_2

TRANSLATOR_TO_V6_1V6_TO_TRANSLATOR_5

V6_CPLD_0

V6_CPLD_2V6_CPLD_1

V6_CPLD_3

FMC1_HA14_PFMC1_HA14_NFMC1_LA08_PFMC1_LA08_NFMC1_LA21_PFMC1_LA21_NFMC1_LA31_P

FMC1_LA25_PFMC1_LA31_N

FMC1_LA25_NFMC1_HA05_PFMC1_HA05_N

FMC1_LA24_NFMC1_LA24_P

FMC1_LA33_PFMC1_LA33_NFMC1_LA30_P

FMC1_LA00_P_CCFMC1_LA30_N

FMC1_LA00_N_CCFMC1_LA17_P_CCFMC1_LA17_N_CC

FMC1_HA00_N_CCFMC1_HA00_P_CC

VRN_14VRP_14

FMC1_LA07_PFMC1_LA07_NFMC1_HB21_PFMC1_HB21_N


FMC1_LA29_PFMC1_LA29_NFMC1_LA26_PFMC1_LA26_NFMC1_LA16_PFMC1_LA16_NFMC1_HA03_PFMC1_HA03_N

FPGA_DONEFPGA_M1FPGA_M2

FPGA_PROGRAM_B

FMC1_HB03_PFMC1_HB03_NFMC1_HB13_PFMC1_HB13_NFMC1_HB15_PFMC1_HB15_NFMC1_HB02_P

FMC1_HB14_PFMC1_HB02_N

FMC1_HB14_NFMC1_HB05_PFMC1_HB05_NFMC1_HB04_PFMC1_HB04_NFMC1_HB08_PFMC1_HB08_NFMC1_HB06_P_CC

FMC1_HB00_P_CCFMC1_HB06_N_CC

FMC1_HB00_N_CCFMC1_HB17_P_CCFMC1_HB17_N_CCFMC1_HB01_PFMC1_HB01_NFMC1_HB12_PFMC1_HB12_NFMC1_HB16_PFMC1_HB16_NFMC1_HB18_PFMC1_HB18_N

FMC1_HB10_NFMC1_HB10_P

FMC1_HB07_PFMC1_HB07_NFMC1_HB09_PFMC1_HB09_NFMC1_HB19_PFMC1_HB19_NFMC1_HB11_PFMC1_HB11_N

BGA

XC6VLX130T-1FFG1156CES

10K

FMC1_HA02_NFMC1_HA08_PFMC1_HA08_NFMC1_HA07_P

FMC1_LA28_P

FMC1_LA03_P

FMC1_HA17_P_CC

FMC1_LA10_P

49.949.9

FMC1_HA01_P_CCFMC1_LA18_N_CC

FMC1_HA01_N_CC

FMC1_HA15_NFMC1_LA04_P

FMC1_HA15_P

FMC1_LA04_N

FMC1_LA28_N

FMC1_HA09_PFMC1_HA09_N


FMC1_CLK1_C2M_PFMC1_CLK1_C2M_N

FMC1_HA21_NFMC1_HA12_P

FMC1_LA19_NFPGA_CLKOUT

FMC1_HA20_NFMC1_HA16_PFMC1_HA16_N

FMC1_HA20_PFMC1_LA06_N


FMC1_LA15_P

FMC1_VIO_B_M2C 3 2 1 0

VCC0_12<3..0>

4.7K

4.7K

4.7K4.7K

4.7K

4.7K

4.7K

4.7K4.7K

4.7K

4.7K

4.7K

1K33

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

FMC1_HA18_N



FMC1_HA21_P


FMC1_LA03_N

FMC1_HA17_N_CC

FMC1_HA06_P

FMC1_LA02_P

FMC1_HA02_PFMC1_LA02_N


SRAM1_DQC5

SRAM1_DQC7SRAM1_DQD0

SRAM1_DQD1SRAM1_DQC6SRAM1_A11

SRAM1_A6SRAM1_A18

SRAM1_A16SRAM1_A17

SRAM1_DQD2

SRAM1_A10SRAM1_A3

SRAM1_A12

SRAM1_DQPBSRAM1_DQB0

SRAM1_DQA5

SRAM1_DQA7SRAM1_DQB3SRAM1_DQD3

SRAM1_A7

SRAM1_ADV_LD_LSRAM1_A4

SRAM1_DQB5SRAM1_DQB6SRAM1_DQB4SRAM1_DQB2SRAM1_DQB7SRAM1_DQA0SRAM1_DQA6

SRAM1_DQA3

SRAM1_DQA4SRAM1_DQB1

SRAM1_A20SRAM1_A22

SRAM1_DQA2

SRAM1_DQPASRAM1_DQA1

SRAM1_A19

V6_TCLKA_DR_EN

FMC2_PRSNT_M2C_LV6_CDCE_REF_SEL

FMC1_PRSNT_M2C_LV6_ICS874003_OEV6_XPOINT_S10V6_XPOINT_S00SFP4_MOD_ABSSFP4_TXFAULTSFP1_MOD_ABSSFP1_RXLOS

SFP4_RXLOSSFP3_TXFAULT

SFP2_MOD_ABSSFP3_RXLOSSFP1_TXFAULT

FPGA_SCLFPGA_SDA

V6_CDCE_SPI_MOSIV6_CDCE_PWR_DOWNV6_XPOINT_S11

V6_CDCE_SPI_LEV6_ICS874003_MR

V6_CDCE_SPI_CLKV6_ICS874003_FSELV6_XPOINT_S03

V6_TCLKB_DR_ENV6_XPOINT_S02

V6_FMC_XPOINT_S0V6_FMC_XPOINT_S1V6_XPOINT_S12

V6_CDCE_SYNCV6_XPOINT_S01

V6_XPOINT_S13CDCE_PLL_LOCKCDCE_SPI_MISO

FMC1_LA09_P

FMC1_LA10_N

FMC1_HA06_N

FMC1_LA09_N

FMC1_HA07_N




FMC1_LA01_N_CC

FMC1_CLK0_C2M_PFMC1_CLK0_C2M_N

FMC1_LA18_P_CC

FMC1_LA01_P_CC

FMC1_LA19_P

FMC1_LA05_PFMC1_LA05_NFMC1_HA23_PFMC1_HA23_N


BGA


1%1%



FMC1_LA22_NFMC1_LA22_PFMC1_HA19_NFMC1_HA19_P

330E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

P2V5

P2V5

GND

P2V5

P2V5

P2V5

P2V5

P2V5

+ -

BANK 16 BANK 23

BANK 22BANK 15

Sym 2/5

IO_L0P_22IO_L0N_22IO_L1P_22

IO_L2P_22IO_L1N_22

IO_L2N_22IO_L3P_22IO_L3N_22

IO_L4N_VREF_22IO_L4P_22


IO_L7P_22IO_L6N_22

IO_L7N_22IO_L8P_SRCC_22IO_L8N_SRCC_22

IO_L9N_MRCC_22IO_L9P_MRCC_22

IO_L10P_MRCC_22IO_L10N_MRCC_22IO_L11P_SRCC_22IO_L11N_SRCC_22IO_L12P_VRN_22IO_L12N_VRP_22

IO_L13N_22IO_L13P_22

IO_L14P_22IO_L14N_VREF_22

IO_L15P_22IO_L15N_22IO_L16P_22IO_L16N_22IO_L17P_22IO_L17N_22


IO_L19P_22IO_L19N_22

IO_L0P_15

IO_L1P_15IO_L0N_15

IO_L1N_15

IO_L2N_SM8N_15IO_L2P_SM8P_15

IO_L3N_SM9N_15IO_L4P_15

IO_L3P_SM9P_15

IO_L4N_VREF_15IO_L5P_SM10P_15

IO_L6N_SM11N_15



IO_L8P_SRCC_15IO_L8N_SRCC_15IO_L9P_MRCC_15

IO_L10P_MRCC_15IO_L9N_MRCC_15

IO_L10N_MRCC_15IO_L11P_SRCC_15IO_L11N_SRCC_15


IO_L13P_SM14P_15IO_L13N_SM14N_15IO_L14P_15IO_L14N_VREF_15


IO_L16P_VRN_15IO_L16N_VRP_15


IO_L18P_15IO_L18N_15IO_L19P_15IO_L19N_15

IO_L0P_23

IO_L1P_23IO_L0N_23


IO_L3N_23IO_L4P_23

IO_L3P_23

IO_L4N_VREF_23IO_L5P_23IO_L5N_23IO_L6P_23IO_L6N_23IO_L7P_23IO_L7N_23

IO_L8N_SRCC_23IO_L9P_MRCC_23

IO_L8P_SRCC_23

IO_L9N_MRCC_23IO_L10P_MRCC_23IO_L10N_MRCC_23IO_L11P_SRCC_23IO_L11N_SRCC_23

IO_L12N_VRP_23IO_L12P_VRN_23

IO_L13P_23


IO_L15N_23





IO_L19N_23


IO_L2N_16IO_L2P_16

IO_L3N_16IO_L4P_16

IO_L3P_16


IO_L6N_16

IO_L5N_16IO_L6P_16

IO_L7N_16IO_L7P_16

IO_L9P_MRCC_16IO_L8N_SRCC_16IO_L8P_SRCC_16


IO_L12N_VRP_16IO_L12P_VRN_16

IO_L13P_16





IO_L17P_16


IO_L19N_16

VCCO_22[5]VCCO_15[5]


GND

GND

BANK 12

BANK 0Sym 1/5

BANK 14

BANK 13

IO_L0P_13



IO_L4P_13IO_L3N_13

IO_L4N_VREF_13

IO_L5N_13IO_L5P_13


IO_L8P_SRCC_13

IO_L9P_MRCC_13IO_L8N_SRCC_13


IO_L10N_MRCC_13IO_L11P_SRCC_13IO_L11N_SRCC_13IO_L12P_VRN_13

IO_L13P_13IO_L12N_VRP_13


IO_L14N_VREF_13


IO_L16P_13IO_L16N_13IO_L17P_13IO_L17N_13IO_L18P_13IO_L18N_13IO_L19P_13IO_L19N_13

VCCO_13[5]

IO_L0P_14IO_L0N_14IO_L1P_14IO_L1N_14IO_L2P_14IO_L2N_14IO_L3P_14

IO_L4P_14IO_L3N_14

IO_L4N_VREF_14IO_L5P_14IO_L5N_14

IO_L6N_14IO_L6P_14

IO_L7P_14IO_L7N_14

IO_L8P_SRCC_14


IO_L9N_MRCC_14IO_L10P_MRCC_14IO_L10N_MRCC_14

IO_L11N_SRCC_14IO_L11P_SRCC_14



IO_L14N_VREF_14



VCCO_14[4]

IO_L19N_14

INIT_B_0DONE_0M1_0M2_0HSWAPEN_0PROGRAM_B_0M0_0AVSS_0AVDD_0

VREFP_0VP_0

VN_0VREFN_0DXP_0DXN_0VBATT_0DIN_0RDWR_B_0CSI_B_0

CCLK_0DOUT_BUSY_0

TDO_0TCK_0TMS_0TDI_0VFS_0

VCCO_0[2]


IO_L4P_12IO_L3N_12

IO_L4N_VREF_12IO_L5P_12IO_L5N_12IO_L6P_12IO_L6N_12IO_L7P_12IO_L7N_12IO_L8P_SRCC_12


IO_L9N_MRCC_12IO_L10P_MRCC_12IO_L10N_MRCC_12IO_L11P_SRCC_12IO_L11N_SRCC_12IO_L12P_VRN_12IO_L12N_VRP_12IO_L13P_12IO_L13N_12IO_L14P_12IO_L14N_VREF_12



VCCO_12[4]

IO_L19N_12

P2V5

GND

P2V5P2V5

GND

GND

P2V5

GND

P2V5

33R CLOSE TO IC

FA20FA21

DIFF.IMPEDANCE 100RSWAP BY PAIR

BANK 25:

SWAP BETWEEN BANKS 13,14,15,16,22,23,25,26,32,33,35 IS ALLOWED

SWAP _CC PAIRS ONLY BETWEEN THEMSWAP BY PAIRDIFF.IMPEDANCE 100R

FWE_B

FD2

FA3

FA22

FA19

FD1FD0FCS_BFOE_B

EXCEPT AC15

NO SWAP

FD4

FD6

FD8

FD12FD13FD14FD15

FA4FA5FA6FA7FA8FA9FA10FA11FA12FA13FA14FA15

BANK 36:

BANK 24:

FA16FA17FA18

FA0FA1FA2

BANK 34: NO SWAP

FD3

33R CLOSE TO ICFPGA PART2

AS LONG AS ALL INDIVIDUAL RESTRICTIONS ARE RESPECTED

UNCONDITIONAL SWAPBANK 26:

FD7

FD5

L18P_24

BANK 33: BANK 35:DIFF.IMPEDANCE 100RSWAP BY PAIR DIFF.IMPEDANCE 100RSWAP _CC PAIRS ONLY BETWEEN THEM

FD9FD10FD11

BANK 26:DIFF.IMPEDANCE 100RSWAP BY PAIR SWAP _CC PAIRS ONLY BETWEEN THEM

SWAP BY PAIR

EXCEPT H28,H29,B31,A31




4/15

SYSTEM: <SYSTEM>


MODULE:glib


R211

R212

R103R104

R105R107

R102R84 AC15

B20

C28

J25

AD15

C19

B28

J24

AH17

F19

D24

T24

AG17

F20

E24

T23

H25

AP16

A20

B27

H24

AP15

A21

C27

R24

AJ17

E22

G26

P24

AJ16

E23

G27

H23

AN15

B21

B26

G23

AM15

B22

A26

N23

AG16

J20

D27

N24

AF16

J21

E27

F24

AL15

B23

B25

F23

AL14

C23

A25

M23

AJ15

G21

E26

L24

AH15

G22

F26

K24

AK14

A23

C24

K23

AJ14

A24

C25

B31 AL16

C22AC22

A31 AK16

D22AD22

H28 AE18

L20AC23

H29 AF18

L21AC24

AE23

AK18

B18

C30

AE22

AK17

C18

D30

E29

AA23

AD17

K21

F29

AB23

AE17

K22

AF23

AM17

A18

A30

AG23

AM16

A19

B30

Y24

AJ19

H22

F28

AA24

AH19

J22

E28

AF25

AN17

E19

A28

AF24

AP17

D19

A29

AH18

D21V24

H27AG18

E21W24

G28

AC18

H19

F25

AD24

AC17

H20

G25

AE24

AE16

F21

C29

U23

AD16

G20

D29

V23

L23

AG15

C20

D25

M22

AF15

D20

D26

IC2

K16

L13

L10

AC13

L16

M13

M10

AC12

G18

K14

L9

AJ10

H18

J14

K9

AH10

B12

B8 M18

AL11B13

C8 M17

AM11

H10

E8 K19

AG11G10

E9 J19

AG10

F14

A9 C17

AM10E14

A8 B17

AL10

C9 L19

G12AF11

D9 L18

H13AE11

A13

C10 H17

AK12A14

D10 G17

AJ12

G11

F9 K18

AD14F11

F10 K17

AC14

A10 E18

D14AJ11

B10 D17

C14AK11

AN10

D11

D15

AP14

AP10

E11

C15

AN14

K13

AG8 H15

AH13K12

AH8 J15

AH14

AN9 M16

D12AK13

AP9 M15

E12AL13

K11

AF9 G15

AG12L11

AF10 F15

AH12

E13

AK9 A15

AN13F13

AL9 B15

AM13

AD9 J17

J11AE14

AE9 J16

J10AF14

A11

AK8 E16

AM12B11

AL8 D16

AN12

F16

AF13 H12

AD10G16

AG13 J12

AC9

A16

C13

AH9

AP11

B16

C12

AJ9

AP12

L15

M12

AC10

AD12

L14

M11

AB10

AD11

J9 F18

G13AE13

H9 E17

H14AE12

IC2

4.7K

4.7K



FMC2_LA12_NFMC2_LA12_PFMC2_HA17_N_CCFMC2_HA17_P_CCFMC2_LA17_N_CCFMC2_LA17_P_CC

FMC2_LA29_N

FMC2_LA15_N





FMC2_HB08_N

FMC2_HB10_P

FMC2_HB03_N

FMC2_HB02_P



FMC2_HB17_N_CCFMC2_HB17_P_CCFMC2_HB06_N_CC

FMC2_HB02_N

FMC2_HB04_NFMC2_HB00_P_CCFMC2_HB00_N_CCFMC2_HB06_P_CC


FMC2_HB04_P

FMC2_HB16_N

FMC2_HB18_P


VCC0_36<3..0>




FMC2_HB21_NFMC2_LA32_PFMC2_LA32_NFMC2_HA12_PFMC2_HA12_NFMCX_CLK0_M2C_COPY2_PFMCX_CLK0_M2C_COPY2_N


FMC2_LA13_NFMC2_LA13_PFMC2_LA14_NFMC2_LA14_PFMC2_HA02_N


FMC2_HA19_P

SRAM2_A7

FPGA_RS0FPGA_RS1

SRAM2_WE_L

FMC2_LA19_N

VRP_34VRN_34

SRAM2_A16

SRAM2_A18SRAM2_A17


SRAM2_DQD6SRAM2_A0

SRAM2_A2SRAM2_A1

SRAM2_A3SRAM2_DQD7

SRAM2_ADV_LD_L

SRAM2_CEN_LSRAM2_MODE

SRAM2_DQPBSRAM2_DQPASRAM2_A4SRAM2_A5SRAM2_A6


SRAM2_A12SRAM2_A11


MCLK_0_PMCLK_0_N

XPOINT_CLK3_NXPOINT_CLK3_P

FMC2_HA20_P


FMC2_HA11_N


AMC_P2_RX_PAMC_P2_TX_NAMC_P2_TX_P

AMC_P3_TX_PAMC_P2_RX_N

AMC_P3_TX_NAMC_P3_RX_PAMC_P3_RX_N

AMC_P12_RX_P

AMC_P12_TX_PAMC_P12_TX_N

AMC_P12_RX_NAMC_P13_TX_P

AMC_P13_RX_PAMC_P13_TX_N

AMC_P13_RX_NAMC_P14_TX_PAMC_P14_TX_N

AMC_P15_TX_P

AMC_P14_RX_PAMC_P14_RX_N

AMC_P15_TX_NAMC_P15_RX_PAMC_P15_RX_N

FMC2_LA24_N



FMC2_HB21_P

FMC1_CLK1_M2C_N

FMC2_HB18_N

MGT_REFCLK_COPY_1_NSRAM2_DQB7SRAM2_DQB6SRAM2_DQB5


SRAM2_DQD2SRAM2_CE1_L

FMC2_LA06_NFMC2_HA13_P


FMC2_HA13_N


SRAM2_DQB0

SRAM2_DQA5


FMC2_HA01_P_CCFMC2_HA00_N_CC

FMC2_VIO_B_M2C

49.949.9

49.949.9

3333 SRAM1_CLKSRAM2_CLKFMC1_LA23_N

FMC2_LA07_NFMC2_LA07_PFMC2_HA09_N

FMC2_LA10_N

SRAM2_DQPCSRAM2_DQPDSRAM2_DQD4SRAM2_DQD3

SRAM1_DQPDSRAM1_DQD4

GBE_SDASRAM1_DQC0

GBE_INT_N

SRAM1_DQC4SRAM1_A14

SRAM1_A24

SRAM1_MODESRAM1_A2

SRAM1_A15SRAM1_A21

SRAM1_CE1_LSRAM1_A5

SRAM1_DQD5SRAM1_DQC1SRAM1_OE_LSRAM1_A13

SRAM1_DQC3SRAM1_A9

SRAM1_DQC2

SRAM1_DQD6

SRAM1_A8SRAM1_DQD7

SRAM1_CEN_LSRAM1_WE_L

SRAM1_A0SRAM1_A23

SRAM1_DQPC

GBE_SCLSRAM1_A1

GBE_RESET_N

MGT_REFCLK_COPY_0_PMGT_REFCLK_COPY_0_NMGT_REFCLK_COPY_1_P

SRAM2_DQB4

SRAM2_DQB2

SRAM2_DQA4

SRAM2_DQC5

SRAM2_DQC0SRAM2_DQA3SRAM2_DQA2

SRAM2_CE2SRAM2_OE_L

SRAM2_DQD5VRN_24VRP_24

FMC2_HA03_PFMC2_HA03_NFMC2_HA04_PFMC2_HA04_N

CLK125_0_PFMC2_CLK1_C2M_NFMC2_CLK1_C2M_P

FMC2_CLK1_M2C_PCLK125_0_N

FMC2_CLK1_M2C_N

3 012

FMC2_CLK0_C2M_NFMC2_CLK0_C2M_P

FMC2_HA00_P_CC

FMC1_LA14_N

FMC2_HA01_N_CCFMC1_LA14_P


FMC2_HA09_P


FMC1_LA23_P

FMC2_LA06_P

FMC2_LA05_NFMC2_LA05_PFMC2_HA16_NFMC2_HA16_P



SRAM2_DQC1SRAM2_DQC2SRAM2_DQC3SRAM2_DQC4


SRAM2_DQB1

FMC2_LA24_P


SRAM2_DQB3

FMC2_LA02_P

FMC2_HA15_PFMC2_HA15_NFMC2_HA02_P

FMC2_LA02_N

FMC2_HA19_N

FMC2_LA18_P_CCFMC2_LA18_N_CCFMC2_LA00_P_CC





FMC2_LA10_P

FMC2_HA21_NFMC2_LA28_PFMC2_LA28_NFMC2_LA15_P


BGA

FMC2_LA00_N_CCFMC2_LA01_P_CCFMC2_LA01_N_CC



BGA

FMC2_LA29_P

FMC2_LA19_P

FMC2_HA14_N

FMC2_HA06_PFMC2_HA10_NFMC2_HA10_PFMC2_HA20_N


FMC2_HA14_P

FMC2_HB05_P


FMC2_HA21_P




FMC1_CLK1_M2C_P

FMC2_HB08_P


E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

P2V5

P2V5

P2V5

P2V5 P2V5

P2V5

P2V5

GND

GND

Sym 3/5BANK 26BANK 24

BANK 25 BANK 32


IO_L4P_26IO_L3N_26

IO_L5N_26IO_L5P_26

IO_L4N_VREF_26

IO_L6P_26IO_L6N_26

IO_L7N_26IO_L7P_26

IO_L8P_SRCC_26



IO_L11P_SRCC_26IO_L11N_SRCC_26IO_L12P_VRN_26

IO_L13P_26IO_L12N_VRP_26

IO_L14N_VREF_26IO_L14P_26IO_L13N_26


IO_L16P_26




VCCO_26[5]


IO_L2N_32IO_L2P_32

IO_L3N_32IO_L4P_32

IO_L3P_32


IO_L6N_32

IO_L5N_32IO_L6P_32

IO_L7N_32IO_L7P_32




IO_L12N_VRP_32IO_L13P_32

IO_L12P_VRN_32



IO_L15N_32




VCCO_32[5]

IO_L19N_32

IO_L0P_GC_24IO_L0N_GC_24IO_L1P_GC_24IO_L1N_GC_24IO_L2P_D15_24IO_L2N_D14_24IO_L3P_D13_24

IO_L4P_D11_24IO_L3N_D12_24

IO_L5P_D9_24IO_L5N_D8_24

IO_L4N_VREF_D10_24

IO_L6P_D7_24IO_L6N_D6_24

IO_L7N_D4_24IO_L7P_D5_24

IO_L8P_SRCC_24



IO_L11P_SRCC_24IO_L11N_SRCC_24IO_L12P_D3_24

IO_L13P_D1_FS1_24IO_L12N_D2_FS2_24

IO_L14P_FCS_B_24IO_L14N_VREF_24

IO_L13N_D0_FS0_24

IO_L15N_RS1_24IO_L15P_FWE_B_24

IO_L16N_CSO_B_24IO_L16P_RS0_24

IO_L17P_VRN_24IO_L17N_VRP_24IO_L18P_24


VCCO_24[6]


IO_L2N_25IO_L2P_25



IO_L6N_25

IO_L5N_25IO_L6P_25

IO_L7N_25IO_L7P_25




IO_L12P_25



IO_L15N_25IO_L16P_VRN_25IO_L16N_VRP_25

IO_L18P_GC_25IO_L17N_25IO_L17P_25

IO_L19P_GC_25IO_L18N_GC_25

VCCO_25[4]

IO_L19N_GC_25P2V5


BANK 36BANK 34

IO_L19N_VRP_34IO_L19P_VRN_34IO_L18N_A16_34

IO_L17N_A18_34IO_L18P_A17_34

IO_L17P_A19_34IO_L16N_A20_34IO_L16P_A21_34

IO_L15P_A23_34IO_L15N_A22_34

IO_L14N_VREF_A24_34IO_L14P_A25_34IO_L13N_A00_D16_34

IO_L12N_A02_D18_34IO_L13P_A01_D17_34

IO_L12P_A03_D19_34IO_L11N_SRCC_34IO_L11P_SRCC_34


IO_L9N_MRCC_34IO_L9P_MRCC_34IO_L8N_SRCC_34IO_L8P_SRCC_34IO_L7N_A04_D20_34IO_L7P_A05_D21_34

IO_L6P_A07_D23_34IO_L6N_A06_D22_34

IO_L5N_A08_D24_34IO_L5P_A09_D25_34IO_L4N_VREF_A10_D26_34

IO_L3N_A12_D28_34IO_L4P_A11_D27_34

IO_L3P_A13_D29_34IO_L2N_A14_D30_34IO_L2P_A15_D31_34


IO_L0N_GC_34IO_L0P_GC_34


IO_L2N_33IO_L2P_33

IO_L3P_33

IO_L4P_33IO_L3N_33


IO_L6P_33IO_L5N_33

IO_L6N_33

IO_L7N_33IO_L7P_33




IO_L13P_33





IO_L18P_33



IO_L0N_35IO_L0P_35

IO_L1P_35

IO_L2P_SM0P_35IO_L1N_35

IO_L3N_SM1N_35IO_L3P_SM1P_35IO_L2N_SM0N_35


IO_L5P_SM2P_35IO_L5N_SM2N_35IO_L6P_SM3P_35IO_L6N_SM3N_35IO_L7P_SM4P_35

IO_L8N_SRCC_35IO_L8P_SRCC_35IO_L7N_SM4N_35


IO_L10P_MRCC_35IO_L10N_MRCC_35IO_L11P_SRCC_35

IO_L12N_SM5N_35IO_L12P_SM5P_35IO_L11N_SRCC_35

IO_L13P_SM6P_35IO_L13N_SM6N_35


IO_L15P_SM7P_35IO_L15N_SM7N_35IO_L16P_VRN_35


IO_L16N_VRP_35


IO_L19N_GC_35IO_L19P_GC_35




IO_L15N_36




IO_L11N_SRCC_36IO_L11P_SRCC_36IO_L10N_MRCC_36

IO_L9N_MRCC_36IO_L10P_MRCC_36

IO_L8P_SRCC_36IO_L8N_SRCC_36IO_L9P_MRCC_36

IO_L7N_36IO_L7P_36IO_L6N_36IO_L6P_36IO_L5N_36



IO_L2N_36IO_L2P_36IO_L1N_36IO_L1P_36IO_L0N_36IO_L0P_36


VCCO_35[5\]VCCO_33[5]

P2V5 P

2V5

P2V5

FMC1_GA0

FMC1_VADJ

FMC1_RES1

FMC1_VADJ

FMC1_VREF_B_M2C

FMC1_VADJ

FMC#1

10100 GA1 GA0I2C ADDRESS

FMC1_RES0

IS POWERED BY 3V3AUX

FMC1_GA1

THE I2C EEPROM OF THE FMC

FMC1_VREF_A_M2C

33R CLOSE TO CONNECTOR

FMC1_33P3VAUX

FMC1_VADJ




5/15

SYSTEM: <SYSTEM>


MODULE:glib


K40K39K38K37K36K35K34K33K32K31K30K29K28K27K26K25K24K23K22K21K20K19K18K17K16K15K14K13K12K11K10K9K8K7K6K5K4K3K2K1

J40J39J38J37J36J35J34J33J32J31J30J29J28J27J26J25J24J23J22J21J20J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1

J2

H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1

G40G39G38G37G36G35G34G33G32G31G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9G8G7G6G5G4G3G2G1

J2

F40F39F38F37F36F35F34F33F32F31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1

E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1

J2

D40D39D38D37D36D35D34D33D32D31D30D29D28D27D26D25D24D23D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1

C40C39C38C37C36C35C34C33C32C31C30C29C28C27C26C25C24C23C22C21C20C19C18C17C16C15C14C13C12C11C10C9C8C7C6C5C4C3C2C1

J2

B40B39B38B37B36B35B34B33B32B31B30B29B28B27B26B25B24B23B22B21B20B19B18B17B16B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1

A40A39A38A37A36A35A34A33A32A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1

J2

R8933 FMC1_TDO

FMC1_LA26_N

FMC1_TCK

FMC1_LA26_PGND

FMC1_DP0_C2M_P

FMC1_DP1_C2M_N GND

SEAF-40-06.5-S-10-A

GND

GND

FMC1_TRST_LFMC1_TMS

FMC1_TDI

GND

FMC1_LA23_NFMC1_LA23_PGNDFMC1_LA17_N_CCFMC1_LA17_P_CCGND


GND


FMC1_LA05_P

GNDFMC1_LA05_N

FMC1_LA01_N_CCGND

FMC1_LA01_P_CCGNDGND

GNDGNDFMCX_PG_C2M

GND

GND

GNDGND

GND

MMC_SDA

GNDFMC1_LA27_N

GNDMMC_SCL

FMC1_LA18_N_CCFMC1_LA18_P_CC

FMC1_LA27_P

GNDGND

GND

FMC1_LA14_P

GNDFMC1_LA14_N

GNDGND

GNDGNDFMC1_LA10_PFMC1_LA10_N

FMC1_LA06_N

FMC1_DP0_M2C_N

GNDGND

FMC1_DP0_M2C_PGNDGNDFMC1_DP0_C2M_N

GND

FMC1_LA06_P

FMC1_HB09_P

FMC1_HB13_P

FMC1_HB19_N

FMC1_HB21_PGND

FMC1_HB19_P

P3V3

P3V3

FMC1_CLK0_M2C_N

FMC1_HB11_NGNDFMC1_HB15_P

FMC1_HB18_N

FMC1_CLK0_M2C_PGNDFMC1_PRSNT_M2C_L

GND

FMC1_HA18_P


GNDGND

GNDGND

FMC1_HA00_P_CCGNDGND

SEAF-40-06.5-S-10-A

FMC1_HA16_N

FMC1_HA20_PFMC1_HA20_NGNDFMC1_HB03_P

P3V3


FMC1_CLK1_C2M_NFMC1_CLK1_C2M_P

SEAF-40-06.5-S-10-A

GNDGNDFMC1_HB20_NFMC1_HB20_PFMC1_HB21_NGNDFMC1_HB16_NFMC1_HB16_PGNDFMC1_HB12_NGNDFMC1_HB12_PFMC1_HB13_NGNDFMC1_HB08_NGNDFMC1_HB08_PFMC1_HB09_NGNDFMC1_HB04_NGNDFMC1_HB04_PFMC1_HB05_NGNDFMC1_HB05_PFMC1_HB02_NGNDFMC1_HB02_PFMC1_HB03_NGNDFMC1_HA19_NFMC1_HA19_PGNDFMC1_HA15_NGNDFMC1_HA15_PGNDFMC1_HA16_PFMC1_HA12_NGNDFMC1_HA12_PFMC1_HA13_NGNDFMC1_HA13_PFMC1_HA08_NGNDFMC1_HA08_PFMC1_HA09_NGNDFMC1_HA09_PFMC1_HA04_NGNDFMC1_HA04_PFMC1_HA05_NGNDFMC1_HA05_PFMC1_HA00_N_CCGND

GNDFMC1_HA01_N_CCFMC1_HA01_P_CC

FMC1_PG_M2CGND

GNDGNDFMC1_LA32_NGNDFMC1_LA32_PFMC1_LA33_NGNDFMC1_LA33_PFMC1_LA30_NGNDFMC1_LA30_PFMC1_LA31_NGNDFMC1_LA31_PFMC1_LA28_NGNDFMC1_LA28_PFMC1_LA29_NGNDFMC1_LA29_PFMC1_LA24_NGNDFMC1_LA24_PFMC1_LA25_NGNDFMC1_LA25_PFMC1_LA21_NGNDFMC1_LA21_PFMC1_LA22_NGNDFMC1_LA22_PFMC1_LA19_NGNDFMC1_LA19_PFMC1_LA20_NGNDFMC1_LA20_PFMC1_LA15_NGNDFMC1_LA15_PFMC1_LA16_NGNDFMC1_LA16_PFMC1_LA11_NGNDFMC1_LA11_PFMC1_LA12_NGNDFMC1_LA12_PFMC1_LA07_NGNDFMC1_LA07_PFMC1_LA08_NGNDFMC1_LA08_PFMC1_LA04_NGNDFMC1_LA04_PFMC1_LA03_NGNDFMC1_LA03_PFMC1_LA02_NGNDFMC1_LA02_PFMC1_LA00_N_CCGNDFMC1_LA00_P_CC

GNDGNDFMC1_CLK0_C2M_NFMC1_CLK0_C2M_PGND

SEAF-40-06.5-S-10-A

FMC1_VIO_B_M2CGNDGNDFMC1_VIO_B_M2CFMC1_HB17_N_CCGNDFMC1_HB17_P_CCGNDFMC1_HB18_PFMC1_HB14_NGNDFMC1_HB14_PFMC1_HB15_NGNDFMC1_HB10_NFMC1_HB10_PGNDFMC1_HB11_PFMC1_HB06_N_CCGNDFMC1_HB06_P_CCFMC1_HB07_NGNDFMC1_HB07_PFMC1_HB00_N_CCGNDFMC1_HB00_P_CCFMC1_HB01_NGNDFMC1_HB01_PFMC1_HA23_NGNDFMC1_HA23_PGNDFMC1_HA21_NGNDFMC1_HA21_PFMC1_HA18_NGNDFMC1_HA17_N_CCGNDFMC1_HA17_P_CCFMC1_HA14_NGNDFMC1_HA14_PFMC1_HA10_NGNDFMC1_HA10_PFMC1_HA11_NGNDFMC1_HA11_PFMC1_HA06_NGNDFMC1_HA06_PFMC1_HA07_NGNDFMC1_HA07_PFMC1_HA02_NGNDFMC1_HA02_PGNDFMC1_CLK1_M2C_NGNDFMC1_CLK1_M2C_PGNDGNDGND

GND

SEAF-40-06.5-S-10-A

P3V3

GNDFMC1_DP1_M2C_P GNDFMC1_DP1_M2C_N GNDGNDGNDFMC1_DP2_M2C_P GNDFMC1_DP2_M2C_N GNDGNDGNDFMC1_DP3_M2C_PFMC1_DP3_M2C_NGNDGND

GNDGND

GNDGND

GNDGND

GNDGNDFMC1_DP2_C2M_P GNDFMC1_DP2_C2M_N GNDGNDGNDFMC1_DP3_C2M_P GNDFMC1_DP3_C2M_N GNDGND

GND

GNDGND

GNDGND

P3V3GND

GND

GND

FMC1_DP1_C2M_P

GND

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

K40J40K39J39K38J38K37J37K36J36K35J35K34J34K33J33K32J32K31J31K30J30K29J29K28J28K27J27K26J26K25J25K24J24K23J23K22J22K21J21K20J20K19J19K18J18K17J17K16J16K15J15K14J14K13J13K12J12K11J11K10J10K9J9K8J8K7J7K6J6K5J5K4J4K3J3K2J2K1J1

H40G40H39G39H38G38H37G37H36G36H35G35H34G34H33G33H32G32H31G31H30G30H29G29H28G28H27G27H26G26H25G25H24G24H23G23H22G22H21G21H20G20H19G19H18G18H17G17H16G16H15G15H14G14H13G13H12G12H11G11H10G10H9G9H8G8H7G7H6G6H5G5H4G4H3G3H2G2H1G1

F40E40F39E39F38E38F37E37F36E36F35E35F34E34F33E33F32E32F31E31F30E30F29E29F28E28F27E27F26E26F25E25F24E24F23E23F22E22F21E21F20E20F19E19F18E18F17E17F16E16F15E15F14E14F13E13F12E12F11E11F10E10F9E9F8E8F7E7F6E6F5E5F4E4F3E3F2E2F1E1

D39D40

D37D38

D36D35D34

D32D33

D31D30D29D28D27D26D25D24D23D22D21D20D19

D17D18

D16

D14D15

D11

D13D12

D9D10

D8D7D6D5D4D3D2D1

C40C39

C37C38

C32C33C34

C36C35

C31

C28C27

C29C30

C23C22

C26

C24C25

C21

C18

C20C19

C17C16

C12C13C14C15

C11

C7

C9C8

C6C5C4C3C2C1

C10

B40A40B39A39B38A38B37A37B36A36B35A35B34A34B33A33B32A32B31A31B30A30B29A29B28A28B27A27B26A26B25A25B24A24B23A23B22A22B21A21B20A20B19A19B18A18B17A17B16A16B15A15B14A14B13A13B12A12B11A11B10A10B9A9B8A8B7A7B6A6B5A5B4A4B3A3B2A2B1A1

P2V5

GND

GND

P2V5

P2V5

P2V5

P12V

P12V

FMC2_ADJFMC2_VADJ

FMC2_VREF_B_M2CFMC2_VREF_A_M2C

FMC2_ADJ

FMC2_GA0

FMC2_RES0

FMC2_RES1

IS POWERED BY 3V3AUX

I2C ADDRESS

FMC2_ADJ


FMC#2

10100 GA1 GA0

THE I2C EEPROM OF THE FMC

FMC2_GA1

FMC2_3P3VAUX




6/15

SYSTEM: <SYSTEM>


MODULE:glib


FMC2_LA05_N

C15C16C17

D25D26

FMC2_TCKFMC2_TDI

R91

D28

D24D23

GND

GND

C18

FMC2_LA26_PFMC2_LA26_NGND

FMC2_TMSFMC2_TRST_L

H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21H20H19H18H17H16H15H14H13H12H11H10H9H8H7H6H5H4H3H2H1

G40G39G38G37G36G35G34G33G32G31G30G29G28G27G26G25G24G23G22G21G20G19G18G17G16G15G14G13G12G11G10G9G8G7G6G5G4G3G2G1

J1

K40K39K38K37K36K35K34K33K32K31K30K29K28K27K26K25K24K23K22K21K20K19K18K17K16K15K14K13K12K11K10K9K8K7K6K5K4K3K2K1

J40J39J38J37J36J35J34J33J32J31J30J29J28J27J26J25J24J23J22J21J20J19J18J17J16J15J14J13J12J11J10J9J8J7J6J5J4J3J2J1

J1

F40F39F38F37F36F35F34F33F32F31F30F29F28F27F26F25F24F23F22F21F20F19F18F17F16F15F14F13F12F11F10F9F8F7F6F5F4F3F2F1

E40E39E38E37E36E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1

J1

D40D39D38D37D36D35D34D33D32D31D30D29

D27

D22D21D20D19D18D17D16D15D14D13D12D11D10D9D8D7D6D5D4D3D2D1

C40C39C38C37C36C35C34C33C32C31C30C29C28C27C26C25C24C23C22C21C20C19

C14C13C12C11C10C9C8C7C6C5C4C3C2C1

J1

B40B39B38B37B36B35B34B33B32B31B30B29B28B27B26B25B24B23B22B21B20B19B18B17B16B15B14B13B12B11B10B9B8B7B6B5B4B3B2B1

A40A39A38A37A36A35A34A33A32A31A30A29A28A27A26A25A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1

J1

GND

FMC2_DP0_C2M_N

GND

FMC2_LA25_N

FMC2_LA11_NFMC2_HA18_PFMC2_HA18_N

FMC2_HB02_N


FMC2_HB05_P

FMC2_LA17_P_CCFMC2_LA17_N_CC

FMC2_TDOP3V3


FMC2_HA14_NGND


FMC2_LA15_P

FMC2_DP0_M2C_N

SEAF-40-06.5-S-10-A

GND


GND

GND

GNDFMC2_LA23_NFMC2_LA23_P

GND


GND


FMC2_LA05_P

GND

FMC2_LA01_N_CCGND

FMC2_LA01_P_CCGNDGND

GNDGNDFMCX_PG_C2M

GND

GND

GNDGND

GND

FPGA_SDA

GNDFMC2_LA27_N

FPGA_SCL

FMC2_LA18_N_CCFMC2_LA18_P_CC

FMC2_LA27_P

GNDGND

GND

FMC2_LA14_P

GNDFMC2_LA14_N

GNDGND

GNDFMC2_LA06_N

GNDGND

FMC2_DP0_M2C_PGND

FMC2_DP0_C2M_PGND

FMC2_LA06_P

P3V3

GNDFMC2_CLK1_C2M_PFMC2_CLK1_C2M_N



GND

FMC2_HB05_NGNDFMC2_HB09_PFMC2_HB09_NGNDFMC2_HB13_P

GND

P3V3

SEAF-40-06.5-S-10-A

GND

GNDGND

GNDGND

SEAF-40-06.5-S-10-A

GND

FMC2_HB07_N

FMC2_HB11_N

FMC2_VIO_B_M2C

GND

SEAF-40-06.5-S-10-A

GNDGNDGND

GNDGND

GNDGND

GND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GNDGND

GND

GND

GNDGNDFMC2_HB20_NGNDFMC2_HB20_PFMC2_HB21_NGNDFMC2_HB21_PFMC2_HB16_NGNDFMC2_HB16_PFMC2_HB19_NGNDFMC2_HB19_PFMC2_HB12_NFMC2_HB12_PFMC2_HB13_NGNDFMC2_HB08_NFMC2_HB08_PGND

GND

FMC2_HB02_PFMC2_HB03_NGNDFMC2_HB03_PFMC2_HA19_NGNDFMC2_HA19_PFMC2_HA20_NGNDFMC2_HA20_PFMC2_HA15_NGNDFMC2_HA15_PFMC2_HA16_NGNDFMC2_HA16_PFMC2_HA12_NGNDFMC2_HA12_PFMC2_HA13_NGNDFMC2_HA13_PFMC2_HA08_NGNDFMC2_HA08_PFMC2_HA09_NGNDFMC2_HA09_PFMC2_HA04_NGNDFMC2_HA04_PFMC2_HA05_NGNDFMC2_HA05_PFMC2_HA00_N_CCGNDFMC2_HA00_P_CCGNDGNDFMC2_HA01_N_CCGNDFMC2_HA01_P_CCFMC2_PG_M2CGND

FMC2_VIO_B_M2CGNDGNDFMC2_HB17_N_CCGNDFMC2_HB17_P_CCFMC2_HB18_NGNDFMC2_HB18_PFMC2_HB14_NGNDFMC2_HB14_PFMC2_HB15_NGNDFMC2_HB15_PFMC2_HB10_NGNDFMC2_HB10_PGNDFMC2_HB11_PFMC2_HB06_N_CCGNDFMC2_HB06_P_CCGNDFMC2_HB07_PFMC2_HB00_N_CCGNDFMC2_HB00_P_CCFMC2_HB01_NGNDFMC2_HB01_PFMC2_HA23_NGNDFMC2_HA23_PGNDFMC2_HA21_NGNDFMC2_HA21_PGNDFMC2_HA17_N_CCFMC2_HA17_P_CCGNDFMC2_HA14_PFMC2_HA10_NGNDFMC2_HA10_PGNDFMC2_HA06_NGNDFMC2_HA06_PGNDFMC2_HA02_NGNDFMC2_HA02_PGNDFMC2_CLK1_M2C_NGNDFMC2_CLK1_M2C_PGNDGNDGND

GNDGNDFMC2_LA32_NGNDFMC2_LA32_PFMC2_LA33_NGNDFMC2_LA33_PFMC2_LA30_NGNDFMC2_LA30_PFMC2_LA31_NGNDFMC2_LA31_PFMC2_LA28_NGNDFMC2_LA28_PFMC2_LA29_N

FMC2_LA29_PFMC2_LA24_NGNDFMC2_LA24_PGNDFMC2_LA25_PFMC2_LA21_NGNDFMC2_LA21_PFMC2_LA22_NGNDFMC2_LA22_PFMC2_LA19_NGNDFMC2_LA19_PFMC2_LA20_NGNDFMC2_LA20_PFMC2_LA15_NGND

FMC2_LA16_NGNDFMC2_LA16_P

GNDFMC2_LA11_PFMC2_LA12_NGNDFMC2_LA12_PFMC2_LA07_NGNDFMC2_LA07_PFMC2_LA08_NGNDFMC2_LA08_PFMC2_LA04_NGNDFMC2_LA04_PFMC2_LA03_NGNDFMC2_LA03_PFMC2_LA02_NGNDFMC2_LA02_PFMC2_LA00_N_CC

FMC2_LA00_P_CCFMC2_CLK0_M2C_NGNDFMC2_CLK0_M2C_PGNDGNDFMC2_CLK0_C2M_NFMC2_PRSNT_M2C_LFMC2_CLK0_C2M_P

GND

SEAF-40-06.5-S-10-A

P3V3

33

P3V3P3V3

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

H40G40H39G39H38G38H37G37H36G36H35G35H34G34H33G33H32G32H31G31H30G30H29G29H28G28H27G27H26G26H25G25H24G24H23G23H22G22H21G21H20G20H19G19H18G18H17G17H16G16H15G15H14G14H13G13H12G12H11G11H10G10H9G9H8G8H7G7H6G6H5G5H4G4H3G3H2G2H1G1

K40J40K39J39K38J38K37J37K36J36K35J35K34J34K33J33K32J32K31J31K30J30K29J29K28J28K27J27K26J26K25J25K24J24K23J23K22J22K21J21K20J20K19J19K18J18K17J17K16J16K15J15K14J14K13J13K12J12K11J11K10J10K9J9K8J8K7J7K6J6K5J5K4J4K3J3K2J2K1J1

F40E40F39E39F38E38F37E37F36E36F35E35F34E34F33E33F32E32F31E31F30E30F29E29F28E28F27E27F26E26F25E25F24E24F23E23F22E22F21E21F20E20F19E19F18E18F17E17F16E16F15E15F14E14F13E13F12E12F11E11F10E10F9E9F8E8F7E7F6E6F5E5F4E4F3E3F2E2F1E1

D39D40

D37D38

D36D35D34

D32D33

D31D30D29D28D27D26D25D24D23D22D21D20D19

D17D18

D16

D14D15

D11

D13D12

D9D10

D8D7D6D5D4D3D2D1

C40C39

C37C38

C32C33C34

C36C35

C31

C28C27

C29C30

C23C22

C26

C24C25

C21

C18

C20C19

C17C16

C12C13C14C15

C11

C7

C9C8

C6C5C4C3C2C1

C10

B40A40B39A39B38A38B37A37B36A36B35A35B34A34B33A33B32A32B31A31B30A30B29A29B28A28B27A27B26A26B25A25B24A24B23A23B22A22B21A21B20A20B19A19B18A18B17A17B16A16B15A15B14A14B13A13B12A12B11A11B10A10B9A9B8A8B7A7B6A6B5A5B4A4B3A3B2A2B1A1

P2V5

P2V5

P2V5

P2V5

P12V

P12V

G4-H4

R121 R122 R123 are not mounted

R113 R114 are not mounted

R124 R125 are not mounted

BPI-UP CONFIGURATION MODE

PULL-UP/DOWN RESISTORS ARE USED LINES DRIVENJTAG DRIVER PINS HAVE 33R IN SERIES

NO PULL-UPSSLAVE

LEDS EG L29K G2J1

DECOUPLING

H3-H6

MMC RELOAD FPGAS IS OPEN DRAIN

PGOOD ARE OPEN DRAIN

WHEN FMC PRESENT, PRSNT_M2C -> LOW

- CPLD JTAG HEADER

- JTAG FSM DRIVEN BY V6

- MMC JTAG

JTAG "SLAVES" ARE:

I/O BANK2: ALL SWAPPABLE

CAPACITORS

MASTERPULL-UPS

I/O BANK1: ALL SWAPPABLE EXCEPT PIN22

"FOE"

PLACEMENT:

CONFIGURATIONB2-A6

- AMC JTAG

- JTAG HEADER FOR V6 & MMC

33R CLOSE TO IC

JTAG "MASTERS" ARE:

BY PLUGGABLE JTAG DEVICES

JTAG SCHEME

CLPD AS "SLAVE" : DRIVES "MASTER"DEVICE'S TDI

"FWE""FCS"

FOR PLATFORM FLASH XL WITH

UG438, PAGE34, FIGURE 3-2

"L18P24"

- V6, FMCS, SRAMS, GBE

INDIRECT PROGRAMMINS SUPPORT

M[2:0]=010




7/15

SYSTEM: <SYSTEM>


MODULE:glib


R123R122R121

R113R114

ST2

ST3

ST1

R97

R95

R96

TP9

C218

C225

C219

C223

C224

C222

C220

C221

R130

R152

R131R129

R128R132R137R136R135R134R133R138R139

R140

R143

R144R145

R146

R147

R148R150R149R151

R154

R153

R21

R22R20R19

R18R17

R142R141

R156R155R157R158

R160R162R161

R159

R15R14

R16

5

4783

4548

49505253

4142434446

81807978

8987868582

77

5859606163

545556

64

70686766

7674737271

65

33323029

403937363534

28

959697

9091929394

2199

1817161514

19

27

2322

24

9101112

678

13

43

IC3

C215

C213C214

R118

TP11

2468

1357

SW3

R77

R78

R79

R80

R120R116R117R111R115R112

2468

1357

SW2

R10

R11

R12

R13

R214

R82

R215

R213

R83

R81

R125R124

14 1312 1110 98 76 54 32 1

J12

14 1312 1110 98 76 54 32 1

J13

G2

G8

H4

A4

G4

D4

B8

H1F1

F8B4

E7G7H5F5F4F3E3E1H7G6G5E5E4G3E2F2

G1A8C8C7B7A7D8D7C5B5A5C4D3C3B3A3C2A2D2D1C1B1A1

IC4

10V220NF

4.7K

FPGA_TCK 33FPGA_TMS 33

FPGA_TDI 33

GBE_TCK 33

GBE_TRST_B 33

GBE_TDI 33GBE_TMS 33

PGOOD_2V510K

0R0

SRAM2_A13SRAM2_A12SRAM2_A11SRAM2_A10SRAM2_A9SRAM2_A8SRAM2_A7SRAM2_A6SRAM2_A5SRAM2_A4SRAM2_A3SRAM2_A2SRAM2_A1SRAM2_A0

SRAM2_WE_LSRAM2_CE2SRAM2_OE_LFPGA_PROGRAM_B

FPGA_CCLK

0R00R00R0

0R0

XCF128XFTG64C

SRAM2_DQA5

100100

4.7K4.7K

4.7K4.7K4.7K


SRAM2_TCK

33

FMC2_TMS

33

MMC_PG410K

MMC_PE6

10K

MMC_TDOJTAG_HEADER_TMS

FMCX_PG_C2MFMC1_PG_M2C

FMC2_TCKFMC2_TDIFMC1_TMSFMC1_TDIFMC1_TCK

FMC2_TRST_L

FMC1_TRST_LFMC1_TDO 10K

33

SRAM1_TMS

RTM_3.3V_ENRTM_I2C_EN

JTAG_HEADER_TDIJTAG_HEADER_TDOJTAG_HEADER_TCK

FMC2_PG_M2CFMC2_TDO

SRAM2_DQA0SRAM2_DQA1SRAM2_DQA2SRAM2_DQA3SRAM2_DQA4

SRAM2_DQB4SRAM2_DQB5

JTAG_HEADER_TDOJTAG_HEADER_TDIJTAG_HEADER_TCK

3301/16W

FPGA_INIT_B

220NF

FPGA_M0

SRAM2_TDOSRAM2_TMSSRAM2_TDISRAM1_TCKSRAM1_TDO

SRAM1_TDIFPGA_DONEFPGA_INIT_BFPGA_PROGRAM_B

FPGA_RS1FPGA_RS0

10K

4.7K

4.7K

FPGA_M1

FPGA_M2

MMC_FPGA_2_INIT_DONE

RTM_12V_EN

RTM_PS


AMC_TRST_BAMC_TDO

MMC_RESET_FPGA_NMMC_RELOAD_FPGAS_N

MMC_LOW_VOLTAGE_POK

FMC2_PRSNT_M2C_L

CPLD_HEADER_TCK

220NF

220NF

SFPX_RS0SFPX_RS1SFPX_TXDIS

10K

10K

10V

333333

33

4.7K

P3V3

SW1SW2

SW4SW3

FTG64C

AMC_TDI

MMC_TDI

CPLD_HEADER_TDI

SW1SW2SW3

SW4

MMC_TMS

MMC_TCK

AMC_TCKAMC_TMS

GBE_TDOFPGA_TDO

V6_CPLD_4

FPGA_RESET_B

V6_CPLD_2V6_CPLD_1

CPLD_HEADER_TMSCPLD_HEADER_TDO

PGOOD_1V0

10K

10K

10K

10K

10K

10K

1%

10K

10K

3310K10K10K10K

10K

10K

10K

33

33

10K10K

33

33

10K

10K

10K

220NF10V

10V

220NF

220NF

220NF

220NF

220NF

220NF

10V

10K

10K

10K

CPLD_HEADER_TDO

CPLD_HEADER_TCKCPLD_HEADER_TDI

PGOOD_3V3

MOLEX_87831

V6_CPLD_0

3333

3333

33

PGOOD_1V510K

FMC1_PRSNT_M2C_L10K10K

33

CPLD_HEADER_TMS

SRAM2_A19SRAM2_A18SRAM2_A17SRAM2_A16

MOLEX_87831

JTAG_HEADER_TMS

SRAM2_CE1_L

SRAM2_DQB3SRAM2_DQB2SRAM2_DQB1SRAM2_DQB0SRAM2_DQA7SRAM2_DQA6

MCLK_CPLD

V6_CPLD_5V6_CPLD_3

SRAM2_A15

SRAM2_DQB7SRAM2_DQB6

SRAM2_A14

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

P3V3A

GND

GND

GND

P2V5

JUMPER

JUMPER

JUMPER

GND

GND

P2V5A

P1V8A

GND

P3V3A

P3V3A

GND

GND

P2V5A

I/O BANK 2

I/O BANK 1

XC2C128_VQ100

(2) (3) (2) (1)

B7_MC6

B8_MC3

VCCIO2

TDI

B2_MC2

B2_MC11

B2_CDRST_MC15

TCK

TMSTDO

B8_MC2B6_MC16B6_MC14B6_MC12

B6_MC4B6_MC3B6_MC2B6_MC1

B4_MC15B4_MC16

B4_MC14

B4_MC12B4_MC13

B4_MC6B4_MC7B4_MC11

B4_MC5B4_MC4

B2_GCK2_MC16

B2_GCK1_MC14

B2_MC5B2_MC6

B2_MC4B2_MC3

B1_MC1B1_MC3B1_MC4B1_MC5B1_MC6

B1_MC11B1_MC12B1_MC13

B1_GTS1_MC15

B3_GTS3_MC2B1_GTS0_MC16

B3_MC5

B3_GTS2_MC3B3_GSR_MC4

B3_MC6B3_MC7

B3_MC14

B3_MC11B3_MC13

B3_MC16B3_MC15

B5_MC1B5_MC2B5_MC3

B5_MC7B5_MC5

B5_MC11B5_MC12B5_MC13

B5_MC15B5_MC14

B7_MC1

B8_MC6B8_MC4

B8_MC12B8_MC13

B8_MC15B8_MC16

B7_MC15B7_MC16

B7_MC14B7_MC13

B7_MC5

B7_MC11

B7_MC4B7_MC2

VCC VAUX

B8_MC14

B2_GCK0_MC13

B4_DGE_MC1

VCCIO1

B6_MC6B6_MC5

P1V8

GND

P3V3A

P2V5

GND

131197531

42

6

108

1214

GND

GND

131197531

42

6

108

1214

P2V5

P2V5

P2V5

GND

GND

P1V8

GNDGND

P2V5

A<22>

E*G*

VDD<1-0>VDDQ

VPP

READY_WAIT

K

WP*RP*

L*

W*

A<21>A<20>A<19>A<18>A<17>A<16>A<15>A<14>A<13>A<12>A<11>A<10>A<9>A<8>A<7>A<6>A<5>A<4>A<3>A<2>A<1>A<0>

DQ<15>DQ<14>DQ<13>DQ<12>DQ<11>DQ<10>DQ<9>DQ<8>DQ<7>DQ<6>DQ<5>DQ<4>DQ<3>DQ<2>DQ<1>DQ<0>

VSSQVSS<1-0>

GND

P2V5

P3V3A

P3V3A

P3V3A

TERMINATION SELECTIONON:HCSL, OFF:MLVDS

PLACE ICS874003CLOSE TO DS90LV001

CLOSE TO ICS874003

SS[1:0]=11 : NO SPREADPIN13-PIN12

HCSL LEVELS

FCLKA JUMPER FOR

CLOCK DISTRIBUTION 1 OF 2

125MHZ (DEFAULT) OR 250MHZ

10NF DECOUPLING CAPSFOR VDD, VDDO

PIN7-PIN16

S[1:0]=10 : 125MHZ

MINIMIZE THE STUB

HIGH PRIORITY ROUTINGDIFF.IMPEDANCE 100R FOR ALL DIFF PAIRS

1-2: XTAL AS LOCALCLK IN3-4: LEMO AS FPGACLK OUT2-3: LEMO AS LOCALCLK INLOCAL CLK JUMPER SETTINGS

USE SMA INSTEAD?

PLACE THE TWO SN65LVDS1 & THE 33R VERY CLOSE




8/15

SYSTEM: <SYSTEM>


MODULE:glib


C323

C327

C324

C53

C52

C328

C317

C318

C320

C319

C2

C1

C281C315

C314

C313

C316

54

16 12

83

21

69

7 13

1011

1415

IC35

3

45 IC12

R3

R191R190

134

32

109

76

514

IC33

R189

R197R196

R192R193

R47

11

14

16

19

12

15

17

20

76

8

3

2

54

IC34

R48

35

32

26

23

36

33

27

24

2

6

15

19

1

5

14

18

34

31

25

22

4

8

13

17

3

7

12

16

IC31

R186

R188

R187

4321 J14

6

7

3

28

IC37

R2

21

J8

13

11

14

10

53

4

127

2

6

IC25

1

SMA1

C325

R199R200

C326

R201810

1718

20143

15

11

5

14

1696

1312

IC36

R195

C322 C321

C51C50

3

45 IC11

4

31

QZ2

31

QZ3

134

32

109

76

514

IC32

P3V3

VDD=P3V3

TCLKA_FROM_GLIB_P

220NF

SN65LVDS1DBVMCLK_0_N

P3V3

IDT5V5216PGG

MCLK_0_P

MCLK_1_N

FMC1_CLK0_M2C_NFMC1_CLK0_M2C_P

FMC_XPOINT_S0FMC_XPOINT_S1

AMC_TCLKA_P10K

TCLKA_DR_EN

TCLKA_TO_GLIB_PTCLKA_TO_GLIB_N

P3V3

33

VCC=P3V3

TCLKB_FROM_GLIB_N

49.9

P3V3

VDD=P3V3IDT5V5216PGG

TSSOP

P3V3

FMCX_CLK0_M2C_COPY2_NFMCX_CLK0_M2C_COPY2_P

FMCX_CLK0_M2C_COPY1_P

TCLKA_TO_GLIB_PTCLKA_TO_GLIB_N

TSSOPVCC=P3V3

MCLK MCLK_CPLD

P3V3

TSSOP

P3V3

P3V3

P3V3

ICS874003_CLK0_PICS874003_CLK0_NICS874003_CLK1_PICS874003_CLK1_N

SMA_142_0701

ICS874003_FSEL

ICS874003_MR

ICS874003_OE

FMCX_CLK0_M2C_COPY1_P

XPOINT_CLK0_PXPOINT_CLK0_N


TCLKB_FROM_GLIB_NTCLKB_FROM_GLIB_P

TCLKA_FROM_GLIB_NTCLKA_FROM_GLIB_P

TCLKB_TO_GLIB_NTCLKB_TO_GLIB_P

FMCX_CLK0_M2C_COPY1_N

LVDS_FCLKA_NLVDS_FCLKA_P

P3V3 XPOINT_S13XPOINT_S03

XPOINT_S12XPOINT_S02



FMC2_CLK0_M2C_NFMC2_CLK0_M2C_P

P3V3

TSSOP

TCLKA_FROM_GLIB_N

AMC_TCLKA_N

P3V3

P3V3

P3V3

AMC_TCLKB_PAMC_TCLKB_N

TCLKB_TO_GLIB_PTCLKB_TO_GLIB_N

SN65LVDT125DBT

P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

VDD=P3V3

CLK125_2_P

CLK125_3_NCLK125_3_PCLK125_2_N

CLK125_1_NCLK125_1_P

CLK125_0_PCLK125_0_N

TSX-3225

SMD

TSSOP

AMC_FCLKA_N

FPGA_CLKOUT

LVDS_FCLKA_N

LVDS_FCLKA_P

P3V3

P3V3

P3V3

LEMO_CLK

VCC=P3V3SN65LVDT122PW

FMCX_CLK0_M2C_COPY1_N

TCLKB_FROM_GLIB_P

TCLKB_DR_EN

P3V3

TSSOP

TSSOPICS8543BGLF

VCC=P3V3

ICS557G-03LF

GND=GND

MCLK_1_PSN65LVDS1DBV

GND=GNDVCC=P3V3

FXO-HC736R-40

P3V3

AMC_FCLKA_P

25MHZ

10

5151

100100

4.7K

1%

49.91%49.91%

49.91%49.91%

4.7K

100100

4751/16W

1%

10UF_X5R

10NF

220NF

220NF

220NF

220NF220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

15PF

10NF16V_GEN

2PF50V

2PF50V

10K0603

0603

220NF

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

GND

ICS874003_02

QA0QA0*QA1

QA1*

QB0QB0*

F_SEL2

CLKCLK*

OEBMR VDDO[2]

VDDVDDA

GND

F_SEL1

OEAF_SEL0

P3V3

GND GND

GNDGND

GND

GND

GND

RE_EN*DR_EN

IN_BIN_A

TYPE_SELDIFF_SEL

M_BM_A

OUT_BOUT_A

GND

VDD GND

OUTE/D

GND

GND

CLK0CLK0*

CLK1*CLK1

S0S1

SS0SS1

X1/ICLKX2

VDDXDGNDXD GNDODA

VDDODA

OEIREF

GND

GND+ -

GND

RE_EN*DR_EN

IN_BIN_A

TYPE_SELDIFF_SEL

M_BM_A

OUT_BOUT_A

GND

GND

GND

GND

GND

QQ*

Q*

Q*Q

Q

QQ*

OE

PCLKPCLK*CLK_SEL

CLK_ENCLKCLK*

Z[3]*Y[3]

DE[3]

Y[2]Z[2]*

DE[2]

Z[1]*Y[1]

DE[1]

Z[0]*Y[0]

DE[0]

B[3]

S1[3]A[3]

S0[3]

B[2]

S1[2]A[2]

S0[2]

B[1]A[1]S1[1]S0[1]

B[0]A[0]

S0[0]S1[0]

GND

GND

GND

GND

GND

GND

GND

21

34

DR

DS90LV001

GND+ -

21

Z[0]Y[0]

DE[0]B[0]A[0]

B[1] Z[1]Y[1]

DE[1]

A[1]

S0S1

GND

GND

GND

EN/D OUT

GND GND

GND

R184 is not mounted

KEEP IT SHORT

220NF DECOUPLING CAPS FOR VCC_OUT & VCC_AUXOUT

CLOCK DISTRIBUTION 2 OF 2

HIGH PRIORITY ROUTING

220NF DECOUPLING CAPS FOR VCC_VCO

220NF DECOUPLING CAPS FOR VCC1_PLL & VCC2_PLL

220NF DECOUPLING CAPS FOR VCC_IN_PRI, VCC_IN_SEC & VCC_AUXIN




9/15

SYSTEM: <SYSTEM>


MODULE:glib


TP6

R184

C288

C302

C301

C292

C307

C308

C294

C306

C305

C290

C296

C297

C298

C299

C300

C295

C291

21

L13

C310

21

L11

C289

C303

C312R185

C311

C304

C309C293

R181

R183

R182

3

45 IC29

21

L12

147

15

44

5

48

67

910

1617

1920

2728

3033

14

2322

2524

23

384

3112

4645

37

36

49

4041

13

43

IC30

EXT_LFN

CDCE62005RGZ

270

1.0UF

10UF_X5R

10UF_X5R

CDCE_PLL_LOCK

330

MGT_REFCLK_COPY1

EXT_LFNFP_REFCLK0_P

CDCE_REF_SEL

CDCE_SPI_LE

CDCE_PWR_DOWN

CDCE_SPI_CLKCDCE_SPI_MISOCDCE_SPI_MOSI

MGT_REFCLK_COPY_1_P

MGT_REFCLK_COPY_0_PMGT_REFCLK_COPY_0_N

VCC_VCO

VCC_PLL

EXT_LFP

P3V3

1

VCC_IN

XX

VCCVCO<1..0>

CDCE_SYNC 220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

10UF_X5R

10UF_X5R

10UF_X5R

10UF_X5R10UF_X5R

100

1K

BLM15HD102SN1

BLM15HD102SN1

BLM15HD102SN1P3V3

MGT_REFCLK_COPY_1_NSN65LVDS1DBV

VCC=P3V3GND=GND

QFN

SFP_REFCLK0_NSFP_REFCLK0_P

EXTFP_REFCLK0_PEXTFP_REFCLK0_N

FP_REFCLK0_N

FMC1_REFCLK0_PFMC1_REFCLK0_N

MCLK_1_NMCLK_1_P


EXT_LFP

P3V3

P3V3

P3V3

P3V3

VCC_IN

VCC_VCO

VCC_PLL

01VCC2_PLL<1..0>

0

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

GND

GND

GND

GND

GND

GND GND

GND

GND

VBB

PAD/GND

SPI_MOSI

SPI_CLKSPI_MISO

SPI_LE

SYNC*PWR_DOWN*REF_SEL

EXT_LFNEXT_LFPAUX_IN

SEC_REF+SEC_REF-

PRI_REF+PRI_REF-

U4PU4N

U3NU3P

U2NU2P

U1NU1P

U0PU0N

REG_CAP1

TESTOUTAREG_CAP2

TEST_MODE

AUX_OUT

PLL_LOCK

GND_VCCO

VCC_OUT[7]VCC_AUXOUT

VCC1_PLLVCC2_PLL[2]

VCC_VCO[2]VCC_IN_PRIVCC_IN_SEC

VCC_AUXIN

SFP CAGE

TO THE THE RESISTOR PINS MUST BE EQUAL IN LENGTH & GEOMETRY

ALL DIFF. PAIRS OF BANKS 112,113,114,115,116MUST HAVE DIFF. IMPEDANCE 100 OHM.

TRACE LENGTH FROM THE FPGA PINS MGTRREF AND MGTVTTRCAL

SERIAL INTERFACES

NO SWAPPING POSSIBLEHIGHEST PRIORITY ROOTING - HIGH SPEED LINES ~5GBPS

NOTE1

NOTE2

BANK[112..116]: DIFF.IMPEDANCE 100RHIGH SPEED: ALL AMC_*, FMC*, SFP*, GBE*HIGH PRIORITY ROUTING

SEE NOTE1 BELOW

NO SWAP100NF CLOSE TO FPGA




10/15

SYSTEM: <SYSTEM>


MODULE:glib


C5

C6

R73R72

R66R65

R59R58

R52R51

R222

R224R223

R221

1011

89

43

21

IC14

1011

89

43

21

IC13

LD9

LD8

LD7

LD6

LD5

LD4

R76

R75

R69

R68

R62

R61

R55 LD3

LD2R54

C56

C62

C74

C68

C69

C57

C63

C75

20171

141110

16 15

23

1918

45

9 7

1213

68

J18

20171

141110

16 15

23

1918

45

9 7

1213

68

J17

20171

141110

16 15

23

1918

45

9 7

1213

68

J16

20171

141110

16 15

23

1918

45

9 7

1213

68

J15SFP1

C254C255

L1

L3

L5

L7

L6 L8

L4L2

C64

C66

C76

C78

C70

C72

C73

C77

C67

C71

C55

C59

C61

C65

C60

C58

R106

C241C240

C238C239

C265C264

C244C245

C250C251

C253C252

C227C226

C229C228

C242

C243

C247

C246

C248

C249

C257

C256

C259

C258

C261

C260

C263

C262

C237

C236

C234

C235

C233

C232

C231

C230

9697

9091

6665

6059

5150

4544

3635

162163

3029

156157

150151

144145

132133

126127

120121

114115

108109

102103

2120

1211

166168169

13813913513678777574

165

7156

9394

8788

6968

6362

5453

4847

3938

159160

3332

153154

147148

141142

129130

123124

117118

111112

105106

99100

2423

1514

86

4

26175

8180

167

38341

J3

A3

F1

P1

AB1

AK1

B1

H1

T1

AD1

AM1

C3

K1

V1

AF1

AN3

D1

M1

Y1

AH1

AP1

A4

F2

P2

AB2

AK2

B2

H2

T2

AD2

AM2

C4

K2

V2

AF2

AN4

D2

M2

Y2

AH2

AP2

B5

J3

R3

AC3

AJ3

D5

K5

U3

AE3

AL3

E3

L3

W3

AF5

AM5

G3

N3

AA3

AG3

AP5

B6

J4

R4

AC4

AJ4

D6

K6

U4

AE4

AL4

E4

L4

W4

AF6

AM6

G4

N4

AA4

AG4

AP6

AN7

F6

M6

T6

AB6

AH6

F5

M5

T5

AB5

AH5

H6

P6

V6

AD6

AK6

H5

P5

V5

AD5

AK5AP7

IC2

SFP3_VCCR

SFP4_RXP

SFP4_MOD_ABS

CLK125_2_N

AMC_P1_TX_N

AMC_P1_TX_PAMC_P1_RX_P

AMC_P0_RX_PAMC_P0_TX_P

AMC_P0_RX_N

SFP4_RXN

P3V3

AMC_P1_RX_N

100NF

22UF

P3V3

AMC_P0_TX_N

4.7K

4.7UH

GBE_SIN_N

GBE_SIN_P

GBE_SOUT_P

100NF

100NF

100NF

100NF

GBE_SOUT_N

100NF100NFCLK125_2_P

100NF

SFPX_RS0

SFP4_TXN

SFP1_RXLOS

TSSOPVCC=P3V3

SFP1_VCCT

SFP2_TXFAULT

SFP2_RXLOS4.7UH

P3V3

SFP4_TXFAULT

SFP4_RXLOS

SFP3_TXFAULT

SFP3_RXLOS

SFP2_VCCT

SFPX_RS0AMC_P8_RX_NAMC_P8_TX_PAMC_P8_RX_P

FMC1_DP0_M2C_PFMC1_DP0_C2M_PFMC1_DP0_M2C_NFMC1_DP0_C2M_NFMC1_DP1_M2C_P

AMC_P7_TX_NAMC_P7_RX_NAMC_P7_TX_PAMC_P7_RX_PAMC_P6_TX_NAMC_P6_RX_NAMC_P6_TX_P

AMC_P6_RX_P0.1%_GEN

FP_REFCLK0_P

AMC_P11_TX_N100NF

100NF

100NF

100NF

BGA

SFP4_TXNSFP4_RXNSFP4_TXPSFP4_RXPSFP3_TXNSFP3_RXN

AMC_P11_RX_NAMC_P11_TX_PAMC_P11_RX_PAMC_P10_TX_NAMC_P10_RX_NAMC_P10_TX_P

ICS874003_CLK1_PICS874003_CLK1_N

AMC_P10_RX_PEXTFP_REFCLK0_P

AMC_P9_TX_N

AMC_P8_TX_N

100NF

100NF

SFP1_TXFAULT

VCC=P3V3

330

330

330

100NFFMC2_DP0_M2C_PFMC2_DP0_C2M_P

100NF

4.7UH

FMC2_DP0_C2M_N

GBETX_N

100NF

100NF

SFP3_RXNSFP3_RXP

GBETX_P

FMC1_DP3_M2C_N

FMC1_DP3_M2C_PFMC1_DP3_C2M_P

FMC1_DP3_C2M_N

FMC1_DP2_C2M_PFMC1_DP2_M2C_NFMC1_DP2_C2M_N

100NF100NF

100NF100NF

SFPX_TXDIS

SFPX_TXDIS

SFPX_TXDIS

SFPX_TXDIS

SFP4_VCCR

SFP2_VCCR

SFP1_VCCR

AMC.0_R2.0

EDGE

1888247-1

1888247-1

1888247-1

1888247-1

SFP4_TXP

SFPX_RS1

SFP4_RXLOS

SFP4_VCCT

SFP3_TXPSFP3_TXN

SFPX_RS1

SFP3_RXLOS

SFP3_VCCT

SFP2_TXPSFP2_TXN

SFPX_RS1

SFP2_RXLOS

SFPX_RS0

SFP1_TXPSFP1_TXN

SFPX_RS1

SFP1_VCCT

SFP1_RXNSFP1_RXP

SFPX_RS0

AMC_GA2AMC_GA1AMC_GA0

AMC_MP

AMC_SDAAMC_SCL

AMC_FCLKA_N

AMC_TCLKA_NAMC_TCLKB_PAMC_TCLKB_N

AMC_FCLKA_P

AMC_P0_RX_NAMC_P0_RX_PAMC_P1_RX_NAMC_P1_RX_PAMC_P2_RX_NAMC_P2_RX_PAMC_P3_RX_NAMC_P3_RX_PAMC_P4_RX_N

AMC_P5_RX_NAMC_P4_RX_P

AMC_P5_RX_PAMC_P6_RX_NAMC_P6_RX_PAMC_P7_RX_NAMC_P7_RX_PAMC_P8_RX_N


AMC_P9_RX_PAMC_P10_RX_NAMC_P10_RX_PAMC_P11_RX_NAMC_P11_RX_PAMC_P12_RX_NAMC_P12_RX_PAMC_P13_RX_N


AMC_P14_RX_P

AMC_P15_RX_PAMC_P15_RX_N

AMC_P17_RX_NAMC_P17_RX_PAMC_P18_RX_NAMC_P18_RX_PAMC_P19_RX_NAMC_P19_RX_PAMC_P20_RX_NAMC_P20_RX_P

AMC_P9_TX_PAMC_P10_TX_NAMC_P10_TX_PAMC_P11_TX_NAMC_P11_TX_P


AMC_P13_TX_NAMC_P13_TX_PAMC_P14_TX_NAMC_P14_TX_PAMC_P15_TX_NAMC_P15_TX_P


AMC_P18_TX_NAMC_P18_TX_PAMC_P19_TX_NAMC_P19_TX_PAMC_P20_TX_NAMC_P20_TX_P

AMC_P0_TX_N

AMC_P1_TX_NAMC_P0_TX_P

AMC_P1_TX_PAMC_P2_TX_NAMC_P2_TX_PAMC_P3_TX_N

AMC_P4_TX_NAMC_P3_TX_P

AMC_P4_TX_PAMC_P5_TX_NAMC_P5_TX_P


AMC_P7_TX_NAMC_P7_TX_PAMC_P8_TX_NAMC_P8_TX_PAMC_P9_TX_N

SFP3_TXP

SFP2_TXN

SFP1_TXN

SFP1_TXP

AMC_P9_TX_P

SFP2_RXN

SFP3_RXP

SFP1_RXP

SFP2_VCCT

SFP4_VCCTSFP3_VCCT

AMC_ENABLE_N

AMC_PS1_NAMC_PS0_N

FMC1_DP1_M2C_N

AMC_TCLKA_P

2007178

SML-311UT

SFP1_RXLOSSFP1_TXFAULT

SFP3_TXFAULT

SFP2_TXFAULT

SFP4_TXFAULT

AMC_TDI

SML-311UT

SML-311UT

SML-311UT

SML-311UT

SML-311UT

SML-311UT

SML-311UT

SFP3_MOD_ABS

SFP2_MOD_ABS

SFP1_MOD_ABS

SFP2_RXNSFP2_RXP


P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

P3V3

AMC_P9_RX_N

AMC_P9_RX_P

CLK125_1_PCLK125_1_N

SFP_REFCLK0_N

EXTFP_REFCLK0_N

SFP_REFCLK0_P

FMC1_REFCLK0_PFMC1_REFCLK0_N

P3V3

AMC_TCK

AMC_TMSAMC_TRST_B

AMC_TDO

4.7UH

4.7UH

4.7UH 4.7UH

4.7UH

330

330

330

330

330

33

3333

33

4.7K4.7K

4.7K4.7K

4.7K4.7K

4.7K

100

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF

100NF100NF

22UF

6.3V

22UF

6.3V

22UF

6.3V

22UF

6.3V

6.3V

22UF

6.3V

22UF

6.3V

22UF

6.3V

100NF

100NF

100NF

100NF

100NF

100NF100NF

100NF

100NF

100NF100NF

100NF

ICS874003_CLK0_PICS874003_CLK0_N

FP_REFCLK0_N

AMC_P4_RX_NAMC_P4_TX_P

CLK125_3_N

SFP2_TXP

P3V3

SFP1_RXN

SFP2_RXP

100NF

AMC_P5_TX_NAMC_P5_RX_NAMC_P5_TX_PAMC_P5_RX_PAMC_P4_TX_N

100NF

100NF

100NF

100NF

100NF

100NF

100NF

FMC1_DP2_M2C_P

CLK125_3_P

AMC_P4_RX_P

FMC1_DP1_C2M_P

FMC1_DP1_C2M_N

FMC2_DP0_M2C_N

P3V3

100NF

TSSOP

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

JTAG

POWER

RX0-RX0+RX1-RX1+RX2-RX2+RX3-RX3+RX4-

RX5-RX4+

RX5+RX6-RX6+RX7-RX7+RX8-

RX9-RX8+

RX9+RX10-RX10+RX11-RX11+RX12-RX12+RX13-

RX14-RX13+

RX14+

RX15+RX15-

RX17-RX17+RX18-RX18+RX19-RX19+

RX20+RX20-

TX0-

TX1-TX0+

TX1+TX2-TX2+TX3-

TX4-TX3+

TX4+TX5-TX5+

TX6+TX6-

TX7-TX7+TX8-TX8+TX9-TX9+

TX10-TX10+TX11-TX11+

TX12+TX12-


TX17+TX17-


RSRVD8RSRVD6

MP

GA0

ENABLE*PS0*PS1*

FCLKA+FCLKA-

GA1GA2

TDO

GND[54]

SCL_LSDA_L

TCLKA+TCLKA-TCLKB+TCLKB-TCLKC+TCLKC-TCLKD+TCLKD-

TCK

TRST*

TDITMS

PWR[8]

GND

GND

GND

GND

GND

GND

GND

GND

VTT

P2V5P1V0

VTT

VCCA

VCCA

VTT

GND

LCX04

LCX04

LCX04

LCX04

LCX04

LCX04

LCX04

LCX04

TD+TD-

TX_DIS

VEETVEETVEET

TX_FAULT

RS1

LOS

VCCT

RD-RD+

SCASDA

RS0

VCCR

MOD_ABS

VEER

VEERVEER

TD+TD-

TX_DIS

VEETVEETVEET

TX_FAULT

RS1

LOS

VCCT

RD-RD+

SCASDA

RS0

VCCR

MOD_ABS

VEER

VEERVEER

TD+TD-

TX_DIS

VEETVEETVEET

TX_FAULT

RS1

LOS

VCCT

RD-RD+

SCASDA

RS0

VCCR

MOD_ABS

VEER

VEERVEER

TD+TD-

TX_DIS

VEETVEETVEET

TX_FAULT

RS1

LOS

VCCT

RD-RD+

SCASDA

RS0

VCCR

MOD_ABS

VEER

VEERVEER

SFP1

SFP4

SFP3

SFP2

GND

GND

GND

GND

GND

GND

GND

GND

GND

P12V


BANK 113

BANK 116

BANK 114NA

MGTAVTT_S[9..0]

MGTAVCC_S[9..0]

MGTAVCC_N[5..0]

MGTAVTT_N[5..0]

MGTTXP0_114MGTRXP0_114

MGTRXN0_114

MGTRXP1_114MGTTXN0_114

MGTTXP1_114

MGTTXN1_114MGTRXN1_114

MGTREFCLK0N_114MGTREFCLK0P_114MGTRXP2_114MGTREFCLK1N_114MGTREFCLK1P_114

MGTTXN2_114

MGTTXP2_114MGTRXN2_114



VCCINT[54..0]

GND[252..0]

VCCAUX[12..0]

MGTRXP0_116

MGTTXN0_116

MGTTXP0_116MGTRXN0_116


MGTRXN1_116MGTTXN1_116

MGTREFCLK0N_116MGTREFCLK0P_116

MGTRXP2_116MGTREFCLK1N_116

MGTTXP2_116MGTREFCLK1P_116

MGTRXN2_116


MGTTXP3_116


MGTRXN0_113

MGTRXP0_113MGTTXP0_113


MGTTXP1_113MGTRXN1_113MGTTXN1_113

MGTREFCLK0P_113MGTRXP2_113

MGTREFCLK0N_113

MGTREFCLK1P_113MGTREFCLK1N_113

MGTTXN2_113MGTRXN2_113MGTTXP2_113



MGTRXP0_112MGTTXP0_112MGTRXN0_112


MGTTXP1_112


MGTREFCLK0N_112MGTREFCLK0P_112MGTRXP2_112


MGTTXP2_112MGTRXN2_112MGTTXN2_112MGTRXP3_112MGTTXP3_112



MGTRXP1_115MGTTXN0_115MGTRXN0_115

MGTTXP1_115MGTRXN1_115MGTTXN1_115

MGTREFCLK0N_115MGTREFCLK0P_115

MGTRREF_115MGTAVTTRCAL_115

MGTRXP2_115


MGTRXN2_115MGTTXP2_115

MGTTXN2_115MGTRXP3_115MGTTXP3_115MGTRXN3_115MGTTXN3_115

MICROSWITCHFRONT PANEL'S

1001110

EN internally pulled up

I2C ADDRESS

FRONT PANEL'S BLUE LED

I2C ADDRESS1010 A2 A1 A0MODULE MANAGEMENT

FPGA TEMPERATURE

MMC_REG_ENABLE

I2C ADDRESS0011010

FRONT PANEL'S LED2

TRI-LEVEL I2C ADDRESSING

FASTER RESET SUPERVISOR?

FRONT PANEL'S LED1

USE TLC7725 INSTEAD

TD=2.1US ???

I2C ADDRESSING

MEASUREMENT

I2C ADDRESS


0101010

1010110: GLIB EEPROMI2CBUS2: I2C MASTER: FPGA

XXXXX00: FMC#11001110: GLIB BOARD TEMPERATURE #20011010: GLIB BOARD TEMPERATURE #10101010: GLIB FPGA TEMPERATURE

I2CBUS1: I2C MASTER: MMC

XXXXX11: FMC#2

LAST_MODIFIED=Fri May 06 15:03:42 2011


MODULE:glib 11/15

DATE: <DATE>PCB by: PV


PROJECT:GLIBSYSTEM: <SYSTEM>

11/15

EDA-02180-V2-0

R28

330

MMC_PE4_INT4MMC_PE6RTM_I2C_EN

RTM_3.3V_ENRTM_12V_EN

17

12MMC_RED_LED_NMMC_BLUE_LED_NMMC_GREEN_LED_NMMC_RELOAD_FPGAS_NMMC_RESET_FPGA_N

LD10

330

SML-311UT

2

4.7KMMC_DCDC_ENABLE R194

J7

SS4-20-3.50-L-D-L-K-TR

LGL29K-G2J1-24

MMC_TDO33

MMC_SCL

100PF

POWER_ON_RESET_B

MMC_DCDC_ENABLE

220NF220NF220NF

CRITICAL_TEMP_BCRITICAL_TEMP_BFPGA_DXP

FPGA_DXN

QSOPQSOPQSOP

MMC_SCLMMC_SDA

CRITICAL_TEMP_B

MMC_SDAMMC_SCL

24AA025E48

FPGA_SDA

220NF

20849-209

MMC_BLUE_LED_N

MMC_GREEN_LED_N

LNJ926W8CRA

20849-209

VDD=P2V5

100K

MMC_TCK

MMC_SCLMMC_SDA

AMC_ENABLE_N

AMC_SCL

MMC_TMS

MMC_PG4


MMC_TDI

MMC_RED_LED_N

AMC_GA2

MMC_PF1_ADC1MMC_PF2_ADC2MMC_PF3_ADC3

AMC_SDA

MMC_MICROSWITCH_CLOSED_NMMC_LOW_VOLTAGE_POKAMC_GA1

4.7K

AMC_PS0_NAMC_PS1_NAMC_GA0

MMC_PE5_INT5

RTM_PS

FPGA_SCL MMC_SCL

MMC_SDA

FPGA_SCL

FPGA_SDA


MMC_SDA

SOIC

4.7K

MSOP

PCA9517DGKR

220NF

220NF

220NF

IC21

106

43

11

1412

16

2

IC9

106

43

11

1412

16

2

IC7

106

43

11

1412

16

2

IC16

13 6

527

R86

R198

C80

R30LD11

TP3TP2TP1

TP5TP4

12

IC24

123

6 5

8 4

C280

C268 C35C54

C79

R881 2R871 2

SW1

A BC D

SW4

A BC D1 2

3 45 67 89 10

1113 1415 16

1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

IC20

5

2 73 6

1 8

C267

C266

LD1R29

330

J6

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

GND

P3V3A

LM82

ADD[0]ADD[1]

GND VCC

T_CRIT_A*

INT*

SMBDSMBCLK

D+D-

LM82

ADD[0]ADD[1]

GND VCC

T_CRIT_A*

INT*

SMBDSMBCLK

D+D-

GND

GND

GND

P3V3A

GND

GND

P2V5

P3V3AP2V5

ENVCCBVCCA

SDDA SDABSCLBSCLA

3840

32

3634

3028

1820

2422

26

810121416

6

24

3739

35

27293133

2523211917

1315

1197531P3V3A

P3V3A

GND

GND

P12V

P3V3AGND

TLC7733

CONTROL

SENSERESINCT

RESETRESET

GND

GNDGND

GND

P2V5

A2A1A0

VCC VSS

SDASCL

P3V3A

P3V3A

P3V3AP3V3AP3V3A

P3V3A

P3V3A

P3V3A G

ND

21

P2V5

P2V5

P2V5

P2V5

GND

GND

GND

GND

GND

LM82

ADD[0]ADD[1]

GND VCC

T_CRIT_A*

INT*

SMBDSMBCLK

D+D-

CFG4: HWCFGMD[2] HWCFGMD[1] HWCFGMD[0] :100

CFG0: PHYADR[2] PHYADR[1] PHYADR[0] :111

100: LED_LINK1000

CFG6: SEL BDT INT_POL 75/50 OHM :110

CFG2: AUTONEG[3] AUTONEG[2] AUTONEG[1] :111CGF1: ENA PAUSE PHYADR[4] PHYADR[3] :000

CGF5: DISABLE FC DIS SLEEP HWCFGMD[3] :110

CFG3: AUTONEG[0] ENABLE XC DIS125MHZ :111

111: VCC2V5

000: GND

110: LED_LINK10101: LED_LINK100

010: LED_RX001: LED_TX

011: LED_DUPLEX

GBE PHY




12/15

SYSTEM: <SYSTEM>


MODULE:glib


J11

C333

C335

C337

C330

C334

C339

C336

C329

C331

C332

C338

4.7K4.7K

4.7K R8

TP7TP8

R9

R7

R6R202R5

J9

H9

H7

J2J1H3H1H2G3G2F1

F2

E1D1

M9L8

K8

L7

L9

H8

A8

A7

A4A3

A6A5

C5A2A1C4B3C3D3B2

D2

B1

C1

K3M2

M1

N9N8N7N6N4N3N2N1

L3

D9C9

A9B8C8

E8

L1

M6M5

E2

B5G8G9F9G7F8E9D8

L4

B6

K2

IC1

L14

R220

R219

21 R216

C341

C345

C346

C342

R204

R207

R210

R205

R203

R208

R209

R206

C340

C344

C347

C343

9

87

65

4

3

2

1211

10

1

1617

15

1314

C19 C203

QZ1

220NF

LED_LINK10

0R0

LED_LINK10LED_LINK1000

GBE_SIN_PGBE_SIN_N

MDI3_NMDI3_P

MDI2_PMDI1_NMDI1_PMDI0_N

MDI2_N

33GBE_TCK

220NF

1368392-2

TSX-3225

MDI3_P

GBE_XTAL1

51

LED_TX

51

LED_RX

51

SH<1..0>

GBE_XTAL2

9PF50V

25MHZ

9PF50V

51220NF

MDI2_P

LED_LINK1000

51220NF

MDI3_N

51 MDI0_N220NF

51 MDI1_P220NF

MDI0_P

MDI1_N

MDI2_N

51

01

220NF

220NF

220NF

51

RJ45

51

51

1G18

GBE_SOUT_N

GBE_SCL

GBE_RESET_N

GBE_TMSGBE_TDI

MDI0_P

GBE_XTAL1

GBE_TRST_B

4.99K

GBE_TDO

LED_TXLED_RX

TFBGA

GBE_SOUT_PLED_LINK10

LED_LINK1000

GBE_XTAL2

GBE_SDAGBE_INT_N

MPZ1608S221A

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

P2V5

GND

GNDGND

EN/D OUT

P2V5P1V0

GND

GND

GND

P1V0 P2V5

P2V5

P2V5

GND

GND

GND

P2V5

88E1111_TFBGA

VSSC<1>

RX_CLKRX_ER

INTNMDIO

MDI0+

MDI2+MDI2-MDI3+MDI3-

LED_TXXTAL2

LED_RX

LED_LINK1000LED_DUPLEX

LED_LINK100LED_LINK10

S_OUT+COLCRS

RXD7

RXD5RXD6

RXD4RXD3

RXD1RXD2

RXD0

S_OUT-RX_DV

DVDD<8>

TX_ER

TX_ENGTX_CLK

TXD0TXD1TXD2

TXD4TXD3

TXD5TXD6

COMA

TXD7MDC

RESETRESETN

TDITMSTRSTN

TDOTCK

XTAL1CONFIG6CONFIG5

CONFIG3CONFIG4

CONFIG2

CONFIG0CONFIG1

S_IN-S_CLK-S_CLK+

VSS<23>

S_IN+HSDAC-HSDAC+SEL_FREQ

MDI1-MDI1+MDI0-

VDDO<3>

125CLKTX_CLK

VDDOH<3>AVDD<6>

VDDOX<2>

GND

GND

GND

GND

GND

GND

GND

GND

P2V5

P2V5

GND

RJ-5RJ-6

RJ-4RJ-3

RJ-1RJ-2

RJ-8RJ-7

LED2C2LED2COMLED2C1

P9P7P8

P1P2

P3

P5

P4P6

P10P12P11

LED1ALED1C

SH[2]

DO THE MGT_AVTT & MGT_AVCC DECOUPLING AS IN UG366 PAGE286

FPGA DECOUPLING CAPS

MGT_AVTT (PAGE10)

VCCIO_26VCCIO_24

VCCIO_15 VCCIO_23

VCCIO_32VCCIO_25VCCIO_36

VCCIO_34VCCIO_33

FPGA VCCINT (PAGE10)2.2UF: NO MORE THAN 3" FROM PERIPHERY OF FPGA BUT AS CLOSE AS POSSIBLE22ONF: NO MORE THAN 1" FROM PERIPHERY OF FPGA BUT AS CLOSE AS POSSIBLE330UF,47UF,33UF,22UF,10UF: ANYWHERE ON BOARD BUT AS CLOSE AS POSSIBLE TO FPGAFPGA DECOUPLING CAPS PLACEMENT RULES:

VCCIO_13

VCCIO_0 VCCIO_12

FPGA VCCIO (PAGE4)

VCCAUX (PAGE10)

TANT,2.5V

VCCIO_14

220NF,10V,X7R 2.2UF,10V,X7R

VCCIO_22

VCCIO_35

MGT_AVCC (PAGE10)

FPGA VCCIO (PAGE3)

VCCIO_16

LAST_MODIFIED=Fri May 06 09:48:54 2011

C180

C178

C172

C179

C149

C148

C132

C181

C176

C127

C84C85 C131

C111

C110

C161

C140

C138

C121

C135

C113

C115

C137

C167

C103

C102

C160

C184

C159

C158

C171

C173

C174

C177C99

C98C107

C108C129C91C147

C146

C139

C155

C175C90

C87C88C100

C130

C152

C157

C136

C119

C118

C117

C133

C114

C191

C93

C105

C104

C95

C122

C124

C125

C142

C143

C166

C164

C163

C185

C182

C188

C189

C141

C190

C94

C25

C96

C106

C123

C126

C144

C165

C183

C145

C192

C97

C21

C81

C120

C186 C187 C92 C151

C169

C168

C89 C83 C86 C156

C170

C154C82C109

C3

C128

C26

C23

C101

C22C193

C150

C4

C24

C162

C27

C7

C153

2.2uF

2.2uF2.2uF

2.2uF

2.2uF2.2uF

2.2uF

220NF

220NF

220NF

220NF

220NF

220NF 220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

330UF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

4V

4V

4V

220NF

220NF

220NF

220NF

FMC1_VIO_B_M2C

220NF

220NF

220NF

220NF

220NF

220NF

4V4.7UF

220NF

220NF

4V

4V

4.7UF

4.7UF

4.7UF

330UF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF 220NF 220NF 220NF

220NF220NF220NF

220NF

220NF220NF220NF

220NF

220NF220NF

220NF220NF

47UF 47UF47UF

47UF

GIGABIT LINK INTERFACE BOARD

GLIB

1 XX X

220NF

220NF

220NF

330UF

4.7UF

4.7UF

220NF

220NF

220NF

220NF

220NF

220NF

FMC2_VIO_B_M2C47UF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

PAGE:

DATE:

ABBREV:

TITLE:

1211 GENEVA 23

REF:

ETUDE:

5

D

B

1

D

8

8 7

7 6

6 5

4

4 3

3 2

2

1

CC

B

AA

EE

PCB: SYSTEM:REF:EDMS

IT/CE

SWITZERLAND

DIV.

DESSIN:

VERSION:

DRAWING

P2V5P2V5P2V5P2V5P2V5

P2V5P2V5

P2V5P2V5P1V0

P2V5P2V5P2V5

+

GND

GND

++

+

GND

GND

GND

GND

+

GNDGND

GND

GNDGNDGND

GND

GND

GNDGND

P2V5P2V5

VCCA

GND

+

GND

+

VTT

GND

GND

VTT

GND

+

VCCA

P2V5

GND

GND

SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET")

UNCONDITIONAL SWAP OF BUS TRANSLATOR_TO_MLVDSUNCONDITIONAL SWAP OF BUS MLVDS_TO_TRANSLATOR

NOTE: PHYSICS PROFILE SUGGESTION

SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET") SWAP BY PAIR ("NET" WITH THE CORRESPONDING "V6_NET")

AMC MLVDS, LEVEL TRANSLATORS




14/15

SYSTEM: <SYSTEM>


MODULE:glib


C11

C10

C12

C8

C9

C15

C18

C14

C17

C13

C16

C284

C285

C286

C287 C283

C282

222

1415161718192021

109876543

IC41

222

1415161718192021

109876543

IC40

222

1415161718192021

109876543

IC39

222

1415161718192021

109876543

IC26

222

1415161718192021

109876543

IC28

222

1415161718192021

109876543

IC27

3356

59

50

53

44

47

38

41

2

1

4

3

30

29

32

31

57

58

51

52

45

46

39

40

9

7

15

13

21

19

27

25

8

6

14

12

20

18

26

24

IC42

P3V3

V6_TO_TRANSLATOR_3V6_TO_TRANSLATOR_1V6_TO_TRANSLATOR_7V6_TO_TRANSLATOR_5V6_TO_TRANSLATOR_4V6_TO_TRANSLATOR_6


MLVDS_TO_TRANSLATOR_5TRANSLATOR_TO_MLVDS_10TRANSLATOR_TO_MLVDS_11



P3V3

TRANSLATOR_TO_V6_2TRANSLATOR_TO_V6_5

P3V3

V6_TO_TRANSLATOR_11V6_TO_TRANSLATOR_9V6_TO_TRANSLATOR_15V6_TO_TRANSLATOR_13

V6_FMC_XPOINT_S0V6_FMC_XPOINT_S1

V6_ICS874003_MR

VCCA=P2V5;VCCB=P3V3TSSOP

TCLKB_DR_ENTCLKA_DR_EN

V6_ICS874003_FSELV6_ICS874003_OE

V6_TCLKB_DR_ENV6_TCLKA_DR_ENV6_XPOINT_S03

V6_XPOINT_S13XPOINT_S03XPOINT_S13XPOINT_S02XPOINT_S12

V6_XPOINT_S02V6_XPOINT_S12V6_XPOINT_S01V6_XPOINT_S11

TSSOPVCCA=P2V5;VCCB=P3V3

V6_XPOINT_S10V6_XPOINT_S00



P3V3

P3V3

V6_CDCE_PWR_DOWN

TRANSLATOR_TO_V6_1

MLVDS_TO_TRANSLATOR_0





VCCA=P2V5;VCCB=P3V3

V6_TO_TRANSLATOR_12

TSSOP

TRANSLATOR_TO_MLVDS_4

V6_TO_TRANSLATOR_14V6_TO_TRANSLATOR_8V6_TO_TRANSLATOR_10


TRANSLATOR_TO_MLVDS_2TRANSLATOR_TO_MLVDS_3


VCC=P3V3

AMC_P20_RX_P

AMC_P20_TX_P

AMC_P19_RX_P

AMC_P18_RX_P

AMC_P17_TX_P

AMC_P18_TX_P

AMC_P17_RX_P

AMC_P17_TX_N

AMC_P17_RX_N

AMC_P18_TX_N

AMC_P18_RX_N

AMC_P19_RX_N

AMC_P20_TX_N

AMC_P20_RX_N

P3V3

P3V3

V6_CDCE_REF_SEL

V6_CDCE_SPI_MOSIV6_CDCE_SPI_LEV6_CDCE_SPI_CLK


TRANSLATOR_TO_V6_0TRANSLATOR_TO_V6_3

TRANSLATOR_TO_V6_4TRANSLATOR_TO_V6_7TRANSLATOR_TO_V6_6



V6_TO_TRANSLATOR_2


V6_TO_TRANSLATOR_0


CDCE_SPI_MOSICDCE_SYNCCDCE_PWR_DOWNCDCE_REF_SEL

V6_CDCE_SYNCICS874003_OEICS874003_FSELICS874003_MRFMC_XPOINT_S1FMC_XPOINT_S0

220NF

220NF220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

220NF

CDCE_SPI_LECDCE_SPI_CLK


E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

GND

P2V5

P2V5

GND

GND

GND

GND

GND

SN65MLVD080

B

B

B

B

B

B

B

B

A

ADE

A

D

D

DE

R

R

DEDR

DEDR

DEDR

R

D

A

A

A

A

A

DDE

D

R

DE

DE

RRE*

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

GND

GND

P2V5

GND

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

P2V5

P2V5

GND

GNDP2V5

GND

GND

GND

P2V5

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

GNDP2V5

OE

74AVC8T245

B6

BBBBBB

DIR

AAAAAAA 6543210

543210

7B

7A

P2V5

GNDGND

P2V5

GNDGND

GNDGND

P2V5

HEATSINK POWERfor 12V fan, mount 0R

3.3V POWER

2V5MP

AMC_MP OR LTM4606 3V3SELECT 3V3MP SOURCE

POWERING

1V8MP

MGT POWER

PREFERABLY IN COMPONENT SIDE

PLACE THE GND TESTPOINTSIN DIFFERENT LOCATIONS

1.0V POWER

3V3MP

MANAGEMENT POWER (3.3V, 2.5V, 1.8V)2.5V POWER

90K6 IS NEEDED BUT NOT EXISTING.

90K6 IS NEEDED BUT NOT EXISTING.

EXTERNAL POWER

P3V3 IS THE MASTER TRACKING VOLTAGE

ESD PROTECTION

1.8V POWER




15/15

SYSTEM: <SYSTEM>


MODULE:glib


56

J9

SS_1V5

R44

R45

1K

R1

R169

60.4K

19K1

R168

SS_2V5

R172J10

IC19

IC38

R126

(GND:1,7)

3

4

8

2

6

5

R217

R39R109

R166

3

(GND:1,7)

IC10LTM4606EV#PBF

A8C36

10UF_LESR C41

100PF

RESD2

C279

0.003

0.003

6.3V

RESD1

SS_1V0

SS_3V3

R33

R41

C277

C40

C32

C46

C47

C49

C48

C42

C43

C44

C45

C217

C216

C349

C348

C212

C211

R37

R31

R34

R40

R173

R170

R165

C278

C38C39

C30C31

C275C276

C271C272

C37

C28

C29

C273

C274

C269

C270

321

J4

4321

R110 5

6

2

8

4

IC18

R127

R218

C33

C34

R32

R163

R167

R171

R35

R36

R38R46

R42

R43

R164

321

R4321

J5

R851

10

3 7654

92

IC15

5

6

2

8

4

3

F12

A9

B9A10

G12

B11A12

C11D12C12

A7

B12

M12D11A11

F12

A9

B9A10

A8

G12

B11A12

C11D12C12

A7

B12

M12D11A11

IC23

12

1110987

15

654321

14

13

17

16

RG2

12

1110987

15

654321

14

13

17

16

RG1

F12

A9

B9A10

A8

G12

B11A12

C11D12C12

A7

B12

M12D11A11

IC8

L12

F12A9

H12

A10

J12

A8

G12

M12A12

D12C12

A7

B12

E12 K12

A11

IC22

PGOOD_2V5

0R0

10M

10UF_X5R

VD_2V5<1..0>

0

ESD3

ESD2

POWER_ENABLE

INTVCC_2V5

(GND:1,7)

PGOOD_1V5

VD_3V3<1..0>

DRVCC_3V3<2..0>

CLKSYNC2

1 0

2 1 02 0

01

0

1

12

DRVCC_2V5<2..0>

CLKSYNC3

CLKSYNC2CLKSYNC3CLKSYNC4

CLKSYNC1

PGOOD_1V0

PGOOD_3V3

MSOPLTC6902IMS

LGA

LGA

LTM4606EV#PBF

LGA

QFN

LGA

P3V3

QFN

DVDD

SS_3V3SS_2V5

60.4K

40K2

19K1 13K31%1/16W

20K

160K

20K

230K

160K

20K

59K

100K

0R0

0R0

0R0

0R0

0R0

0R0

1K

60.4K

1K

1K1%

1K

1K4

100PF

100PF

10NF

25V

25V

10UF_LESR

10UF_LESR

100UF_X5R

100UF_X5R

100UF_X5R

100UF_X5R

100UF_X5R

100UF_X5R

10NF

10UF_X5R

10UF_X5R

6.3V

10UF_X5R6.3V

10UF_X5R

6.3V

10UF_X5R6.3V

10UF_X5R

10UF_X5R

10UF_X5R

10UF_LESR

10UF_LESR

10UF_X5R

10UF_X5R

0.003

POWER_ENABLE

10UF_LESR

P3V3

0.003

100UF_X5R

P3V3

40K2POWER_ENABLE

10UF_LESR

10UF_LESR

10UF_LESR

SS_1V0

MMC_DCDC_ENABLE

100UF_X5R

MOLEX_87427-0443

1

AMC_MP

10UF_X5R

DRVCC_1V5<2..0>

VD_1V5<1..0>

LTM4601EV#PBF

POWER_ENABLE

SS_1V590K9

MOLEX_22_27_2031LTM4606EV#PBF

10UF_LESR

10UF_LESR

90K9

10UF_X5R

10UF_LESR

CLKSYNC4

POWER_ENABLE

ESD1

10M

E E

A A

B

C C

2

23

3456

67

78

8

D

1

B

D

5 1


Project:Sheet:


4

EN/ICE

VCCA

GND

GND

P1V5

P1V5

GND GND

GNDGND

GND

GND

PGND[39..0]

VFBMARG0MARG1

VOUT_LCLDIFFVOUT

MPGM

SGND FSET

RUNCOMPINTVCCDRVCC

TRACK/SS

VOSNS+VOSNS-

PLLIN

PGOOD VOUT[42..0]

VIN

P1V5

P1V5

GND

GND

GND

P12V

P12V

P3V3A

P3V3A

P3V3A

P2V5A

P1V8A

P3V3A

GND

GND

3

12

GND

P2V5

P3V3B

P3V3B

P3V3B

P1V5

P2V5

P1V5B

P2V5B P3V3B

RES_SENSE

RES_SENSE

RES_SENSE

RES_SENSE

GND

GND

GND

GNDP3V3A

GND

GND

GND

GND

P12V

GND

GND

3

12

GNDGND

GND

GND

GND

P12V

GND

P1V0

P12V

GND

P12V

GND

P12V

GND

GND

3

12

GND

P12V

21

34

P1V8

P2V5

P1V8

P2V5

GND

LT3021ES8

PGNDAGNDIN

OUT

SHDN*

ADJ

GND

GND

GND

SETV+

PHDIVMOD

OUT1

OUT4OUT3OUT2

P1V0

VCCAVTT

P12V

P3V3AP2V5A

P1V8A

LT3021ES8

PGNDAGNDIN

OUT

SHDN*

ADJ

P1V5

LT3021ES8

PGNDAGNDIN

OUT

SHDN*

ADJ

TRACK/SS

MARG0FCB

MARG1MARG1MPGMMPGM

PGND[45]SGND[2]

VD[2]

FSETDRVCC[3]INTVCC

COMP2COMP1

RUN1RUN2

PGOOD

VIN[18]

VFB

VOUT[44]

PLLIN

GND

TRACK/SS

MARG0FCB

MARG1MARG1MPGMMPGM

PGND[45]SGND[2]

VD[2]

FSETDRVCC[3]INTVCC

COMP2COMP1

RUN1RUN2

PGOOD

VIN[18]

VFB

VOUT[44]

PLLIN

GND

GND

GND GNDGND

MAX8556

FBEN

IN5IN6

IN4IN3

IN1IN2

NCGND EP

POK

OUT5OUT4

OUT2OUT3

OUT1

P12V

MAX8556

FBEN

IN5IN6

IN4IN3

IN1IN2

NCGND EP

POK

OUT5OUT4

OUT2OUT3

OUT1

GND

GND

GND

GND GNDGND

P12V

GND

GND

GND

GNDGNDGND

P12V

VTT

TRACK/SS

MARG0FCB

MARG1MARG1MPGMMPGM

PGND[45]SGND[2]

VD[2]

FSETDRVCC[3]INTVCC

COMP2COMP1

RUN1RUN2

PGOOD

VIN[18]

VFB

VOUT[44]

PLLIN

Documents

PAGE 08: CLOCK DISTRIBUTION 1 OF 2 PAGE 15: POWERING · 2012. 11. 6. · PAGE 12: GBE PHY 1/15 LAST_MODIFIED=Tue Apr 26 17:33:29 2011 Project file:glib.cpm PCB by: PV DATE: