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Package Trends for Today’s and Future mm-Wave ApplicationsMaciej Wojnowski, Klaus Pressel, Grit Sommer, Mario Engl
Page 2
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 3
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 4
Introduction
Cost &Time toMarket
Low/HighPower
Reliability & Failure Analysis
Size
ThermalPerformance
Functionality(System Integration)
Speed
Increasing industrial demands
Page 5
P-DIP
P-TQFP
BGA
Technology
P-TSOP I/IIChip ScalePackage
Chip ScalePackage
SMD
1st
EvolutionTHT
(Peripheral)Grid Array
2nd
EvolutionSMD
(Area)High performanceStacked Chips /3D PackagingWafer Level Packaging
3rd
Evolution
System IntegrationSystem Integration
Flip-ChipFlip-Chip
FunctionalityFunctionality
PackingSize
PackingSize
Pack
age
Dow
nsiz
ing
Pack
age
Dow
nsiz
ing
Electrical Performance
Thermal Performance
Pin Count
Modules(SoB) System in Package
SiP/SoP3D-Packaging
- in Package- on Board
4th
Evolution
22 mm
9,34 mm
13 mm
Package EvolutionUntil Today and Towards Tomorrow
Page 6
Packaging – Growing Challenges
IC Chip – Peripheral Pad Pitch
(100 30 µm)
Customer Board
(1000 500 µm)
in special cases400µm, but high board cost!!
Frontend Waferfab
Customer
Environmental protection
Electrical interface
Thermal interface
Size of component
Cost
Reliability & Failure Analysis
Shielding
RF-Performance
Signal interface (Sensors)
Interconnect Gap
Backend Production
Package as Interposer
Bridging the
Interconnect Gap
Page 7
Semiconductor Development Impact on Packaging
Combining SoC and SiP: Higher Value Systems
More than Moore: Diversification
BiochipsSensorsActuators
HVPowerAnalog/RF Passives
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
2008
32nm
Mo
re M
oo
re:
Min
iatu
riza
tio
n
Base
lin
e C
MO
S:
CP
U,
Mem
ory
, Log
ic
130nm
90nm
65nm
22nm...V
45nm
LogicDRAMFlash
Wireless Analog/RF Automotive
Medical
Page 8
stacked
side-by-side
Modulespassive integration
MCM
stacked die
>2 dies
WB/WB
FC/ WB
stacked package
F2F µ-FlipChip
embedded
Si thru hole
Pack. on Pack.
Technology for System in Package: Infineon’s Technology Tree for BGA type
eWLB
Pack. on SiP
Increasin
g in
tegratio
n d
ensity
>1 die
Page 9
Trends in Packaging: System-in-Package
Laminate based BGA
Embedded Wafer Level BGA
impedance-matched low loss TLs, integrated passives (L, C)
Today
Tomorrow
Form Factor Form Factor Interconnect Size, CostInterconnect Size, Cost
L C
Page 10
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 11
THD through hole DIP, TO 220
Pitch: 2.54mm
SMD gull wingSO, QFP
DSO-Pitch: 1.27mmSSOP-Pitch:0.65...0.5mmQFP-Pitch.0.8...0.65...0.5...0.4mm
SMD solder ballsBGA
Pitch:1.5...1.27...1.0mm
0.8…0.65...0.5mm[0.4…0,3]
SMD leadlessVQFN, TSLP
Pitch:0.8, 0.65, 0.5 mm[0,4; staggered lands]
Package Overview/Evolution
Small OutlineQuad Flat Package
Ball Grid ArrayDual Inline Plastic PackageVery thin Quad Flat No LeadThin Small Leadless Package
Page 12
ProcessesThinning and DicingDie attachWire bondingFlip chip in PackageMoldingThin film technologyWLP processes…
Physics of PackageSignal IntegrityRF capability Heat dissipationReliability PhysicsFA incl. adhesionMiniaturisationPower
PackagePlatformsPackage
Platforms
Methods/CCNCo-design Simulation&ModelingBDRTestKGDStandards
Materials&SubstratesGreen Laminate substrates (xBGA)Leadframes (TSLP, UFLGA, VQFN, ...)
LeadlessPackage
s
Laminate WLB
System in Package
LeadframePackages
Technology Development & Package Development
Integration enabler
QFPDSO
TSSOP
QFN BGA/SGA/LGARF-Modules
SG-WLBPG-eWLB
Page 13
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 14
The Leadless Package Concept TSLP
TSLP – Thin Small Leadless Package
Leadless package based on a leadframe concept
Low to medium pin count (< 80 I/Os)
Green package
Wirebond and Flip-Chip capabilities
Main advantages
Small dimensions (few mm)
Short interconnects
Excellent RF capabilities
Improved thermalperformance
Page 15
1. Die Bonding
2b. Wirebonding
3. Molding4. Copper Removal and Final Plating
6. Electrical Test5. Singulation
2a. Flip-Chip BondingCu Leadframe
DieNiAu Contact
50 µm
Au - Layer
Ni - Bump
The Leadless Package Concept TSLP
Page 16
Flexible leadframe concept
Typical padsizes range from 100 µm to 300 µm
Nearly arbitrary pad geometries
¬ Circular
¬ Rectangular
¬ …
Improved thermal performance
Power / GND supply
The Leadless Package Concept TSLP
Page 17
Wirebond Interconnects – Wire LengthVariation
0 10 20 30 40-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
S11
[dB
]
Frequency [GHz]
l = 1000 µm l = 600 µm l = 300 µm
0 10 20 30 40-6
-5
-4
-3
-2
-1
0
S21
[dB
]
Frequency [GHz]
l = 1000 µm l = 600 µm l = 300 µm
Page 18
Wirebond Interconnects – Padsize Variation
0 20 40 60 80-50
-40
-30
-20
-10
0
S11
[dB
]
Frequency [GHz]
w = 100 µm w = 200 µm w = 300 µm
0 20 40 60 80-6
-4
-2
0
S21
[dB
]
Frequency [GHz]
w = 100 µm w = 200 µm w = 300 µm
Page 19
Flip-Chip Interconnects – Padsize Variation
0 20 40 60 80-60
-50
-40
-30
-20
-10
0
S11
[dB
]
Frequency [GHz]
w = 300 µm w = 200 µm w = 100 µm
0 20 40 60 80-3
-2
-1
0
S21
[dB
]
Frequency [GHz]
w = 300 µm w = 200 µm w = 100 µm
Page 20
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 21
WLB Basic PlatformsFan-In / Fan-Out
WLB Fan-Inrestricted to chip size
WLB Fan-Out (eWLB)offers fan-out possibility
SG
-UFW
LB-4
9
WLBs Fan-In are chip size packagesAll balls must fit UNDER chip shadow
• Number and pitch of Interconnects must be adapted to the chip size
• Fan-in WLBs are available on market
WLB without WLB withredistribution layer
Package design of Fan-Out Packageis INDEPENDENT from chip size:
• Fan-out area adaptable to needs• No restrictions for ball pitch • Fan-Out WLB actually strongly in
the focus of the market
eWLB
Test
Veh
icle
: Chip size: Package size
Page 22
Schematic Process Flow for eWLB Package
M. Brunnbauer, et al., “Embedded Wafer LevelBall Grid Array (eWLB),” 8th EPTC, Dec. 2006.
Page 23
Transmission Lines in eWLB Techology
CPW
W/S = 87/20 µm
Re Z0 = 49.2 Ω (Mold)
Re Z0 = 42.8 Ω (Si 1-100 Ωcm)
TFMSL
W/T = 20/3 µm
H = 10 µm
Re Z0 = 49.2 Ω (BCB)
MSL
W/T = 317/35 µm
H = 130 µm
Re Z0 = 46.9 Ω (RO3003) RO3003
Si 1-100 Ωcm
Mold (eWLB)/Si 1-100 Ωcm
BCB
Page 24
Transmission Lines cont.
Excellent performance of TMLs manufactured in eWLBInsertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz
eWLBeWLB
Measured performance
Page 25
Determination of charactersiticimpedance of the CPW
Transmission Lines cont.
Line Parameters RLCG
R ~ √f G ~ ωCtanδ
tanδ = 0.017(data-sheet = 0.026)
Page 26
Separation of the electrical effects of the conductors and dielectrics
where
Transmission Lines cont.
Further improvement of the performance of thetransmission lines by applying low-loss thin-film dielectrics
αC/αD = 90% αC/αD = 70%
Page 27
Layout parameters
Measured performance
Single-Layer Spiral Inductors
Page 28
Single-Layer Spiral Inductors cont.
Measured performance
Inductors in eWLB offer significantly better performancecompared to inductors in standard on-chip technologies
Page 29
MIM/Interdigital Inductors
MIM capacitors
Interdigital capacitors
Page 30
MIM/Interdigital Inductors cont.
Measured Performance
Further improvement of the quality factor of theintegrated capacitors by using low-loss thin-film dielectrics
Page 31
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 32
Via hole Dielectric layer
Silicon IC Die Metal layer (Cu)
µFC interconnect
Standard Solder Ball
More fan out WLBs : Silicon Carrier Concept
Passive Si carrier with regular grid of TSVHigh integration density (Wafer technology for RDL)Passive integration of L and CHigh reliability interconnects IC and carrier (CTE match)Low cost concept(Standard circuit dies, cost optimized carrier concept)
Macro porous silicon
Page 33
Embedded Passives in Si Low Cost Technology
No Resistor component in focus due to costs (missing specific material)
Inductor Capacitor
Resistor
Planar L using of RDL for loops
Si through hole via for inductor loops
C = 35pF/mm2Q = 500 – 2000Fres= 1-20 GHz
MIM Caps using RDL for plates
Trench Caps using Si – trough holes
C = 3000pF/mm2Q < 1000Fres < 10 GHz
L = 0.5 − 35 nHQ = 20 − 25Fres = 1 − 35 GHz
Page 34
Measurement
HFSS Model
Coplanar Waveguide (CPW) over TSVs
Floating TSVs Grounded TSVs
Gnd
Page 35
TFMSL and CPW over Floating TSVs
Influenceof TSVs
Influence of TSVs
Excellent performance of TMLs manufactured in SCInsertion loss 0.1 dB/mm @ 10GHz, 0.25 dB/mm @ 60GHz
Page 36
Single-layer inductors over floating TSVs
Double-layer inductors over floating TSVs
Single/Double-Layer Spiral Inductors
The inductors in SC offer significantly better performancecompared to inductors in standard on-chip technologies
Page 37
Single/double-layer inductors over floating TSVs vs. grounded TSVs
Influence of Floating/Grounded Configuration
Single-layer spiral inductor of L = 2.0 nH
Groundingof TSVs
Influenceof TSVs∆Q = 12
Page 38
3D Spiral Inductor
The low quality factor is caused by the losses for thecurrents induced in TSVs distributed around the windings
Page 39
3D inductors over floating TSVs vs. grounded TSVs
Influence of Floating/Grounded Configuration
Groundingof TSVs
Influenceof TSVs∆Q = 15
3D spiral inductor of L = 5.6 nH
Page 40
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 41
17 GHz WLAN Receiver
Fully assembled in TSLP-24
Package dimensions 3.5 mm x 3.5 mm
Package height 400 µm
Wirebond interconnect technology
Au wirebonds
500 µm wirelength at critical RF output
Approx. 400 pH parasitic inductance
Inductance of the wirebonds used as external impedance matching network
Page 42
17 GHz WLAN Receiver
400 µm
300 µm
Mold CompoundChip
Rogers RO4003 Substrate
Ni-Pad
400 µm
300 µm
Mold CompoundChip
Rogers RO4003 Substrate
Ni-Pad
Polished cut image
Evaluation board
Page 43
17 GHz WLAN Receiver
Measured gain
Two-tone measurement
Page 44
Fully assembled in TSLP-24
Package dimensions 3.5 mm x 3.5 mm
Package height 400 µm
Total power consumption of 2 W
Flip-Chip interconnect technology not possible
Wirebond technology and die-attach to leadframe forefficient thermal management
Wirebond interconnect technology
Au wirebonds
300 µm wirelength at critical RF output
250 pH parasitic inductance
80 GHz Voltage Controlled Oscillator
Page 45
80 GHz Voltage Controlled Oscillator
Page 46
80 GHz Voltage Controlled Oscillator
80 GHz Output80 GHz Output
2.4 GHz Output2.4 GHz Output
19.125 GHz Output19.125 GHz Output
Page 47
5.6 dBm81.888 GHz5V
5.83 dBm81.536 GHz4V
6.4 dBm81.088 GHz3V
6.67 dBm80.384 GHz2V
5.75 dBm79.136 GHz1V
5.45 dBm75.07 GHz0V
Output PowerfVCOVTUNE
Vss = 5.7 V
(Core temp ≈ 100°C)
Vss = 6 V
(Core temp ≈ 100°C)
6.11 dBm81.664 GHz5V
6.47 dBm81.31 GHz4V
6.92 dBm80.85 GHz3V
6.92 dBm80.128 GHz2V
6.11 dBm78.848 GHz1V
5.99 dBm74.656 GHz0V
Output PowerfVCOVTUNE
80 GHz Voltage Controlled Oscillator
Page 48
77 GHz SiGe Mixer
Chip size 550 × 550 µm2
Gain G = 21.4 dB @ 77 GHz
Noise Figure NFSSB = 11.8 @ 77 GHz
Page 49
Package Design for 77 GHz SiGe Mixer
Manufactured package family
Package size 2.5 × 1.5 mm²and 2.0 × 1.5 mm²
Full surface capability
Standard pitch 0.5 mm
Package P1X
extremely short RF and LO signal paths (about 100 µm)
Package P2X
longer signal paths (about 360 µm)
Three different RDL metallization profiles
Page 50
77 GHz SiGe MixerGain and Noise Figure Measurements
Page 51
TSV - RF Demonstrator on RF Test Board
Fully functional & fully programmableRX & TX chain fully functionalVCO locks on all channelsKey RF parameters within spec limitSpurious performance need improvementRemark:No design of application optimizationwas done for the Si Carrier Demonstrator
Page 52
TransceiverSi Carrier
2 Layer RDL
1st Cu RDL Layer2st Cu RDL Layer
DielectricRDL VIA
µ-Bump 50 µm
FC Ball 250 µm
SiliconCu-Alloy Si-Through Contacts Copper
TSV - RF Demonstrator : Cross Section
Dimensions: 7,5mm x 8,0 mm
Page 53
Outline
Introduction
Package Overview
Thin Small Leadless Package (TSLP)
Embedded Wafer-Level Ball Grid Arry (eWLB)
Through Silicon Vias (TSV)
Experimental Results
Conclusion
Page 54
Conclusion
Thin Small Leadless Package
Low cost solution based on leadframe concept
Suited for low pin count applications
Good RF performance for dedicated applications
Embedded Wafer-Level Ball Grid Array
Excellent RF capabilities
High pin count
Passive device integration capabilities
Through Silicon Vias
High interconnect density
Passive device integration capabilities