Package Net Group Creation...NEXXIM / EM Co-Design 32ports S-Element IBIS PWR/GND Plane Impedance N-Ports S-Parameters 90 ohm Transient TDR (spec) Transient Eye Diagram w/Jitter Jitter

Package Net Group Creation

TPA Example Net Groupings

Parametric Variations

Routing (width and spacing)Bondwire profileSolderball profile

DSO – Distributed Solve Option

……

Paradigm shift:Old: 1 computer to 1 engineerNew: n number of CPU’s to 1 engineer

Host

Nodes

Trace width

Optimize PerformanceParametric Q3D Extractor

®project

Trace width and spacing changing

Optimize Performance

Near-End Crosstalk noise dataTr=200ps

Nominal Case

Improved Case

DesignerSITM/Nexxim®

Schematic view

3D EM Based circuit co-designChanged Routing

Trace length and spacingCrosstalk analysis

DSO Solution TimeDSO Solution Time

Optimize Simulation Run Times

7hr 2 min7hr 2 min

DSO Setup25 Parametric Case7 nodes used2.6 GHz Opteron 8 GB of RAM

Without DSO7 hr 2 min

Using DSO Time1hr 2 min

** Linear Speed Increase **~ 7X speed up with 7 nodes

SI Thermal EffectsePhysicsTM

Critical 3D Thermal and stress analysisSolderball interconnect reliabilityStress induced strains in solder joints

Thermal distribution wire padsThermal distribution wire padsNo wirebonds presentNo wirebonds present

Thermal distribution on bondwiresThermal distribution on bondwiresSingle vs. double bondwireSingle vs. double bondwire

DT: 64.56[C] DT: 61.51[C]

SI Mechanical EffectsePhysicsTM

Reduced design cycle time limits the use of testing to evaluate reliability.Stress induced strains in solder joints

PCB Thermal and Stress Analysis

Features:

- Complex geometry;- Anisotropic thermalmaterial properties;

- Anisotropic stressmaterial properties;

- Large thermal / stressFEM models

Forced convection model

“Bed of pins” stresssimulation

Thermal PCB simulation

10/31/2006 11

0 0

0

0

0

0

IZ=0ohm

PNUM=1RZ=0ohm

LDQ0_src36

LDQ1_src35LDQ2_src33



LDQ7_src37LDQS_src38

LDQSB_src41RDQS_src39

RDQSB_src42VDD_vddsrc

VDDQ_vddqsrc

VSS_vsssrcVSSQ_vssqsrc

LDQ0_Sink

LDQ1_Sink

LDQ2_SinkLDQ3_Sink

LDQ4_SinkLDQ5_Sink

LDQ6_SinkLDQ7_Sink

LDQS_SinkLDQSB_Sink

RDQS_SinkRDQSB_Sink

VDD_SinkVDDQ_SinkVSS_Sink

VSSQ_SinkGround_Bias

V596 V597

50

R598

Cin

/2

C59

9

Cin

/2

C60

0 cloa

d

C60

1

50

R602

V603

Port2Port11 2

ref

VDDQVDDQ

VSSQVSSQ

LDQ0

VDDQ

VSSQ

LDQ0

LDQ0_1

VDDQ1

LDQ1LDQ2

LDQ4

LDQ6LDQ7

VDDQ

VDDQ

LDQ1_1

LDQ2_1LDQ3_1

LDQ6_1

LDQ7_1

LDQ4_1LDQ5_1

LDQ3

LDQ5

LDQ0_1

LDQS_1LDQS_1

DDR2 Memory Channel

Digital Source

TRL line FBGA model

8Bit DQ Bus Channel

Direct import function keeps track of connections

S-parameter model

Unique Bit sequence sourcefor jitter analysis

S-parameter model

DDR2 package

DDR2 Package on PCB

NEXXIM / EM Co-Design

32ports S-Element

IBIS

PWR/GND Plane Impedance N-Ports S-Parameters

90 ohm

Transient TDR

(spec)

Transient Eye Diagram w/Jitter

Jitter

DDR Memory Test System

0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3

DC1_posPC1_DQ0_D46_posPD1_DQ0_D50_pos

P_U156_AE22_1_pos

P_U156_B4_1_posP_U156_C3_1_pos

VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90

DQ0_driver_posDQ0_term_pos

P_U1_C8_1_posP_U2_C8_1_pos

Cylinder1:Source1Rectangle11_1_1:Source2

Cylinder1:Sink1Rectangle11_1_1:Sink2



Coax_probe:Source1Gnd:Source2

Coax_probe:Sink1Gnd:Sink2



Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

0 0

Port1 Port2

3e-0

12

0.21.27e-009

8.4e

-013

C_comp

L_pkg R_pkg

C_pkg

IBIS Driver and Package

* C_comp is important

IBIS Driver


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Main Board DQ0 lines : SIwave

* Series R and Swt. Included in DQ line


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Connector and Interface Board : HFSS


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Interface Board to Coaxial interconnection : Q3D Extractor


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Coaxial Cable : Ansoft Designer

* Er and TAND Optimized from Data Sheet (Delay and Attenuation)


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Coaxial to DUT Board interconnection : Q3D Extractor


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

DUT Board : SIwave


0

0

0

BitList=010101

BitList=010101

BitList=010101

400MbpsPW:2.5n

400MbpsPW:2.5n

400MbpsPW:2.5n

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VV_driverA_out

VV_logicA

VV_driverB_out

VV_logicB

1e-

006

L107

8

12345

678910

ref

Port1 Port2

U2Chip_Package3

Port1 Port2

U3Chip_Package3

Port1 Port2

U4Chip_Package3


P_U156_AE22_1_pos


VTT_pos

VV_dutA_out

8.5

e-0

13

C10

89

2000

0

R10

90











Port1Port1_ref

Port2Port2_ref

Port1Port1_ref

Port2Port2_ref

VV_comp

Test Probe modeling :From Data Sheet* Important

Ansoft Results : 50Mbps DQ0

Measurement and Ansoft Results

: Ansoft

: Measurement

50Mbps DQ0



: Ansoft

: Measurement

400Mbps DQ0


: Ansoft

: Measurement

400Mbps DQ0



: Ansoft

: Measurement

830Mbps DQ0


: Ansoft

: Measurement

830Mbps DQ0

10/31/2006 29

Bit Pattern1. - Jitter noise analysis (time domain)

0 0 0

0

0

0 0 0

0 0 0 0

IZ=0ohm

PNUM=1RZ=0ohm

IZ=0ohm

PNUM=2RZ=0ohm

IZ=0ohm

PNUM=3RZ=0ohm

IZ=0ohm

PNUM=4RZ=0ohm

IZ=0ohm

PNUM=5RZ=0ohm

IZ=0ohm

PNUM=6RZ=0ohm IZ=0ohm

PNUM=7RZ=0ohm

IZ=0ohm

PNUM=8RZ=0ohm

LDQ0_src36LDQ1_src35LDQ2_src33LDQ3_src34LDQ4_src31LDQ5_src32LDQ6_src40LDQ7_src37LDQS_src38

LDQSB_src41RDQS_src39

RDQSB_src42VDD_vddsrc

VDDQ_vddqsrcVSS_vsssrc

VSSQ_vssqsrc

LDQ0_SinkLDQ1_SinkLDQ2_SinkLDQ3_SinkLDQ4_SinkLDQ5_SinkLDQ6_SinkLDQ7_SinkLDQS_Sink

LDQSB_SinkRDQS_SinkRDQSB_Sink

VDD_SinkVDDQ_SinkVSS_Sink

VSSQ_SinkGround_Bias

V731 V732 V733

18

R736

Cin

/2

C737

Cin/

2

C738

75

R741Port2Port1

U3FBGA_00

1 2

ref

V

Vodt_0

V

18

R787

Cin

/2

C788

Cin/

2

C789

18

R795

Cin

/2

C796

Cin/

2

C797

18

R802

Cin

/2

C803

Cin/

2

C804

18

R809

Cin/

2

C810

Cin/

2

C811

18

R820

Cin/

2

C821

Cin/

2

C822

18

R823

Cin

/2

C824

Cin/

2

C825

18

R834

Cin

/2

C835

Cin/

2

C836

cloa

d

C855

75

R867Port2Port1

U4FBGA_00

1 2

ref

VVodt_1

cloa

d

C871

75

R884Port2Port1

U6FBGA_00

1 2

ref

VVodt_2

cloa

d

C888

75

R895Port2Port1

U8FBGA_00

1 2

ref

VVodt_3

cloa

d

C899

75

R906Port2Port1

U10FBGA_00

1 2

ref

VVodt_4

cloa

d

C91

0

75

R917Port2Port1

U12FBGA_00

1 2

ref

VVodt_5

cloa

d

C92

1

75

R928Port2Port1

U14FBGA_00

1 2

ref

VVodt_6

cloa

d

C93

2

75

R939Port2Port1

U16FBGA_00

1 2

ref

VVodt_7

cloa

d

C94

3

VDDQ VSSQ VDDQ1

LDQ0

VDDQ

VSSQ

LDQ0_1

VDDQ

VSSQ

VDDQ

VSSQ

LDQ0 LDQ0_1

LDQ1

VDDQ

VSSQ

LDQ2

VDDQ

VSSQ

LDQ3

VDDQ

VSSQ

LDQ4

VDDQ

VSSQ

LDQ5

VDDQ

VSSQ

LDQ6

VDDQ

VSSQ

LDQ7

VDDQ

VSSQ

VDDQ1 LDQ1_1 VDDQ1 LDQ2_1 VDDQ1 LDQ3_1 VDDQ1

LDQ4_1 VDDQ1 LDQ5_1 VDDQ1 LDQ6_1 VDDQ1 LDQ7_1 VDDQ1

LDQ1LDQ2LDQ3LDQ4LDQ5LDQ6LDQ7

LDQ1_1LDQ2_1LDQ3_1LDQ4_1LDQ5_1LDQ6_1LDQ7_1

Eye diagram is useful for jitter analysis for DQ Bus. 1 DQ pin is Victim, another pin is Aggressor.

AggressorVictim

Source is text file.(voltage profile)

DDR2 Channel Jitter AnalysisJitter Noise analysis in Vodt pin (Within 2 % signal voltage)

Skew Analysis (LDQ Bus vs. LDQS)

Maximum Skew valueLDQS

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1n1

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1n1

n1n1

n1n1

n1n1

n1n1

n1n1

n1n1

n1n1

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

n1

0

c0

I/O

P OW E R

GND

logic_in

enable

I/O

P OW E R

GND

logic_in

enable

I/O

P OW E R

GND

logic_in

enable

negative

positive

V 44

negative

positive

negative

positive

V 53

Vn1

coax_core:S ource1

coax_gnd:S ource2

coax_core:S ink1

coax_gnd:S ink2

Vn1

Vn1

Vn1

Vn1

object1_Aobject1_B

Ground_B ias

coax_core:S ource1

coax_gnd:S ource2

coax_core:S ink1

coax_gnd:S ink2

negative

positive

V 133

Vn1

negative

positive

V 174

Vn1

terminals_1terminals_0

1

R242

terminals_1terminals_0

1

R243

object1_A

object1_B

Ground_B ias1

2

3

45

6

7

8

9

ref

1

2

3

45

6

7

8

9

ref

I/O

P OW E R

GND

logic_in

enable

P in_01:S ource1

P in_02:S ource2

P in_03:S ource3

P in_04:S ource4P in_05:S ource5

P in_06:S ource6

P in_07:S ource7

P in_08:S ource8P in_09:S ource9

P in_10:S ource10

P in_11:S ource11

P in_12:S ource12

P in_01:S ink1

P in_02:S ink2

P in_03:S ink3

P in_04:S ink4P in_05:S ink5

P in_06:S ink6

P in_07:S ink7

P in_08:S ink8P in_09:S ink9

P in_10:S ink10

P in_11:S ink11

P in_12:S ink12

coax_core:S ource1

coax_gnd:S ource2

coax_core:S ink1

coax_gnd:S ink2

coax_core:S ource1

coax_gnd:S ource2

coax_core:S ink1

coax_gnd:S ink2

P _J11_3_pos

P _J11_5_pos

P _J15_17_pos

P _J15_19_posP _J15_33_pos

P _J15_35_pos

P _K 44_3_pos

P _K 44_4_posP _K 48_3_pos

P _K 48_4_pos

P _K 89_3_pos

P _K 89_4_posP _K 93_3_pos

P _K 93_4_pos

P _K 140_3_pos

P _K 140_4_pos

P _K X 9_5_posP _K X 9_6_pos

P _U6_A E 22_pos

P _U6_A F17_pos

P _U6_B 4_posP _U6_C3_pos

P _U6_C18_pos

P _U6_D19_pos

P _U6_V 18_posP _V TT_pos

negative

positive

V 410

negative

positive

V 435

negative

positive

V 521 U6_B 4

U6_C3

pattern0101pattern_ZZZ_B 4

pattern_ZZZ_C3

pattern0101

pattern0101

V _dcin

V _dcin

U6_B 4

U6_C3

K 89_3

K 89_4

K 89_4 K 89_3

J11_3

J11_3

sig1

sig1

sig1_coax

sig1_coaxcoax_out sig1_coax_outcoax_out

insert

U1_C8

J43_1

coax_out_b

coax_out_b sig2_coax

sig2_coax

sig2

sig2J11_5

K 93_3 K 93_4

K 93_4

U6_A E 22

V _enable

sig1_coax_out

insert_d

insert_d

cio_d8

cio_r50

Board #1

Connector

Insert

Board #2

Coax_cable_40cm

Board #3

K89

K4T51_DQ

Insert

Full Channel Analysis

Allegro to SIwave

PCB modeling Connector/cable modeling

HFSS

F_connectorM_connector

Coaxial cable-> K89.4 -> K89.3 -> R489.1 -> J11.3U6.B4 -> RN1.1,4 U6.C3 -> RN1.2,3

K93.4 <- K93.3 <- J11.5U6.AE22 <- RP29.1,2L33.1,2 <- RP30.1,2

Coaxial cable

J44.1

U1.C8

J43.1

Board #1 Board #2

=> Need Nexxim ++

Q3D Extractor

FBDIMM

Electromagnetics is key to chip/package/board simulation

Model order reduction is key to bringing electromagnetics into circuit toolsThe new methodology provides an effective environment for chip/package/board co-design

Conclusions

Documents

Package Net Group Creation...NEXXIM / EM Co-Design 32ports S-Element IBIS PWR/GND Plane Impedance N-Ports S-Parameters 90 ohm Transient TDR (spec) Transient Eye Diagram w/Jitter Jitter