IP Modules for Motor Control FPGA/ASIC Integration

Y. Kebbati, Y. A. Chapuis, F. BraunLEPSI-IN2P3/ULP

23 Rue du Loess, BP 20 67037 Strasbourg, FRANCEkebbati@lepsi.in2p3.fr

AbstractThe authors of this paper presente a reuse

methodology based on Intellectual Property modules (IPmodules) for control algorithms of ac motor. Theypropose to build a IP-based ac motor control library forASIC (Application-Specific-Integrated Circuit) andFPGA (Field Programmable Gate Array) hardwaretargets. A methodology of IP conceptions is presented inthe case of a vector control algorithms which is quitewell-used in control ac motor. Moreover, an architectureof a specific IP module is developped and applied on awhole vector control structure called Direct TorqueControl (DTC). Finally, Hardware results and ASIClayout of the design also will be presented.

1. Introduction

Recently, new microprocessor solutions as specificDigital Signal Processor (DSP) have been developpedand adapted to digital motor drive implementation. In afirst application, the DSP was considered as a commonsolution for different algorithm implementations. Indeed,a DSP is based on a specific architecture which takesadvantages of software progammation and reuseflexibility. Afterwards, main DSP manufacturingcompanies started to propose DSP solutions includinghardware or software specific fonctions used in mostmotor control algorithms [1]. These solutions are usuallyassociated to a software environment as Matlab/Simulinkin order to help the designer and minimise the conceptiontime. Finally, the whole software design is build fromdifferent sub-algorithm blocks already defined andavailable. Although this approach is particularly adaptedto modern implementation of control algorithms, it alsoincreases strongly execution times and limits expansionpossibilities of the controller [2].

Recent development in Very Large Scale Integration- VLSI technologies started to change the way of digitalimplementation. Indeed, VLSI devices can reach veryhigh speed treatments, exploiting by example theparallelism presents in most algorithms. Also, thesetechnologies can be used to optimise the need inhardware development while applying high clockfrequency which allows to keep time performances.

However, in spite of the impressive recent expansion inmicroelectronics and Conception Aid Developers(CAD), a whole integrated circuit (IC) is still complexeto design, requiring a specific conception methodology[3]. The

, which is quite well-know in VLSI conception, can be easily applied for ICaimed to power driver applications and motor controlalgorithms. Recent developments propose to build an IC-based control algorithm from a specific library of hardmodules [4]. in a way, the last approach can be comecloser of the previously DSP implementation methode.

The authors of this paper presente a reusemethodology based on Intellectual Property modules (IPmodules) for control algorithms of ac motor. Theypropose to build a IP-based ac motor control library forApplication-Specific-Integrated Circuit (ASIC) and FieldProgrammable Gate Array (FPGA) hardware targets.After giving IP definitions, a methodology of IPconceptions is presented in the case of a vector controlalgorithms which is quite well-used in control ac motor.Finally, an architecture of a specific IP module isdevelopped and applied on a whole vector controlstructure called Direct Torque Control (DTC). Hardwareresults and ASIC layout of the design also will bepresented.

2. IP reuse

2.1. IP definition

The IP term encompassing all products, technology,software, and so forth that have been protected throughpatents, copyright and trade secrets (definition given byVirtual Socket Interface Alliance [5]). In this paper, wemean by IP, the silicon intellectual property that havebeen protected by laws. IP should not be considered asonly an Register Transfer Level (RTL) description orlayout ; it also includes know-how for implementing,validating, integrating, and verifying it.

2.2. IP categorisation

It is already common to classify IP in terms of theirreusable models : , ! and "$#%'& [5]. Depending on

toto totoVLSI-SOC 200111th International Conference on Very Large Scale Integrationdecember 3-5, Montpellier, France2-9517461-0-5

the type of a model, the flexibility, predictability, andcost vary. Figure 1 shows the different IP types.

Behavioral

RTL

Gates

Gates + Floorplan

Portable Layout

Fixed Layout

Soft

Hard

Firm

Pred

icta

bilit

y

Flex

ibili

ty

Figure 1 : IP types

Definition of each IP type is :

(*)+-,/.'021 The RTL descriptions are the primarysource of soft IPs today. Properly written RTLsources can be sythesized into most technologies, butthe freedom to change timing, area or power is not asgreat as in the case of behavioural models that can besynthesized via behavioural synthesis. Furthermore,the soft IP also permits FPGA implementation.

34576 8!92: Technology-mapped gate-level netlistconstitute a firm IP with less predictability thanlayout, but allow significant flexibility during placeand route. When technology-mapped gates (or logic)and predetermined floor-planning are used, theresulting firm IPs are both flexible and morepredictable.

;=A@CB!D2E IP delivered in GDSII data format solvesthe quality of implementation problem posed by thesoft IP. The component is fully optimized to a targettechnology and is ready to integrate into a design. Buthard IP is often not portable or flexible and may bedifficult to integrate if the physical implementationchosen by the IP vendor is incompatible with thephysical IC design methods chosen by the integrator.In others words, hard IP may create place and routeproblems due to their rigidity.

2.3. IP classification according to target

We propose to design IP in order to build a IP-basedac motor control library for ASIC and FPGA hardwaretargets. Consequently, we classify IP according to the

target chosen. For ASIC integration, the soft, firm andhard IPs can be used. However, in FPGAimplementation, we use only soft IPs to carry out a chip.

3. Reuse conception methodology

3.1. Modular conception approach

Reusability is one of the most advanced concept fortodays complex ASIC designs [6]. In fact, designers usethat concept to improve verification and FGHIJFKHLM'NOIF constraints. However, design reuse require aspecific methodology based on modular conceptionapproach. This methodology allows to handle verycomplex design with structured concept. Modular designproceeds by partitioning a system into modules. Theimplementation details of these modules are hidden.Proper partitioning allows independence between thedesign of the different parts. The decomposition isgenerally guided by structuring rules aimed to hide localdesign decisions, such that only the interface of eachmodule is visible [7].Structured design concept is based on the divide-and-conquer principle [8]. For VLSI design, it consists of thethree main steps in the design-flow : Partitioning can be applied on the system

specification in order to split the system into simplersubsystems or modules.

Each module thus generated can be designedindependently using specific library of components.

The abstraction of the system has to be done in orderto enable its reuse as a complex library element. Thisabstraction extracts the necessary information forsynthesis as data exchange protocols, physicalinformations, ...

3.2. IPs conception for motor control

3.2.1. From motor control algorithm to IPs

In figure 3, we apply the modular conceptionapproach in the case of a common control algorithms forac motor : the vector control [9]. In first step, calledalgorithm decomposition, the ac motor controlalgorithms can be decomposed in different independentsub-algorithms like : direct Concordia/Park, inverseConcordia/Park, space vector PWM, Hysteresis control,PI regulation, PID regulation, asynchronous motormodel,... as shown in figure 2.

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Figure 2 : IPs conception method for motor control

In the next step, called partition (hardware partition), wehave extract and define the hardware architecture ofdifferent reuse modules which will be called IPafterwards. For IP architecture definition, we havefollows some priciples as :

regroup the same sub-algoritms in one reuse module.

regroup the sub-algoritms that use the same hardwareressource.

regroup the specific sub-algorithms that can not usethe both principles defined previousely. However,this sub-algotims are very reused in vector controlalgorithms of ac motor.

This reuse modules are :

Interface module : In this module, we have regroupin one reuse module direct and inverseConcordia/Park sub-algorithms because they have asimilar algorithms.

Computation module : In the same way, System andRegulation models provide motor control algorithmexecution. It requires the same arithmetic operatorsas : multipliers, divider, cordic, ... and it can beregrouped in reuse module called Computationmodule.

Control module : The space vector PWM, three-phase sine PWM and Hysteresis control sub-algorithms have specific algorithms and can notdefine one architecture for all. Thus, according motordrive algorithm, the Control module is composed byan Hysteresis control or space vector PWM or three-phase sine PWM IP modules.

3.2.2. IPs modelisation and library structure

For reuse modules, we have developed a genericarchitecture in VHDL language at Register TransferLevel. Moreover, the ASIC integration is made in AMS0.6 m technology for 16 bits fixed point format. Thus,we dispose in IPs library for ac motor control hard, firmand soft reuse modules. The hard and firm IP is deliveredto designer only in AMS 0.6 m technology.Furthermore in our laboratory, we have develop a set ofarithmetic operators and their generic VHDL descriptionand ASIC integration .

In order to successfully handle design projects, it isnecessary to have a well defined data structure of library.This is even more important to reduce design time withreuse methodology. The database is defined on UNIXenvironment. It consists of the directory tree thatcontains VHDL source code, verification directory,synthesis directory ... . Figure 3 shows the generalstructure of IPs library for ac motor control.

!#"%$'&("*)+,)%-/.0214365/798#7#:

- Module design directory

- VHDL source code

- Verification directory- Testbench file- Module timing information

- Synthesis directory- Synthesis constraints- Netlist files- Report files

- Module documentation

; =?@A

- Layout file (AMS 0.6 m technology)

Figure 3 : IPs motor control library structure

The functional verification is made at differentlevels : behaviour, RTL, gates and layout. However, it isimportant to note that in submicron technology, theinterconnect becomes a major component inperformances. Thus, timing verification must take placeafter layout and must account for all interconnectsegments. Thus, we can not consider a node on a netlistto be a single point, it may be represented byinterconnect that travels all the way across a chip. In fact,any multipoint node can have all problems associatedwith clock trees [10].

In the next paragraphs, we will present anarchitecture of the Interface module. Afterwards, wevalidate the IP-based design methodology using anexample of a whole motor control integration with : thehard IP Interface module.

4. IP Interface module design

4.1. IP Interface module specification

The IP Interface module execute commonConcordia/Park algorithms. However, before integration,we must transform algorithm in numerical form. Itconsists to define for all real values B a data picturecalled C coded in D bits signed format. For the dataformat choice, a behaviour description in VHDLlanguage was developped which is used for simulationwith Leapfrog numerical simulator of Cadenceenvironment. Thus, we choose 16 bits fixed point formatfor all algorithm datas. This format is a goodcompromise between calculus accuracy and architectureressource. For IP module, the specifications is madethrough VHDL packages.

4.2. Architecture analyse of IP Interface module

To define Interface module architecture differentways can be proposed. However, both transformationsused in Concordia/Park algorithms need differentarithmetic operators. In order to reduce the size of thechip, we use only one operators of each type. Thus, wechoose a EGFIHF>JKFIHLNMKOQPQHSROITTSUVR model that mostly followsa W,XIY[Z]\V^K_a`IY architecture [11]. This universal modelcan be partitioned into two parts : an bdcfeVghQiSjklemcKhIgi , alsocalled nIoQpSodqKoIpr , and a sltQuQvSwtIxmyKzIwv or {V|I}Q~S|ISV . Thedatapath is the place where things happen, while thecontroller is the place where decisions are taken. Thecontroller consists of a finite state machine (FSM) whichinputs the external control signals and datapath flags, anddrives the operative parts through its control signals. Thedatapath is the execution part. It is composed of fourtypes of units : VdSQISdaKa : also called computation

unit execute operations specified in the algorithm.

9QI4d : hold the values of variables andconstants generated and consumed during theexecution of the algorithm.

aIGNSVQdSQS : construct the communicationnetwork for data transfers between storage units,functional unit and external ports.

KQ ,I/VQNG4lQdIN4 : realise the interfacesbetween external ports and the others units of thedatapath.

However, this approach is too specific in comparisonwith processor architecture. Here, the proposal is thatalgorithm treatment can be entirely optimised with agood compromise between size, speed, evolutivity andaccuracy. Thus, we add a program ROM to controllerthat include instructions for algorithm execution.The figure 4 shows the final Interface modulearchitecture. The controller manages data loading andtransmission in datapath. Also, It allows instructions

sequencements like reading, decoding and generatingcontrol signals. Controller operations are translated byinstructions which are integrated in a program ROM. Theprogram ROM is extended until 45 words of 12-bit.The controller works at 25 MHz. Each instruction have 2clock cycles (80 ns). The signal QVSQI (3 bits) allows toselect one of the Concordia/Park transformations toexecute. Also, a simple communication protocol (QSQand lQSQIQS ) is used to link Interface module toothers modules.

Reset

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Ready X1out

X1in X2in X3inSel_alg3 bits

X2out X3out X4out

X4in

ROM Program

ALU

StorageUnits

S1

S2 S3

Figure 4 : Interface module architecture

4.3. Conception of hard IP Interface module

In order to supply to designers a wide range of IPmodules for ac motor control integration, 2 Interfacearchitectures are developped. The first one calledQSV IVl

is based on *QII parallel multiplier andanother named Il VQlVQ use *QIQI]QI serialmultiplier. The two multipliers are two in-housedevelopping operators [12]. The Table 1 presentsQSV IVl

and ASIC hardware integrationresults with AMS 0.6 m technology. From Table 1, wenote that the designer have the choice to use one of

or !"# according design constraintsin size or in executive time.

Table 1 : IP Interface module ASIC results

Interface MultiplierExec-time

Clock InterfaceExec-time

Size

Interface_P 15 ns 40 ns 370 ns 2 mm2Interface_S 340 ns 40 ns 1 s 1 mm2

5. DTC integration from IP module

5.1. DTC Specification

The algorithm to be integrated is based on a classicdirect vector control for induction motor. However, inorder to validate reuse methodology with IP modules inthe case of motor control ASIC/FPGA integration, the$&%')(*+-,/.'102(435.6+').7

(8:9?@BACDEF)GHIJK= : direct Concordia, system model(flux and torque estimation), hysteresis control, fluxposition estimation and table of switching logic controlgeneration. Moreover, we have develop anotherarchitecture using one IP module from the globalarchitecture. In this case, we have replace the directConcordia part in global architecture by IP Interfacemodule (figure 5). The Interface module allows toimplement direct Concordia transformation through thesignal LMNOPNQ .

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In this case, we choose to use Interface module withBooth2 multiplier ( ). The figures 6(a), 6(b)show the two DTC ASIC layout.

B1tbYj )b^bb

1b

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(a) DTC Specific layout (b) DTC layout from hard IP

Figure 6 : The two DTC layouts

Table 2 presents ASIC hardware implementationresults in AMS 0.6 m technology.

From table 2, it is clear that specific DTC architecturehave better integration performances than based on hardIP interface module. However, the use of IP module tobuild a design permit a significant gain on conceptionand debugging time. Beside, the Concordia/Parktransformation is very used in motor control algorithmsand the use IP Interface two or three times allow tojustify design for reuse.

Table 2 : DTC ASIC integration

DTC Format Clock Exec-time AreaSpecific 16 bits 40 ns 1.8 s 7.7 mm2

From IP 16 bits 40 ns 2.4 s 11 mm2

6. IPs library developpement

After the validation presented previousely, we havecontinue to implement the different motor control sub-algorithm in the three reuse modules (Interface,Computation and Control). The table 3 summarize thishard implementation in AMS 0.6 m technology.

Table 3 : Features of IP modules library

IP modules Format(bits)

Clock(Mhz)

Executiontime

Area(mm2)

Interface- Interface_S- Interface_P

1616

2525

1 s370 ns

12

Computation- PI 16 25 880 ns 3

Control-Three-phasesine PWM-Hysteresiscontrol

12

16

25

25

-

110 ns

2.5

0.4

6. Conclusion

This work presented IP modules conception for motorcontrol FPGA and ASIC integration. The reusemethodology was used to create IP modules library thatis suitable to develop motor control applications. Besidein order to validate IP-based on reuse methodology, wehave applied IP Concordia/Park (Interface module) tobuild DTC architecture. The ASIC integrationperformances was presented. Moreover, the use of IPmodule permits a significant gain on conception anddebugging time. Besides, the use of IP module two orthree times allows to justify design for reuse. In a nearfutur, the IP-based reuse methodology should be used inmost motion control hardware integration.

7. References

[1] S. Beierke, J.C. Soroka ans P. Vas DSP-BasedIntelligent Motion Control, European Power ElectronicConference (EPE) proceeding, Aug. 2001.

[2] Y.Y. Tzou and J.J. Jyang A programmable CurrentVector control IC for AC Motor Drives, IEEE IECONConference proceeding,. pp. 216-221, Nov. 1999.

[3] J.C.G. Pimentel and H. Le-Huy A VHDL-BasedMethodology to develop High Performance ServoDrivers, IEEE Industrial Application Society (IAS)Conference proceeding, Oct. 2000.

[4] T. Riesgo, Y. Torroja, E. De la Torre DesignMethodologies Based on Hardware DescriptionLanguages, IEEE Transaction on Industrial Electronics,Vol. 46, Feb. 2000.

[5] Virtual socket interface architecture documentation,VSI Alliance, www.vsi.org, Nov 1996.

[6] C.A Mead and L.A Conway, Introduction to VLSIsystems , Addison-Wesley Publishing, March 1980.

[7] A.A Jerraya, H. Ding, P.Kission and M.Rahmouni, Behavioral synthesis and componentreuse with VHDL , Kluwer Academic Publishers,1997.

[8] R. Seepold and A. Kunzmann, ,Reuse Techniques for VLSI Design , Kluwer AcademicPublishers, 1999.

[9] W. Leonhard, Control of Electrical Drives,Springer Verlag, 1985.

[10] T. Thomas, Technology for IP reuse andportability , IEEE design & test of computers, Oct-Dec1999.

[11] J. L. Hennessy and D. A. Patterson, !"##$

, Architecture des ordinateurs , EdiscienceInternational.

[12] H. S. Kebbati, J. P. Blonde, F. Braun, A CMOSstandard cell based parallel 32x32 bits signedmultiplier , Design of Circuits and Integrated SystemsConference (DCIS) proceeding, Nov 2000.

[13] I. Takahashi and T. Noguchi, A new quickresponse and high efficiency control strategy of aninduction motor , IEEE Industry Applications Society(IAS) Conference Proceeding, pp. 495-502, 1985.

[14] Y. Kebbati, C. Girerd, Y. A. Chapuis, F. Braun, Advances in FPGA/ASIC digital integration solutionsfor vector control of motor drives , International PowerElectronics Conference (IPEC) proceedings, April 2000.