November 16, 2001 ElectricalP. Earle p1

SNAPElectrical Design Estimates

November 16, 2001C. Paul Earle

Super Nova/Acceleration Probe

November 16, 2001 ElectricalP. Earle p2

Figure 1.

Scene

Dooropen / close

FocusControl

ReadoutControl Logic

FPE

Instrument Control

Electronics

Dat

a B

uff

eri

ng

Thermal Control & Monitoring

FPA

Det

ec

tors

Sh

utt

er

Fil

ters

CD

S

A/D

DC-DCConverter

1553 I/F

Science Data I/F

Mass Storage(S/C)

ICE

SNAP Functional Block Diagram

S/C Power

S/C C&DH

Do

or

Spectrograph

ShutterControl

Bright ObjectDetector

A/D

November 16, 2001 ElectricalP. Earle p3

200Secintegration

20Ssecreadout

220Sec

Science Data Rate

FPA Size:

144 CCDs @ 1.6Kx1.6K each ~ 368.6 Mpix

44 HgCdTe @ 2Kx2K each ~ 176 Mpix

Spectrograph: 1Kx1K ~ 1Mpix

Average Data Rate:

==> 545 Mpix for each 200Sec exposure

==> Data rate (avg) ~ (545Mpix/220Sec) ~ 2.5Mpix/s

~ 40 Mbps @16-bits/pix

~ 20 Mbps (with 2:1 loss-less compression)

November 16, 2001 ElectricalP. Earle p4

CCD Readout ASIC (3” x 3”) each• 4 A/Ds• 4 CDS chips (Correlated Double Sampling)• Bias & Power Generation• Sequencer & Clock Drivers

188 Readout ASICs~ 10 boards (12” x 12”) 18 ASICs each, 9 ASICs per side 2 boxes ~ (13.5”x13.5”x6”) each ~ 9lbs each Total Power: 156Watt (peak), 22 Watt (avg.)

Focal Plane Electronics

November 16, 2001 ElectricalP. Earle p5

Requirements:

- 70 zones, controlled within +0.5 deg. C of set point- 1 Heater and 1 Temperature Sensor per zone- Each CCD controlled within +0.1 deg. C of set point- Unregulated Heater Power (120Watts)

Thermal Control

HeaterSensor(AD590)

i (T)

V+

(1 of 258)

CurrentTLM

V+ V+

Figure 2.

November 16, 2001 ElectricalP. Earle p6

CCD Temperatures

Mux16-chAD506

.

.

.

A/D Conv.

AD 1672

To Memory

PowerTemp...

H/KFIFO

+

-V-

V-

Housekeeping Data

Figure 3.

CCD temps(188)

Mux16-chAD506

A/D Conv.

AD 1672

To MemoryH/KFIFO

Zone Temperatures & Other Telemetry points

(1 of 11)

(1 of 5)

November 16, 2001 ElectricalP. Earle p7

FIFOBuffer

Readout Data Buffering

To Storage

Figure 4.

Capture& Control LogicFPGA

(1 of 1)

Processor Card I/F

DigitalMUX(4:1)

CCD I/F

FPE I/F

4 1

(1 of 188)

(1 of 188)

November 16, 2001 ElectricalP. Earle p8

On/Off CmdFrom PLDController

DriverAmp

I+

-+

-+

Door

Actuator

TempSensor

SensorAmp

HK

Mux

+

-

ToCentral HK

Actuator Current

Actuator Voltage

Mechanism Control

Figure 6.

(Door Control Electronics)

November 16, 2001 ElectricalP. Earle p9

CPUUTMC69R000

Processor & Memory Board

Startup ROM

EEPROM Memory(Data Processing)

Ethernet I/F

1553 I/F

1553 I/F

xcvrxfmr

xcvr

xfmr

xfmr

xfmr

RAM(Data Processing)

S/W Dev.

Figure 5.

November 16, 2001 ElectricalP. Earle p10

DC/DCConverters

+28 VDC

Power Distribution

Figure 7.

-+Current Sense

-+Voltage Sense

+15 VI+

+5 VI+

End Items Avg. Power

Main Power Board

20 Watts

Thermal Control 12 Watts

Main Processor 4 Watts

Mechanism Control

6 Watts

Housekeeping 16 Watts

Data Buffering 9 Watts

FPE Power Boards

9.4Watts(33Watts peak)

FPE Boxes 22Watts(156 Watts peak)

Main Box Total: 76.4 Watts

Mechanisms 4 Watts

Thermal S/S 100 Watts

Instrument Total:

202 Watts

November 16, 2001 ElectricalP. Earle p11

Figure 8.

Board Estimates

Thermal Control (4W)

Thermal Control (4W)

Thermal Control (4W)

9 in

10 in

Data Buffer (3W)

Data Buffer (3W)

Data Buffer (3W)

Processor (4W)

Mech Control (6W)

Housekeeping (16W)

Main Power (20W)

FPE Power (9.4W)

November 16, 2001 ElectricalP. Earle p12

Figure 9.

Main Electronics Box Summary

11 in

19 in

10 in

Estimated Mass ~ 44 lbsEstimated Power ~ 76 Watts (avg.) Estimated Size ~ (19 x 11 x 10) in.