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von Neumann architecture All contemporary computer design are base on three key concepts : Data and instructions are stored in a single read-write memory. The contents of this memory are addressable by location Execution occurs in a sequential fashion from one instruction to the next
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Overview v on Neumann Architecture Computer component Computer function Instruction set CPU Memory I/O
von Neumann architectureAll contemporary computer design are base on three key concepts : Data and instructions are stored in a
single read-write memory. The contents of this memory are
addressable by location Execution occurs in a sequential fashion
from one instruction to the next
Computer Component Arithmetic and Logical Unit (ALU) Control Unit (CU) Memory Unit I/O devices
Central Processing Unit (CPU)
Storage devices System bus
Computer Function The b asic functi on is program execut
ion. The Program to be executed consists
of a set of instruction stored in memory.
The CPU does actual work by executi ng instructions specified in the progr
am.
Instruction Sets Instruction : An individual pattern
which instructs the computer to do a task.
Consists of two part OP-code Operand or Address
Instruction set classifies CPU into model or family
Central Processing Unit (CPU) Processor Where the data are manipulated
by executing instruction Two basic parts are
Control Unit (CU) Arithmetic and Logical Unit (ALU)
Computer Component
Executing InstructionInstruction cycle Fetch cycle : CPU read (fetches)
instructions from memory one at a time.
Execution cycle : CPU executes each instruction
Instruction CycleStart
halt
Are the Instruction awaiting execution?Fetch the next instruction
Execute the instructionAre there interrupts require services?
Transfer control to interrupt handling program
Yes
Yes
No
No
Control Unit (CU) Controls each part of components
to perform instruction or program procedure
load program into memory fetch instruction one at a time decode, create and send control signal
s
CPU
Control Unit Components The CU has three components
Program Counter(PC): contains the address of the next instruction to be executed
Instruction Register (IR) : holds the actual instruction that is being executed
Instruction Decoder : determines the type of operation currently in the IR and sends control signal to implement that operation
CPU
Control Unit Function Instruction sequencing : selects
instruction from memory to executed
Instruction Interpretation : interprets and sends control signals to CPU through control lines
Instruction sequencing PC = PC’ + K PC : next instruction address PC’: previous instruction address k : instruction length
Op Code Address 0 3 4 15
(a) Instruction Format0001 = Load AC From Memory0010 = Store AC To Memory0101 = Add to AC from Memory
(b) Partial List of Opcodes
Example of program execution1 9 4 05 9 4 12 9 4 1
300301302
3 0 0
1 9 4 0
PCACIR
CPU Registers0 0 0 30 0 0 2
940941
... ...1 9 4 05 9 4 12 9 4 1
300301302
3 0 0 0 0 0 31 9 4 0
PCACIR
0 0 0 30 0 0 2
940941
... ...
1 9 4 05 9 4 12 9 4 1
300301302
0 0 0 30 0 0 2
940941
... ...1 9 4 05 9 4 12 9 4 1
300301302
0 0 0 30 0 0 2
940941
... ...
1 9 4 05 9 4 12 9 4 1
300301302
0 0 0 30 0 0 2
940941
... ...1 9 4 05 9 4 12 9 4 1
300301302
0 0 0 30 0 0 5
940941
... ...
11 22
33 44
55 66
3 0 1 0 0 0 35 9 4 1
PCACIR
3 0 1 0 0 0 55 9 4 1
PCACIR
3 0 2 0 0 0 52 9 4 1
PCACIR
3 0 2 0 0 0 52 9 4 1
PCACIR
316 + 216 = 516
Control Unit
ALUInput data Output data
C’’ in C” outC’ in C’ out
Instruction Interpretation
Implementation Method Hardwired Control Unit Microprogram Control Unit
Arithmetic and Logical Unit (ALU)The ALU has two part Functional unit : perform the
operation (arithmetic operations and logical operations)
Register : hold operands, results, errors and status information
CPU
Functional Unit Arithmetic
integer adder integer subtractor integer multiplier integer divider arithmetic shift unit incrementor & decre
mentor - floating point arithm
etic unit
Logical comparator logic shift unit NOT unit AND unit OR unit
CPU
Operation of functional unit Arithmetic
+ add- subtract* multiply/ divide^ raise by a power
Logical=, = equal, not equal >, > greater than,
not greater than<, < less than,
not less than>, > greater than or
equal, not ...<, < less than or
equal, not ...
CPU
Diagram of functional unitStart/Stop signalfrom control unit
Timing signal
Z := X op YopX
Y
Z
E
Left
Right
Result
Error/Status
Control signalData
? Register
CPU
Register high-speed memory location contain data for functional unit register size -> word size
16-bit processor 32-bit processor 64-bit processor
CPU
Register Type Accumulator register : operand,
result Index register : address Special-purpose register
Overflow register Carry register Shift register Temporary register
Stack register Floating-point register Status information register
General purpose register
CPU
Register & Memory reference by name instead of
unsigned binary address : A, R1 higher speed than memory use for specific job, not general job use specific path for transfer data
CPU
Processor families Intel : Pentium AMD : K6, K7 Cyrix : Cyrix Motorola : 680X0
Memory Stores and retrieves (fetch) information It is divided into cells , and data are acce
ssed by means of the unique address of the cell.
2n - words of m bit memory with address es 0 ,1 ,2 ,…,2 n-1
Computer Component
Access data in memory Store
นำ�ขอ้มูลเข�้ไปบรรจุใน memory ณ ตำ�แหน่งท่ีระบุ
Fetch ดึงขอ้มูลจ�ก memory
Memory component Memory Address Register(MAR): contains the
address of the word we want to store or fetch
Memory Buffer Register (MBR) : contains the contents of the location we want to do with
Decoder : decodes address to be the location Read/Write Control Lines : provides the signal
to control the memory perform a fetch or stor e operation.
address00000001000200030004………………2n-1
size
m-1 .. .. .. ... 2 1 0Memory width
Decoder
MBR
MARRead control linesWrite control lines
Flow of informationControl Signal
Memory component
Read procedure Stores address of data in MAR. Sends read signal through read control
line. Decodes data in MAR to be the location
in memory bank. Reads data from that location and
stores in MBR.
Write procedure Stores address of data in MAR. Stores data we want to write in MBR. Sends write signal throgh write control li
ne. Decodes data in MAR to be the location i
n memory bank. Writes data in MBR into that location.
Memory Hierarchy Register Caches : L1, L2, .. Main Memory Magnetic Disk Magnetic Tape
Characteristics Location
CPU Internal External
Capacity Word size Number of words
Unit of Transfer Word Block
Access Method Sequential Direct Random Associative
Characteristics (cont.) Performance
Access time Memory cycle
time Transfer rate
Physical type Semiconductor Magnetic surface
Physical characteristics Volatile/Non-
volatile Erasable/Non-
erasable
RAM Random Access Memory
EDO RAM (Extended Data-Out RAM) DRAM (Dynamic RAM) SRAM (Static RAM) SDRAM (Synchronous DRAM) DDR SDRAM (Double Data Rate
SDRAM) VRAM (Video RAM)
ROM Read only memory : contain a
permanent pattern of data for starting a computer to work
ROM Typed PROM (Programmable ROM) EPROM (Erasable ROM) EEPROM (Electrical Erasable PROM)
Data in ROM Important memory routines of
system Loader program Compiler and interpreter Important error-recovers
procedures some part of Operating System
Cache Memory Disk cache Memory cache
L1 cache : internal cache L2 cache : external cache
CPU L2 Cache MainMemory
L1Word transferBlock transfer
Input/Output I/O module I/O function I/O devices components Data transfer Techniques
I/O Module The entity with in a computer responsible for
the control of one or more external devices and for the exchange of data between those devices and main memory and/or CPU register.
The major function for an I/O module control and timing CPU communication Device communication Data buffering Error detection
I/O Function The third key element of a computer is
a set of I/O module. Each module interface to the system
bus or central switch and controls one or more peripheral devices.
I/O module contains logic for performing a communication function between the peripheral and the bus.
The Component of I/O devices I/O Mechanism
The mechanical, electrical that make up I/O devices
I/O ControllerThe component that manages the flow of information between the I/O device and
the computer
Data Transfer Techniques Programmed I/O Interrupt Driven I/O DMA I/O Controller
Programmed I/O Data are exchanged between the CPU and
the I/O module. The CPU executes a program that gives it
direct control of the I/O operation. When the CPU issues to the I/O modules,
it must wait until the I/O operation is complete.
If the CPU is faster than the I/O module, this is wasteful of CPU time.
Issue read command to I/O module
Read statusof I/O module
Check status
Read word fromI/O module
Write word intomemory
Done?Yes
No
ReadyError Condition
NotReady
CPU --> I/O
I/O --> CPU
I/O --> CPU
CPU --> Memory
Programmed I/OProgrammed I/O
Interrupt-Driven I/O The CPU send START signal to I/O
controller for start working. After send signal, the CPU can continue
their jobs When I/O controller finish work, it send
interrupt signal to the CPU The CPU suspend their works and load
data into memory
Issue read command to I/O module
Read statusof I/O module
Check status
Read word fromI/O module
Write word intomemory
Done?Yes
No
ReadyError Condition
Do Something ElseCPU --> I/O
I/O --> CPU
I/O --> CPU
CPU --> Memory
Interrupt-Driven I/OInterrupt-Driven I/O
Interrupt
DMA I/O Controller Consist of 2 registers
DAR (DMA Address Register) : stores address of data in memory
WC (Word Count Register) : specifies data size to write in memory
DMA I/O Controller (cont.) Store address of data in DAR Store size of data in WC Send START signal to I/O Controller When finishing data transfer, it send
interrupt signal to the CPU
Issue read blockcommand to DMA moduleRead statusof DMA module
Do Something ElseCPU --> DMA
DMA --> CPU
Direct Memory AccessDirect Memory Access
Interrupt