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Overview of the read-out electronics for the TPCs at T2K ND280m. P. Baron, D. Calvet , X. De La Broïse, E. Delagnes, F. Druillole, J-L Fallou, J-M. Reymond, E. Virique, E. Zonca DSM/DAPNIA/SEDI, CEA Saclay 91191 Gif-sur-Yvette Cedex, France. Plan. Context TPC Read-out Architecture Summary. - PowerPoint PPT Presentation
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Overview of the read-out electronics for the TPCs at T2K ND280m
P. Baron, D. Calvet, X. De La Broïse, E. Delagnes, F. Druillole, J-L Fallou,J-M. Reymond, E. Virique, E. Zonca
DSM/DAPNIA/SEDI, CEA Saclay 91191 Gif-sur-Yvette Cedex, France
[email protected] 3 Paris 12 September 2006
TPC Configuration
Features
• 3 TPCs stations; each with 2 planes of 2 x 6 detector modules
• Each detector module: Micromegas, 27-30 cm square
• Module segmentation: 1728 pads of 9.7 mm x 6.9 mm
• Total number of pads: 124.416
• 512 space points in z-axis, (2.5 mm spacing)
3 TPC stations
1 m
2.5 m
x
y
z
2.5 m
Detector module
[email protected] 4 Paris 12 September 2006
Outline of Requirements
Non Functional and Environmental
• Compact, low power, modest magnetic field (0.2 T), no radiation
• Underground experiment (Japan), fire and seismic safety rules
Functional and Performance
• Noise, dynamic range, resolution, linearity
SNR=100 (i.e. 700 e- rms for 12 fC MIP), 10 MIP on 12 bits, 1-5%
• Event rate: ~0.3 Hz spill + cosmic. For DAQ: 20 Hz mean and max.
• 512 space points, various gas: 14-500 µs drift (1.25 m drift distance)
• Support for GEM and Micromegas charge amplification technology
Demands on front-end electronics and data acquisition
• Highly segmented detector (124 k channels)
• Extreme burstiness of initial data (several Tbaud/s peak)
• Large event size (90 MB) but modest event rate (few Hz)
→ Strategy: re-use ALTRO based electronics for detector R&D;
while designing new read-out electronics
[email protected] 5 Paris 12 September 2006
Complete Logical Read-Out Flow
Architecture principles
• Front-end ASIC with analog memory (Switch Capacitor Array)
• ADC + digital buffer mounted close to the detector
• Multiple optical fibers send data to off-detector concentrators
• Interface to common DAQ via standard network
Pre-amp and shapers
Samplers and analog memory buffers
Analog to digital conversion
Digital buffer
Data concentration
~124.000 channels
1728 Frontend ASICs
On-detector electronics
72 Optical fibers
1-6 Tbaud*/s peak*1 baud = 10 bit
~2 ms retention max.
34 Gbaud/s peak
400 Gbit/s peak
~1-10 Gbit/s averaged
Shared DAQ system~0.1-1 Gbit/sStandard LAN
connection(s)
432 Frontend cards
6 Concentrator Cards
72 Mezzanines
[email protected] 6 Paris 12 September 2006
Detector Module Read-out
72 modules in total
72-channel ASIC
Quad-channel ADC
digital Front-endMezzanine card (FEM)
Optical Transceiver
FPGA
80-pin connector
288-channel analogFront-End Card (FEC)
1728-pad detector plane
Slow-controlnetwork
Fiber toDCC
Power bar Low-voltagepower
[email protected] 7 Paris 12 September 2006
TPC Plane Readout Off-detectorInside the Magnet
• 1 of 6 TPC planes shown – 3 TPC stations
• 6 x 2 detector modules per TPC plane – 72 modules in total
• 1 duplex optical readout fiber per detector module
• 1 external data concentrator per TPC plane – 6 concentrators in total
Data Concentrator Card
DetectorModule
12 opticalfibers
Front-End Card
TPC plane
Front-EndMezzanine card
Optical link
x 6
[email protected] 8 Paris 12 September 2006
TPC Event Building, DAQ Interface
Principles
• Event Building for TPC data over backplane bus with a PC or each concentrator send data directly to the DAQ via a LAN connection
• Interface to common DAQ system via standard Gigabit Ethernet LAN
• TPCs (like other detectors) compliant to the experiment wide physical interface specifications, protocols and software framework
TCP/IP
CommercialLinux PC
6 concentrators
VME/PCIbackplane bus
GigabitEthernet
NetworkCommonDAQ
Run Control
DetectorB
DetectorA
Detector TPCsGlobal ClockTrigger
[email protected] 9 Paris 12 September 2006
Front-end ASIC Synopsis
Serial Interface
Trigger
CK
In Test
512 cells
SCAFILTER
Tpeak;Gain
CSA
1 channel
X64
BUFFER
SLOW CONTROL
TEST
SCA MANAGER
Stop CK
ADC
Asic T2K
GAIN
Number of channels 72 Sampling frequency 1MHz to 50MHz
Number of Time bins 511 Shaping Time 100ns to 2µs
MIP 12fC to 60fC Read out frequency 20 to 25MHz
MIP/noise 100 Signal Polarity Negative (TPC) or positive
Dynamic range 10 MIPS on 12bits Calibration Selection 1/72
I.N.L 1% [0-3 MIPS];5% [3-10 MIPS] Test 1 capacitor / channel
Gain Adjustable (4 values)
[email protected] 10 Paris 12 September 2006
Front-end ASIC: AFTER
AFTER : Asic For Tpc Electronic Read-out
Technology: Technology: AMS CMOS 0.35AMS CMOS 0.35m m
Area: Area: 75467546m x 7139 m x 7139 mm
Submission: Submission: 24 April 200624 April 2006
Delivered: Delivered: end of Julyend of July
Package: Package: LQFP 160 pins; PlasticLQFP 160 pins; Plasticdimensions: dimensions: 30mm x 30mm 30mm x 30mm thickness: thickness: 1.4mm 1.4mm pitch:pitch: 0.65mm 0.65mm
Number of transistors: Number of transistors: 400,000 400,000
SCA:76x511 Cells
[email protected] 11 Paris 12 September 2006
Analog Front-end Card
Features
– 6 Analog Front-end cards per detector module; i.e. 432 cards in total
– Throughput: 0.96 Gbps per card, 414 Gbps total
– Plugs at the back of detector plane; inside the magnet – water cooling
– Conceptual design in progress – first prototype expected Q2-Q3 2006
ASIC ASIC ASIC ASIC
4 channelADC
Passive Components
Connectors to detector plane
288 channel FE card
Digital output
~25 cm
~14 cm
[email protected] 12 Paris 12 September 2006
ASIC Test Card
Features
– Essentially FEC pre-prototype; 4 ASICs (1 socketed)
– Board under assembly; expected in the next few days
ZIF Socket
Interface connector to FEM
[email protected] 13 Paris 12 September 2006
Connector Evaluation: Detector R&D
The GEM and Micromegas detector R&D on HARP used the proposed connector on the protection card
→ Proposed connector is now validated
Protection Card
PrototypeMicromegas
Detector plane
[email protected] 14 Paris 12 September 2006
Digital Front-end Mezzanine Card
Architecture
– Commercial FPGA, memory and optical transceiver
– Target: Xilinx Virtex-2 Pro / Virtex 4 with RocketIO transceiver
– Design in progress – supports 4-6 FE cards
– First prototype: end 2006; i.e. 6 months after number of FE card frozen
Analog FECard
ClockTriggerControl
Data1.2 Gbit/s peak
Analog FECard
Analog FECard
Analog FECard
FPGALogic
Memory~6 Mbit
~5 Gbit/s
~12 Mbit/s
~5 Gbit/s
ClockTriggerControl
Optical LinkAverage rate < 50 Mbit/s
Digital Front endMezzanine Card
[email protected] 15 Paris 12 September 2006
Reduced FEM card
Architecture
– Daughter card for a commercial Memec FPGA kit; can drive one FEC
→ Setup used for ASIC test, and prototype boards validation
[email protected] 16 Paris 12 September 2006
Off-Detector Concentrator Card
Principles
• Standard form factor (6U or 9U); VME or Compact PCI backplane bus
• Clock, trigger and control signals fanout, slow control interface
FPGAlogic
VME orPCI
Opticaltransceivers
Main data 1-2 Gbit/s
Slow control data
Slow control commands
Global clock
TriggerGlobal clock
Trigger
Slow control
Main data
[email protected] 17 Paris 12 September 2006
Integration, Resources On-detector Electronics
• Power supplies and power distribution, forced cooling; 3 kW
Common/shared services
• Trigger generation
• Global clock source and inter-detector synchronization
• DAQ hardware interface and software
• Slow control, configuration, monitoring
• Racks, type of crate, common hardware/software platforms
• Cooling water and heat exchanger
Resources for TPC electronics
• ~30 FTE (Saclay, Lpnhe, Barcelona); investment: ~480 k€
Planning
• 1 TPC detector module equipped with prototypes in mid-2007
• Mass production of electronic cards and tests in 2008
• Installation and commissioning for operation in April 2009