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OVERVIEW OF DIGITAL SYSTEMS

Hardware Description Language

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DEFINITIONA hardware description language is the

language that describes the hardware of digital systems in textual form and resembles a programming language, but specifically oriented to describing hardware structures and behavior.

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HARDWARE DESCRIPTION LANGUAGE (HDL) Basic idea is a programming language to

describe hardware Initial purpose was to allow abstract design

and simulation Design could be verified then implemented in

hardware Now Synthesis tools allow direct

implementation from HDL code. Large improvement in designer productivity

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HARDWARE DESCRIPTION LANGUAGE (HDL) HDL allows write-run-debug cycle for

hardware development. Similar to programming software Much, much faster than design-implement-debug

Combined with modern Field Programmable Gate Array chips large complex circuits (>100000s of gates) can be implemented.

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Advantages of HDL

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HDLS There are many different HDLs

Verilog HDL ABEL VHDL

VHDL is the most common Large standard developed by US DoD VHDL = VHSIC HDL VHSIC = Very High Speed Integrated Circuit

Verilog HDL is second most common Easier to use in many ways = better for teaching C - like syntax

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STANDARD HDL SUPPORTED BY IEEE VHDL – (Very high speed integrated circuit

Hardware Description Language) ) became IEEE standard 1076 in 1987. It was updated in 1993 and is known today as "IEEE standard 1076 1993

- a Department of Defense mandated language that was initially used by defense contractors, but is now used commercially and in research universities.

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STANDARD HDL SUPPORTED BY IEEEVerilog – ". The Verilog hardware description

language has been used far longer than VHDL and has been used extensively since it was launched by Gateway in 1983. Cadence bought Gateway in 1989 and opened Verilog to the public domain in 1990. It became IEEE standard 1364 in December 1995.

- a proprietary HDL promoted by a company called Cadence Data systems, but Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI).

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A TALE OF TWO HDLSVHDL Verilog

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DIGITAL DESIGN USING VERILOG

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HISTORY

Paper or breadboardGate level

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• Too low-level for initial functional specification

• Early high-level design explorationAbstract behavioral model

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VERILOG HDL Verilog constructs are use defined keywords

Examples: and, or, wire, input output One important construct is the module

Modules have inputs and outputs Modules can be built up of Verilog primatives or

of user defined submodules.

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We will use Verilog…

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VERILOG CAPABILITIES

Primitive logic gates , such as and, or and nand, are built-in into the language.

It has built-in logic functions such as & (bitwise-and) and | (bitwise-or).

Flexibility of creating a user-defined primitive (UDP). Such a primitive could either be a combinational logic primitive or a sequential logic primitive.

Switch-level modeling primitive gates, such as pmos and nmos, are also built-in into the language.

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VERILOG CAPABILITIES Explicit language constructs are

provided for specifying pin-to-pin delays, path delays and timing checks of a design.

A design can be modeled in three different styles or in a mixed style. These styles are: behavioral style- modeled using procedural constructs; dataflow style – modeled using continuous assignments; and structural style- modeled using gate and module instantiations.

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VERILOG CAPABILITIES There are two data types in Verilog

HDL; the net data type and the register data type.

Hierarchical designs can be described, up to any level , using the module instantiation construct.

A design can be of arbitrary size. Verilog HDL is non-proprietary and is

an IEEE standard. It is human and machine readable.

Thus, it can be used as an exchange language between tools and designers.

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VERILOG CAPABILITIES The capabilities of the Verilog HDL

language can be further extended by using the programming language interface (PLI) mechanism.

A design can be described in a wide range of levels, ranging from switch-level, gate-level, register-transfer-level (RTL) to algorithmic-level, including process and queuing-level.

A design can be modeled entirely at the switch-level using the built-in switch-level primitives.

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VERILOG CAPABILITIES

switch algorithm

gate switch

RTLgate

Mixed-Level Modeling

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VERILOG CAPABILITIES The same single language can be used

to generate stimulus for the design and for specifying test constraints, such as specifying the values of inputs.

Verilog HDL can be used to perform response monitoring of the design under test.

High-level programming language constructs such as conditionals, case statements, and loops are available in the language.

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Notion of concurrency and time can be explicitly modeled.

Powerful file read and write capabilities are provided.

The language is non-deterministic under certain situations.

Verilog Capabilities

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QUICK TUTORIAL OF THE LANGUAGE

Module. The basic unit of description and is the building block in Verilog. It describes the functionality or structure of a design and also describes the ports through which it communicates externally with other modules.

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EXAMPLE: SIMPLE CIRCUIT HDLmodule smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e;

and g1(e,A,B); not g2(y, C); or g3(x,e,y);endmodule

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BASIC SYNTAX OF A MODULEmodule module_name (port_list);

Declarations: reg,wire,parameter,

input,output,inout, function, task,… Statements: Initial statement Always statementModule instantiationGate instantiationUDP instantiationContinuous assignmentendmodule

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EXAMPLE

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FULL ADDER

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FULL ADDER

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FULL ADDER

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