Overview of Chapter 4 °Design digital circuit from specification °Digital inputs and outputs known Need to determine logic that can transform data °Start

Overview of Chapter 4

° Design digital circuit from specification

° Digital inputs and outputs known• Need to determine logic that can transform data

° Start in truth table form

° Create K-map for each output based on function of inputs

° Determine minimized sum-of-product representation

° Draw circuit diagram

Design Procedure (Mano)

Design a circuit from a specification.

1. Determine number of required inputs and outputs.

2. Derive truth table

3. Obtain simplified Boolean functions

4. Draw logic diagram and verify correctness

A00001111

B00110011

C01010101

R00000001

S01111111

S = A + B + CR = ABC

Previously, we have learned…

° Boolean algebra can be used to simplify expressions, but not obvious:• how to proceed at each step, or

• if solution reached is minimal.

° Have seen five ways to represent a function:• Boolean expression

• truth table

• logic circuit

• minterms/maxterms

• Karnaugh map

Combinational logic design

° Use multiple representations of logic functions

° Use graphical representation to assist in simplification of function.

° Use concept of “don’t care” conditions.

° Example - encoding BCD to seven segment display.

° Similar to approach used by designers in the field.

BCD to Seven Segment Display

° Used to display binary coded decimal (BCD) numbers using seven illuminated segments.

° BCD uses 0’s and 1’s to represent decimal digits 0 - 9. Need four bits to represent required 10 digits.

° Binary coded decimal (BCD) represents each decimal digit with four bits

a

b

c

g

e

d

f

10019

00018

11107

01002

10001

00000

BCD to seven segment display

0 a,b,c,d,e,f1 b,c2 a,b,d,e,g3 a,b,c,d,g4 b,c,f,g5 a,c,d,f,g6 a,c,d,e,f,g7 a,b,c8 a,b,c,d,e,f,g9 a,b,c,d,f,g

a

b

c

g

e

d

f

° List the segments that should be illuminated for each digit.


.0111110019

.1111100018

.0011111107

.

.1101101002

.0011010001

.1111100000

.edcbazyxwDec

° Derive the truth table for the circuit.

° Each output column in one circuit.

Inputs Outputs


1 0

10

1 1

1 1

11

yz

wx

10

11

01

00

10110100

For segment “a” :

Note: Have only filled in ten squares, corresponding to the ten numerical digits we wish to represent.

° Find minimal sum-of-products representation for each output

Don’t care conditions (BCD display) ...

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100


Put in “X” (don’t care), and interpret as either 1 or 0 as desired ….

° Fill in don’t cares for undefined outputs.• Note that these combinations of inputs should never happen.

° Leads to a reduced implementation



yFa1 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

° Circle biggest group of 1’s and Don’t Cares.


Don’t care conditions (BCD display)


wFa2 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100





zxFa3

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

xzFa4

1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100


° All 1’s should be covered by at least one implicant



xzzxwyF 1 0

10

1 1 X X

X X X X

1 1

11

yz

wx

10

11

01

00

10110100

° Put all the terms together

° Generate the circuit


.0111110019

.1111100018

.0011111107

.

.1101101002

.0011010001

.1111100000

.edcbazyxwDec

° Derive the truth table for the circuit.

° Each output column in one circuit.

Inputs Outputs


1 1

01

1 1

1 0

11

yz

wx

10

11

01

00

10110100

For segment “b” :

See if you complete this example.

° Find minimal sum-of-products representation for each output

Half Adder

C A B S 0 0 0 1 A 0 B 0

S 0

C 1

0 0 0 00 1 1 01 0 1 01 1 0 1

Dec Binary 1 1+1 +1 2 10

° Add two binary numbers• A0 , B0 -> single bit inputs

• S0 -> single bit sum

• C1 -> carry out

Multiple-bit Addition

A3 A2 A1 A0

0 1 0 1A 0 1 1 1B3 B2 B1 B0

B

0 1 0 10 1 1 1

A

B

0

1

0

1

1

1

1

Ai

+Bi

Ci

Si

Ci+1

° Consider single-bit adder for each bit position.

Each bit position creates a sum and carry

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

1 1

1 1

Ci

AiBi00 01 11 10

0

1

Si

° Full adder includes carry in Ci

° Notice interesting pattern in Karnaugh map.

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1 Si = !Ci & !Ai & Bi

# !Ci & Ai & !Bi

# Ci & !Ai & !Bi

# Ci & Ai & Bi

° Full adder includes carry in Ci

° Alternative to XOR implementation

Full Adder &:and , #:or , $: xor

Si = !Ci & !Ai & Bi

# !Ci & Ai & !Bi

# Ci & !Ai & !Bi

# Ci & Ai & Bi

Si = !Ci & (!Ai & Bi # Ai & !Bi)

# Ci & (!Ai & !Bi # Ai & Bi)

Si = !Ci & (Ai $ Bi)

# Ci & !(Ai $ Bi)

Si = Ci $ (Ai $ Bi)

° Reduce and/or representations into XORs

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1

1

1 11

Ci

AiBi00 01 11 10

0

1

Ci+1

° Now consider implementation of carry out

° Two outputs per full adder bit (Ci+1, Si)

Note: 3 inputs

Full Adder

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

Ci Ai Bi Si Ci+1 Ci

AiBi00 01 11 10

0

1

1

1 11

Ci+1

Ci+1 = Ai & Bi

# Ci & Bi

# Ci & Ai

° Now consider implementation of carry out

° Minimize circuit for carry out - Ci+1

Full Adder

Ci+1 = Ai & Bi

# Ci !Ai & Bi

# Ci & Ai & !Bi

Ci+1 = Ai & Bi

# Ci & (!Ai & Bi # Ai & !Bi)

Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

Recall:Si = Ci $ (Ai $ Bi)

Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

Full Adder

A

B

S

C

C i+1

i

i

i

i

Si = Ci $ (Ai $ Bi)

Half-adder Half-adder

Ci+1 = Ai & Bi # Ci & (Ai $ Bi)

° Full adder made of several half adders

Full Adder

half-adder

half-adderA

B

i

i

C i

C i+1

S i

S

C

C

A full adder can be made fromtwo half adders (plus an OR gate).

° Hardware repetition simplifies hardware design

Full Adder

Full Adder

A B

C C

S

i i

i+1 i

i

Block Diagram

° Putting it all together • Single-bit full adder

• Common piece of computer hardware

4-Bit Adder

Full Adder

A B

0 C

S

0 0

1

0

Full Adder

A B

C

S

1 1

2

1

Full Adder

A B

C

S

2 2

3

2

Full Adder

A B

C S

3 3

4 3

C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0

° Chain single-bit adders together.

° What does this do to delay?

Negative Numbers – 2’s Complement.

110 = 0116 = 00000001-110 = FF16 = 11111111

12810 = 8016 = 10000000-12810 = 8016 = 10000000

° Subtracting a number is the same as:1. Perform 2’s complement

2. Perform addition

° If we can augment adder with 2’s complement hardware?

4-bit Subtractor: E = 1

Full Adder

A B

C

0 0

1

0

Full Adder

A B

C

1 1

2

1

Full Adder

A B

C

2 2

3

2

Full Adder

A B

C SD

3 3

4 3 SD SD SD

E

+1

Add A to B’ (one’s complement) plus 1

That is, add A to two’s complement of BD = A - B

Adder- Subtractor Circuit

Overflow in two’s complement addition

° Definition: When two values of the same signs are added:

• Result won’t fit in the number of bits provided

• Result has the opposite sign.

Overflow?

CN-1

CN

Assumes an N-bit adder, with bit N-1 the MSB

10 1101 1010-------- 0111

11 1110 1101-------- 1011

01 0011 0110-------- 1001

00 0010 0011-------- 0101

00 0010 1100-------- 1110

11 1110 0100-------- 0010

Addition cases and overflow

OFL OFL

235

3 6-7

-2-3-5

-3-6 7

2-4-2

-2 4 2

Magnitude Comparator

° The comparison of two numbers• outputs: A>B, A=B, A<B

° Design Approaches• the truth table

- 22n

entries - too cumbersome for large n

• use inherent regularity of the problem

- reduce design efforts

- reduce human errors

MagnitudeCompare

A[3..0]

B[3..0]A = B

A < B

A > B


A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

How can we find A > B?

How many rows would a truth table have?

28 = 256


A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

If A = 1001 and B = 0111is A > B?Why?

Because A3 > B3i.e. A3 . B3’ = 1

Therefore, one term in thelogic equation for A > B isA3 . B3’

Find A > B


If A = 1010 and B = 1001is A > B?Why? Because A3 = B3 and

A2 = B2 and A1 > B1i.e. C3 = 1 and C2 = 1 and A1 . B1’ = 1

Therefore, the next term in thelogic equation for A > B isC3 . C2 . A1 . B1’

A > B = A3 . B3’ + C3 . A2 . B2’ + …..

Magnitude Comparison

° Algorithm -> logic• A = A3A2A1A0 ; B = B3B2B1B0

• A=B if A3=B3, A2=B2, A1=B1and A0=B0

° Test each bit:- equality: xi= AiBi+Ai'Bi'

- (A=B) = x3x2x1x0

° More difficult to test less than/greater than• (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

• (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

• Start comparisons from high-order bits

° Implementation• xi = (AiBi'+Ai'Bi)’

Magnitude Comparison

° Hardware chips


° Real-world application• Thermostat controller

Multiplexers

° Select an input value with one or more select bits

° Use for transmitting data

° Allows for conditional transfer of data

° Sometimes called a mux

4– to– 1- Line Multiplexer

Quadruple 2–to–1-Line Multiplexer

° Notice enable bit

° Notice select bit

° 4 bit inputs

Multiplexer as combinational modules° Connect input variables to select inputs of

multiplexer (n-1 for n variables)

° Set data inputs to multiplexer equal to values of function for corresponding assignment of select variables

° Using a variable at data inputs reduces size of the multiplexer

Implementing a Four- Input Function with a Multiplexer

Typical multiplexer uses

Three-state gates

• A multiplexer can be constructed with three-state gates

• Output state: 0, 1, and high-impedance (open ckts)

• If the select input (E) is 0, the three-state gate has no output

Opposite true here,

No output if E is 1

Three-state gates

• A multiplexer can be constructed with three-state gates

• Output state: 0, 1, and high-impedance (open ckts)

• If the select input is low, the three-state gate has no output

Decoders and Encoders

° Binary decoders• Converts an n-bit code to a single active output

• Can be developed using AND/OR gates

• Can be used to implement logic circuits.

° Binary encoders• Converts one of 2n inputs to an n-bit output

• Useful for compressing data

• Can be developed using AND/OR gates

° Both encoders and decoders are extensively used in digital systems

Binary Decoder

° Black box with n input lines and 2n output lines

° Only one output is a 1 for any given input

BinaryDecoder

ninputs 2n outputs

2-to-4 Binary Decoder2-to-4 Binary Decoder

° From truth table, circuit for 2x4 decoder is:

° Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

X Y F0 F1 F2 F3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

F0 = X'Y'

F1 = X'Y

F2 = XY'

F3 = XY

X Y

Truth Table:

2-to-4Decoder

X

Y

F0

F1

F2

F3

3-3-to-8 to-8 BinaBinary ry DecDecoderoderx y z F0 F1 F2 F3 F4 F5 F6 F7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

F1 = x'y'z

x zy

F0 = x'y'z'

F2 = x'yz'

F3 = x'yz

F5 = xy'z

F4 = xy'z'

F6 = xyz'

F7 = xyz

Truth Table:

3-to-8Decoder

X

Y

F0

F1

F2

F3

F4

F5

F6

F7

Z

Implementing Functions Using Decoders

° Any n-variable logic function can be implemented using a single n-to-2n decoder to generate the minterms

• OR gate forms the sum.

• The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate.

° Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n decoder with m OR gates.

° Suitable when a circuit has many outputs, and each output function is expressed with few minterms.

Implementing Functions Using Decoders

° Example: Full adderS(x, y, z) = (1,2,4,7)

C(x, y, z) = (3,5,6,7)

3-to-8Decoder

S2

S1

S0

x

y

z

0

1

2

3

4

5

6

7

S

C

x y z C S0 0 0 0 00 0 1 0 10 1 0 0 10 1 1 1 01 0 0 0 11 0 1 1 01 1 0 1 01 1 1 1 1

Standard MSI Binary Decoders ExampleStandard MSI Binary Decoders Example

74138 (3-to-8 decoder)

(a) Logic circuit. (b) Package pin configuration. (c) Function table.

Building a Binary Decoder with NAND Gates

° Start with a 2-bit decoder• Add an enable signal (E) Note: use of NANDs

only one 0 active!

if E = 0

Use two 3 to 8 decoders to make 4 to 16 decoder

° Enable can also be active high

° In this example, only one decoder can be active at a time.

° x, y, z effectively select output line for w

Encoders

° If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder.

e.g. 2n-to-n

° The simplest encoder is a 2n-to-n binary encoder• One of 2n inputs = 1

• Output is an n-bit binary number

.

.

.

.

.

.

2n

inputsn outputs

Binaryencoder

8-to-3 Binary Encoder8-to-3 Binary EncoderAt any one time, only one input line has a value of 1.

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0

1 0 0 0 0 0 0 0 0 0 00 1 0 0 0 0 0 0 0 0 10 0 1 0 0 0 0 0 0 1 00 0 0 1 0 0 0 0 0 1 10 0 0 0 1 0 0 0 1 0 00 0 0 0 0 1 0 0 1 0 10 0 0 0 0 0 1 0 1 1 00 0 0 0 0 0 0 1 1 1 1

I0

I1

I2

I3

I4

I5

I6

I7

y0 = I1 + I3 + I5 + I7

y1 = I2 + I3 + I6 + I7

y2 = I4 + I5 + I6 + I7

8-to-3 Priority Encoder8-to-3 Priority Encoder

• What if more than one input line has a value of 1?• Ignore “lower priority” inputs.• Idle indicates that no input is a 1.• Note that polarity of Idle is opposite from Table 4-8 in Mano

Inputs Outputs

I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 y2 y1 y0 Idle

0 0 0 0 0 0 0 0 x x x 11 0 0 0 0 0 0 0 0 0 0 0X 1 0 0 0 0 0 0 0 0 1 0X X 1 0 0 0 0 0 0 1 0 0X X X 1 0 0 0 0 0 1 1 0X X X X 1 0 0 0 1 0 0 0X X X X X 1 0 0 1 0 1 0X X X X X X 1 0 1 1 0 0X X X X X X X 1 1 1 1 0

Priority Encoder (8 to 3 encoder)

° Assign priorities to the inputs

° When more than one input are asserted, the output generates the code of the input with the highest priority

° Priority Encoder : H7=I7 (Highest Priority) H6=I6.I7’ H5=I5.I6’.I7’ H4=I4.I5’.I6’.I7’ H3=I3.I4’.I5’.I6’.I7’ H2=I2.I3’.I4’.I5’.I6’.I7’ H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’

° Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7

Y1

Y2

Y0

IDLE

I1

I2

I3 Y1

Y2I4

I5

I6

I0

Y0

I7

Binary encoder

I1

I2

I3

I4

I5

I6

I0

I7

Priority Circuit

H1

H2

H3

H4

H5

H6

H0

H7

IDLE

I1

I2

I3

I4

I5

I6

I0

I7

Priority encoder

Encoder Application (Monitoring Unit)

Action

Encoder Controller

Machine Code

Machine 1

Machine 2

Machine n

Alarm Signal

Contoller Response

° Encoder identifies the requester and encodes the value

° Controller accepts digital inputs.

Documents

Overview of Chapter 4 °Design digital circuit from specification °Digital inputs and outputs known Need to determine logic that can transform data °Start