Overview Digital Design Arithmetic II€¦ · Booth’s Algorithm Current bit Bit to right ... NR Division Example Iteration Step Divisor Remainder 0 Initial values 0010 0000 0111

EE260: Logic Design, Spring 2018 11-Mar-18

Chapter 8: Arithmetic II 1

EE 260: Introduction toDigital DesignArithmetic II

Yao ZhengDepartment of Electrical Engineering

University of Hawaiʻi at Mānoa

Overviewn Integer multiplication

n Booth’s algorithmn Integer division

n Restoring, non-restoringn Floating point representationn Floating point addition, multiplication

Multiplication

n Flashback to 3rd graden Multipliern Multiplicandn Partial productsn Final sum

n Base 10: 8 x 9 = 72n PP: 8 + 0 + 0 + 64 = 72

n How wide is the result?n log(n x m) = log(n) + log(m)n 32b x 32b = 64b result

1 0 0 0

x 1 0 0 1

1 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

1 0 0 1 0 0 0

Array Multipliern Adding all partial

products simultaneously using an array of basic cells

1 0 0 0

x 1 0 0 1

1 0 0 0

0 0 0 0

0 0 0 0

1 0 0 0

1 0 0 1 0 0 0

Full Adder

Sin Cin Ai Bj

Cout Sout

Ai ,Bj

16-bit Array Multiplier

l Conceptually straightforwardl Fairly expensive hardware, integer multiplies relatively rare

l Mostly used in array address calc: replace with shifts

Instead: Multicycle Multipliersn Combinational multipliers

n Very hardware-intensiven Integer multiply relatively raren Not the right place to spend resources

n Multicycle multipliersn Iterate through bits of multipliern Conditionally add shifted multiplicand



Multiplier1 0 0 0

x 1 0 0 11 0 0 0

0 0 0 00 0 0 0

1 0 0 01 0 0 1 0 0 0

Multiplier

Done

1. Test Multiplier0

1a. Add multiplicand to product and place the result in Product register

2. Shift the Multiplicand register left 1 bit

3. Shift the Multiplier register right 1 bit

32nd repetition?

Start

Multiplier0 = 0Multiplier0 = 1

No: < 32 repetitions

Yes: 32 repetitions

1 0 0 0x 1 0 0 11 0 0 0

0 0 0 00 0 0 0

1 0 0 01 0 0 1 0 0 0

Multiplier Improvementsn Do we really need a 64-bit adder?

n No, since low-order bits are not involvedn Hence, just use a 32-bit adder

n Shift product register right on every stepn Do we really need a separate multiplier

register?n No, since low-order bits of 64-bit product are

initially unusedn Hence, just store multiplier there initially

Multiplier

Control testWrite

32 bits

64 bits

Shift rightProduct

Multiplicand

32-bit ALU

1 0 0 0x 1 0 0 11 0 0 0

0 0 0 00 0 0 0

1 0 0 01 0 0 1 0 0 0

Multiplier

Done

1. Test Product0

1a. Add multiplicand to the left half of the product and place the result in the left half of the Product register

2. Shift the Product register right 1 bit

32nd repetition?

Start

Product0 = 0Product0 = 1


Yes: 32 repetitions

1 0 0 0x 1 0 0 11 0 0 0

0 0 0 00 0 0 0

1 0 0 01 0 0 1 0 0 0

Signed Multiplicationn Recall

n For p = a x b, if a<0 or b<0, then p < 0n If a<0 and b<0, then p > 0n Hence sign(p) = sign(a) xor sign(b)

n Hencen Convert multiplier, multiplicand to positive

number with (n-1) bitsn Multiply positive numbersn Compute sign, convert product accordingly

n Or,n Perform sign-extension on shifts for prev. designn Right answer falls out



Signed Multiplication Booth’s Encodingn Recall grade school trick

n When multiplying by 9:n Multiply by 10 (easy, just shift digits left)n Subtract once

n E.g.n 123454 x 9 = 123454 x (10 – 1) = 1234540 – 123454n Converts addition of six partial products to one shift and one

subtractionn Booth’s algorithm applies same principle

n Except no ‘9’ in binary, just ‘1’ and ‘0’n So, it’s actually easier!

Booth’s Encodingn Search for a run of ‘1’ bits in the multiplier

n E.g. ‘0110’ has a run of 2 ‘1’ bits in the middlen Multiplying by ‘0110’ (6 in decimal) is equivalent to

multiplying by 8 and subtracting twice, since 6 x m = (8 – 2) x m = 8m – 2m

n Hence, iterate right to left and:n Subtract multiplicand from product at first ‘1’n Add multiplicand to product after last ‘1’n Don’t do either for ‘1’ bits in the middle

Booth’s Algorithm

Current bit

Bit to right

Explanation Example Operation

1 0 Begins run of ‘1’ 00001111000 Subtract

1 1 Middle of run of ‘1’ 00001111000 Nothing

0 1 End of a run of ‘1’ 00001111000 Add

0 0 Middle of a run of ‘0’ 00001111000 Nothing

Booth’s Encodingn Really just a new way to encode numbers

n Normally positionally weighted as 2n

n With Booth, each position has a sign bitn Can be extended to multiple bits

0 1 1 0 Binary+1 0 -1 0 1-bit Booth+2 -2 2-bit Booth

2-bits/cycle Booth Multipliern For every pair of multiplier bits

n If Booth’s encoding is ‘-2’n Shift multiplicand left by 1, then subtract

n If Booth’s encoding is ‘-1’n Subtract

n If Booth’s encoding is ‘0’n Do nothing

n If Booth’s encoding is ‘1’n Add

n If Booth’s encoding is ‘2’n Shift multiplicand left by 1, then add



2 bits/cycle Booth’s

Current Previous Operation Explanation

00 0 +0;shift 2 [00] => +0, [00] => +0; 2x(+0)+(+0)=+0

00 1 +M; shift 2 [00] => +0, [01] => +M; 2x(+0)+(+M)=+M

01 0 +M; shift 2 [01] => +M, [10] => -M; 2x(+M)+(-M)=+M

01 1 +2M; shift 2 [01] => +M, [11] => +0; 2x(+M)+(+0)=+2M

10 0 -2M; shift 2 [10] => -M, [00] => +0; 2x(-M)+(+0)=-2M

10 1 -M; shift 2 [10] => -M, [01] => +M; 2x(-M)+(+M)=-M

11 0 -M; shift 2 [11] => +0, [10] => -M; 2x(+0)+(-M)=-M

11 1 +0; shift 2 [11] => +0, [11] => +0; 2x(+0)+(+0)=+0

1 bit Booth00 +001 +M;10 -M;11 +0

Booth’s Examplen Negative multiplicand:

-6 x 6 = -361010 x 0110, 0110 in Booth’s encoding is +0-0Hence:

1111 1010 x 0 0000 00001111 0100 x –1 0000 11001110 1000 x 0 0000 0000

1101 0000 x +1 1101 0000Final Sum: 1101 1100 (-36)

Booth’s Examplen Negative multiplier:

-6 x -2 = 121010 x 1110, 1110 in Booth’s encoding is 00-0Hence:

1111 1010 x 0 0000 00001111 0100 x –1 0000 11001110 1000 x 0 0000 0000

1101 0000 x 0 0000 0000Final Sum: 0000 1100 (12)

Integer Division

n Again, back to 3rd grade (74 ÷ 8 = 9 rem 2)1 0 0 1 Quotient

Divisor 1 0 0 0 1 0 0 1 0 1 0 Dividend

- 1 0 0 0

1 0

1 0 1

1 0 1 0

- 1 0 0 0

1 0 Remainder

Integer Divisionn How does hardware know if division fits?

n Condition: if remainder ≥ divisorn Use subtraction: (remainder – divisor) ≥ 0

n OK, so if it fits, what do we do?n Remaindern+1 = Remaindern – divisor

n What if it doesn’t fit?n Have to restore original remainder

n Called restoring division

Integer Division

64-bit ALU

Control test

QuotientShift left

RemainderWrite

DivisorShift right

64 bits

64 bits

32 bits

1 0 0 1 QuotientDivisor 1 0 0 0 1 0 0 1 0 1 0 Dividend

- 1 0 0 01 01 0 11 0 1 0

- 1 0 0 01 0 Remainder



Integer Division

Done

Test Remainder

2a. Shift the Quotient register to the left, setting the new rightmost bit to 1

3. Shift the Divisor register right 1 bit

33rd repetition?

Start

Remainder < 0


Yes: 33 repetitions

2b. Restore the original value by adding the Divisor register to the Remainder

register and place the sum in the Remainder register. Also shift the

Quotient register to the left, setting the new least significant bit to 0

1. Subtract the Divisor register from the Remainder register and place the result in the Remainder register

Remainder > 0

–

1 0 0 1 QuotientDivisor 1 0 0 0 1 0 0 1 0 1 0 Dividend

- 1 0 0 01 01 0 11 0 1 0

- 1 0 0 01 0 Remainder

Integer Division

Division Improvementsn Hardware similar to multiplier

n Can store quotient in remainder registern Only need 32b ALU

n Shift remainder left vs. divisor right

Improved Divider

Write

32 bits

64 bits

Shift leftShift right

Remainder

32-bit ALU

Divisor

Control test

Division Improvementsn Skip first subtract

n Can’t shift ‘1’ into quotient anywayn Hence shift first, then subtract

n Undo extra shift at end

Improved Divider

Done. Shift left half of Remainder right 1 bit

Test Remainder

3a. Shift the Remainder register to the left, setting the new rightmost bit to 1

32nd repetition?

Start

Remainder < 0


Yes: 32 repetitions

3b. Restore the original value by adding the Divisor register to the left half of the Remainder register and place the sum

in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new rightmost bit to 0

2. Subtract the Divisor register from the left half of the Remainder register and place the result in the left half of the

Remainder register

Remainder 0

1. Shift the Remainder register left 1 bit

–>



Improved Divider Further Improvementsn Division still takes:

n 2 ALU cycles per bit positionn 1 to check for divisibility (subtract)n One to restore (if needed)

n Can reduce to 1 cycle per bitn Called non-restoring divisionn Avoids restore of remainder when test fails

Non-restoring Divisionn Consider remainder to be restored:

Ri = Ri-1 – d < 0n Since Ri is negative, we must restore it, right?n Well, maybe not. Consider next step i+1:

Ri+1 = 2 x (Ri) – d = 2 x (Ri – d) + dn Hence, we can compute Ri+1 by not restoring Ri,

and adding d instead of subtracting dn Same value for Ri+1 results

n Throughput of 1 bit per cycle

NR Division ExampleIteration Step Divisor Remainder

0Initial values 0010 0000 0111Shift rem left 1 0010 0000 1110

12: Rem = Rem - Div 0010 1110 11103b: Rem < 0 (add next), sll 0 0010 1101 1100

22: Rem = Rem + Div 0010 1111 11003b: Rem < 0 (add next), sll 0 0010 1111 1000

32: Rem = Rem + Div 0010 0001 10003a: Rem > 0 (sub next), sll 1 0010 0011 0001

4Rem = Rem – Div 0010 0001 0001Rem > 0 (sub next), sll 1 0010 0010 0011Shift Rem right by 1 0010 0001 0011

Floating Pointn Want to represent larger range of

numbersn Fixed point (integer): -2n-1 … (2n-1 –1)

n How? Sacrifice precision for range by providing exponent to shift relative weight of each bit position

n Similar to scientific notation:3.14159 x 1023

n Cannot specify every discrete value in the range, but can span much larger range

Floating Point

n Still use a fixed number of bitsn Sign bit S, exponent E, significand Fn Value: (-1)S x F x 2E

n IEEE 754 standardSize Exponent Significand Range

Single precision 32b 8b 23b 2x10+/-38

Double precision 64b 11b 52b 2x10+/-308

S E F



Floating Point Exponentn Exponent specified in biased or excess

notationn Why?

n To simplify sortingn Sign bit is MSB to ease sortingn 2’s complement exponent:

n Large numbers have positive exponentn Small numbers have negative exponent

n Sorting does not follow naturally

Excess or Biased Exponent

Exponent 2’s Compl Excess-127-127 1000 0001 0000 0000-126 1000 0010 0000 0001… … …+127 0111 1111 1111 1110

n Value: (-1)S x F x 2(E-bias)

n SP: bias is 127n DP: bias is 1023

Floating Point Normalizationn S,E,F representation allows more than one

representation for a particular value, e.g. 1.0 x 105 = 0.1 x 106 = 10.0 x 104

n This makes comparison operations difficultn Prefer to have a single representation

n Hence, normalize by convention:n Only one digit to the left of the floating pointn In binary, that digit must be a 1

n Since leading ‘1’ is implicit, no need to store itn Hence, obtain one extra bit of precision for free

FP Overflow/Underflown FP Overflow

n Analogous to integer overflown Result is too big to representn Means exponent is too big

n FP Underflown Result is too small to representn Means exponent is too small (too negative)

n Both can raise an exception under IEEE754

IEEE754 Special CasesSingle Precision Double Precision Value

Exponent Significand Exponent Significand

0 0 0 0 0

0 nonzero 0 nonzero denormalized

1-254 anything 1-2046 anything fp number

255 0 2047 0 infinity

255 nonzero 2047 nonzero NaN (Not a Number)

FP Roundingn Rounding is important

n Small errors accumulate over billions of opsn FP rounding hardware helps

n Compute extra guard bit beyond 23/52 bitsn Further, compute additional round bit beyond that

n Multiply may result in leading 0 bit, normalize shifts guard bit into product, leaving round bit for rounding

n Finally, keep sticky bit that is set whenever ‘1’ bits are “lost” to the rightn Differentiates between 0.5 and 0.500000000001



Floating Point Additionn Just like grade school

n First, align decimal pointsn Then, add significandsn Finally, normalize result

n Example9.997 x 102 9.997000 x 102

4.631 x 10-1 0.004631 x 102

Sum 10.001631 x 102

Normalized 1.0001631 x 103

FP Adder

0 10 1 0 1

Control

Small ALU

Big ALU

Sign Exponent Significand Sign Exponent Significand

Exponent difference

Shift right

Shift left or right

Rounding hardware

Sign Exponent Significand

Increment or decrement

0 10 1

Shift smaller number right

Compare exponents

Add

Normalize

Round

FP Multiplicationn Sign: Ps = As xor Bsn Exponent: PE = AE + BE

n Due to bias/excess, must subtract biase = e1 + e2E = e + 1023 = e1 + e2 + 1023E = (E1 – 1023) + (E2 – 1023) + 1023E = E1 + E2 –1023

n Significand: PF = AF x BFn Standard integer multiply (23b or 52b + g/r/s bits)n Use Wallace tree of CSAs to sum partial products

Carry Save AdderA + B => SSave carries A + B => S, CoutUse Cin A + B + C => S1, S2 (3# to 2# in

parallel)Used in combinational multipliers by building a

Wallace Treec b a

c s

CSA

Adding Up Many Bits

CSA CSA

CSA

CSAS0

S1S2

abcdef

FP Multiplicationn Compute sign, exponent, significandn Normalize

n Shift left, right by 1n Check for overflow, underflown Roundn Normalize again (if necessary)



Logical Operationsn Bitwise AND, OR, XOR, NOR

n Implement w/ 32 gates in paralleln Shifts and rotates

n rol => rotate left (MSB->LSB)n ror => rotate right (LSB->MSB)n sll -> shift left logical (0->LSB)n srl -> shift right logical (0->LSB)n sra -> shift right arithmetic (old MSB->new MSB)

Shifter

shamt0

d0 0d7 d6

shift based on 0th bit by 0 or 1

shamt1

s00 s02s07

shift based on 1st bit by 0 or 2

shamt2

s10 0s17 s13

shift based on 2nd bit by 0 or 4

stage0

stage1

dout

s06 s00 0s01 0

s14 s10 s13 0

s07 s00

s17 s10

dout7 dout7

d1 d0

Mux

Mux

Mux

Shifter

E.g., Shift left logical for d<7:0> and shamt<2:0>

Using 2-1 Muxes called Mux(select, in0, in1)

stage0<7:0> = Mux(shamt<0>,d<7:0>, 0 || d<7:1>)

stage1<7:0> = Mux(shamt<1>, stage0<7:0>, 00 || stage0<6:2>)

dout<7:0) = Mux(shamt<2>, stage1<7:0>, 0000 || stage1<3:0>)

For Barrel shifter used wider muxes

Summaryn Integer multiply

n Combinationaln Multicyclen Booth’s algorithm

n Integer dividen Multicycle restoringn Non-restoring

Summaryn Floating point representation

n Normalizationn Overflow, underflown Rounding

n Floating point addn Floating point multiply

Documents

Overview Digital Design Arithmetic II€¦ · Booth’s Algorithm Current bit Bit to right ... NR Division Example Iteration Step Divisor Remainder 0 Initial values 0010 0000 0111