John EllisSr. Staff R&D EngineerSynopsys, Inc.

Overcoming Obstacles to Closing Timing for DDR3-1600 and Beyond

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Agenda

Timing budgets 1600 2133Mbps ? Static vs. Dynamic Uncertainty Sources

• Benefits of Deskew Technologies Reducing Dynamic Uncertainty

• Crosstalk, ISI and Reflections• Package Power Delivery

Conclusions

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DDRn Timing

DDR Interfaces are Source Synchronous• Total delay doesn’t matter (within reason)• Delay difference or Skew is Critical

Set up

Vref

Vref

Strobe

Data

Hold

Delay of DQ must tightly match the delay of differential DQS Optimal Strobe placement maximizes Set up

and Hold

ASIC DRAM1 DRAM2

Strobe (DQS)

Data (DQ)

(Data Write Shown)

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Three Regions of Uncertainty Host

• Launch signals in quadrature during Write Operations, Center Strobe within Data during Reads

SDRAM• Receive signals during Writes, launch edge-aligned during

Reads Interconnect

• Maintain alignment and signal integrity between Host and SDRAM

• Power delivery90°

Strobe

Data Launched 90° Out ofPhase with Strobe

Strobe

Data Received Edge-Aligned with strobe

Write Read

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Uncertainty Contributors within the Host

Signal skew between Data and Strobe within the PHY

Clock Skew with in the PHY Across silicon process and line width

variation Jitter from source clock or DLL if applicable Delay differences between rising and falling

edges. Granularity of delay line structures

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SDRAM Consumes ~50% of the Available Read and Write Budgets at 1600Mbps+

Set Up andHold

Output Skew andHold Skew Factor

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Agenda

Timing budgets 1600 2133Mbps ?Static vs. Dynamic Uncertainty Sources

• Benefits of Deskew Technologies Reducing Dynamic Uncertainty

• Crosstalk, ISI and Reflections• Package Power Delivery

Conclusions

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Static Uncertainty Static uncertainty is

timing uncertainty that does not vary with switching patterns or number of signals switching• Example – Routing skew

between DQ and DQS

Deskew can remove most static uncertainty • Training sequence

implemented• Bits are first aligned• Strobe is placed in center of

newly constructed eye.

Skew: PCB, PHY, Internal Clock Skew…

Dynamic Uncertainty Dynamic uncertainty will vary with switching

patterns. Example – Crosstalk, ISI, SSO pushout,

reflections from modal impedance changes Cannot be reliably deskewed since it can

vary on a bit by bit basis.

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ISI

SSO Pushout

A QCrosstalk

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Agenda

Timing budgets 1600 2133Mbps ? Static vs. Dynamic Uncertainty Sources

• Benefits of Deskew TechnologiesReducing Dynamic Uncertainty

• Crosstalk, ISI and Reflections• Package Power Delivery

Conclusions

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Dynamic Uncertainty – Crosstalk. Timing Impact of Cross section

In Stripline:• Signals will travel at

the same velocities no matter what coupling modes are excited because of the uniform dielectric.

In Microstrip:• Different coupling

modes will travel at different velocities because of the impact of the mixed dielectric cross section.

Even ModeOdd ModeNo coupling

Stripline

Microstrip

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Different Modes Yield Different Flight Times

Odd coupled arrives 27ps earlier

Even coupled arrives 31ps later

Total uncertainty is 59 ps

No Coupling Odd Mode Even Mode

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Longer Length = Greater Divergence

2” routed length yields 59ps of uncertainty

6” routed length yields 148ps of uncertainty

ODD

EVEN

ODD

EVEN

2” Routed Length

6” Routed Length

148ps

59ps

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Striplines Have Equal Mode Velocities

Whether uncoupled or Even or Odd coupled, mode velocities are the same in stripline.

Total divergence in 6” of stripline ~30ps

ODD

EVEN

6” Microstrip

6” Stripline

EVENODD and UNCOUPLED

148ps

30ps

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Increased spacing equals increase isolation

Increased soldermask thickness yields more uniform dielectric constant

No Coupling Odd Mode Even Mode

Options for Reducing Timing Divergence

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Intersymbol Interference and DDR Signaling

Routed lengths on DDR signals are relatively short, < 6” typically.• Fly-by Address can be considerably longer

The number of SDRAM loads will have a larger ISI effect on the interface.

2” Vs. 6” 1 Load Vs. 2 Loads

554ps 525ps 554ps 500s

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Termination Mismatch can be a Significant Contributor

468ps

525ps

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ISI and Reflections lead to Uncertainty at the Vref Level

95ps 39ps 24ps

19ps 22ps 24ps

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Switching Modes also Impact PCB Impedance

59Ω

71Ω

49Ω

TDR traces

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How SSO Impacts Timing

73ps

303ps

294ps

257ps

230ps

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Use DDR Devices as a Guide for Power Ratios

DDR3 SDRAM Device

Try to match the via/ball count to the number of power/ground pad connections as closely as possible

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Carry Ratios Through Entire Connection

1/2 the number of connections as a minimum should be the goal.

It is important that the via/ball connections be regularly spaced around the die to minimize the size of the current loops.

Place signal trace vias near vias from the reference layer to minimize current loop size and resulting crosstalk

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Agenda

Timing budgets 1600 2133Mbps ? Static vs. Dynamic Uncertainty Sources

• Benefits of Deskew Technologies Reducing Dynamic Uncertainty

• Crosstalk, ISI and Reflections• Package Power DeliveryConclusions

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In Summary As data rates exceed 1600Mbps, the SDRAM requirements will

consume ~50% of the budget.

Deskew solutions are available, but they will only correct for static offsets between the data and its related strobe. They don’t work on dynamic contributors.

Good interconnect design can retrieve a great deal of margin.

Pay attention to modal effects especially in microstrip configurations.

Pay attention to package power/ground to signal ratios as well as placement of vias and balls to control inductance.

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Predictable Success